1 //===-- HexagonExpandPredSpillCode.cpp - Expand Predicate Spill Code ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // The Hexagon processor has no instructions that load or store predicate
10 // registers directly. So, when these registers must be spilled a general
11 // purpose register must be found and the value copied to/from it from/to
12 // the predicate register. This code currently does not use the register
13 // scavenger mechanism available in the allocator. There are two registers
14 // reserved to allow spilling/restoring predicate registers. One is used to
15 // hold the predicate value. The other is used when stack frame offsets are
18 //===----------------------------------------------------------------------===//
21 #include "HexagonMachineFunctionInfo.h"
22 #include "HexagonSubtarget.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/CodeGen/LatencyPriorityQueue.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
32 #include "llvm/CodeGen/SchedulerRegistry.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
44 void initializeHexagonExpandPredSpillCodePass(PassRegistry&);
50 class HexagonExpandPredSpillCode : public MachineFunctionPass {
53 HexagonExpandPredSpillCode() : MachineFunctionPass(ID) {
54 PassRegistry &Registry = *PassRegistry::getPassRegistry();
55 initializeHexagonExpandPredSpillCodePass(Registry);
58 const char *getPassName() const override {
59 return "Hexagon Expand Predicate Spill Code";
61 bool runOnMachineFunction(MachineFunction &Fn) override;
65 char HexagonExpandPredSpillCode::ID = 0;
68 bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
70 const HexagonSubtarget &QST = Fn.getSubtarget<HexagonSubtarget>();
71 const HexagonInstrInfo *TII = QST.getInstrInfo();
73 // Loop over all of the basic blocks.
74 for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
75 MBBb != MBBe; ++MBBb) {
76 MachineBasicBlock* MBB = MBBb;
77 // Traverse the basic block.
78 for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
80 MachineInstr *MI = MII;
81 int Opc = MI->getOpcode();
82 if (Opc == Hexagon::STriw_pred) {
83 // STriw_pred [R30], ofst, SrcReg;
84 unsigned FP = MI->getOperand(0).getReg();
85 assert(FP == QST.getRegisterInfo()->getFrameRegister() &&
86 "Not a Frame Pointer, Nor a Spill Slot");
87 assert(MI->getOperand(1).isImm() && "Not an offset");
88 int Offset = MI->getOperand(1).getImm();
89 int SrcReg = MI->getOperand(2).getReg();
90 assert(Hexagon::PredRegsRegClass.contains(SrcReg) &&
91 "Not a predicate register");
92 if (!TII->isValidOffset(Hexagon::S2_storeri_io, Offset)) {
93 if (!TII->isValidOffset(Hexagon::A2_addi, Offset)) {
94 BuildMI(*MBB, MII, MI->getDebugLoc(),
95 TII->get(Hexagon::CONST32_Int_Real),
96 HEXAGON_RESERVED_REG_1).addImm(Offset);
97 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_add),
98 HEXAGON_RESERVED_REG_1)
99 .addReg(FP).addReg(HEXAGON_RESERVED_REG_1);
100 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrpr),
101 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
102 BuildMI(*MBB, MII, MI->getDebugLoc(),
103 TII->get(Hexagon::S2_storeri_io))
104 .addReg(HEXAGON_RESERVED_REG_1)
105 .addImm(0).addReg(HEXAGON_RESERVED_REG_2);
107 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_addi),
108 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
109 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrpr),
110 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
111 BuildMI(*MBB, MII, MI->getDebugLoc(),
112 TII->get(Hexagon::S2_storeri_io))
113 .addReg(HEXAGON_RESERVED_REG_1)
115 .addReg(HEXAGON_RESERVED_REG_2);
118 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrpr),
119 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
120 BuildMI(*MBB, MII, MI->getDebugLoc(),
121 TII->get(Hexagon::S2_storeri_io)).
122 addReg(FP).addImm(Offset).addReg(HEXAGON_RESERVED_REG_2);
124 MII = MBB->erase(MI);
126 } else if (Opc == Hexagon::LDriw_pred) {
127 // DstReg = LDriw_pred [R30], ofst.
128 int DstReg = MI->getOperand(0).getReg();
129 assert(Hexagon::PredRegsRegClass.contains(DstReg) &&
130 "Not a predicate register");
131 unsigned FP = MI->getOperand(1).getReg();
132 assert(FP == QST.getRegisterInfo()->getFrameRegister() &&
133 "Not a Frame Pointer, Nor a Spill Slot");
134 assert(MI->getOperand(2).isImm() && "Not an offset");
135 int Offset = MI->getOperand(2).getImm();
136 if (!TII->isValidOffset(Hexagon::L2_loadri_io, Offset)) {
137 if (!TII->isValidOffset(Hexagon::A2_addi, Offset)) {
138 BuildMI(*MBB, MII, MI->getDebugLoc(),
139 TII->get(Hexagon::CONST32_Int_Real),
140 HEXAGON_RESERVED_REG_1).addImm(Offset);
141 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_add),
142 HEXAGON_RESERVED_REG_1)
144 .addReg(HEXAGON_RESERVED_REG_1);
145 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::L2_loadri_io),
146 HEXAGON_RESERVED_REG_2)
147 .addReg(HEXAGON_RESERVED_REG_1)
149 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrrp),
150 DstReg).addReg(HEXAGON_RESERVED_REG_2);
152 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_addi),
153 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
154 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::L2_loadri_io),
155 HEXAGON_RESERVED_REG_2)
156 .addReg(HEXAGON_RESERVED_REG_1)
158 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrrp),
159 DstReg).addReg(HEXAGON_RESERVED_REG_2);
162 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::L2_loadri_io),
163 HEXAGON_RESERVED_REG_2).addReg(FP).addImm(Offset);
164 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrrp),
165 DstReg).addReg(HEXAGON_RESERVED_REG_2);
167 MII = MBB->erase(MI);
178 //===----------------------------------------------------------------------===//
179 // Public Constructor Functions
180 //===----------------------------------------------------------------------===//
182 static void initializePassOnce(PassRegistry &Registry) {
183 const char *Name = "Hexagon Expand Predicate Spill Code";
184 PassInfo *PI = new PassInfo(Name, "hexagon-spill-pred",
185 &HexagonExpandPredSpillCode::ID,
186 nullptr, false, false);
187 Registry.registerPass(*PI, true);
190 void llvm::initializeHexagonExpandPredSpillCodePass(PassRegistry &Registry) {
191 CALL_ONCE_INITIALIZATION(initializePassOnce)
195 llvm::createHexagonExpandPredSpillCode() {
196 return new HexagonExpandPredSpillCode();