1 //===--- HexagonExpandPredSpillCode.cpp - Expand Predicate Spill Code ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===////
9 // The Hexagon processor has no instructions that load or store predicate
10 // registers directly. So, when these registers must be spilled a general
11 // purpose register must be found and the value copied to/from it from/to
12 // the predicate register. This code currently does not use the register
13 // scavenger mechanism available in the allocator. There are two registers
14 // reserved to allow spilling/restoring predicate registers. One is used to
15 // hold the predicate value. The other is used when stack frame offsets are
18 //===----------------------------------------------------------------------===//
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/LatencyPriorityQueue.h"
23 #include "llvm/CodeGen/SchedulerRegistry.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineLoopInfo.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "HexagonTargetMachine.h"
38 #include "HexagonSubtarget.h"
39 #include "HexagonMachineFunctionInfo.h"
43 #include "llvm/Support/CommandLine.h"
51 class HexagonExpandPredSpillCode : public MachineFunctionPass {
52 HexagonTargetMachine& QTM;
53 const HexagonSubtarget &QST;
57 HexagonExpandPredSpillCode(HexagonTargetMachine& TM) :
58 MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {}
60 const char *getPassName() const {
61 return "Hexagon Expand Predicate Spill Code";
63 bool runOnMachineFunction(MachineFunction &Fn);
67 char HexagonExpandPredSpillCode::ID = 0;
70 bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
72 const HexagonInstrInfo *TII = QTM.getInstrInfo();
74 // Loop over all of the basic blocks.
75 for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
76 MBBb != MBBe; ++MBBb) {
77 MachineBasicBlock* MBB = MBBb;
78 // Traverse the basic block.
79 for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
81 MachineInstr *MI = MII;
82 int Opc = MI->getOpcode();
83 if (Opc == Hexagon::STriw_pred) {
84 // STriw_pred [R30], ofst, SrcReg;
85 unsigned FP = MI->getOperand(0).getReg();
86 assert(FP == QTM.getRegisterInfo()->getFrameRegister() &&
87 "Not a Frame Pointer, Nor a Spill Slot");
88 assert(MI->getOperand(1).isImm() && "Not an offset");
89 int Offset = MI->getOperand(1).getImm();
90 int SrcReg = MI->getOperand(2).getReg();
91 assert(Hexagon::PredRegsRegClass.contains(SrcReg) &&
92 "Not a predicate register");
93 if (!TII->isValidOffset(Hexagon::STriw, Offset)) {
94 if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) {
95 BuildMI(*MBB, MII, MI->getDebugLoc(),
96 TII->get(Hexagon::CONST32_Int_Real),
97 HEXAGON_RESERVED_REG_1).addImm(Offset);
98 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr),
99 HEXAGON_RESERVED_REG_1)
100 .addReg(FP).addReg(HEXAGON_RESERVED_REG_1);
101 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
102 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
103 BuildMI(*MBB, MII, MI->getDebugLoc(),
104 TII->get(Hexagon::STriw))
105 .addReg(HEXAGON_RESERVED_REG_1)
106 .addImm(0).addReg(HEXAGON_RESERVED_REG_2);
108 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),
109 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
110 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
111 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
112 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::STriw))
113 .addReg(HEXAGON_RESERVED_REG_1)
115 .addReg(HEXAGON_RESERVED_REG_2);
118 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
119 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
120 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::STriw)).
121 addReg(FP).addImm(Offset).addReg(HEXAGON_RESERVED_REG_2);
123 MII = MBB->erase(MI);
125 } else if (Opc == Hexagon::LDriw_pred) {
126 // DstReg = LDriw_pred [R30], ofst.
127 int DstReg = MI->getOperand(0).getReg();
128 assert(Hexagon::PredRegsRegClass.contains(DstReg) &&
129 "Not a predicate register");
130 unsigned FP = MI->getOperand(1).getReg();
131 assert(FP == QTM.getRegisterInfo()->getFrameRegister() &&
132 "Not a Frame Pointer, Nor a Spill Slot");
133 assert(MI->getOperand(2).isImm() && "Not an offset");
134 int Offset = MI->getOperand(2).getImm();
135 if (!TII->isValidOffset(Hexagon::LDriw, Offset)) {
136 if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) {
137 BuildMI(*MBB, MII, MI->getDebugLoc(),
138 TII->get(Hexagon::CONST32_Int_Real),
139 HEXAGON_RESERVED_REG_1).addImm(Offset);
140 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr),
141 HEXAGON_RESERVED_REG_1)
143 .addReg(HEXAGON_RESERVED_REG_1);
144 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw),
145 HEXAGON_RESERVED_REG_2)
146 .addReg(HEXAGON_RESERVED_REG_1)
148 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_PdRs),
149 DstReg).addReg(HEXAGON_RESERVED_REG_2);
151 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),
152 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
153 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw),
154 HEXAGON_RESERVED_REG_2)
155 .addReg(HEXAGON_RESERVED_REG_1)
157 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_PdRs),
158 DstReg).addReg(HEXAGON_RESERVED_REG_2);
161 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw),
162 HEXAGON_RESERVED_REG_2).addReg(FP).addImm(Offset);
163 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_PdRs),
164 DstReg).addReg(HEXAGON_RESERVED_REG_2);
166 MII = MBB->erase(MI);
177 //===----------------------------------------------------------------------===//
178 // Public Constructor Functions
179 //===----------------------------------------------------------------------===//
181 FunctionPass *llvm::createHexagonExpandPredSpillCode(HexagonTargetMachine &TM) {
182 return new HexagonExpandPredSpillCode(TM);