1 //===--- HexagonExpandPredSpillCode.cpp - Expand Predicate Spill Code ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===////
9 // The Hexagon processor has no instructions that load or store predicate
10 // registers directly. So, when these registers must be spilled a general
11 // purpose register must be found and the value copied to/from it from/to
12 // the predicate register. This code currently does not use the register
13 // scavenger mechanism available in the allocator. There are two registers
14 // reserved to allow spilling/restoring predicate registers. One is used to
15 // hold the predicate value. The other is used when stack frame offsets are
18 //===----------------------------------------------------------------------===//
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/LatencyPriorityQueue.h"
23 #include "llvm/CodeGen/SchedulerRegistry.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineLoopInfo.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "HexagonTargetMachine.h"
38 #include "HexagonSubtarget.h"
39 #include "HexagonMachineFunctionInfo.h"
43 #include "llvm/Support/CommandLine.h"
51 class HexagonExpandPredSpillCode : public MachineFunctionPass {
52 HexagonTargetMachine& QTM;
53 const HexagonSubtarget &QST;
57 HexagonExpandPredSpillCode(HexagonTargetMachine& TM) :
58 MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {}
60 const char *getPassName() const {
61 return "Hexagon Expand Predicate Spill Code";
63 bool runOnMachineFunction(MachineFunction &Fn);
67 char HexagonExpandPredSpillCode::ID = 0;
70 bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
72 const HexagonInstrInfo *TII = QTM.getInstrInfo();
73 const HexagonRegisterInfo *RegInfo = QTM.getRegisterInfo();
75 // Loop over all of the basic blocks.
76 for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
77 MBBb != MBBe; ++MBBb) {
78 MachineBasicBlock* MBB = MBBb;
79 // Traverse the basic block.
80 for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
82 MachineInstr *MI = MII;
83 int Opc = MI->getOpcode();
84 if (Opc == Hexagon::STriw_pred) {
85 // STriw_pred [R30], ofst, SrcReg;
86 unsigned FP = MI->getOperand(0).getReg();
87 assert(FP == RegInfo->getFrameRegister() &&
88 "Not a Frame Pointer, Nor a Spill Slot");
89 assert(MI->getOperand(1).isImm() && "Not an offset");
90 int Offset = MI->getOperand(1).getImm();
91 int SrcReg = MI->getOperand(2).getReg();
92 assert(Hexagon::PredRegsRegClass.contains(SrcReg) &&
93 "Not a predicate register");
94 if (!TII->isValidOffset(Hexagon::STriw, Offset)) {
95 if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) {
96 BuildMI(*MBB, MII, MI->getDebugLoc(),
97 TII->get(Hexagon::CONST32_Int_Real),
98 HEXAGON_RESERVED_REG_1).addImm(Offset);
99 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr),
100 HEXAGON_RESERVED_REG_1)
101 .addReg(FP).addReg(HEXAGON_RESERVED_REG_1);
102 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
103 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
104 BuildMI(*MBB, MII, MI->getDebugLoc(),
105 TII->get(Hexagon::STriw))
106 .addReg(HEXAGON_RESERVED_REG_1)
107 .addImm(0).addReg(HEXAGON_RESERVED_REG_2);
109 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),
110 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
111 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
112 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
113 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::STriw))
114 .addReg(HEXAGON_RESERVED_REG_1)
116 .addReg(HEXAGON_RESERVED_REG_2);
119 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
120 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
121 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::STriw)).
122 addReg(FP).addImm(Offset).addReg(HEXAGON_RESERVED_REG_2);
124 MII = MBB->erase(MI);
126 } else if (Opc == Hexagon::LDriw_pred) {
127 // DstReg = LDriw_pred [R30], ofst.
128 int DstReg = MI->getOperand(0).getReg();
129 assert(Hexagon::PredRegsRegClass.contains(DstReg) &&
130 "Not a predicate register");
131 unsigned FP = MI->getOperand(1).getReg();
132 assert(FP == RegInfo->getFrameRegister() &&
133 "Not a Frame Pointer, Nor a Spill Slot");
134 assert(MI->getOperand(2).isImm() && "Not an offset");
135 int Offset = MI->getOperand(2).getImm();
136 if (!TII->isValidOffset(Hexagon::LDriw, Offset)) {
137 if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) {
138 BuildMI(*MBB, MII, MI->getDebugLoc(),
139 TII->get(Hexagon::CONST32_Int_Real),
140 HEXAGON_RESERVED_REG_1).addImm(Offset);
141 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr),
142 HEXAGON_RESERVED_REG_1)
144 .addReg(HEXAGON_RESERVED_REG_1);
145 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw),
146 HEXAGON_RESERVED_REG_2)
147 .addReg(HEXAGON_RESERVED_REG_1)
149 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_PdRs),
150 DstReg).addReg(HEXAGON_RESERVED_REG_2);
152 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),
153 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
154 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw),
155 HEXAGON_RESERVED_REG_2)
156 .addReg(HEXAGON_RESERVED_REG_1)
158 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_PdRs),
159 DstReg).addReg(HEXAGON_RESERVED_REG_2);
162 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw),
163 HEXAGON_RESERVED_REG_2).addReg(FP).addImm(Offset);
164 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_PdRs),
165 DstReg).addReg(HEXAGON_RESERVED_REG_2);
167 MII = MBB->erase(MI);
178 //===----------------------------------------------------------------------===//
179 // Public Constructor Functions
180 //===----------------------------------------------------------------------===//
182 FunctionPass *llvm::createHexagonExpandPredSpillCode(HexagonTargetMachine &TM) {
183 return new HexagonExpandPredSpillCode(TM);