1 //===-- HexagonFrameLowering.cpp - Define frame lowering ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "HexagonFrameLowering.h"
13 #include "HexagonInstrInfo.h"
14 #include "HexagonMachineFunctionInfo.h"
15 #include "HexagonRegisterInfo.h"
16 #include "HexagonSubtarget.h"
17 #include "HexagonTargetMachine.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/AsmPrinter.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/RegisterScavenging.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MachineLocation.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetOptions.h"
39 static cl::opt<bool> DisableDeallocRet(
40 "disable-hexagon-dealloc-ret",
42 cl::desc("Disable Dealloc Return for Hexagon target"));
44 /// determineFrameLayout - Determine the size of the frame and maximum call
46 void HexagonFrameLowering::determineFrameLayout(MachineFunction &MF) const {
47 MachineFrameInfo *MFI = MF.getFrameInfo();
49 // Get the number of bytes to allocate from the FrameInfo.
50 unsigned FrameSize = MFI->getStackSize();
52 // Get the alignments provided by the target.
53 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
54 // Get the maximum call frame size of all the calls.
55 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
57 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
58 // that allocations will be aligned.
59 if (MFI->hasVarSizedObjects())
60 maxCallFrameSize = RoundUpToAlignment(maxCallFrameSize, TargetAlign);
62 // Update maximum call frame size.
63 MFI->setMaxCallFrameSize(maxCallFrameSize);
65 // Include call frame size in total.
66 FrameSize += maxCallFrameSize;
68 // Make sure the frame is aligned.
69 FrameSize = RoundUpToAlignment(FrameSize, TargetAlign);
72 MFI->setStackSize(FrameSize);
76 void HexagonFrameLowering::emitPrologue(MachineFunction &MF) const {
77 MachineBasicBlock &MBB = MF.front();
78 MachineFrameInfo *MFI = MF.getFrameInfo();
79 MachineModuleInfo &MMI = MF.getMMI();
80 MachineBasicBlock::iterator MBBI = MBB.begin();
81 const HexagonRegisterInfo *QRI =
82 static_cast<const HexagonRegisterInfo *>(MF.getTarget().getRegisterInfo());
83 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
84 determineFrameLayout(MF);
86 // Check if frame moves are needed for EH.
87 bool needsFrameMoves = MMI.hasDebugInfo() ||
88 !MF.getFunction()->needsUnwindTableEntry();
90 // Get the number of bytes to allocate from the FrameInfo.
91 int NumBytes = (int) MFI->getStackSize();
93 // LLVM expects allocframe not to be the first instruction in the
95 MachineBasicBlock::iterator InsertPt = MBB.begin();
98 // ALLOCA adjust regs. Iterate over ADJDYNALLOC nodes and change the offset.
100 HexagonMachineFunctionInfo *FuncInfo =
101 MF.getInfo<HexagonMachineFunctionInfo>();
102 const std::vector<MachineInstr*>& AdjustRegs =
103 FuncInfo->getAllocaAdjustInsts();
104 for (std::vector<MachineInstr*>::const_iterator i = AdjustRegs.begin(),
105 e = AdjustRegs.end();
107 MachineInstr* MI = *i;
108 assert((MI->getOpcode() == Hexagon::ADJDYNALLOC) &&
109 "Expected adjust alloca node");
111 MachineOperand& MO = MI->getOperand(2);
112 assert(MO.isImm() && "Expected immediate");
113 MO.setImm(MFI->getMaxCallFrameSize());
116 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
118 if (needsFrameMoves) {
119 // Advance CFA. DW_CFA_def_cfa
120 unsigned FPReg = QRI->getFrameRegister();
121 unsigned RAReg = QRI->getRARegister();
123 MachineLocation Dst(MachineLocation::VirtualFP);
124 MachineLocation Src(FPReg, -8);
125 Moves.push_back(MachineMove(0, Dst, Src));
128 MachineLocation LRDst(RAReg, -4);
129 MachineLocation LRSrc(RAReg);
130 Moves.push_back(MachineMove(0, LRDst, LRSrc));
133 MachineLocation SPDst(FPReg, -8);
134 MachineLocation SPSrc(FPReg);
135 Moves.push_back(MachineMove(0, SPDst, SPSrc));
139 // Only insert ALLOCFRAME if we need to.
142 // Check for overflow.
143 // Hexagon_TODO: Ugh! hardcoding. Is there an API that can be used?
144 const int ALLOCFRAME_MAX = 16384;
145 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
147 if (NumBytes >= ALLOCFRAME_MAX) {
148 // Emit allocframe(#0).
149 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(0);
151 // Subtract offset from frame pointer.
152 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::CONST32_Int_Real),
153 HEXAGON_RESERVED_REG_1).addImm(NumBytes);
154 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::SUB_rr),
155 QRI->getStackRegister()).
156 addReg(QRI->getStackRegister()).
157 addReg(HEXAGON_RESERVED_REG_1);
159 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(NumBytes);
163 // Returns true if MBB has a machine instructions that indicates a tail call
165 bool HexagonFrameLowering::hasTailCall(MachineBasicBlock &MBB) const {
166 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
167 unsigned RetOpcode = MBBI->getOpcode();
169 return RetOpcode == Hexagon::TCRETURNtg || RetOpcode == Hexagon::TCRETURNtext;
172 void HexagonFrameLowering::emitEpilogue(MachineFunction &MF,
173 MachineBasicBlock &MBB) const {
174 MachineBasicBlock::iterator MBBI = prior(MBB.end());
175 DebugLoc dl = MBBI->getDebugLoc();
177 // Only insert deallocframe if we need to. Also at -O0. See comment
178 // in emitPrologue above.
180 if (hasFP(MF) || MF.getTarget().getOptLevel() == CodeGenOpt::None) {
181 MachineBasicBlock::iterator MBBI = prior(MBB.end());
182 MachineBasicBlock::iterator MBBI_end = MBB.end();
184 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
186 if (MBBI->getOpcode() == Hexagon::EH_RETURN_JMPR) {
187 assert(MBBI->getOperand(0).isReg() && "Offset should be in register!");
188 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME));
189 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::ADD_rr),
190 Hexagon::R29).addReg(Hexagon::R29).addReg(Hexagon::R28);
193 // Replace 'jumpr r31' instruction with dealloc_return for V4 and higher
195 if (STI.hasV4TOps() && MBBI->getOpcode() == Hexagon::JMPret
196 && !DisableDeallocRet) {
197 // Check for RESTORE_DEALLOC_RET_JMP_V4 call. Don't emit an extra DEALLOC
198 // instruction if we encounter it.
199 MachineBasicBlock::iterator BeforeJMPR =
200 MBB.begin() == MBBI ? MBBI : prior(MBBI);
201 if (BeforeJMPR != MBBI &&
202 BeforeJMPR->getOpcode() == Hexagon::RESTORE_DEALLOC_RET_JMP_V4) {
203 // Remove the JMPR node.
208 // Add dealloc_return.
209 MachineInstrBuilder MIB =
210 BuildMI(MBB, MBBI_end, dl, TII.get(Hexagon::DEALLOC_RET_V4));
211 // Transfer the function live-out registers.
212 MIB->copyImplicitOps(*MBB.getParent(), &*MBBI);
213 // Remove the JUMPR node.
215 } else { // Add deallocframe for V2 and V3, and V4 tail calls.
216 // Check for RESTORE_DEALLOC_BEFORE_TAILCALL_V4. We don't need an extra
217 // DEALLOCFRAME instruction after it.
218 MachineBasicBlock::iterator Term = MBB.getFirstTerminator();
219 MachineBasicBlock::iterator I =
220 Term == MBB.begin() ? MBB.end() : prior(Term);
221 if (I != MBB.end() &&
222 I->getOpcode() == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4)
225 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME));
230 bool HexagonFrameLowering::hasFP(const MachineFunction &MF) const {
231 const MachineFrameInfo *MFI = MF.getFrameInfo();
232 const HexagonMachineFunctionInfo *FuncInfo =
233 MF.getInfo<HexagonMachineFunctionInfo>();
234 return (MFI->hasCalls() || (MFI->getStackSize() > 0) ||
235 FuncInfo->hasClobberLR() );
239 unsigned uniqueSuperReg(unsigned Reg, const TargetRegisterInfo *TRI) {
240 MCSuperRegIterator SRI(Reg, TRI);
241 assert(SRI.isValid() && "Expected a superreg");
242 unsigned SuperReg = *SRI;
244 assert(!SRI.isValid() && "Expected exactly one superreg");
249 HexagonFrameLowering::spillCalleeSavedRegisters(
250 MachineBasicBlock &MBB,
251 MachineBasicBlock::iterator MI,
252 const std::vector<CalleeSavedInfo> &CSI,
253 const TargetRegisterInfo *TRI) const {
254 MachineFunction *MF = MBB.getParent();
255 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
261 // We can only schedule double loads if we spill contiguous callee-saved regs
262 // For instance, we cannot scheduled double-word loads if we spill r24,
264 // Hexagon_TODO: We can try to double-word align odd registers for -O2 and
266 bool ContiguousRegs = true;
268 for (unsigned i = 0; i < CSI.size(); ++i) {
269 unsigned Reg = CSI[i].getReg();
272 // Check if we can use a double-word store.
274 unsigned SuperReg = uniqueSuperReg(Reg, TRI);
275 bool CanUseDblStore = false;
276 const TargetRegisterClass* SuperRegClass = 0;
278 if (ContiguousRegs && (i < CSI.size()-1)) {
279 unsigned SuperRegNext = uniqueSuperReg(CSI[i+1].getReg(), TRI);
280 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg);
281 CanUseDblStore = (SuperRegNext == SuperReg);
285 if (CanUseDblStore) {
286 TII.storeRegToStackSlot(MBB, MI, SuperReg, true,
287 CSI[i+1].getFrameIdx(), SuperRegClass, TRI);
288 MBB.addLiveIn(SuperReg);
291 // Cannot use a double-word store.
292 ContiguousRegs = false;
293 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
294 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), RC,
303 bool HexagonFrameLowering::restoreCalleeSavedRegisters(
304 MachineBasicBlock &MBB,
305 MachineBasicBlock::iterator MI,
306 const std::vector<CalleeSavedInfo> &CSI,
307 const TargetRegisterInfo *TRI) const {
309 MachineFunction *MF = MBB.getParent();
310 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
316 // We can only schedule double loads if we spill contiguous callee-saved regs
317 // For instance, we cannot scheduled double-word loads if we spill r24,
319 // Hexagon_TODO: We can try to double-word align odd registers for -O2 and
321 bool ContiguousRegs = true;
323 for (unsigned i = 0; i < CSI.size(); ++i) {
324 unsigned Reg = CSI[i].getReg();
327 // Check if we can use a double-word load.
329 unsigned SuperReg = uniqueSuperReg(Reg, TRI);
330 const TargetRegisterClass* SuperRegClass = 0;
331 bool CanUseDblLoad = false;
332 if (ContiguousRegs && (i < CSI.size()-1)) {
333 unsigned SuperRegNext = uniqueSuperReg(CSI[i+1].getReg(), TRI);
334 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg);
335 CanUseDblLoad = (SuperRegNext == SuperReg);
340 TII.loadRegFromStackSlot(MBB, MI, SuperReg, CSI[i+1].getFrameIdx(),
342 MBB.addLiveIn(SuperReg);
345 // Cannot use a double-word load.
346 ContiguousRegs = false;
347 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
348 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
355 void HexagonFrameLowering::
356 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
357 MachineBasicBlock::iterator I) const {
358 MachineInstr &MI = *I;
360 if (MI.getOpcode() == Hexagon::ADJCALLSTACKDOWN) {
361 // Hexagon_TODO: add code
362 } else if (MI.getOpcode() == Hexagon::ADJCALLSTACKUP) {
363 // Hexagon_TODO: add code
365 llvm_unreachable("Cannot handle this call frame pseudo instruction");
370 int HexagonFrameLowering::getFrameIndexOffset(const MachineFunction &MF,
372 return MF.getFrameInfo()->getObjectOffset(FI);