1 //===--- HexagonGenExtract.cpp --------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/ADT/STLExtras.h"
11 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
12 #include "llvm/IR/Constants.h"
13 #include "llvm/IR/Dominators.h"
14 #include "llvm/IR/Function.h"
15 #include "llvm/IR/Instructions.h"
16 #include "llvm/IR/IntrinsicInst.h"
17 #include "llvm/IR/IRBuilder.h"
18 #include "llvm/IR/PatternMatch.h"
19 #include "llvm/Pass.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/raw_ostream.h"
27 static cl::opt<unsigned> ExtractCutoff("extract-cutoff", cl::init(~0U),
28 cl::Hidden, cl::desc("Cutoff for generating \"extract\""
31 // This prevents generating extract instructions that have the offset of 0.
32 // One of the reasons for "extract" is to put a sequence of bits in a regis-
33 // ter, starting at offset 0 (so that these bits can then be used by an
34 // "insert"). If the bits are already at offset 0, it is better not to gene-
35 // rate "extract", since logical bit operations can be merged into compound
36 // instructions (as opposed to "extract").
37 static cl::opt<bool> NoSR0("extract-nosr0", cl::init(true), cl::Hidden,
38 cl::desc("No extract instruction with offset 0"));
40 static cl::opt<bool> NeedAnd("extract-needand", cl::init(true), cl::Hidden,
41 cl::desc("Require & in extract patterns"));
44 void initializeHexagonGenExtractPass(PassRegistry&);
45 FunctionPass *createHexagonGenExtract();
50 class HexagonGenExtract : public FunctionPass {
53 HexagonGenExtract() : FunctionPass(ID), ExtractCount(0) {
54 initializeHexagonGenExtractPass(*PassRegistry::getPassRegistry());
56 virtual const char *getPassName() const override {
57 return "Hexagon generate \"extract\" instructions";
59 virtual bool runOnFunction(Function &F) override;
60 virtual void getAnalysisUsage(AnalysisUsage &AU) const override {
61 AU.addRequired<DominatorTreeWrapperPass>();
62 AU.addPreserved<DominatorTreeWrapperPass>();
63 AU.addPreserved<MachineFunctionAnalysis>();
64 FunctionPass::getAnalysisUsage(AU);
67 bool visitBlock(BasicBlock *B);
68 bool convert(Instruction *In);
70 unsigned ExtractCount;
74 char HexagonGenExtract::ID = 0;
77 INITIALIZE_PASS_BEGIN(HexagonGenExtract, "hextract", "Hexagon generate "
78 "\"extract\" instructions", false, false)
79 INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
80 INITIALIZE_PASS_END(HexagonGenExtract, "hextract", "Hexagon generate "
81 "\"extract\" instructions", false, false)
84 bool HexagonGenExtract::convert(Instruction *In) {
85 using namespace PatternMatch;
87 ConstantInt *CSL = 0, *CSR = 0, *CM = 0;
88 BasicBlock *BB = In->getParent();
89 LLVMContext &Ctx = BB->getContext();
92 // (and (shl (lshr x, #sr), #sl), #m)
94 bool Match = match(In, m_And(m_Shl(m_LShr(m_Value(BF), m_ConstantInt(CSR)),
99 // (and (shl (ashr x, #sr), #sl), #m)
101 Match = match(In, m_And(m_Shl(m_AShr(m_Value(BF), m_ConstantInt(CSR)),
106 // (and (shl x, #sl), #m)
108 CSR = ConstantInt::get(Type::getInt32Ty(Ctx), 0);
109 Match = match(In, m_And(m_Shl(m_Value(BF), m_ConstantInt(CSL)),
115 // (and (lshr x, #sr), #m)
117 CSL = ConstantInt::get(Type::getInt32Ty(Ctx), 0);
118 Match = match(In, m_And(m_LShr(m_Value(BF), m_ConstantInt(CSR)),
122 // (and (ashr x, #sr), #m)
124 CSL = ConstantInt::get(Type::getInt32Ty(Ctx), 0);
125 Match = match(In, m_And(m_AShr(m_Value(BF), m_ConstantInt(CSR)),
130 // (shl (lshr x, #sr), #sl)
132 Match = match(In, m_Shl(m_LShr(m_Value(BF), m_ConstantInt(CSR)),
133 m_ConstantInt(CSL)));
137 // (shl (ashr x, #sr), #sl)
139 Match = match(In, m_Shl(m_AShr(m_Value(BF), m_ConstantInt(CSR)),
140 m_ConstantInt(CSL)));
145 Type *Ty = BF->getType();
146 if (!Ty->isIntegerTy())
148 unsigned BW = Ty->getPrimitiveSizeInBits();
149 if (BW != 32 && BW != 64)
152 uint32_t SR = CSR->getZExtValue();
153 uint32_t SL = CSL->getZExtValue();
156 // If there was no and, and the shift left did not remove all potential
157 // sign bits created by the shift right, then extractu cannot reproduce
159 if (!LogicalSR && (SR > SL))
161 APInt A = APInt(BW, ~0ULL).lshr(SR).shl(SL);
162 CM = ConstantInt::get(Ctx, A);
165 // CM is the shifted-left mask. Shift it back right to remove the zero
166 // bits on least-significant positions.
167 APInt M = CM->getValue().lshr(SL);
168 uint32_t T = M.countTrailingOnes();
170 // During the shifts some of the bits will be lost. Calculate how many
171 // of the original value will remain after shift right and then left.
172 uint32_t U = BW - std::max(SL, SR);
173 // The width of the extracted field is the minimum of the original bits
174 // that remain after the shifts and the number of contiguous 1s in the mask.
175 uint32_t W = std::min(U, T);
179 // Check if the extracted bits are contained within the mask that it is
180 // and-ed with. The extract operation will copy these bits, and so the
181 // mask cannot any holes in it that would clear any of the bits of the
184 // If the shift right was arithmetic, it could have included some 1 bits.
185 // It is still ok to generate extract, but only if the mask eliminates
186 // those bits (i.e. M does not have any bits set beyond U).
187 APInt C = APInt::getHighBitsSet(BW, BW-U);
188 if (M.intersects(C) || !APIntOps::isMask(W, M))
191 // Check if M starts with a contiguous sequence of W times 1 bits. Get
192 // the low U bits of M (which eliminates the 0 bits shifted in on the
193 // left), and check if the result is APInt's "mask":
194 if (!APIntOps::isMask(W, M.getLoBits(U)))
199 Intrinsic::ID IntId = (BW == 32) ? Intrinsic::hexagon_S2_extractu
200 : Intrinsic::hexagon_S2_extractup;
201 Module *Mod = BB->getParent()->getParent();
202 Value *ExtF = Intrinsic::getDeclaration(Mod, IntId);
203 Value *NewIn = IRB.CreateCall(ExtF, {BF, IRB.getInt32(W), IRB.getInt32(SR)});
205 NewIn = IRB.CreateShl(NewIn, SL, CSL->getName());
206 In->replaceAllUsesWith(NewIn);
211 bool HexagonGenExtract::visitBlock(BasicBlock *B) {
212 // Depth-first, bottom-up traversal.
213 DomTreeNode *DTN = DT->getNode(B);
214 typedef GraphTraits<DomTreeNode*> GTN;
215 typedef GTN::ChildIteratorType Iter;
216 for (Iter I = GTN::child_begin(DTN), E = GTN::child_end(DTN); I != E; ++I)
217 visitBlock((*I)->getBlock());
219 // Allow limiting the number of generated extracts for debugging purposes.
220 bool HasCutoff = ExtractCutoff.getPosition();
221 unsigned Cutoff = ExtractCutoff;
223 bool Changed = false;
224 BasicBlock::iterator I = std::prev(B->end()), NextI, Begin = B->begin();
226 if (HasCutoff && (ExtractCount >= Cutoff))
228 bool Last = (I == Begin);
230 NextI = std::prev(I);
231 Instruction *In = &*I;
232 bool Done = convert(In);
233 if (HasCutoff && Done)
244 bool HexagonGenExtract::runOnFunction(Function &F) {
245 DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
248 // Traverse the function bottom-up, to see super-expressions before their
250 BasicBlock *Entry = GraphTraits<Function*>::getEntryNode(&F);
251 Changed = visitBlock(Entry);
257 FunctionPass *llvm::createHexagonGenExtract() {
258 return new HexagonGenExtract();