1 //===-- HexagonHardwareLoops.cpp - Identify and generate hardware loops ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass identifies loops where we can generate the Hexagon hardware
11 // loop instruction. The hardware loop can perform loop branches with a
12 // zero-cycle overhead.
14 // The pattern that defines the induction variable can changed depending on
15 // prior optimizations. For example, the IndVarSimplify phase run by 'opt'
16 // normalizes induction variables, and the Loop Strength Reduction pass
17 // run by 'llc' may also make changes to the induction variable.
18 // The pattern detected by this phase is due to running Strength Reduction.
20 // Criteria for hardware loops:
21 // - Countable loops (w/ ind. var for a trip count)
22 // - Assumes loops are normalized by IndVarSimplify
23 // - Try inner-most loops first
24 // - No nested hardware loops.
25 // - No function calls in loops.
27 //===----------------------------------------------------------------------===//
29 #include "llvm/ADT/SmallSet.h"
31 #include "HexagonTargetMachine.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/CodeGen/MachineDominators.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineFunctionPass.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineLoopInfo.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/PassSupport.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/raw_ostream.h"
43 #include "llvm/Target/TargetInstrInfo.h"
49 #define DEBUG_TYPE "hwloops"
52 static cl::opt<int> HWLoopLimit("max-hwloop", cl::Hidden, cl::init(-1));
55 STATISTIC(NumHWLoops, "Number of loops converted to hardware loops");
58 void initializeHexagonHardwareLoopsPass(PassRegistry&);
63 struct HexagonHardwareLoops : public MachineFunctionPass {
65 MachineRegisterInfo *MRI;
66 MachineDominatorTree *MDT;
67 const HexagonTargetMachine *TM;
68 const HexagonInstrInfo *TII;
69 const HexagonRegisterInfo *TRI;
77 HexagonHardwareLoops() : MachineFunctionPass(ID) {
78 initializeHexagonHardwareLoopsPass(*PassRegistry::getPassRegistry());
81 virtual bool runOnMachineFunction(MachineFunction &MF);
83 const char *getPassName() const { return "Hexagon Hardware Loops"; }
85 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
86 AU.addRequired<MachineDominatorTree>();
87 AU.addRequired<MachineLoopInfo>();
88 MachineFunctionPass::getAnalysisUsage(AU);
92 /// Kinds of comparisons in the compare instructions.
97 L = 0x04, // Less-than property.
98 G = 0x08, // Greater-than property.
99 U = 0x40, // Unsigned property.
110 static Kind getSwappedComparison(Kind Cmp) {
111 assert ((!((Cmp & L) && (Cmp & G))) && "Malformed comparison operator");
112 if ((Cmp & L) || (Cmp & G))
113 return (Kind)(Cmp ^ (L|G));
118 /// \brief Find the register that contains the loop controlling
119 /// induction variable.
120 /// If successful, it will return true and set the \p Reg, \p IVBump
121 /// and \p IVOp arguments. Otherwise it will return false.
122 /// The returned induction register is the register R that follows the
123 /// following induction pattern:
125 /// R = phi ..., [ R.next, LatchBlock ]
126 /// R.next = R + #bump
127 /// if (R.next < #N) goto loop
128 /// IVBump is the immediate value added to R, and IVOp is the instruction
129 /// "R.next = R + #bump".
130 bool findInductionRegister(MachineLoop *L, unsigned &Reg,
131 int64_t &IVBump, MachineInstr *&IVOp) const;
133 /// \brief Analyze the statements in a loop to determine if the loop
134 /// has a computable trip count and, if so, return a value that represents
135 /// the trip count expression.
136 CountValue *getLoopTripCount(MachineLoop *L,
137 SmallVectorImpl<MachineInstr *> &OldInsts);
139 /// \brief Return the expression that represents the number of times
140 /// a loop iterates. The function takes the operands that represent the
141 /// loop start value, loop end value, and induction value. Based upon
142 /// these operands, the function attempts to compute the trip count.
143 /// If the trip count is not directly available (as an immediate value,
144 /// or a register), the function will attempt to insert computation of it
145 /// to the loop's preheader.
146 CountValue *computeCount(MachineLoop *Loop,
147 const MachineOperand *Start,
148 const MachineOperand *End,
151 Comparison::Kind Cmp) const;
153 /// \brief Return true if the instruction is not valid within a hardware
155 bool isInvalidLoopOperation(const MachineInstr *MI) const;
157 /// \brief Return true if the loop contains an instruction that inhibits
158 /// using the hardware loop.
159 bool containsInvalidInstruction(MachineLoop *L) const;
161 /// \brief Given a loop, check if we can convert it to a hardware loop.
162 /// If so, then perform the conversion and return true.
163 bool convertToHardwareLoop(MachineLoop *L);
165 /// \brief Return true if the instruction is now dead.
166 bool isDead(const MachineInstr *MI,
167 SmallVectorImpl<MachineInstr *> &DeadPhis) const;
169 /// \brief Remove the instruction if it is now dead.
170 void removeIfDead(MachineInstr *MI);
172 /// \brief Make sure that the "bump" instruction executes before the
173 /// compare. We need that for the IV fixup, so that the compare
174 /// instruction would not use a bumped value that has not yet been
175 /// defined. If the instructions are out of order, try to reorder them.
176 bool orderBumpCompare(MachineInstr *BumpI, MachineInstr *CmpI);
178 /// \brief Get the instruction that loads an immediate value into \p R,
179 /// or 0 if such an instruction does not exist.
180 MachineInstr *defWithImmediate(unsigned R);
182 /// \brief Get the immediate value referenced to by \p MO, either for
183 /// immediate operands, or for register operands, where the register
184 /// was defined with an immediate value.
185 int64_t getImmediate(MachineOperand &MO);
187 /// \brief Reset the given machine operand to now refer to a new immediate
188 /// value. Assumes that the operand was already referencing an immediate
189 /// value, either directly, or via a register.
190 void setImmediate(MachineOperand &MO, int64_t Val);
192 /// \brief Fix the data flow of the induction varible.
193 /// The desired flow is: phi ---> bump -+-> comparison-in-latch.
196 /// where "bump" is the increment of the induction variable:
197 /// iv = iv + #const.
198 /// Due to some prior code transformations, the actual flow may look
200 /// phi -+-> bump ---> back to phi
202 /// +-> comparison-in-latch (against upper_bound-bump),
203 /// i.e. the comparison that controls the loop execution may be using
204 /// the value of the induction variable from before the increment.
206 /// Return true if the loop's flow is the desired one (i.e. it's
207 /// either been fixed, or no fixing was necessary).
208 /// Otherwise, return false. This can happen if the induction variable
209 /// couldn't be identified, or if the value in the latch's comparison
210 /// cannot be adjusted to reflect the post-bump value.
211 bool fixupInductionVariable(MachineLoop *L);
213 /// \brief Given a loop, if it does not have a preheader, create one.
214 /// Return the block that is the preheader.
215 MachineBasicBlock *createPreheaderForLoop(MachineLoop *L);
218 char HexagonHardwareLoops::ID = 0;
220 int HexagonHardwareLoops::Counter = 0;
223 /// \brief Abstraction for a trip count of a loop. A smaller vesrsion
224 /// of the MachineOperand class without the concerns of changing the
225 /// operand representation.
228 enum CountValueType {
243 explicit CountValue(CountValueType t, unsigned v, unsigned u = 0) {
245 if (Kind == CV_Register) {
252 bool isReg() const { return Kind == CV_Register; }
253 bool isImm() const { return Kind == CV_Immediate; }
255 unsigned getReg() const {
256 assert(isReg() && "Wrong CountValue accessor");
257 return Contents.R.Reg;
259 unsigned getSubReg() const {
260 assert(isReg() && "Wrong CountValue accessor");
261 return Contents.R.Sub;
263 unsigned getImm() const {
264 assert(isImm() && "Wrong CountValue accessor");
265 return Contents.ImmVal;
268 void print(raw_ostream &OS, const TargetMachine *TM = 0) const {
269 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
270 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }
271 if (isImm()) { OS << Contents.ImmVal; }
274 } // end anonymous namespace
277 INITIALIZE_PASS_BEGIN(HexagonHardwareLoops, "hwloops",
278 "Hexagon Hardware Loops", false, false)
279 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
280 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
281 INITIALIZE_PASS_END(HexagonHardwareLoops, "hwloops",
282 "Hexagon Hardware Loops", false, false)
285 /// \brief Returns true if the instruction is a hardware loop instruction.
286 static bool isHardwareLoop(const MachineInstr *MI) {
287 return MI->getOpcode() == Hexagon::LOOP0_r ||
288 MI->getOpcode() == Hexagon::LOOP0_i;
291 FunctionPass *llvm::createHexagonHardwareLoops() {
292 return new HexagonHardwareLoops();
296 bool HexagonHardwareLoops::runOnMachineFunction(MachineFunction &MF) {
297 DEBUG(dbgs() << "********* Hexagon Hardware Loops *********\n");
299 bool Changed = false;
301 MLI = &getAnalysis<MachineLoopInfo>();
302 MRI = &MF.getRegInfo();
303 MDT = &getAnalysis<MachineDominatorTree>();
304 TM = static_cast<const HexagonTargetMachine*>(&MF.getTarget());
305 TII = static_cast<const HexagonInstrInfo*>(TM->getInstrInfo());
306 TRI = static_cast<const HexagonRegisterInfo*>(TM->getRegisterInfo());
308 for (MachineLoopInfo::iterator I = MLI->begin(), E = MLI->end();
311 if (!L->getParentLoop())
312 Changed |= convertToHardwareLoop(L);
319 bool HexagonHardwareLoops::findInductionRegister(MachineLoop *L,
324 MachineBasicBlock *Header = L->getHeader();
325 MachineBasicBlock *Preheader = L->getLoopPreheader();
326 MachineBasicBlock *Latch = L->getLoopLatch();
327 if (!Header || !Preheader || !Latch)
330 // This pair represents an induction register together with an immediate
331 // value that will be added to it in each loop iteration.
332 typedef std::pair<unsigned,int64_t> RegisterBump;
334 // Mapping: R.next -> (R, bump), where R, R.next and bump are derived
335 // from an induction operation
337 // where bump is an immediate value.
338 typedef std::map<unsigned,RegisterBump> InductionMap;
342 typedef MachineBasicBlock::instr_iterator instr_iterator;
343 for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
344 I != E && I->isPHI(); ++I) {
345 MachineInstr *Phi = &*I;
347 // Have a PHI instruction. Get the operand that corresponds to the
348 // latch block, and see if is a result of an addition of form "reg+imm",
349 // where the "reg" is defined by the PHI node we are looking at.
350 for (unsigned i = 1, n = Phi->getNumOperands(); i < n; i += 2) {
351 if (Phi->getOperand(i+1).getMBB() != Latch)
354 unsigned PhiOpReg = Phi->getOperand(i).getReg();
355 MachineInstr *DI = MRI->getVRegDef(PhiOpReg);
356 unsigned UpdOpc = DI->getOpcode();
357 bool isAdd = (UpdOpc == Hexagon::ADD_ri);
360 // If the register operand to the add is the PHI we're
361 // looking at, this meets the induction pattern.
362 unsigned IndReg = DI->getOperand(1).getReg();
363 if (MRI->getVRegDef(IndReg) == Phi) {
364 unsigned UpdReg = DI->getOperand(0).getReg();
365 int64_t V = DI->getOperand(2).getImm();
366 IndMap.insert(std::make_pair(UpdReg, std::make_pair(IndReg, V)));
372 SmallVector<MachineOperand,2> Cond;
373 MachineBasicBlock *TB = 0, *FB = 0;
374 bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false);
378 unsigned CSz = Cond.size();
379 assert (CSz == 1 || CSz == 2);
380 unsigned PredR = Cond[CSz-1].getReg();
382 MachineInstr *PredI = MRI->getVRegDef(PredR);
383 if (!PredI->isCompare())
386 unsigned CmpReg1 = 0, CmpReg2 = 0;
387 int CmpImm = 0, CmpMask = 0;
388 bool CmpAnalyzed = TII->analyzeCompare(PredI, CmpReg1, CmpReg2,
390 // Fail if the compare was not analyzed, or it's not comparing a register
391 // with an immediate value. Not checking the mask here, since we handle
392 // the individual compare opcodes (including CMPb) later on.
396 // Exactly one of the input registers to the comparison should be among
397 // the induction registers.
398 InductionMap::iterator IndMapEnd = IndMap.end();
399 InductionMap::iterator F = IndMapEnd;
401 InductionMap::iterator F1 = IndMap.find(CmpReg1);
406 InductionMap::iterator F2 = IndMap.find(CmpReg2);
407 if (F2 != IndMapEnd) {
416 Reg = F->second.first;
417 IVBump = F->second.second;
418 IVOp = MRI->getVRegDef(F->first);
423 /// \brief Analyze the statements in a loop to determine if the loop has
424 /// a computable trip count and, if so, return a value that represents
425 /// the trip count expression.
427 /// This function iterates over the phi nodes in the loop to check for
428 /// induction variable patterns that are used in the calculation for
429 /// the number of time the loop is executed.
430 CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L,
431 SmallVectorImpl<MachineInstr *> &OldInsts) {
432 MachineBasicBlock *TopMBB = L->getTopBlock();
433 MachineBasicBlock::pred_iterator PI = TopMBB->pred_begin();
434 assert(PI != TopMBB->pred_end() &&
435 "Loop must have more than one incoming edge!");
436 MachineBasicBlock *Backedge = *PI++;
437 if (PI == TopMBB->pred_end()) // dead loop?
439 MachineBasicBlock *Incoming = *PI++;
440 if (PI != TopMBB->pred_end()) // multiple backedges?
443 // Make sure there is one incoming and one backedge and determine which
445 if (L->contains(Incoming)) {
446 if (L->contains(Backedge))
448 std::swap(Incoming, Backedge);
449 } else if (!L->contains(Backedge))
452 // Look for the cmp instruction to determine if we can get a useful trip
453 // count. The trip count can be either a register or an immediate. The
454 // location of the value depends upon the type (reg or imm).
455 MachineBasicBlock *Latch = L->getLoopLatch();
462 bool FoundIV = findInductionRegister(L, IVReg, IVBump, IVOp);
466 MachineBasicBlock *Preheader = L->getLoopPreheader();
468 MachineOperand *InitialValue = 0;
469 MachineInstr *IV_Phi = MRI->getVRegDef(IVReg);
470 for (unsigned i = 1, n = IV_Phi->getNumOperands(); i < n; i += 2) {
471 MachineBasicBlock *MBB = IV_Phi->getOperand(i+1).getMBB();
472 if (MBB == Preheader)
473 InitialValue = &IV_Phi->getOperand(i);
474 else if (MBB == Latch)
475 IVReg = IV_Phi->getOperand(i).getReg(); // Want IV reg after bump.
480 SmallVector<MachineOperand,2> Cond;
481 MachineBasicBlock *TB = 0, *FB = 0;
482 bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false);
486 MachineBasicBlock *Header = L->getHeader();
487 // TB must be non-null. If FB is also non-null, one of them must be
488 // the header. Otherwise, branch to TB could be exiting the loop, and
489 // the fall through can go to the header.
490 assert (TB && "Latch block without a branch?");
491 assert ((!FB || TB == Header || FB == Header) && "Branches not to header?");
492 if (!TB || (FB && TB != Header && FB != Header))
495 // Branches of form "if (!P) ..." cause HexagonInstrInfo::AnalyzeBranch
496 // to put imm(0), followed by P in the vector Cond.
497 // If TB is not the header, it means that the "not-taken" path must lead
499 bool Negated = (Cond.size() > 1) ^ (TB != Header);
500 unsigned PredReg = Cond[Cond.size()-1].getReg();
501 MachineInstr *CondI = MRI->getVRegDef(PredReg);
502 unsigned CondOpc = CondI->getOpcode();
504 unsigned CmpReg1 = 0, CmpReg2 = 0;
505 int Mask = 0, ImmValue = 0;
506 bool AnalyzedCmp = TII->analyzeCompare(CondI, CmpReg1, CmpReg2,
511 // The comparison operator type determines how we compute the loop
513 OldInsts.push_back(CondI);
514 OldInsts.push_back(IVOp);
516 // Sadly, the following code gets information based on the position
517 // of the operands in the compare instruction. This has to be done
518 // this way, because the comparisons check for a specific relationship
519 // between the operands (e.g. is-less-than), rather than to find out
520 // what relationship the operands are in (as on PPC).
521 Comparison::Kind Cmp;
522 bool isSwapped = false;
523 const MachineOperand &Op1 = CondI->getOperand(1);
524 const MachineOperand &Op2 = CondI->getOperand(2);
525 const MachineOperand *EndValue = 0;
528 if (Op2.isImm() || Op1.getReg() == IVReg)
540 case Hexagon::CMPEQri:
541 case Hexagon::CMPEQrr:
542 Cmp = !Negated ? Comparison::EQ : Comparison::NE;
544 case Hexagon::CMPGTUri:
545 case Hexagon::CMPGTUrr:
546 Cmp = !Negated ? Comparison::GTu : Comparison::LEu;
548 case Hexagon::CMPGTri:
549 case Hexagon::CMPGTrr:
550 Cmp = !Negated ? Comparison::GTs : Comparison::LEs;
552 // Very limited support for byte/halfword compares.
553 case Hexagon::CMPbEQri_V4:
554 case Hexagon::CMPhEQri_V4: {
559 // Since the comparisons are "ri", the EndValue should be an
560 // immediate. Check it just in case.
561 assert(EndValue->isImm() && "Unrecognized latch comparison");
562 EndV = EndValue->getImm();
563 // Allow InitialValue to be a register defined with an immediate.
564 if (InitialValue->isReg()) {
565 if (!defWithImmediate(InitialValue->getReg()))
567 InitV = getImmediate(*InitialValue);
569 assert(InitialValue->isImm());
570 InitV = InitialValue->getImm();
574 if (CondOpc == Hexagon::CMPbEQri_V4) {
575 if (!isInt<8>(InitV) || !isInt<8>(EndV))
577 } else { // Hexagon::CMPhEQri_V4
578 if (!isInt<16>(InitV) || !isInt<16>(EndV))
581 Cmp = !Negated ? Comparison::EQ : Comparison::NE;
589 Cmp = Comparison::getSwappedComparison(Cmp);
591 if (InitialValue->isReg()) {
592 unsigned R = InitialValue->getReg();
593 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
594 if (!MDT->properlyDominates(DefBB, Header))
596 OldInsts.push_back(MRI->getVRegDef(R));
598 if (EndValue->isReg()) {
599 unsigned R = EndValue->getReg();
600 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
601 if (!MDT->properlyDominates(DefBB, Header))
605 return computeCount(L, InitialValue, EndValue, IVReg, IVBump, Cmp);
608 /// \brief Helper function that returns the expression that represents the
609 /// number of times a loop iterates. The function takes the operands that
610 /// represent the loop start value, loop end value, and induction value.
611 /// Based upon these operands, the function attempts to compute the trip count.
612 CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
613 const MachineOperand *Start,
614 const MachineOperand *End,
617 Comparison::Kind Cmp) const {
618 // Cannot handle comparison EQ, i.e. while (A == B).
619 if (Cmp == Comparison::EQ)
622 // Check if either the start or end values are an assignment of an immediate.
623 // If so, use the immediate value rather than the register.
624 if (Start->isReg()) {
625 const MachineInstr *StartValInstr = MRI->getVRegDef(Start->getReg());
626 if (StartValInstr && StartValInstr->getOpcode() == Hexagon::TFRI)
627 Start = &StartValInstr->getOperand(1);
630 const MachineInstr *EndValInstr = MRI->getVRegDef(End->getReg());
631 if (EndValInstr && EndValInstr->getOpcode() == Hexagon::TFRI)
632 End = &EndValInstr->getOperand(1);
635 assert (Start->isReg() || Start->isImm());
636 assert (End->isReg() || End->isImm());
638 bool CmpLess = Cmp & Comparison::L;
639 bool CmpGreater = Cmp & Comparison::G;
640 bool CmpHasEqual = Cmp & Comparison::EQ;
642 // Avoid certain wrap-arounds. This doesn't detect all wrap-arounds.
643 // If loop executes while iv is "less" with the iv value going down, then
645 if (CmpLess && IVBump < 0)
647 // If loop executes while iv is "greater" with the iv value going up, then
649 if (CmpGreater && IVBump > 0)
652 if (Start->isImm() && End->isImm()) {
653 // Both, start and end are immediates.
654 int64_t StartV = Start->getImm();
655 int64_t EndV = End->getImm();
656 int64_t Dist = EndV - StartV;
660 bool Exact = (Dist % IVBump) == 0;
662 if (Cmp == Comparison::NE) {
665 if ((Dist < 0) ^ (IVBump < 0))
669 // For comparisons that include the final value (i.e. include equality
670 // with the final value), we need to increase the distance by 1.
672 Dist = Dist > 0 ? Dist+1 : Dist-1;
674 // assert (CmpLess => Dist > 0);
675 assert ((!CmpLess || Dist > 0) && "Loop should never iterate!");
676 // assert (CmpGreater => Dist < 0);
677 assert ((!CmpGreater || Dist < 0) && "Loop should never iterate!");
679 // "Normalized" distance, i.e. with the bump set to +-1.
680 int64_t Dist1 = (IVBump > 0) ? (Dist + (IVBump-1)) / IVBump
681 : (-Dist + (-IVBump-1)) / (-IVBump);
682 assert (Dist1 > 0 && "Fishy thing. Both operands have the same sign.");
684 uint64_t Count = Dist1;
686 if (Count > 0xFFFFFFFFULL)
689 return new CountValue(CountValue::CV_Immediate, Count);
692 // A general case: Start and End are some values, but the actual
693 // iteration count may not be available. If it is not, insert
694 // a computation of it into the preheader.
696 // If the induction variable bump is not a power of 2, quit.
697 // Othwerise we'd need a general integer division.
698 if (!isPowerOf2_64(abs64(IVBump)))
701 MachineBasicBlock *PH = Loop->getLoopPreheader();
702 assert (PH && "Should have a preheader by now");
703 MachineBasicBlock::iterator InsertPos = PH->getFirstTerminator();
704 DebugLoc DL = (InsertPos != PH->end()) ? InsertPos->getDebugLoc()
707 // If Start is an immediate and End is a register, the trip count
708 // will be "reg - imm". Hexagon's "subtract immediate" instruction
709 // is actually "reg + -imm".
711 // If the loop IV is going downwards, i.e. if the bump is negative,
712 // then the iteration count (computed as End-Start) will need to be
713 // negated. To avoid the negation, just swap Start and End.
715 std::swap(Start, End);
718 // Cmp may now have a wrong direction, e.g. LEs may now be GEs.
719 // Signedness, and "including equality" are preserved.
721 bool RegToImm = Start->isReg() && End->isImm(); // for (reg..imm)
722 bool RegToReg = Start->isReg() && End->isReg(); // for (reg..reg)
724 int64_t StartV = 0, EndV = 0;
726 StartV = Start->getImm();
728 EndV = End->getImm();
731 // To compute the iteration count, we would need this computation:
732 // Count = (End - Start + (IVBump-1)) / IVBump
733 // or, when CmpHasEqual:
734 // Count = (End - Start + (IVBump-1)+1) / IVBump
735 // The "IVBump-1" part is the adjustment (AdjV). We can avoid
736 // generating an instruction specifically to add it if we can adjust
737 // the immediate values for Start or End.
740 // Need to add 1 to the total iteration count.
743 else if (End->isImm())
749 if (Cmp != Comparison::NE) {
751 StartV -= (IVBump-1);
752 else if (End->isImm())
758 unsigned R = 0, SR = 0;
759 if (Start->isReg()) {
761 SR = Start->getSubReg();
764 SR = End->getSubReg();
766 const TargetRegisterClass *RC = MRI->getRegClass(R);
767 // Hardware loops cannot handle 64-bit registers. If it's a double
768 // register, it has to have a subregister.
769 if (!SR && RC == &Hexagon::DoubleRegsRegClass)
771 const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass;
773 // Compute DistR (register with the distance between Start and End).
774 unsigned DistR, DistSR;
776 // Avoid special case, where the start value is an imm(0).
777 if (Start->isImm() && StartV == 0) {
778 DistR = End->getReg();
779 DistSR = End->getSubReg();
781 const MCInstrDesc &SubD = RegToReg ? TII->get(Hexagon::SUB_rr) :
782 (RegToImm ? TII->get(Hexagon::SUB_ri) :
783 TII->get(Hexagon::ADD_ri));
784 unsigned SubR = MRI->createVirtualRegister(IntRC);
785 MachineInstrBuilder SubIB =
786 BuildMI(*PH, InsertPos, DL, SubD, SubR);
789 SubIB.addReg(End->getReg(), 0, End->getSubReg())
790 .addReg(Start->getReg(), 0, Start->getSubReg());
791 } else if (RegToImm) {
793 .addReg(Start->getReg(), 0, Start->getSubReg());
795 SubIB.addReg(End->getReg(), 0, End->getSubReg())
802 // From DistR, compute AdjR (register with the adjusted distance).
803 unsigned AdjR, AdjSR;
809 // Generate CountR = ADD DistR, AdjVal
810 unsigned AddR = MRI->createVirtualRegister(IntRC);
811 const MCInstrDesc &AddD = TII->get(Hexagon::ADD_ri);
812 BuildMI(*PH, InsertPos, DL, AddD, AddR)
813 .addReg(DistR, 0, DistSR)
820 // From AdjR, compute CountR (register with the final count).
821 unsigned CountR, CountSR;
827 // The IV bump is a power of two. Log_2(IV bump) is the shift amount.
828 unsigned Shift = Log2_32(IVBump);
830 // Generate NormR = LSR DistR, Shift.
831 unsigned LsrR = MRI->createVirtualRegister(IntRC);
832 const MCInstrDesc &LsrD = TII->get(Hexagon::LSR_ri);
833 BuildMI(*PH, InsertPos, DL, LsrD, LsrR)
834 .addReg(AdjR, 0, AdjSR)
841 return new CountValue(CountValue::CV_Register, CountR, CountSR);
845 /// \brief Return true if the operation is invalid within hardware loop.
846 bool HexagonHardwareLoops::isInvalidLoopOperation(
847 const MachineInstr *MI) const {
849 // call is not allowed because the callee may use a hardware loop
850 if (MI->getDesc().isCall())
853 // do not allow nested hardware loops
854 if (isHardwareLoop(MI))
857 // check if the instruction defines a hardware loop register
858 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
859 const MachineOperand &MO = MI->getOperand(i);
860 if (!MO.isReg() || !MO.isDef())
862 unsigned R = MO.getReg();
863 if (R == Hexagon::LC0 || R == Hexagon::LC1 ||
864 R == Hexagon::SA0 || R == Hexagon::SA1)
871 /// \brief - Return true if the loop contains an instruction that inhibits
872 /// the use of the hardware loop function.
873 bool HexagonHardwareLoops::containsInvalidInstruction(MachineLoop *L) const {
874 const std::vector<MachineBasicBlock *> &Blocks = L->getBlocks();
875 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
876 MachineBasicBlock *MBB = Blocks[i];
877 for (MachineBasicBlock::iterator
878 MII = MBB->begin(), E = MBB->end(); MII != E; ++MII) {
879 const MachineInstr *MI = &*MII;
880 if (isInvalidLoopOperation(MI))
888 /// \brief Returns true if the instruction is dead. This was essentially
889 /// copied from DeadMachineInstructionElim::isDead, but with special cases
890 /// for inline asm, physical registers and instructions with side effects
892 bool HexagonHardwareLoops::isDead(const MachineInstr *MI,
893 SmallVectorImpl<MachineInstr *> &DeadPhis) const {
894 // Examine each operand.
895 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
896 const MachineOperand &MO = MI->getOperand(i);
897 if (!MO.isReg() || !MO.isDef())
900 unsigned Reg = MO.getReg();
901 if (MRI->use_nodbg_empty(Reg))
904 typedef MachineRegisterInfo::use_nodbg_iterator use_nodbg_iterator;
906 // This instruction has users, but if the only user is the phi node for the
907 // parent block, and the only use of that phi node is this instruction, then
908 // this instruction is dead: both it (and the phi node) can be removed.
909 use_nodbg_iterator I = MRI->use_nodbg_begin(Reg);
910 use_nodbg_iterator End = MRI->use_nodbg_end();
911 if (std::next(I) != End || !I->getParent()->isPHI())
914 MachineInstr *OnePhi = I->getParent();
915 for (unsigned j = 0, f = OnePhi->getNumOperands(); j != f; ++j) {
916 const MachineOperand &OPO = OnePhi->getOperand(j);
917 if (!OPO.isReg() || !OPO.isDef())
920 unsigned OPReg = OPO.getReg();
921 use_nodbg_iterator nextJ;
922 for (use_nodbg_iterator J = MRI->use_nodbg_begin(OPReg);
923 J != End; J = nextJ) {
924 nextJ = std::next(J);
925 MachineOperand &Use = *J;
926 MachineInstr *UseMI = Use.getParent();
928 // If the phi node has a user that is not MI, bail...
933 DeadPhis.push_back(OnePhi);
936 // If there are no defs with uses, the instruction is dead.
940 void HexagonHardwareLoops::removeIfDead(MachineInstr *MI) {
941 // This procedure was essentially copied from DeadMachineInstructionElim.
943 SmallVector<MachineInstr*, 1> DeadPhis;
944 if (isDead(MI, DeadPhis)) {
945 DEBUG(dbgs() << "HW looping will remove: " << *MI);
947 // It is possible that some DBG_VALUE instructions refer to this
948 // instruction. Examine each def operand for such references;
949 // if found, mark the DBG_VALUE as undef (but don't delete it).
950 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
951 const MachineOperand &MO = MI->getOperand(i);
952 if (!MO.isReg() || !MO.isDef())
954 unsigned Reg = MO.getReg();
955 MachineRegisterInfo::use_iterator nextI;
956 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
957 E = MRI->use_end(); I != E; I = nextI) {
958 nextI = std::next(I); // I is invalidated by the setReg
959 MachineOperand &Use = *I;
960 MachineInstr *UseMI = I->getParent();
964 UseMI->getOperand(0).setReg(0U);
965 // This may also be a "instr -> phi -> instr" case which can
970 MI->eraseFromParent();
971 for (unsigned i = 0; i < DeadPhis.size(); ++i)
972 DeadPhis[i]->eraseFromParent();
976 /// \brief Check if the loop is a candidate for converting to a hardware
977 /// loop. If so, then perform the transformation.
979 /// This function works on innermost loops first. A loop can be converted
980 /// if it is a counting loop; either a register value or an immediate.
982 /// The code makes several assumptions about the representation of the loop
984 bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L) {
985 // This is just for sanity.
986 assert(L->getHeader() && "Loop without a header?");
988 bool Changed = false;
989 // Process nested loops first.
990 for (MachineLoop::iterator I = L->begin(), E = L->end(); I != E; ++I)
991 Changed |= convertToHardwareLoop(*I);
993 // If a nested loop has been converted, then we can't convert this loop.
998 // Stop trying after reaching the limit (if any).
999 int Limit = HWLoopLimit;
1001 if (Counter >= HWLoopLimit)
1007 // Does the loop contain any invalid instructions?
1008 if (containsInvalidInstruction(L))
1011 // Is the induction variable bump feeding the latch condition?
1012 if (!fixupInductionVariable(L))
1015 MachineBasicBlock *LastMBB = L->getExitingBlock();
1016 // Don't generate hw loop if the loop has more than one exit.
1020 MachineBasicBlock::iterator LastI = LastMBB->getFirstTerminator();
1021 if (LastI == LastMBB->end())
1024 // Ensure the loop has a preheader: the loop instruction will be
1026 bool NewPreheader = false;
1027 MachineBasicBlock *Preheader = L->getLoopPreheader();
1029 Preheader = createPreheaderForLoop(L);
1032 NewPreheader = true;
1034 MachineBasicBlock::iterator InsertPos = Preheader->getFirstTerminator();
1036 SmallVector<MachineInstr*, 2> OldInsts;
1037 // Are we able to determine the trip count for the loop?
1038 CountValue *TripCount = getLoopTripCount(L, OldInsts);
1042 // Is the trip count available in the preheader?
1043 if (TripCount->isReg()) {
1044 // There will be a use of the register inserted into the preheader,
1045 // so make sure that the register is actually defined at that point.
1046 MachineInstr *TCDef = MRI->getVRegDef(TripCount->getReg());
1047 MachineBasicBlock *BBDef = TCDef->getParent();
1048 if (!NewPreheader) {
1049 if (!MDT->dominates(BBDef, Preheader))
1052 // If we have just created a preheader, the dominator tree won't be
1053 // aware of it. Check if the definition of the register dominates
1054 // the header, but is not the header itself.
1055 if (!MDT->properlyDominates(BBDef, L->getHeader()))
1060 // Determine the loop start.
1061 MachineBasicBlock *LoopStart = L->getTopBlock();
1062 if (L->getLoopLatch() != LastMBB) {
1063 // When the exit and latch are not the same, use the latch block as the
1065 // The loop start address is used only after the 1st iteration, and the
1066 // loop latch may contains instrs. that need to be executed after the
1068 LoopStart = L->getLoopLatch();
1069 // Make sure the latch is a successor of the exit, otherwise it won't work.
1070 if (!LastMBB->isSuccessor(LoopStart))
1074 // Convert the loop to a hardware loop.
1075 DEBUG(dbgs() << "Change to hardware loop at "; L->dump());
1077 if (InsertPos != Preheader->end())
1078 DL = InsertPos->getDebugLoc();
1080 if (TripCount->isReg()) {
1081 // Create a copy of the loop count register.
1082 unsigned CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
1083 BuildMI(*Preheader, InsertPos, DL, TII->get(TargetOpcode::COPY), CountReg)
1084 .addReg(TripCount->getReg(), 0, TripCount->getSubReg());
1085 // Add the Loop instruction to the beginning of the loop.
1086 BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::LOOP0_r))
1090 assert(TripCount->isImm() && "Expecting immediate value for trip count");
1091 // Add the Loop immediate instruction to the beginning of the loop,
1092 // if the immediate fits in the instructions. Otherwise, we need to
1093 // create a new virtual register.
1094 int64_t CountImm = TripCount->getImm();
1095 if (!TII->isValidOffset(Hexagon::LOOP0_i, CountImm)) {
1096 unsigned CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
1097 BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::TFRI), CountReg)
1099 BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::LOOP0_r))
1100 .addMBB(LoopStart).addReg(CountReg);
1102 BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::LOOP0_i))
1103 .addMBB(LoopStart).addImm(CountImm);
1106 // Make sure the loop start always has a reference in the CFG. We need
1107 // to create a BlockAddress operand to get this mechanism to work both the
1108 // MachineBasicBlock and BasicBlock objects need the flag set.
1109 LoopStart->setHasAddressTaken();
1110 // This line is needed to set the hasAddressTaken flag on the BasicBlock
1112 BlockAddress::get(const_cast<BasicBlock *>(LoopStart->getBasicBlock()));
1114 // Replace the loop branch with an endloop instruction.
1115 DebugLoc LastIDL = LastI->getDebugLoc();
1116 BuildMI(*LastMBB, LastI, LastIDL,
1117 TII->get(Hexagon::ENDLOOP0)).addMBB(LoopStart);
1119 // The loop ends with either:
1120 // - a conditional branch followed by an unconditional branch, or
1121 // - a conditional branch to the loop start.
1122 if (LastI->getOpcode() == Hexagon::JMP_t ||
1123 LastI->getOpcode() == Hexagon::JMP_f) {
1124 // Delete one and change/add an uncond. branch to out of the loop.
1125 MachineBasicBlock *BranchTarget = LastI->getOperand(1).getMBB();
1126 LastI = LastMBB->erase(LastI);
1127 if (!L->contains(BranchTarget)) {
1128 if (LastI != LastMBB->end())
1129 LastI = LastMBB->erase(LastI);
1130 SmallVector<MachineOperand, 0> Cond;
1131 TII->InsertBranch(*LastMBB, BranchTarget, 0, Cond, LastIDL);
1134 // Conditional branch to loop start; just delete it.
1135 LastMBB->erase(LastI);
1139 // The induction operation and the comparison may now be
1140 // unneeded. If these are unneeded, then remove them.
1141 for (unsigned i = 0; i < OldInsts.size(); ++i)
1142 removeIfDead(OldInsts[i]);
1149 bool HexagonHardwareLoops::orderBumpCompare(MachineInstr *BumpI,
1150 MachineInstr *CmpI) {
1151 assert (BumpI != CmpI && "Bump and compare in the same instruction?");
1153 MachineBasicBlock *BB = BumpI->getParent();
1154 if (CmpI->getParent() != BB)
1157 typedef MachineBasicBlock::instr_iterator instr_iterator;
1158 // Check if things are in order to begin with.
1159 for (instr_iterator I = BumpI, E = BB->instr_end(); I != E; ++I)
1164 unsigned PredR = CmpI->getOperand(0).getReg();
1165 bool FoundBump = false;
1166 instr_iterator CmpIt = CmpI, NextIt = std::next(CmpIt);
1167 for (instr_iterator I = NextIt, E = BB->instr_end(); I != E; ++I) {
1168 MachineInstr *In = &*I;
1169 for (unsigned i = 0, n = In->getNumOperands(); i < n; ++i) {
1170 MachineOperand &MO = In->getOperand(i);
1171 if (MO.isReg() && MO.isUse()) {
1172 if (MO.getReg() == PredR) // Found an intervening use of PredR.
1178 instr_iterator After = BumpI;
1179 instr_iterator From = CmpI;
1180 BB->splice(std::next(After), BB, From);
1185 assert (FoundBump && "Cannot determine instruction order");
1190 MachineInstr *HexagonHardwareLoops::defWithImmediate(unsigned R) {
1191 MachineInstr *DI = MRI->getVRegDef(R);
1192 unsigned DOpc = DI->getOpcode();
1195 case Hexagon::TFRI64:
1196 case Hexagon::CONST32_Int_Real:
1197 case Hexagon::CONST64_Int_Real:
1204 int64_t HexagonHardwareLoops::getImmediate(MachineOperand &MO) {
1208 unsigned R = MO.getReg();
1209 MachineInstr *DI = defWithImmediate(R);
1210 assert(DI && "Need an immediate operand");
1211 // All currently supported "define-with-immediate" instructions have the
1212 // actual immediate value in the operand(1).
1213 int64_t v = DI->getOperand(1).getImm();
1218 void HexagonHardwareLoops::setImmediate(MachineOperand &MO, int64_t Val) {
1225 unsigned R = MO.getReg();
1226 MachineInstr *DI = defWithImmediate(R);
1227 if (MRI->hasOneNonDBGUse(R)) {
1228 // If R has only one use, then just change its defining instruction to
1229 // the new immediate value.
1230 DI->getOperand(1).setImm(Val);
1234 const TargetRegisterClass *RC = MRI->getRegClass(R);
1235 unsigned NewR = MRI->createVirtualRegister(RC);
1236 MachineBasicBlock &B = *DI->getParent();
1237 DebugLoc DL = DI->getDebugLoc();
1238 BuildMI(B, DI, DL, TII->get(DI->getOpcode()), NewR)
1244 bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) {
1245 MachineBasicBlock *Header = L->getHeader();
1246 MachineBasicBlock *Preheader = L->getLoopPreheader();
1247 MachineBasicBlock *Latch = L->getLoopLatch();
1249 if (!Header || !Preheader || !Latch)
1252 // These data structures follow the same concept as the corresponding
1253 // ones in findInductionRegister (where some comments are).
1254 typedef std::pair<unsigned,int64_t> RegisterBump;
1255 typedef std::pair<unsigned,RegisterBump> RegisterInduction;
1256 typedef std::set<RegisterInduction> RegisterInductionSet;
1258 // Register candidates for induction variables, with their associated bumps.
1259 RegisterInductionSet IndRegs;
1261 // Look for induction patterns:
1262 // vreg1 = PHI ..., [ latch, vreg2 ]
1263 // vreg2 = ADD vreg1, imm
1264 typedef MachineBasicBlock::instr_iterator instr_iterator;
1265 for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
1266 I != E && I->isPHI(); ++I) {
1267 MachineInstr *Phi = &*I;
1269 // Have a PHI instruction.
1270 for (unsigned i = 1, n = Phi->getNumOperands(); i < n; i += 2) {
1271 if (Phi->getOperand(i+1).getMBB() != Latch)
1274 unsigned PhiReg = Phi->getOperand(i).getReg();
1275 MachineInstr *DI = MRI->getVRegDef(PhiReg);
1276 unsigned UpdOpc = DI->getOpcode();
1277 bool isAdd = (UpdOpc == Hexagon::ADD_ri);
1280 // If the register operand to the add/sub is the PHI we are looking
1281 // at, this meets the induction pattern.
1282 unsigned IndReg = DI->getOperand(1).getReg();
1283 if (MRI->getVRegDef(IndReg) == Phi) {
1284 unsigned UpdReg = DI->getOperand(0).getReg();
1285 int64_t V = DI->getOperand(2).getImm();
1286 IndRegs.insert(std::make_pair(UpdReg, std::make_pair(IndReg, V)));
1292 if (IndRegs.empty())
1295 MachineBasicBlock *TB = 0, *FB = 0;
1296 SmallVector<MachineOperand,2> Cond;
1297 // AnalyzeBranch returns true if it fails to analyze branch.
1298 bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false);
1302 // Check if the latch branch is unconditional.
1306 if (TB != Header && FB != Header)
1307 // The latch does not go back to the header. Not a latch we know and love.
1310 // Expecting a predicate register as a condition. It won't be a hardware
1311 // predicate register at this point yet, just a vreg.
1312 // HexagonInstrInfo::AnalyzeBranch for negated branches inserts imm(0)
1313 // into Cond, followed by the predicate register. For non-negated branches
1314 // it's just the register.
1315 unsigned CSz = Cond.size();
1316 if (CSz != 1 && CSz != 2)
1319 unsigned P = Cond[CSz-1].getReg();
1320 MachineInstr *PredDef = MRI->getVRegDef(P);
1322 if (!PredDef->isCompare())
1325 SmallSet<unsigned,2> CmpRegs;
1326 MachineOperand *CmpImmOp = 0;
1328 // Go over all operands to the compare and look for immediate and register
1329 // operands. Assume that if the compare has a single register use and a
1330 // single immediate operand, then the register is being compared with the
1332 for (unsigned i = 0, n = PredDef->getNumOperands(); i < n; ++i) {
1333 MachineOperand &MO = PredDef->getOperand(i);
1335 // Skip all implicit references. In one case there was:
1336 // %vreg140<def> = FCMPUGT32_rr %vreg138, %vreg139, %USR<imp-use>
1337 if (MO.isImplicit())
1340 unsigned R = MO.getReg();
1341 if (!defWithImmediate(R)) {
1342 CmpRegs.insert(MO.getReg());
1345 // Consider the register to be the "immediate" operand.
1350 } else if (MO.isImm()) {
1351 if (CmpImmOp) // A second immediate argument? Confusing. Bail out.
1357 if (CmpRegs.empty())
1360 // Check if the compared register follows the order we want. Fix if needed.
1361 for (RegisterInductionSet::iterator I = IndRegs.begin(), E = IndRegs.end();
1363 // This is a success. If the register used in the comparison is one that
1364 // we have identified as a bumped (updated) induction register, there is
1366 if (CmpRegs.count(I->first))
1369 // Otherwise, if the register being compared comes out of a PHI node,
1370 // and has been recognized as following the induction pattern, and is
1371 // compared against an immediate, we can fix it.
1372 const RegisterBump &RB = I->second;
1373 if (CmpRegs.count(RB.first)) {
1377 int64_t CmpImm = getImmediate(*CmpImmOp);
1378 int64_t V = RB.second;
1379 if (V > 0 && CmpImm+V < CmpImm) // Overflow (64-bit).
1381 if (V < 0 && CmpImm+V > CmpImm) // Overflow (64-bit).
1384 // Some forms of cmp-immediate allow u9 and s10. Assume the worst case
1385 // scenario, i.e. an 8-bit value.
1386 if (CmpImmOp->isImm() && !isInt<8>(CmpImm))
1389 // Make sure that the compare happens after the bump. Otherwise,
1390 // after the fixup, the compare would use a yet-undefined register.
1391 MachineInstr *BumpI = MRI->getVRegDef(I->first);
1392 bool Order = orderBumpCompare(BumpI, PredDef);
1396 // Finally, fix the compare instruction.
1397 setImmediate(*CmpImmOp, CmpImm);
1398 for (unsigned i = 0, n = PredDef->getNumOperands(); i < n; ++i) {
1399 MachineOperand &MO = PredDef->getOperand(i);
1400 if (MO.isReg() && MO.getReg() == RB.first) {
1401 MO.setReg(I->first);
1412 /// \brief Create a preheader for a given loop.
1413 MachineBasicBlock *HexagonHardwareLoops::createPreheaderForLoop(
1415 if (MachineBasicBlock *TmpPH = L->getLoopPreheader())
1418 MachineBasicBlock *Header = L->getHeader();
1419 MachineBasicBlock *Latch = L->getLoopLatch();
1420 MachineFunction *MF = Header->getParent();
1423 if (!Latch || Header->hasAddressTaken())
1426 typedef MachineBasicBlock::instr_iterator instr_iterator;
1428 // Verify that all existing predecessors have analyzable branches
1429 // (or no branches at all).
1430 typedef std::vector<MachineBasicBlock*> MBBVector;
1431 MBBVector Preds(Header->pred_begin(), Header->pred_end());
1432 SmallVector<MachineOperand,2> Tmp1;
1433 MachineBasicBlock *TB = 0, *FB = 0;
1435 if (TII->AnalyzeBranch(*Latch, TB, FB, Tmp1, false))
1438 for (MBBVector::iterator I = Preds.begin(), E = Preds.end(); I != E; ++I) {
1439 MachineBasicBlock *PB = *I;
1441 bool NotAnalyzed = TII->AnalyzeBranch(*PB, TB, FB, Tmp1, false);
1447 MachineBasicBlock *NewPH = MF->CreateMachineBasicBlock();
1448 MF->insert(Header, NewPH);
1450 if (Header->pred_size() > 2) {
1451 // Ensure that the header has only two predecessors: the preheader and
1452 // the loop latch. Any additional predecessors of the header should
1453 // join at the newly created preheader. Inspect all PHI nodes from the
1454 // header and create appropriate corresponding PHI nodes in the preheader.
1456 for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
1457 I != E && I->isPHI(); ++I) {
1458 MachineInstr *PN = &*I;
1460 const MCInstrDesc &PD = TII->get(TargetOpcode::PHI);
1461 MachineInstr *NewPN = MF->CreateMachineInstr(PD, DL);
1462 NewPH->insert(NewPH->end(), NewPN);
1464 unsigned PR = PN->getOperand(0).getReg();
1465 const TargetRegisterClass *RC = MRI->getRegClass(PR);
1466 unsigned NewPR = MRI->createVirtualRegister(RC);
1467 NewPN->addOperand(MachineOperand::CreateReg(NewPR, true));
1469 // Copy all non-latch operands of a header's PHI node to the newly
1470 // created PHI node in the preheader.
1471 for (unsigned i = 1, n = PN->getNumOperands(); i < n; i += 2) {
1472 unsigned PredR = PN->getOperand(i).getReg();
1473 MachineBasicBlock *PredB = PN->getOperand(i+1).getMBB();
1477 NewPN->addOperand(MachineOperand::CreateReg(PredR, false));
1478 NewPN->addOperand(MachineOperand::CreateMBB(PredB));
1481 // Remove copied operands from the old PHI node and add the value
1482 // coming from the preheader's PHI.
1483 for (int i = PN->getNumOperands()-2; i > 0; i -= 2) {
1484 MachineBasicBlock *PredB = PN->getOperand(i+1).getMBB();
1485 if (PredB != Latch) {
1486 PN->RemoveOperand(i+1);
1487 PN->RemoveOperand(i);
1490 PN->addOperand(MachineOperand::CreateReg(NewPR, false));
1491 PN->addOperand(MachineOperand::CreateMBB(NewPH));
1495 assert(Header->pred_size() == 2);
1497 // The header has only two predecessors, but the non-latch predecessor
1498 // is not a preheader (e.g. it has other successors, etc.)
1499 // In such a case we don't need any extra PHI nodes in the new preheader,
1500 // all we need is to adjust existing PHIs in the header to now refer to
1501 // the new preheader.
1502 for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
1503 I != E && I->isPHI(); ++I) {
1504 MachineInstr *PN = &*I;
1505 for (unsigned i = 1, n = PN->getNumOperands(); i < n; i += 2) {
1506 MachineOperand &MO = PN->getOperand(i+1);
1507 if (MO.getMBB() != Latch)
1513 // "Reroute" the CFG edges to link in the new preheader.
1514 // If any of the predecessors falls through to the header, insert a branch
1515 // to the new preheader in that place.
1516 SmallVector<MachineOperand,1> Tmp2;
1517 SmallVector<MachineOperand,1> EmptyCond;
1521 for (MBBVector::iterator I = Preds.begin(), E = Preds.end(); I != E; ++I) {
1522 MachineBasicBlock *PB = *I;
1525 bool NotAnalyzed = TII->AnalyzeBranch(*PB, TB, FB, Tmp2, false);
1526 (void)NotAnalyzed; // suppress compiler warning
1527 assert (!NotAnalyzed && "Should be analyzable!");
1528 if (TB != Header && (Tmp2.empty() || FB != Header))
1529 TII->InsertBranch(*PB, NewPH, 0, EmptyCond, DL);
1530 PB->ReplaceUsesOfBlockWith(Header, NewPH);
1534 // It can happen that the latch block will fall through into the header.
1535 // Insert an unconditional branch to the header.
1537 bool LatchNotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Tmp2, false);
1538 (void)LatchNotAnalyzed; // suppress compiler warning
1539 assert (!LatchNotAnalyzed && "Should be analyzable!");
1541 TII->InsertBranch(*Latch, Header, 0, EmptyCond, DL);
1543 // Finally, the branch from the preheader to the header.
1544 TII->InsertBranch(*NewPH, Header, 0, EmptyCond, DL);
1545 NewPH->addSuccessor(Header);