1 //===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the Hexagon target.
12 //===----------------------------------------------------------------------===//
15 #include "HexagonISelLowering.h"
16 #include "HexagonTargetMachine.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/IR/Intrinsics.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/Compiler.h"
22 #include "llvm/Support/Debug.h"
25 #define DEBUG_TYPE "hexagon-isel"
29 MaxNumOfUsesForConstExtenders("ga-max-num-uses-for-constant-extenders",
30 cl::Hidden, cl::init(2),
31 cl::desc("Maximum number of uses of a global address such that we still us a"
32 "constant extended instruction"));
34 //===----------------------------------------------------------------------===//
35 // Instruction Selector Implementation
36 //===----------------------------------------------------------------------===//
39 void initializeHexagonDAGToDAGISelPass(PassRegistry&);
42 //===--------------------------------------------------------------------===//
43 /// HexagonDAGToDAGISel - Hexagon specific code to select Hexagon machine
44 /// instructions for SelectionDAG operations.
47 class HexagonDAGToDAGISel : public SelectionDAGISel {
48 const HexagonTargetMachine& HTM;
49 const HexagonSubtarget &HST;
51 explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm,
52 CodeGenOpt::Level OptLevel)
53 : SelectionDAGISel(tm, OptLevel), HTM(tm),
54 HST(tm.getSubtarget<HexagonSubtarget>()) {
55 initializeHexagonDAGToDAGISelPass(*PassRegistry::getPassRegistry());
57 virtual void PreprocessISelDAG() override;
59 SDNode *Select(SDNode *N) override;
61 // Complex Pattern Selectors.
62 inline bool SelectAddrGA(SDValue &N, SDValue &R);
63 inline bool SelectAddrGP(SDValue &N, SDValue &R);
64 bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP);
65 bool SelectAddrFI(SDValue &N, SDValue &R);
67 const char *getPassName() const override {
68 return "Hexagon DAG->DAG Pattern Instruction Selection";
71 SDNode *SelectFrameIndex(SDNode *N);
72 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
73 /// inline asm expressions.
74 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
75 unsigned ConstraintID,
76 std::vector<SDValue> &OutOps) override;
77 SDNode *SelectLoad(SDNode *N);
78 SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl);
79 SDNode *SelectIndexedLoad(LoadSDNode *LD, SDLoc dl);
80 SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
82 SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
84 SDNode *SelectBaseOffsetStore(StoreSDNode *ST, SDLoc dl);
85 SDNode *SelectIndexedStore(StoreSDNode *ST, SDLoc dl);
86 SDNode *SelectStore(SDNode *N);
87 SDNode *SelectSHL(SDNode *N);
88 SDNode *SelectSelect(SDNode *N);
89 SDNode *SelectTruncate(SDNode *N);
90 SDNode *SelectMul(SDNode *N);
91 SDNode *SelectZeroExtend(SDNode *N);
92 SDNode *SelectIntrinsicWChain(SDNode *N);
93 SDNode *SelectIntrinsicWOChain(SDNode *N);
94 SDNode *SelectConstant(SDNode *N);
95 SDNode *SelectConstantFP(SDNode *N);
96 SDNode *SelectAdd(SDNode *N);
98 // XformMskToBitPosU5Imm - Returns the bit position which
99 // the single bit 32 bit mask represents.
100 // Used in Clr and Set bit immediate memops.
101 SDValue XformMskToBitPosU5Imm(uint32_t Imm) {
103 bitPos = Log2_32(Imm);
104 assert(bitPos >= 0 && bitPos < 32 &&
105 "Constant out of range for 32 BitPos Memops");
106 return CurDAG->getTargetConstant(bitPos, MVT::i32);
109 // XformMskToBitPosU4Imm - Returns the bit position which the single-bit
110 // 16 bit mask represents. Used in Clr and Set bit immediate memops.
111 SDValue XformMskToBitPosU4Imm(uint16_t Imm) {
112 return XformMskToBitPosU5Imm(Imm);
115 // XformMskToBitPosU3Imm - Returns the bit position which the single-bit
116 // 8 bit mask represents. Used in Clr and Set bit immediate memops.
117 SDValue XformMskToBitPosU3Imm(uint8_t Imm) {
118 return XformMskToBitPosU5Imm(Imm);
121 // Return true if there is exactly one bit set in V, i.e., if V is one of the
122 // following integers: 2^0, 2^1, ..., 2^31.
123 bool ImmIsSingleBit(uint32_t v) const {
124 return isPowerOf2_32(v);
127 // XformM5ToU5Imm - Return a target constant with the specified value, of
128 // type i32 where the negative literal is transformed into a positive literal
129 // for use in -= memops.
130 inline SDValue XformM5ToU5Imm(signed Imm) {
131 assert( (Imm >= -31 && Imm <= -1) && "Constant out of range for Memops");
132 return CurDAG->getTargetConstant( - Imm, MVT::i32);
135 // XformU7ToU7M1Imm - Return a target constant decremented by 1, in range
136 // [1..128], used in cmpb.gtu instructions.
137 inline SDValue XformU7ToU7M1Imm(signed Imm) {
138 assert((Imm >= 1 && Imm <= 128) && "Constant out of range for cmpb op");
139 return CurDAG->getTargetConstant(Imm - 1, MVT::i8);
142 // XformS8ToS8M1Imm - Return a target constant decremented by 1.
143 inline SDValue XformSToSM1Imm(signed Imm) {
144 return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
147 // XformU8ToU8M1Imm - Return a target constant decremented by 1.
148 inline SDValue XformUToUM1Imm(unsigned Imm) {
149 assert((Imm >= 1) && "Cannot decrement unsigned int less than 1");
150 return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
153 // XformSToSM2Imm - Return a target constant decremented by 2.
154 inline SDValue XformSToSM2Imm(unsigned Imm) {
155 return CurDAG->getTargetConstant(Imm - 2, MVT::i32);
158 // XformSToSM3Imm - Return a target constant decremented by 3.
159 inline SDValue XformSToSM3Imm(unsigned Imm) {
160 return CurDAG->getTargetConstant(Imm - 3, MVT::i32);
163 // Include the pieces autogenerated from the target description.
164 #include "HexagonGenDAGISel.inc"
167 bool isValueExtension(const SDValue &Val, unsigned FromBits, SDValue &Src);
168 }; // end HexagonDAGToDAGISel
169 } // end anonymous namespace
172 /// createHexagonISelDag - This pass converts a legalized DAG into a
173 /// Hexagon-specific DAG, ready for instruction scheduling.
176 FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
177 CodeGenOpt::Level OptLevel) {
178 return new HexagonDAGToDAGISel(TM, OptLevel);
182 static void initializePassOnce(PassRegistry &Registry) {
183 const char *Name = "Hexagon DAG->DAG Pattern Instruction Selection";
184 PassInfo *PI = new PassInfo(Name, "hexagon-isel",
185 &SelectionDAGISel::ID, nullptr, false, false);
186 Registry.registerPass(*PI, true);
189 void llvm::initializeHexagonDAGToDAGISelPass(PassRegistry &Registry) {
190 CALL_ONCE_INITIALIZATION(initializePassOnce)
194 // Intrinsics that return a a predicate.
195 static unsigned doesIntrinsicReturnPredicate(unsigned ID)
200 case Intrinsic::hexagon_C2_cmpeq:
201 case Intrinsic::hexagon_C2_cmpgt:
202 case Intrinsic::hexagon_C2_cmpgtu:
203 case Intrinsic::hexagon_C2_cmpgtup:
204 case Intrinsic::hexagon_C2_cmpgtp:
205 case Intrinsic::hexagon_C2_cmpeqp:
206 case Intrinsic::hexagon_C2_bitsset:
207 case Intrinsic::hexagon_C2_bitsclr:
208 case Intrinsic::hexagon_C2_cmpeqi:
209 case Intrinsic::hexagon_C2_cmpgti:
210 case Intrinsic::hexagon_C2_cmpgtui:
211 case Intrinsic::hexagon_C2_cmpgei:
212 case Intrinsic::hexagon_C2_cmpgeui:
213 case Intrinsic::hexagon_C2_cmplt:
214 case Intrinsic::hexagon_C2_cmpltu:
215 case Intrinsic::hexagon_C2_bitsclri:
216 case Intrinsic::hexagon_C2_and:
217 case Intrinsic::hexagon_C2_or:
218 case Intrinsic::hexagon_C2_xor:
219 case Intrinsic::hexagon_C2_andn:
220 case Intrinsic::hexagon_C2_not:
221 case Intrinsic::hexagon_C2_orn:
222 case Intrinsic::hexagon_C2_pxfer_map:
223 case Intrinsic::hexagon_C2_any8:
224 case Intrinsic::hexagon_C2_all8:
225 case Intrinsic::hexagon_A2_vcmpbeq:
226 case Intrinsic::hexagon_A2_vcmpbgtu:
227 case Intrinsic::hexagon_A2_vcmpheq:
228 case Intrinsic::hexagon_A2_vcmphgt:
229 case Intrinsic::hexagon_A2_vcmphgtu:
230 case Intrinsic::hexagon_A2_vcmpweq:
231 case Intrinsic::hexagon_A2_vcmpwgt:
232 case Intrinsic::hexagon_A2_vcmpwgtu:
233 case Intrinsic::hexagon_C2_tfrrp:
234 case Intrinsic::hexagon_S2_tstbit_i:
235 case Intrinsic::hexagon_S2_tstbit_r:
240 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
243 SDValue Chain = LD->getChain();
244 EVT LoadedVT = LD->getMemoryVT();
245 SDValue Base = LD->getBasePtr();
246 SDValue Offset = LD->getOffset();
247 SDNode *OffsetNode = Offset.getNode();
248 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
250 const HexagonInstrInfo &TII = *HST.getInstrInfo();
251 if (TII.isValidAutoIncImm(LoadedVT, Val)) {
252 SDValue TargetConst = CurDAG->getTargetConstant(Val, MVT::i32);
253 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32,
254 MVT::Other, Base, TargetConst,
256 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
257 SDValue(Result_1, 0));
258 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
259 MemOp[0] = LD->getMemOperand();
260 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
261 const SDValue Froms[] = { SDValue(LD, 0),
264 const SDValue Tos[] = { SDValue(Result_2, 0),
265 SDValue(Result_1, 1),
266 SDValue(Result_1, 2) };
267 ReplaceUses(Froms, Tos, 3);
271 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
272 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
273 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Other,
274 Base, TargetConst0, Chain);
275 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
276 SDValue(Result_1, 0));
277 SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
278 Base, TargetConstVal,
279 SDValue(Result_1, 1));
280 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
281 MemOp[0] = LD->getMemOperand();
282 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
283 const SDValue Froms[] = { SDValue(LD, 0),
286 const SDValue Tos[] = { SDValue(Result_2, 0),
287 SDValue(Result_3, 0),
288 SDValue(Result_1, 1) };
289 ReplaceUses(Froms, Tos, 3);
294 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
297 SDValue Chain = LD->getChain();
298 EVT LoadedVT = LD->getMemoryVT();
299 SDValue Base = LD->getBasePtr();
300 SDValue Offset = LD->getOffset();
301 SDNode *OffsetNode = Offset.getNode();
302 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
304 const HexagonInstrInfo &TII = *HST.getInstrInfo();
305 if (TII.isValidAutoIncImm(LoadedVT, Val)) {
306 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
307 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
308 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
309 MVT::i32, MVT::Other, Base,
310 TargetConstVal, Chain);
311 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A4_combineir, dl,
312 MVT::i64, MVT::Other,
314 SDValue(Result_1,0));
315 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
316 MemOp[0] = LD->getMemOperand();
317 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
318 const SDValue Froms[] = { SDValue(LD, 0),
321 const SDValue Tos[] = { SDValue(Result_2, 0),
322 SDValue(Result_1, 1),
323 SDValue(Result_1, 2) };
324 ReplaceUses(Froms, Tos, 3);
328 // Generate an indirect load.
329 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
330 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
331 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
332 MVT::Other, Base, TargetConst0,
334 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A4_combineir, dl,
335 MVT::i64, MVT::Other,
337 SDValue(Result_1,0));
338 // Add offset to base.
339 SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
340 Base, TargetConstVal,
341 SDValue(Result_1, 1));
342 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
343 MemOp[0] = LD->getMemOperand();
344 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
345 const SDValue Froms[] = { SDValue(LD, 0),
348 const SDValue Tos[] = { SDValue(Result_2, 0), // Load value.
349 SDValue(Result_3, 0), // New address.
350 SDValue(Result_1, 1) };
351 ReplaceUses(Froms, Tos, 3);
356 SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
357 SDValue Chain = LD->getChain();
358 SDValue Base = LD->getBasePtr();
359 SDValue Offset = LD->getOffset();
360 SDNode *OffsetNode = Offset.getNode();
361 // Get the constant value.
362 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
363 EVT LoadedVT = LD->getMemoryVT();
366 // Check for zero extended loads. Treat any-extend loads as zero extended
368 ISD::LoadExtType ExtType = LD->getExtensionType();
369 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD);
371 // Figure out the opcode.
372 const HexagonInstrInfo &TII = *HST.getInstrInfo();
373 if (LoadedVT == MVT::i64) {
374 if (TII.isValidAutoIncImm(LoadedVT, Val))
375 Opcode = Hexagon::L2_loadrd_pi;
377 Opcode = Hexagon::L2_loadrd_io;
378 } else if (LoadedVT == MVT::i32) {
379 if (TII.isValidAutoIncImm(LoadedVT, Val))
380 Opcode = Hexagon::L2_loadri_pi;
382 Opcode = Hexagon::L2_loadri_io;
383 } else if (LoadedVT == MVT::i16) {
384 if (TII.isValidAutoIncImm(LoadedVT, Val))
385 Opcode = IsZeroExt ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadrh_pi;
387 Opcode = IsZeroExt ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io;
388 } else if (LoadedVT == MVT::i8) {
389 if (TII.isValidAutoIncImm(LoadedVT, Val))
390 Opcode = IsZeroExt ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrb_pi;
392 Opcode = IsZeroExt ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io;
394 llvm_unreachable("unknown memory type");
396 // For zero extended i64 loads, we need to add combine instructions.
397 if (LD->getValueType(0) == MVT::i64 && IsZeroExt)
398 return SelectIndexedLoadZeroExtend64(LD, Opcode, dl);
399 // Handle sign extended i64 loads.
400 if (LD->getValueType(0) == MVT::i64 && ExtType == ISD::SEXTLOAD)
401 return SelectIndexedLoadSignExtend64(LD, Opcode, dl);
403 if (TII.isValidAutoIncImm(LoadedVT, Val)) {
404 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
405 SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
407 MVT::i32, MVT::Other, Base,
408 TargetConstVal, Chain);
409 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
410 MemOp[0] = LD->getMemOperand();
411 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
412 const SDValue Froms[] = { SDValue(LD, 0),
416 const SDValue Tos[] = { SDValue(Result, 0),
420 ReplaceUses(Froms, Tos, 3);
423 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
424 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
425 SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl,
427 MVT::Other, Base, TargetConst0,
429 SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
430 Base, TargetConstVal,
431 SDValue(Result_1, 1));
432 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
433 MemOp[0] = LD->getMemOperand();
434 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
435 const SDValue Froms[] = { SDValue(LD, 0),
439 const SDValue Tos[] = { SDValue(Result_1, 0),
440 SDValue(Result_2, 0),
443 ReplaceUses(Froms, Tos, 3);
449 SDNode *HexagonDAGToDAGISel::SelectLoad(SDNode *N) {
452 LoadSDNode *LD = cast<LoadSDNode>(N);
453 ISD::MemIndexedMode AM = LD->getAddressingMode();
455 // Handle indexed loads.
456 if (AM != ISD::UNINDEXED) {
457 result = SelectIndexedLoad(LD, dl);
459 result = SelectCode(LD);
466 SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
467 SDValue Chain = ST->getChain();
468 SDValue Base = ST->getBasePtr();
469 SDValue Offset = ST->getOffset();
470 SDValue Value = ST->getValue();
471 SDNode *OffsetNode = Offset.getNode();
472 // Get the constant value.
473 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
474 EVT StoredVT = ST->getMemoryVT();
475 EVT ValueVT = Value.getValueType();
477 // Offset value must be within representable range
478 // and must have correct alignment properties.
479 const HexagonInstrInfo &TII = *HST.getInstrInfo();
480 if (TII.isValidAutoIncImm(StoredVT, Val)) {
483 // Figure out the post inc version of opcode.
484 if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_pi;
485 else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_pi;
486 else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_pi;
487 else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_pi;
488 else llvm_unreachable("unknown memory type");
490 if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) {
491 assert(StoredVT.getSizeInBits() < 64 && "Not a truncating store");
492 Value = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg,
493 dl, MVT::i32, Value);
495 SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, MVT::i32), Value,
497 // Build post increment store.
498 SDNode* Result = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
500 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
501 MemOp[0] = ST->getMemOperand();
502 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
504 ReplaceUses(ST, Result);
505 ReplaceUses(SDValue(ST,1), SDValue(Result,1));
509 // Note: Order of operands matches the def of instruction:
511 // : STInst<(outs), (ins IntRegs:$base, imm:$offset, DoubleRegs:$src1), ...
512 // and it differs for POST_ST* for instance.
513 SDValue Ops[] = { Base, CurDAG->getTargetConstant(0, MVT::i32), Value,
517 // Figure out the opcode.
518 if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_io;
519 else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_io;
520 else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_io;
521 else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_io;
522 else llvm_unreachable("unknown memory type");
524 // Build regular store.
525 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
526 SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
527 // Build splitted incriment instruction.
528 SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
531 SDValue(Result_1, 0));
532 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
533 MemOp[0] = ST->getMemOperand();
534 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
536 ReplaceUses(SDValue(ST,0), SDValue(Result_2,0));
537 ReplaceUses(SDValue(ST,1), SDValue(Result_1,0));
541 SDNode *HexagonDAGToDAGISel::SelectStore(SDNode *N) {
543 StoreSDNode *ST = cast<StoreSDNode>(N);
544 ISD::MemIndexedMode AM = ST->getAddressingMode();
546 // Handle indexed stores.
547 if (AM != ISD::UNINDEXED) {
548 return SelectIndexedStore(ST, dl);
551 return SelectCode(ST);
554 SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
558 // %conv.i = sext i32 %tmp1 to i64
559 // %conv2.i = sext i32 %add to i64
560 // %mul.i = mul nsw i64 %conv2.i, %conv.i
562 // --- match with the following ---
564 // %mul.i = mpy (%tmp1, %add)
567 if (N->getValueType(0) == MVT::i64) {
568 // Shifting a i64 signed multiply.
569 SDValue MulOp0 = N->getOperand(0);
570 SDValue MulOp1 = N->getOperand(1);
575 // Handle sign_extend and sextload.
576 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
577 SDValue Sext0 = MulOp0.getOperand(0);
578 if (Sext0.getNode()->getValueType(0) != MVT::i32) {
579 return SelectCode(N);
583 } else if (MulOp0.getOpcode() == ISD::LOAD) {
584 LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
585 if (LD->getMemoryVT() != MVT::i32 ||
586 LD->getExtensionType() != ISD::SEXTLOAD ||
587 LD->getAddressingMode() != ISD::UNINDEXED) {
588 return SelectCode(N);
591 SDValue Chain = LD->getChain();
592 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
593 OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
595 LD->getBasePtr(), TargetConst0,
598 return SelectCode(N);
601 // Same goes for the second operand.
602 if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
603 SDValue Sext1 = MulOp1.getOperand(0);
604 if (Sext1.getNode()->getValueType(0) != MVT::i32) {
605 return SelectCode(N);
609 } else if (MulOp1.getOpcode() == ISD::LOAD) {
610 LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
611 if (LD->getMemoryVT() != MVT::i32 ||
612 LD->getExtensionType() != ISD::SEXTLOAD ||
613 LD->getAddressingMode() != ISD::UNINDEXED) {
614 return SelectCode(N);
617 SDValue Chain = LD->getChain();
618 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
619 OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
621 LD->getBasePtr(), TargetConst0,
624 return SelectCode(N);
627 // Generate a mpy instruction.
628 SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_dpmpyss_s0, dl, MVT::i64,
630 ReplaceUses(N, Result);
634 return SelectCode(N);
638 SDNode *HexagonDAGToDAGISel::SelectSelect(SDNode *N) {
640 SDValue N0 = N->getOperand(0);
641 if (N0.getOpcode() == ISD::SETCC) {
642 SDValue N00 = N0.getOperand(0);
643 if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
644 SDValue N000 = N00.getOperand(0);
645 SDValue N001 = N00.getOperand(1);
646 if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
647 SDValue N01 = N0.getOperand(1);
648 SDValue N02 = N0.getOperand(2);
650 // Pattern: (select:i32 (setcc:i1 (sext_inreg:i32 IntRegs:i32:$src2,
651 // i16:Other),IntRegs:i32:$src1, SETLT:Other),IntRegs:i32:$src1,
652 // IntRegs:i32:$src2)
653 // Emits: (MAXh_rr:i32 IntRegs:i32:$src1, IntRegs:i32:$src2)
654 // Pattern complexity = 9 cost = 1 size = 0.
655 if (cast<CondCodeSDNode>(N02)->get() == ISD::SETLT) {
656 SDValue N1 = N->getOperand(1);
658 SDValue N2 = N->getOperand(2);
660 N0.getNode()->getValueType(N0.getResNo()) == MVT::i1 &&
661 N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) {
662 SDNode *SextNode = CurDAG->getMachineNode(Hexagon::A2_sxth, dl,
664 SDNode *Result = CurDAG->getMachineNode(Hexagon::A2_max, dl,
666 SDValue(SextNode, 0),
668 ReplaceUses(N, Result);
674 // Pattern: (select:i32 (setcc:i1 (sext_inreg:i32 IntRegs:i32:$src2,
675 // i16:Other), IntRegs:i32:$src1, SETGT:Other), IntRegs:i32:$src1,
676 // IntRegs:i32:$src2)
677 // Emits: (MINh_rr:i32 IntRegs:i32:$src1, IntRegs:i32:$src2)
678 // Pattern complexity = 9 cost = 1 size = 0.
679 if (cast<CondCodeSDNode>(N02)->get() == ISD::SETGT) {
680 SDValue N1 = N->getOperand(1);
682 SDValue N2 = N->getOperand(2);
684 N0.getNode()->getValueType(N0.getResNo()) == MVT::i1 &&
685 N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) {
686 SDNode *SextNode = CurDAG->getMachineNode(Hexagon::A2_sxth, dl,
688 SDNode *Result = CurDAG->getMachineNode(Hexagon::A2_min, dl,
690 SDValue(SextNode, 0),
692 ReplaceUses(N, Result);
701 return SelectCode(N);
705 SDNode *HexagonDAGToDAGISel::SelectTruncate(SDNode *N) {
707 SDValue Shift = N->getOperand(0);
710 // %conv.i = sext i32 %tmp1 to i64
711 // %conv2.i = sext i32 %add to i64
712 // %mul.i = mul nsw i64 %conv2.i, %conv.i
713 // %shr5.i = lshr i64 %mul.i, 32
714 // %conv3.i = trunc i64 %shr5.i to i32
716 // --- match with the following ---
718 // %conv3.i = mpy (%tmp1, %add)
721 if (N->getValueType(0) == MVT::i32) {
723 if (Shift.getNode()->getValueType(0) == MVT::i64) {
724 // Trunc child is logical shift right.
725 if (Shift.getOpcode() != ISD::SRL) {
726 return SelectCode(N);
729 SDValue ShiftOp0 = Shift.getOperand(0);
730 SDValue ShiftOp1 = Shift.getOperand(1);
733 if (ShiftOp1.getOpcode() != ISD::Constant) {
734 return SelectCode(N);
738 cast<ConstantSDNode>(ShiftOp1.getNode())->getSExtValue();
739 if (ShiftConst != 32) {
740 return SelectCode(N);
743 // Shifting a i64 signed multiply
744 SDValue Mul = ShiftOp0;
745 if (Mul.getOpcode() != ISD::MUL) {
746 return SelectCode(N);
749 SDValue MulOp0 = Mul.getOperand(0);
750 SDValue MulOp1 = Mul.getOperand(1);
755 // Handle sign_extend and sextload
756 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
757 SDValue Sext0 = MulOp0.getOperand(0);
758 if (Sext0.getNode()->getValueType(0) != MVT::i32) {
759 return SelectCode(N);
763 } else if (MulOp0.getOpcode() == ISD::LOAD) {
764 LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
765 if (LD->getMemoryVT() != MVT::i32 ||
766 LD->getExtensionType() != ISD::SEXTLOAD ||
767 LD->getAddressingMode() != ISD::UNINDEXED) {
768 return SelectCode(N);
771 SDValue Chain = LD->getChain();
772 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
773 OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
776 TargetConst0, Chain), 0);
778 return SelectCode(N);
781 // Same goes for the second operand.
782 if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
783 SDValue Sext1 = MulOp1.getOperand(0);
784 if (Sext1.getNode()->getValueType(0) != MVT::i32)
785 return SelectCode(N);
788 } else if (MulOp1.getOpcode() == ISD::LOAD) {
789 LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
790 if (LD->getMemoryVT() != MVT::i32 ||
791 LD->getExtensionType() != ISD::SEXTLOAD ||
792 LD->getAddressingMode() != ISD::UNINDEXED) {
793 return SelectCode(N);
796 SDValue Chain = LD->getChain();
797 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
798 OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
801 TargetConst0, Chain), 0);
803 return SelectCode(N);
806 // Generate a mpy instruction.
807 SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_mpy_up, dl, MVT::i32,
809 ReplaceUses(N, Result);
814 return SelectCode(N);
818 SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
820 if (N->getValueType(0) == MVT::i32) {
821 SDValue Shl_0 = N->getOperand(0);
822 SDValue Shl_1 = N->getOperand(1);
824 if (Shl_1.getOpcode() == ISD::Constant) {
825 if (Shl_0.getOpcode() == ISD::MUL) {
826 SDValue Mul_0 = Shl_0.getOperand(0); // Val
827 SDValue Mul_1 = Shl_0.getOperand(1); // Const
828 // RHS of mul is const.
829 if (Mul_1.getOpcode() == ISD::Constant) {
831 cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
833 cast<ConstantSDNode>(Mul_1.getNode())->getSExtValue();
834 int32_t ValConst = MulConst << ShlConst;
835 SDValue Val = CurDAG->getTargetConstant(ValConst,
837 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val.getNode()))
838 if (isInt<9>(CN->getSExtValue())) {
840 CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl,
841 MVT::i32, Mul_0, Val);
842 ReplaceUses(N, Result);
847 } else if (Shl_0.getOpcode() == ISD::SUB) {
848 SDValue Sub_0 = Shl_0.getOperand(0); // Const 0
849 SDValue Sub_1 = Shl_0.getOperand(1); // Val
850 if (Sub_0.getOpcode() == ISD::Constant) {
852 cast<ConstantSDNode>(Sub_0.getNode())->getSExtValue();
854 if (Sub_1.getOpcode() == ISD::SHL) {
855 SDValue Shl2_0 = Sub_1.getOperand(0); // Val
856 SDValue Shl2_1 = Sub_1.getOperand(1); // Const
857 if (Shl2_1.getOpcode() == ISD::Constant) {
859 cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
861 cast<ConstantSDNode>(Shl2_1.getNode())->getSExtValue();
862 int32_t ValConst = 1 << (ShlConst+Shl2Const);
863 SDValue Val = CurDAG->getTargetConstant(-ValConst, MVT::i32);
864 if (ConstantSDNode *CN =
865 dyn_cast<ConstantSDNode>(Val.getNode()))
866 if (isInt<9>(CN->getSExtValue())) {
868 CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl, MVT::i32,
870 ReplaceUses(N, Result);
880 return SelectCode(N);
885 // If there is an zero_extend followed an intrinsic in DAG (this means - the
886 // result of the intrinsic is predicate); convert the zero_extend to
887 // transfer instruction.
889 // Zero extend -> transfer is lowered here. Otherwise, zero_extend will be
890 // converted into a MUX as predicate registers defined as 1 bit in the
891 // compiler. Architecture defines them as 8-bit registers.
892 // We want to preserve all the lower 8-bits and, not just 1 LSB bit.
894 SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
896 SDNode *IsIntrinsic = N->getOperand(0).getNode();
897 if ((IsIntrinsic->getOpcode() == ISD::INTRINSIC_WO_CHAIN)) {
899 cast<ConstantSDNode>(IsIntrinsic->getOperand(0))->getZExtValue();
900 if (doesIntrinsicReturnPredicate(ID)) {
901 // Now we need to differentiate target data types.
902 if (N->getValueType(0) == MVT::i64) {
903 // Convert the zero_extend to Rs = Pd followed by A2_combinew(0,Rs).
904 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
905 SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
907 SDValue(IsIntrinsic, 0));
908 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl,
911 SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl,
912 MVT::i64, MVT::Other,
913 SDValue(Result_2, 0),
914 SDValue(Result_1, 0));
915 ReplaceUses(N, Result_3);
918 if (N->getValueType(0) == MVT::i32) {
919 // Convert the zero_extend to Rs = Pd
920 SDNode* RsPd = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
922 SDValue(IsIntrinsic, 0));
923 ReplaceUses(N, RsPd);
926 llvm_unreachable("Unexpected value type");
929 return SelectCode(N);
933 // Checking for intrinsics which have predicate registers as operand(s)
934 // and lowering to the actual intrinsic.
936 SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
937 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
940 case Intrinsic::hexagon_S2_vsplatrb:
943 case Intrinsic::hexagon_S2_vsplatrh:
947 return SelectCode(N);
950 SDValue const &V = N->getOperand(1);
952 if (isValueExtension(V, Bits, U)) {
953 SDValue R = CurDAG->getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
954 N->getOperand(0), U);
955 return SelectCode(R.getNode());
957 return SelectCode(N);
961 // Map floating point constant values.
963 SDNode *HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) {
965 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
966 APFloat APF = CN->getValueAPF();
967 if (N->getValueType(0) == MVT::f32) {
968 return CurDAG->getMachineNode(Hexagon::TFRI_f, dl, MVT::f32,
969 CurDAG->getTargetConstantFP(APF.convertToFloat(), MVT::f32));
971 else if (N->getValueType(0) == MVT::f64) {
972 return CurDAG->getMachineNode(Hexagon::CONST64_Float_Real, dl, MVT::f64,
973 CurDAG->getTargetConstantFP(APF.convertToDouble(), MVT::f64));
976 return SelectCode(N);
980 // Map predicate true (encoded as -1 in LLVM) to a XOR.
982 SDNode *HexagonDAGToDAGISel::SelectConstant(SDNode *N) {
984 if (N->getValueType(0) == MVT::i1) {
986 int32_t Val = cast<ConstantSDNode>(N)->getSExtValue();
988 // Create the IntReg = 1 node.
990 CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32,
991 CurDAG->getTargetConstant(0, MVT::i32));
994 SDNode* Pd = CurDAG->getMachineNode(Hexagon::C2_tfrrp, dl, MVT::i1,
995 SDValue(IntRegTFR, 0));
998 SDNode* NotPd = CurDAG->getMachineNode(Hexagon::C2_not, dl, MVT::i1,
1002 Result = CurDAG->getMachineNode(Hexagon::C2_xor, dl, MVT::i1,
1003 SDValue(Pd, 0), SDValue(NotPd, 0));
1005 // We have just built:
1007 // Pd = xor(not(Pd), Pd)
1009 ReplaceUses(N, Result);
1014 return SelectCode(N);
1019 // Map add followed by a asr -> asr +=.
1021 SDNode *HexagonDAGToDAGISel::SelectAdd(SDNode *N) {
1023 if (N->getValueType(0) != MVT::i32) {
1024 return SelectCode(N);
1026 // Identify nodes of the form: add(asr(...)).
1027 SDNode* Src1 = N->getOperand(0).getNode();
1028 if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse()
1029 || Src1->getValueType(0) != MVT::i32) {
1030 return SelectCode(N);
1033 // Build Rd = Rd' + asr(Rs, Rt). The machine constraints will ensure that
1034 // Rd and Rd' are assigned to the same register
1035 SDNode* Result = CurDAG->getMachineNode(Hexagon::S2_asr_r_r_acc, dl, MVT::i32,
1037 Src1->getOperand(0),
1038 Src1->getOperand(1));
1039 ReplaceUses(N, Result);
1044 SDNode *HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) {
1045 int FX = cast<FrameIndexSDNode>(N)->getIndex();
1046 SDValue FI = CurDAG->getTargetFrameIndex(FX, MVT::i32);
1047 SDValue Zero = CurDAG->getTargetConstant(0, MVT::i32);
1050 SDNode *R = CurDAG->getMachineNode(Hexagon::TFR_FI, DL, MVT::i32, FI, Zero);
1052 if (N->getHasDebugValue())
1053 CurDAG->TransferDbgValues(SDValue(N, 0), SDValue(R, 0));
1058 SDNode *HexagonDAGToDAGISel::Select(SDNode *N) {
1059 if (N->isMachineOpcode()) {
1061 return nullptr; // Already selected.
1064 switch (N->getOpcode()) {
1066 return SelectConstant(N);
1068 case ISD::ConstantFP:
1069 return SelectConstantFP(N);
1071 case ISD::FrameIndex:
1072 return SelectFrameIndex(N);
1075 return SelectAdd(N);
1078 return SelectSHL(N);
1081 return SelectLoad(N);
1084 return SelectStore(N);
1087 return SelectSelect(N);
1090 return SelectTruncate(N);
1093 return SelectMul(N);
1095 case ISD::ZERO_EXTEND:
1096 return SelectZeroExtend(N);
1098 case ISD::INTRINSIC_WO_CHAIN:
1099 return SelectIntrinsicWOChain(N);
1102 return SelectCode(N);
1106 bool HexagonDAGToDAGISel::
1107 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
1108 std::vector<SDValue> &OutOps) {
1109 SDValue Inp = Op, Res;
1111 switch (ConstraintID) {
1114 case InlineAsm::Constraint_i:
1115 case InlineAsm::Constraint_o: // Offsetable.
1116 case InlineAsm::Constraint_v: // Not offsetable.
1117 case InlineAsm::Constraint_m: // Memory.
1118 if (SelectAddrFI(Inp, Res))
1119 OutOps.push_back(Res);
1121 OutOps.push_back(Inp);
1125 OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
1129 void HexagonDAGToDAGISel::PreprocessISelDAG() {
1130 SelectionDAG &DAG = *CurDAG;
1131 std::vector<SDNode*> Nodes;
1132 for (auto I = DAG.allnodes_begin(), E = DAG.allnodes_end(); I != E; ++I)
1135 // Simplify: (or (select c x 0) z) -> (select c (or x z) z)
1136 // (or (select c 0 y) z) -> (select c z (or y z))
1137 // This may not be the right thing for all targets, so do it here.
1138 for (auto I: Nodes) {
1139 if (I->getOpcode() != ISD::OR)
1142 auto IsZero = [] (const SDValue &V) -> bool {
1143 if (ConstantSDNode *SC = dyn_cast<ConstantSDNode>(V.getNode()))
1144 return SC->isNullValue();
1147 auto IsSelect0 = [IsZero] (const SDValue &Op) -> bool {
1148 if (Op.getOpcode() != ISD::SELECT)
1150 return IsZero(Op.getOperand(1)) || IsZero(Op.getOperand(2));
1153 SDValue N0 = I->getOperand(0), N1 = I->getOperand(1);
1154 EVT VT = I->getValueType(0);
1155 bool SelN0 = IsSelect0(N0);
1156 SDValue SOp = SelN0 ? N0 : N1;
1157 SDValue VOp = SelN0 ? N1 : N0;
1159 if (SOp.getOpcode() == ISD::SELECT && SOp.getNode()->hasOneUse()) {
1160 SDValue SC = SOp.getOperand(0);
1161 SDValue SX = SOp.getOperand(1);
1162 SDValue SY = SOp.getOperand(2);
1165 SDValue NewOr = DAG.getNode(ISD::OR, DLS, VT, SX, VOp);
1166 SDValue NewSel = DAG.getNode(ISD::SELECT, DLS, VT, SC, NewOr, VOp);
1167 DAG.ReplaceAllUsesWith(I, NewSel.getNode());
1168 } else if (IsZero(SX)) {
1169 SDValue NewOr = DAG.getNode(ISD::OR, DLS, VT, SY, VOp);
1170 SDValue NewSel = DAG.getNode(ISD::SELECT, DLS, VT, SC, VOp, NewOr);
1171 DAG.ReplaceAllUsesWith(I, NewSel.getNode());
1178 bool HexagonDAGToDAGISel::SelectAddrFI(SDValue& N, SDValue &R) {
1179 if (N.getOpcode() != ISD::FrameIndex)
1181 FrameIndexSDNode *FX = cast<FrameIndexSDNode>(N);
1182 R = CurDAG->getTargetFrameIndex(FX->getIndex(), MVT::i32);
1186 inline bool HexagonDAGToDAGISel::SelectAddrGA(SDValue &N, SDValue &R) {
1187 return SelectGlobalAddress(N, R, false);
1190 inline bool HexagonDAGToDAGISel::SelectAddrGP(SDValue &N, SDValue &R) {
1191 return SelectGlobalAddress(N, R, true);
1194 bool HexagonDAGToDAGISel::SelectGlobalAddress(SDValue &N, SDValue &R,
1196 switch (N.getOpcode()) {
1198 SDValue N0 = N.getOperand(0);
1199 SDValue N1 = N.getOperand(1);
1200 unsigned GAOpc = N0.getOpcode();
1201 if (UseGP && GAOpc != HexagonISD::CONST32_GP)
1203 if (!UseGP && GAOpc != HexagonISD::CONST32)
1205 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N1)) {
1206 SDValue Addr = N0.getOperand(0);
1207 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Addr)) {
1208 if (GA->getOpcode() == ISD::TargetGlobalAddress) {
1209 uint64_t NewOff = GA->getOffset() + (uint64_t)Const->getSExtValue();
1210 R = CurDAG->getTargetGlobalAddress(GA->getGlobal(), SDLoc(Const),
1211 N.getValueType(), NewOff);
1218 case HexagonISD::CONST32:
1219 // The operand(0) of CONST32 is TargetGlobalAddress, which is what we
1220 // want in the instruction.
1222 R = N.getOperand(0);
1224 case HexagonISD::CONST32_GP:
1226 R = N.getOperand(0);
1235 bool HexagonDAGToDAGISel::isValueExtension(const SDValue &Val,
1236 unsigned FromBits, SDValue &Src) {
1237 unsigned Opc = Val.getOpcode();
1239 case ISD::SIGN_EXTEND:
1240 case ISD::ZERO_EXTEND:
1241 case ISD::ANY_EXTEND: {
1242 SDValue const &Op0 = Val.getOperand(0);
1243 EVT T = Op0.getValueType();
1244 if (T.isInteger() && T.getSizeInBits() == FromBits) {
1250 case ISD::SIGN_EXTEND_INREG:
1251 case ISD::AssertSext:
1252 case ISD::AssertZext:
1253 if (Val.getOperand(0).getValueType().isInteger()) {
1254 VTSDNode *T = cast<VTSDNode>(Val.getOperand(1));
1255 if (T->getVT().getSizeInBits() == FromBits) {
1256 Src = Val.getOperand(0);
1262 // Check if this is an AND with "FromBits" of lower bits set to 1.
1263 uint64_t FromMask = (1 << FromBits) - 1;
1264 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) {
1265 if (C->getZExtValue() == FromMask) {
1266 Src = Val.getOperand(1);
1270 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(1))) {
1271 if (C->getZExtValue() == FromMask) {
1272 Src = Val.getOperand(0);
1280 // OR/XOR with the lower "FromBits" bits set to 0.
1281 uint64_t FromMask = (1 << FromBits) - 1;
1282 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) {
1283 if ((C->getZExtValue() & FromMask) == 0) {
1284 Src = Val.getOperand(1);
1288 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(1))) {
1289 if ((C->getZExtValue() & FromMask) == 0) {
1290 Src = Val.getOperand(0);