1 //===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the Hexagon target.
12 //===----------------------------------------------------------------------===//
15 #include "HexagonISelLowering.h"
16 #include "HexagonMachineFunctionInfo.h"
17 #include "HexagonTargetMachine.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/FunctionLoweringInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/SelectionDAGISel.h"
22 #include "llvm/IR/Intrinsics.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Compiler.h"
25 #include "llvm/Support/Debug.h"
28 #define DEBUG_TYPE "hexagon-isel"
32 MaxNumOfUsesForConstExtenders("ga-max-num-uses-for-constant-extenders",
33 cl::Hidden, cl::init(2),
34 cl::desc("Maximum number of uses of a global address such that we still us a"
35 "constant extended instruction"));
37 //===----------------------------------------------------------------------===//
38 // Instruction Selector Implementation
39 //===----------------------------------------------------------------------===//
42 void initializeHexagonDAGToDAGISelPass(PassRegistry&);
45 //===--------------------------------------------------------------------===//
46 /// HexagonDAGToDAGISel - Hexagon specific code to select Hexagon machine
47 /// instructions for SelectionDAG operations.
50 class HexagonDAGToDAGISel : public SelectionDAGISel {
51 const HexagonTargetMachine& HTM;
52 const HexagonSubtarget *HST;
54 explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm,
55 CodeGenOpt::Level OptLevel)
56 : SelectionDAGISel(tm, OptLevel), HTM(tm) {
57 initializeHexagonDAGToDAGISelPass(*PassRegistry::getPassRegistry());
60 bool runOnMachineFunction(MachineFunction &MF) override {
61 // Reset the subtarget each time through.
62 HST = &MF.getSubtarget<HexagonSubtarget>();
63 SelectionDAGISel::runOnMachineFunction(MF);
67 virtual void PreprocessISelDAG() override;
68 virtual void EmitFunctionEntryCode() override;
70 SDNode *Select(SDNode *N) override;
72 // Complex Pattern Selectors.
73 inline bool SelectAddrGA(SDValue &N, SDValue &R);
74 inline bool SelectAddrGP(SDValue &N, SDValue &R);
75 bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP);
76 bool SelectAddrFI(SDValue &N, SDValue &R);
78 const char *getPassName() const override {
79 return "Hexagon DAG->DAG Pattern Instruction Selection";
82 SDNode *SelectFrameIndex(SDNode *N);
83 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
84 /// inline asm expressions.
85 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
86 unsigned ConstraintID,
87 std::vector<SDValue> &OutOps) override;
88 SDNode *SelectLoad(SDNode *N);
89 SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl);
90 SDNode *SelectIndexedLoad(LoadSDNode *LD, SDLoc dl);
91 SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
93 SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
95 SDNode *SelectBaseOffsetStore(StoreSDNode *ST, SDLoc dl);
96 SDNode *SelectIndexedStore(StoreSDNode *ST, SDLoc dl);
97 SDNode *SelectStore(SDNode *N);
98 SDNode *SelectSHL(SDNode *N);
99 SDNode *SelectMul(SDNode *N);
100 SDNode *SelectZeroExtend(SDNode *N);
101 SDNode *SelectIntrinsicWChain(SDNode *N);
102 SDNode *SelectIntrinsicWOChain(SDNode *N);
103 SDNode *SelectConstant(SDNode *N);
104 SDNode *SelectConstantFP(SDNode *N);
105 SDNode *SelectAdd(SDNode *N);
106 SDNode *SelectBitOp(SDNode *N);
108 // XformMskToBitPosU5Imm - Returns the bit position which
109 // the single bit 32 bit mask represents.
110 // Used in Clr and Set bit immediate memops.
111 SDValue XformMskToBitPosU5Imm(uint32_t Imm) {
113 bitPos = Log2_32(Imm);
114 assert(bitPos >= 0 && bitPos < 32 &&
115 "Constant out of range for 32 BitPos Memops");
116 return CurDAG->getTargetConstant(bitPos, MVT::i32);
119 // XformMskToBitPosU4Imm - Returns the bit position which the single-bit
120 // 16 bit mask represents. Used in Clr and Set bit immediate memops.
121 SDValue XformMskToBitPosU4Imm(uint16_t Imm) {
122 return XformMskToBitPosU5Imm(Imm);
125 // XformMskToBitPosU3Imm - Returns the bit position which the single-bit
126 // 8 bit mask represents. Used in Clr and Set bit immediate memops.
127 SDValue XformMskToBitPosU3Imm(uint8_t Imm) {
128 return XformMskToBitPosU5Imm(Imm);
131 // Return true if there is exactly one bit set in V, i.e., if V is one of the
132 // following integers: 2^0, 2^1, ..., 2^31.
133 bool ImmIsSingleBit(uint32_t v) const {
134 return isPowerOf2_32(v);
137 // XformM5ToU5Imm - Return a target constant with the specified value, of
138 // type i32 where the negative literal is transformed into a positive literal
139 // for use in -= memops.
140 inline SDValue XformM5ToU5Imm(signed Imm) {
141 assert( (Imm >= -31 && Imm <= -1) && "Constant out of range for Memops");
142 return CurDAG->getTargetConstant( - Imm, MVT::i32);
145 // XformU7ToU7M1Imm - Return a target constant decremented by 1, in range
146 // [1..128], used in cmpb.gtu instructions.
147 inline SDValue XformU7ToU7M1Imm(signed Imm) {
148 assert((Imm >= 1 && Imm <= 128) && "Constant out of range for cmpb op");
149 return CurDAG->getTargetConstant(Imm - 1, MVT::i8);
152 // XformS8ToS8M1Imm - Return a target constant decremented by 1.
153 inline SDValue XformSToSM1Imm(signed Imm) {
154 return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
157 // XformU8ToU8M1Imm - Return a target constant decremented by 1.
158 inline SDValue XformUToUM1Imm(unsigned Imm) {
159 assert((Imm >= 1) && "Cannot decrement unsigned int less than 1");
160 return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
163 // XformSToSM2Imm - Return a target constant decremented by 2.
164 inline SDValue XformSToSM2Imm(unsigned Imm) {
165 return CurDAG->getTargetConstant(Imm - 2, MVT::i32);
168 // XformSToSM3Imm - Return a target constant decremented by 3.
169 inline SDValue XformSToSM3Imm(unsigned Imm) {
170 return CurDAG->getTargetConstant(Imm - 3, MVT::i32);
173 // Include the pieces autogenerated from the target description.
174 #include "HexagonGenDAGISel.inc"
177 bool isValueExtension(const SDValue &Val, unsigned FromBits, SDValue &Src);
178 }; // end HexagonDAGToDAGISel
179 } // end anonymous namespace
182 /// createHexagonISelDag - This pass converts a legalized DAG into a
183 /// Hexagon-specific DAG, ready for instruction scheduling.
186 FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
187 CodeGenOpt::Level OptLevel) {
188 return new HexagonDAGToDAGISel(TM, OptLevel);
192 static void initializePassOnce(PassRegistry &Registry) {
193 const char *Name = "Hexagon DAG->DAG Pattern Instruction Selection";
194 PassInfo *PI = new PassInfo(Name, "hexagon-isel",
195 &SelectionDAGISel::ID, nullptr, false, false);
196 Registry.registerPass(*PI, true);
199 void llvm::initializeHexagonDAGToDAGISelPass(PassRegistry &Registry) {
200 CALL_ONCE_INITIALIZATION(initializePassOnce)
204 // Intrinsics that return a a predicate.
205 static unsigned doesIntrinsicReturnPredicate(unsigned ID)
210 case Intrinsic::hexagon_C2_cmpeq:
211 case Intrinsic::hexagon_C2_cmpgt:
212 case Intrinsic::hexagon_C2_cmpgtu:
213 case Intrinsic::hexagon_C2_cmpgtup:
214 case Intrinsic::hexagon_C2_cmpgtp:
215 case Intrinsic::hexagon_C2_cmpeqp:
216 case Intrinsic::hexagon_C2_bitsset:
217 case Intrinsic::hexagon_C2_bitsclr:
218 case Intrinsic::hexagon_C2_cmpeqi:
219 case Intrinsic::hexagon_C2_cmpgti:
220 case Intrinsic::hexagon_C2_cmpgtui:
221 case Intrinsic::hexagon_C2_cmpgei:
222 case Intrinsic::hexagon_C2_cmpgeui:
223 case Intrinsic::hexagon_C2_cmplt:
224 case Intrinsic::hexagon_C2_cmpltu:
225 case Intrinsic::hexagon_C2_bitsclri:
226 case Intrinsic::hexagon_C2_and:
227 case Intrinsic::hexagon_C2_or:
228 case Intrinsic::hexagon_C2_xor:
229 case Intrinsic::hexagon_C2_andn:
230 case Intrinsic::hexagon_C2_not:
231 case Intrinsic::hexagon_C2_orn:
232 case Intrinsic::hexagon_C2_pxfer_map:
233 case Intrinsic::hexagon_C2_any8:
234 case Intrinsic::hexagon_C2_all8:
235 case Intrinsic::hexagon_A2_vcmpbeq:
236 case Intrinsic::hexagon_A2_vcmpbgtu:
237 case Intrinsic::hexagon_A2_vcmpheq:
238 case Intrinsic::hexagon_A2_vcmphgt:
239 case Intrinsic::hexagon_A2_vcmphgtu:
240 case Intrinsic::hexagon_A2_vcmpweq:
241 case Intrinsic::hexagon_A2_vcmpwgt:
242 case Intrinsic::hexagon_A2_vcmpwgtu:
243 case Intrinsic::hexagon_C2_tfrrp:
244 case Intrinsic::hexagon_S2_tstbit_i:
245 case Intrinsic::hexagon_S2_tstbit_r:
250 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
253 SDValue Chain = LD->getChain();
254 EVT LoadedVT = LD->getMemoryVT();
255 SDValue Base = LD->getBasePtr();
256 SDValue Offset = LD->getOffset();
257 SDNode *OffsetNode = Offset.getNode();
258 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
260 const HexagonInstrInfo &TII = *HST->getInstrInfo();
261 if (TII.isValidAutoIncImm(LoadedVT, Val)) {
262 SDValue TargetConst = CurDAG->getTargetConstant(Val, MVT::i32);
263 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32,
264 MVT::Other, Base, TargetConst,
266 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
267 SDValue(Result_1, 0));
268 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
269 MemOp[0] = LD->getMemOperand();
270 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
271 const SDValue Froms[] = { SDValue(LD, 0),
274 const SDValue Tos[] = { SDValue(Result_2, 0),
275 SDValue(Result_1, 1),
276 SDValue(Result_1, 2) };
277 ReplaceUses(Froms, Tos, 3);
281 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
282 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
283 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Other,
284 Base, TargetConst0, Chain);
285 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
286 SDValue(Result_1, 0));
287 SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
288 Base, TargetConstVal,
289 SDValue(Result_1, 1));
290 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
291 MemOp[0] = LD->getMemOperand();
292 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
293 const SDValue Froms[] = { SDValue(LD, 0),
296 const SDValue Tos[] = { SDValue(Result_2, 0),
297 SDValue(Result_3, 0),
298 SDValue(Result_1, 1) };
299 ReplaceUses(Froms, Tos, 3);
304 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
307 SDValue Chain = LD->getChain();
308 EVT LoadedVT = LD->getMemoryVT();
309 SDValue Base = LD->getBasePtr();
310 SDValue Offset = LD->getOffset();
311 SDNode *OffsetNode = Offset.getNode();
312 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
314 const HexagonInstrInfo &TII = *HST->getInstrInfo();
315 if (TII.isValidAutoIncImm(LoadedVT, Val)) {
316 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
317 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
318 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
319 MVT::i32, MVT::Other, Base,
320 TargetConstVal, Chain);
321 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A4_combineir, dl,
322 MVT::i64, MVT::Other,
324 SDValue(Result_1,0));
325 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
326 MemOp[0] = LD->getMemOperand();
327 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
328 const SDValue Froms[] = { SDValue(LD, 0),
331 const SDValue Tos[] = { SDValue(Result_2, 0),
332 SDValue(Result_1, 1),
333 SDValue(Result_1, 2) };
334 ReplaceUses(Froms, Tos, 3);
338 // Generate an indirect load.
339 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
340 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
341 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
342 MVT::Other, Base, TargetConst0,
344 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A4_combineir, dl,
345 MVT::i64, MVT::Other,
347 SDValue(Result_1,0));
348 // Add offset to base.
349 SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
350 Base, TargetConstVal,
351 SDValue(Result_1, 1));
352 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
353 MemOp[0] = LD->getMemOperand();
354 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
355 const SDValue Froms[] = { SDValue(LD, 0),
358 const SDValue Tos[] = { SDValue(Result_2, 0), // Load value.
359 SDValue(Result_3, 0), // New address.
360 SDValue(Result_1, 1) };
361 ReplaceUses(Froms, Tos, 3);
366 SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
367 SDValue Chain = LD->getChain();
368 SDValue Base = LD->getBasePtr();
369 SDValue Offset = LD->getOffset();
370 SDNode *OffsetNode = Offset.getNode();
371 // Get the constant value.
372 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
373 EVT LoadedVT = LD->getMemoryVT();
376 // Check for zero extended loads. Treat any-extend loads as zero extended
378 ISD::LoadExtType ExtType = LD->getExtensionType();
379 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD);
381 // Figure out the opcode.
382 const HexagonInstrInfo &TII = *HST->getInstrInfo();
383 if (LoadedVT == MVT::i64) {
384 if (TII.isValidAutoIncImm(LoadedVT, Val))
385 Opcode = Hexagon::L2_loadrd_pi;
387 Opcode = Hexagon::L2_loadrd_io;
388 } else if (LoadedVT == MVT::i32) {
389 if (TII.isValidAutoIncImm(LoadedVT, Val))
390 Opcode = Hexagon::L2_loadri_pi;
392 Opcode = Hexagon::L2_loadri_io;
393 } else if (LoadedVT == MVT::i16) {
394 if (TII.isValidAutoIncImm(LoadedVT, Val))
395 Opcode = IsZeroExt ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadrh_pi;
397 Opcode = IsZeroExt ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io;
398 } else if (LoadedVT == MVT::i8) {
399 if (TII.isValidAutoIncImm(LoadedVT, Val))
400 Opcode = IsZeroExt ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrb_pi;
402 Opcode = IsZeroExt ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io;
404 llvm_unreachable("unknown memory type");
406 // For zero extended i64 loads, we need to add combine instructions.
407 if (LD->getValueType(0) == MVT::i64 && IsZeroExt)
408 return SelectIndexedLoadZeroExtend64(LD, Opcode, dl);
409 // Handle sign extended i64 loads.
410 if (LD->getValueType(0) == MVT::i64 && ExtType == ISD::SEXTLOAD)
411 return SelectIndexedLoadSignExtend64(LD, Opcode, dl);
413 if (TII.isValidAutoIncImm(LoadedVT, Val)) {
414 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
415 SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
417 MVT::i32, MVT::Other, Base,
418 TargetConstVal, Chain);
419 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
420 MemOp[0] = LD->getMemOperand();
421 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
422 const SDValue Froms[] = { SDValue(LD, 0),
426 const SDValue Tos[] = { SDValue(Result, 0),
430 ReplaceUses(Froms, Tos, 3);
433 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
434 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
435 SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl,
437 MVT::Other, Base, TargetConst0,
439 SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
440 Base, TargetConstVal,
441 SDValue(Result_1, 1));
442 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
443 MemOp[0] = LD->getMemOperand();
444 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
445 const SDValue Froms[] = { SDValue(LD, 0),
449 const SDValue Tos[] = { SDValue(Result_1, 0),
450 SDValue(Result_2, 0),
453 ReplaceUses(Froms, Tos, 3);
459 SDNode *HexagonDAGToDAGISel::SelectLoad(SDNode *N) {
462 LoadSDNode *LD = cast<LoadSDNode>(N);
463 ISD::MemIndexedMode AM = LD->getAddressingMode();
465 // Handle indexed loads.
466 if (AM != ISD::UNINDEXED) {
467 result = SelectIndexedLoad(LD, dl);
469 result = SelectCode(LD);
476 SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
477 SDValue Chain = ST->getChain();
478 SDValue Base = ST->getBasePtr();
479 SDValue Offset = ST->getOffset();
480 SDValue Value = ST->getValue();
481 SDNode *OffsetNode = Offset.getNode();
482 // Get the constant value.
483 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
484 EVT StoredVT = ST->getMemoryVT();
485 EVT ValueVT = Value.getValueType();
487 // Offset value must be within representable range
488 // and must have correct alignment properties.
489 const HexagonInstrInfo &TII = *HST->getInstrInfo();
490 if (TII.isValidAutoIncImm(StoredVT, Val)) {
493 // Figure out the post inc version of opcode.
494 if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_pi;
495 else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_pi;
496 else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_pi;
497 else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_pi;
498 else llvm_unreachable("unknown memory type");
500 if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) {
501 assert(StoredVT.getSizeInBits() < 64 && "Not a truncating store");
502 Value = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg,
503 dl, MVT::i32, Value);
505 SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, MVT::i32), Value,
507 // Build post increment store.
508 SDNode* Result = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
510 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
511 MemOp[0] = ST->getMemOperand();
512 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
514 ReplaceUses(ST, Result);
515 ReplaceUses(SDValue(ST,1), SDValue(Result,1));
519 // Note: Order of operands matches the def of instruction:
521 // : STInst<(outs), (ins IntRegs:$base, imm:$offset, DoubleRegs:$src1), ...
522 // and it differs for POST_ST* for instance.
523 SDValue Ops[] = { Base, CurDAG->getTargetConstant(0, MVT::i32), Value,
527 // Figure out the opcode.
528 if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_io;
529 else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_io;
530 else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_io;
531 else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_io;
532 else llvm_unreachable("unknown memory type");
534 // Build regular store.
535 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
536 SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
537 // Build splitted incriment instruction.
538 SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
541 SDValue(Result_1, 0));
542 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
543 MemOp[0] = ST->getMemOperand();
544 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
546 ReplaceUses(SDValue(ST,0), SDValue(Result_2,0));
547 ReplaceUses(SDValue(ST,1), SDValue(Result_1,0));
551 SDNode *HexagonDAGToDAGISel::SelectStore(SDNode *N) {
553 StoreSDNode *ST = cast<StoreSDNode>(N);
554 ISD::MemIndexedMode AM = ST->getAddressingMode();
556 // Handle indexed stores.
557 if (AM != ISD::UNINDEXED) {
558 return SelectIndexedStore(ST, dl);
561 return SelectCode(ST);
564 SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
568 // %conv.i = sext i32 %tmp1 to i64
569 // %conv2.i = sext i32 %add to i64
570 // %mul.i = mul nsw i64 %conv2.i, %conv.i
572 // --- match with the following ---
574 // %mul.i = mpy (%tmp1, %add)
577 if (N->getValueType(0) == MVT::i64) {
578 // Shifting a i64 signed multiply.
579 SDValue MulOp0 = N->getOperand(0);
580 SDValue MulOp1 = N->getOperand(1);
585 // Handle sign_extend and sextload.
586 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
587 SDValue Sext0 = MulOp0.getOperand(0);
588 if (Sext0.getNode()->getValueType(0) != MVT::i32) {
589 return SelectCode(N);
593 } else if (MulOp0.getOpcode() == ISD::LOAD) {
594 LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
595 if (LD->getMemoryVT() != MVT::i32 ||
596 LD->getExtensionType() != ISD::SEXTLOAD ||
597 LD->getAddressingMode() != ISD::UNINDEXED) {
598 return SelectCode(N);
601 SDValue Chain = LD->getChain();
602 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
603 OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
605 LD->getBasePtr(), TargetConst0,
608 return SelectCode(N);
611 // Same goes for the second operand.
612 if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
613 SDValue Sext1 = MulOp1.getOperand(0);
614 if (Sext1.getNode()->getValueType(0) != MVT::i32) {
615 return SelectCode(N);
619 } else if (MulOp1.getOpcode() == ISD::LOAD) {
620 LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
621 if (LD->getMemoryVT() != MVT::i32 ||
622 LD->getExtensionType() != ISD::SEXTLOAD ||
623 LD->getAddressingMode() != ISD::UNINDEXED) {
624 return SelectCode(N);
627 SDValue Chain = LD->getChain();
628 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
629 OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
631 LD->getBasePtr(), TargetConst0,
634 return SelectCode(N);
637 // Generate a mpy instruction.
638 SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_dpmpyss_s0, dl, MVT::i64,
640 ReplaceUses(N, Result);
644 return SelectCode(N);
647 SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
649 if (N->getValueType(0) == MVT::i32) {
650 SDValue Shl_0 = N->getOperand(0);
651 SDValue Shl_1 = N->getOperand(1);
653 if (Shl_1.getOpcode() == ISD::Constant) {
654 if (Shl_0.getOpcode() == ISD::MUL) {
655 SDValue Mul_0 = Shl_0.getOperand(0); // Val
656 SDValue Mul_1 = Shl_0.getOperand(1); // Const
657 // RHS of mul is const.
658 if (Mul_1.getOpcode() == ISD::Constant) {
660 cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
662 cast<ConstantSDNode>(Mul_1.getNode())->getSExtValue();
663 int32_t ValConst = MulConst << ShlConst;
664 SDValue Val = CurDAG->getTargetConstant(ValConst,
666 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val.getNode()))
667 if (isInt<9>(CN->getSExtValue())) {
669 CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl,
670 MVT::i32, Mul_0, Val);
671 ReplaceUses(N, Result);
676 } else if (Shl_0.getOpcode() == ISD::SUB) {
677 SDValue Sub_0 = Shl_0.getOperand(0); // Const 0
678 SDValue Sub_1 = Shl_0.getOperand(1); // Val
679 if (Sub_0.getOpcode() == ISD::Constant) {
681 cast<ConstantSDNode>(Sub_0.getNode())->getSExtValue();
683 if (Sub_1.getOpcode() == ISD::SHL) {
684 SDValue Shl2_0 = Sub_1.getOperand(0); // Val
685 SDValue Shl2_1 = Sub_1.getOperand(1); // Const
686 if (Shl2_1.getOpcode() == ISD::Constant) {
688 cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
690 cast<ConstantSDNode>(Shl2_1.getNode())->getSExtValue();
691 int32_t ValConst = 1 << (ShlConst+Shl2Const);
692 SDValue Val = CurDAG->getTargetConstant(-ValConst, MVT::i32);
693 if (ConstantSDNode *CN =
694 dyn_cast<ConstantSDNode>(Val.getNode()))
695 if (isInt<9>(CN->getSExtValue())) {
697 CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl, MVT::i32,
699 ReplaceUses(N, Result);
709 return SelectCode(N);
714 // If there is an zero_extend followed an intrinsic in DAG (this means - the
715 // result of the intrinsic is predicate); convert the zero_extend to
716 // transfer instruction.
718 // Zero extend -> transfer is lowered here. Otherwise, zero_extend will be
719 // converted into a MUX as predicate registers defined as 1 bit in the
720 // compiler. Architecture defines them as 8-bit registers.
721 // We want to preserve all the lower 8-bits and, not just 1 LSB bit.
723 SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
726 SDValue Op0 = N->getOperand(0);
727 EVT OpVT = Op0.getValueType();
728 unsigned OpBW = OpVT.getSizeInBits();
730 // Special handling for zero-extending a vector of booleans.
731 if (OpVT.isVector() && OpVT.getVectorElementType() == MVT::i1 && OpBW <= 64) {
732 SDNode *Mask = CurDAG->getMachineNode(Hexagon::C2_mask, dl, MVT::i64, Op0);
733 unsigned NE = OpVT.getVectorNumElements();
734 EVT ExVT = N->getValueType(0);
735 unsigned ES = ExVT.getVectorElementType().getSizeInBits();
736 uint64_t MV = 0, Bit = 1;
737 for (unsigned i = 0; i < NE; ++i) {
741 SDValue Ones = CurDAG->getTargetConstant(MV, MVT::i64);
742 SDNode *OnesReg = CurDAG->getMachineNode(Hexagon::CONST64_Int_Real, dl,
744 if (ExVT.getSizeInBits() == 32) {
745 SDNode *And = CurDAG->getMachineNode(Hexagon::A2_andp, dl, MVT::i64,
746 SDValue(Mask,0), SDValue(OnesReg,0));
747 SDValue SubR = CurDAG->getTargetConstant(Hexagon::subreg_loreg, MVT::i32);
748 return CurDAG->getMachineNode(Hexagon::EXTRACT_SUBREG, dl, ExVT,
749 SDValue(And,0), SubR);
751 return CurDAG->getMachineNode(Hexagon::A2_andp, dl, ExVT,
752 SDValue(Mask,0), SDValue(OnesReg,0));
755 SDNode *IsIntrinsic = N->getOperand(0).getNode();
756 if ((IsIntrinsic->getOpcode() == ISD::INTRINSIC_WO_CHAIN)) {
758 cast<ConstantSDNode>(IsIntrinsic->getOperand(0))->getZExtValue();
759 if (doesIntrinsicReturnPredicate(ID)) {
760 // Now we need to differentiate target data types.
761 if (N->getValueType(0) == MVT::i64) {
762 // Convert the zero_extend to Rs = Pd followed by A2_combinew(0,Rs).
763 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
764 SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
766 SDValue(IsIntrinsic, 0));
767 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl,
770 SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl,
771 MVT::i64, MVT::Other,
772 SDValue(Result_2, 0),
773 SDValue(Result_1, 0));
774 ReplaceUses(N, Result_3);
777 if (N->getValueType(0) == MVT::i32) {
778 // Convert the zero_extend to Rs = Pd
779 SDNode* RsPd = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
781 SDValue(IsIntrinsic, 0));
782 ReplaceUses(N, RsPd);
785 llvm_unreachable("Unexpected value type");
788 return SelectCode(N);
792 // Checking for intrinsics circular load/store, and bitreverse load/store
793 // instrisics in order to select the correct lowered operation.
795 SDNode *HexagonDAGToDAGISel::SelectIntrinsicWChain(SDNode *N) {
796 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
797 if (IntNo == Intrinsic::hexagon_circ_ldd ||
798 IntNo == Intrinsic::hexagon_circ_ldw ||
799 IntNo == Intrinsic::hexagon_circ_lduh ||
800 IntNo == Intrinsic::hexagon_circ_ldh ||
801 IntNo == Intrinsic::hexagon_circ_ldub ||
802 IntNo == Intrinsic::hexagon_circ_ldb) {
804 SDValue Chain = N->getOperand(0);
805 SDValue Base = N->getOperand(2);
806 SDValue Load = N->getOperand(3);
807 SDValue ModifierExpr = N->getOperand(4);
808 SDValue Offset = N->getOperand(5);
810 // We need to add the rerurn type for the load. This intrinsic has
811 // two return types, one for the load and one for the post-increment.
812 // Only the *_ld instructions push the extra return type, and bump the
813 // result node operand number correspondingly.
814 std::vector<EVT> ResTys;
816 unsigned memsize, align;
817 MVT MvtSize = MVT::i32;
819 if (IntNo == Intrinsic::hexagon_circ_ldd) {
820 ResTys.push_back(MVT::i32);
821 ResTys.push_back(MVT::i64);
822 opc = Hexagon::L2_loadrd_pci_pseudo;
825 } else if (IntNo == Intrinsic::hexagon_circ_ldw) {
826 ResTys.push_back(MVT::i32);
827 ResTys.push_back(MVT::i32);
828 opc = Hexagon::L2_loadri_pci_pseudo;
831 } else if (IntNo == Intrinsic::hexagon_circ_ldh) {
832 ResTys.push_back(MVT::i32);
833 ResTys.push_back(MVT::i32);
834 opc = Hexagon::L2_loadrh_pci_pseudo;
838 } else if (IntNo == Intrinsic::hexagon_circ_lduh) {
839 ResTys.push_back(MVT::i32);
840 ResTys.push_back(MVT::i32);
841 opc = Hexagon::L2_loadruh_pci_pseudo;
845 } else if (IntNo == Intrinsic::hexagon_circ_ldb) {
846 ResTys.push_back(MVT::i32);
847 ResTys.push_back(MVT::i32);
848 opc = Hexagon::L2_loadrb_pci_pseudo;
852 } else if (IntNo == Intrinsic::hexagon_circ_ldub) {
853 ResTys.push_back(MVT::i32);
854 ResTys.push_back(MVT::i32);
855 opc = Hexagon::L2_loadrub_pci_pseudo;
860 llvm_unreachable("no opc");
862 ResTys.push_back(MVT::Other);
864 // Copy over the arguments, which are the same mostly.
865 SmallVector<SDValue, 5> Ops;
868 Ops.push_back(ModifierExpr);
869 int32_t Val = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
870 Ops.push_back(CurDAG->getTargetConstant(Val, MVT::i32));
871 Ops.push_back(Chain);
872 SDNode* Result = CurDAG->getMachineNode(opc, dl, ResTys, Ops);
875 MachineMemOperand *Mem =
876 MF->getMachineMemOperand(MachinePointerInfo(),
877 MachineMemOperand::MOStore, memsize, align);
878 if (MvtSize != MVT::i32)
879 ST = CurDAG->getTruncStore(Chain, dl, SDValue(Result, 1), Load,
882 ST = CurDAG->getStore(Chain, dl, SDValue(Result, 1), Load, Mem);
884 SDNode* Store = SelectStore(ST.getNode());
886 const SDValue Froms[] = { SDValue(N, 0),
888 const SDValue Tos[] = { SDValue(Result, 0),
890 ReplaceUses(Froms, Tos, 2);
894 if (IntNo == Intrinsic::hexagon_brev_ldd ||
895 IntNo == Intrinsic::hexagon_brev_ldw ||
896 IntNo == Intrinsic::hexagon_brev_ldh ||
897 IntNo == Intrinsic::hexagon_brev_lduh ||
898 IntNo == Intrinsic::hexagon_brev_ldb ||
899 IntNo == Intrinsic::hexagon_brev_ldub) {
901 SDValue Chain = N->getOperand(0);
902 SDValue Base = N->getOperand(2);
903 SDValue Load = N->getOperand(3);
904 SDValue ModifierExpr = N->getOperand(4);
906 // We need to add the rerurn type for the load. This intrinsic has
907 // two return types, one for the load and one for the post-increment.
908 std::vector<EVT> ResTys;
910 unsigned memsize, align;
911 MVT MvtSize = MVT::i32;
913 if (IntNo == Intrinsic::hexagon_brev_ldd) {
914 ResTys.push_back(MVT::i32);
915 ResTys.push_back(MVT::i64);
916 opc = Hexagon::L2_loadrd_pbr_pseudo;
919 } else if (IntNo == Intrinsic::hexagon_brev_ldw) {
920 ResTys.push_back(MVT::i32);
921 ResTys.push_back(MVT::i32);
922 opc = Hexagon::L2_loadri_pbr_pseudo;
925 } else if (IntNo == Intrinsic::hexagon_brev_ldh) {
926 ResTys.push_back(MVT::i32);
927 ResTys.push_back(MVT::i32);
928 opc = Hexagon::L2_loadrh_pbr_pseudo;
932 } else if (IntNo == Intrinsic::hexagon_brev_lduh) {
933 ResTys.push_back(MVT::i32);
934 ResTys.push_back(MVT::i32);
935 opc = Hexagon::L2_loadruh_pbr_pseudo;
939 } else if (IntNo == Intrinsic::hexagon_brev_ldb) {
940 ResTys.push_back(MVT::i32);
941 ResTys.push_back(MVT::i32);
942 opc = Hexagon::L2_loadrb_pbr_pseudo;
946 } else if (IntNo == Intrinsic::hexagon_brev_ldub) {
947 ResTys.push_back(MVT::i32);
948 ResTys.push_back(MVT::i32);
949 opc = Hexagon::L2_loadrub_pbr_pseudo;
954 llvm_unreachable("no opc");
956 ResTys.push_back(MVT::Other);
958 // Copy over the arguments, which are the same mostly.
959 SmallVector<SDValue, 4> Ops;
962 Ops.push_back(ModifierExpr);
963 Ops.push_back(Chain);
964 SDNode* Result = CurDAG->getMachineNode(opc, dl, ResTys, Ops);
966 MachineMemOperand *Mem =
967 MF->getMachineMemOperand(MachinePointerInfo(),
968 MachineMemOperand::MOStore, memsize, align);
969 if (MvtSize != MVT::i32)
970 ST = CurDAG->getTruncStore(Chain, dl, SDValue(Result, 1), Load,
973 ST = CurDAG->getStore(Chain, dl, SDValue(Result, 1), Load, Mem);
975 SDNode* Store = SelectStore(ST.getNode());
977 const SDValue Froms[] = { SDValue(N, 0),
979 const SDValue Tos[] = { SDValue(Result, 0),
981 ReplaceUses(Froms, Tos, 2);
985 return SelectCode(N);
989 // Checking for intrinsics which have predicate registers as operand(s)
990 // and lowering to the actual intrinsic.
992 SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
993 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
996 case Intrinsic::hexagon_S2_vsplatrb:
999 case Intrinsic::hexagon_S2_vsplatrh:
1003 return SelectCode(N);
1006 SDValue const &V = N->getOperand(1);
1008 if (isValueExtension(V, Bits, U)) {
1009 SDValue R = CurDAG->getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
1010 N->getOperand(0), U);
1011 return SelectCode(R.getNode());
1013 return SelectCode(N);
1017 // Map floating point constant values.
1019 SDNode *HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) {
1021 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
1022 APFloat APF = CN->getValueAPF();
1023 if (N->getValueType(0) == MVT::f32) {
1024 return CurDAG->getMachineNode(Hexagon::TFRI_f, dl, MVT::f32,
1025 CurDAG->getTargetConstantFP(APF.convertToFloat(), MVT::f32));
1027 else if (N->getValueType(0) == MVT::f64) {
1028 return CurDAG->getMachineNode(Hexagon::CONST64_Float_Real, dl, MVT::f64,
1029 CurDAG->getTargetConstantFP(APF.convertToDouble(), MVT::f64));
1032 return SelectCode(N);
1036 // Map predicate true (encoded as -1 in LLVM) to a XOR.
1038 SDNode *HexagonDAGToDAGISel::SelectConstant(SDNode *N) {
1040 if (N->getValueType(0) == MVT::i1) {
1042 int32_t Val = cast<ConstantSDNode>(N)->getSExtValue();
1044 Result = CurDAG->getMachineNode(Hexagon::TFR_PdTrue, dl, MVT::i1);
1045 } else if (Val == 0) {
1046 Result = CurDAG->getMachineNode(Hexagon::TFR_PdFalse, dl, MVT::i1);
1049 ReplaceUses(N, Result);
1054 return SelectCode(N);
1059 // Map add followed by a asr -> asr +=.
1061 SDNode *HexagonDAGToDAGISel::SelectAdd(SDNode *N) {
1063 if (N->getValueType(0) != MVT::i32) {
1064 return SelectCode(N);
1066 // Identify nodes of the form: add(asr(...)).
1067 SDNode* Src1 = N->getOperand(0).getNode();
1068 if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse()
1069 || Src1->getValueType(0) != MVT::i32) {
1070 return SelectCode(N);
1073 // Build Rd = Rd' + asr(Rs, Rt). The machine constraints will ensure that
1074 // Rd and Rd' are assigned to the same register
1075 SDNode* Result = CurDAG->getMachineNode(Hexagon::S2_asr_r_r_acc, dl, MVT::i32,
1077 Src1->getOperand(0),
1078 Src1->getOperand(1));
1079 ReplaceUses(N, Result);
1085 // Map the following, where possible.
1086 // AND/FABS -> clrbit
1088 // XOR/FNEG ->toggle_bit.
1090 SDNode *HexagonDAGToDAGISel::SelectBitOp(SDNode *N) {
1092 EVT ValueVT = N->getValueType(0);
1094 // We handle only 32 and 64-bit bit ops.
1095 if (!(ValueVT == MVT::i32 || ValueVT == MVT::i64 ||
1096 ValueVT == MVT::f32 || ValueVT == MVT::f64))
1097 return SelectCode(N);
1099 // We handly only fabs and fneg for V5.
1100 unsigned Opc = N->getOpcode();
1101 if ((Opc == ISD::FABS || Opc == ISD::FNEG) && !HST->hasV5TOps())
1102 return SelectCode(N);
1105 if (Opc != ISD::FABS && Opc != ISD::FNEG) {
1106 if (N->getOperand(1).getOpcode() == ISD::Constant)
1107 Val = cast<ConstantSDNode>((N)->getOperand(1))->getSExtValue();
1109 return SelectCode(N);
1112 if (Opc == ISD::AND) {
1113 if (((ValueVT == MVT::i32) &&
1114 (!((Val & 0x80000000) || (Val & 0x7fffffff)))) ||
1115 ((ValueVT == MVT::i64) &&
1116 (!((Val & 0x8000000000000000) || (Val & 0x7fffffff)))))
1117 // If it's simple AND, do the normal op.
1118 return SelectCode(N);
1123 // If OR or AND is being fed by shl, srl and, sra don't do this change,
1124 // because Hexagon provide |= &= on shl, srl, and sra.
1125 // Traverse the DAG to see if there is shl, srl and sra.
1126 if (Opc == ISD::OR || Opc == ISD::AND) {
1127 switch (N->getOperand(0)->getOpcode()) {
1132 return SelectCode(N);
1136 // Make sure it's power of 2.
1137 unsigned bitpos = 0;
1138 if (Opc != ISD::FABS && Opc != ISD::FNEG) {
1139 if (((ValueVT == MVT::i32) && !isPowerOf2_32(Val)) ||
1140 ((ValueVT == MVT::i64) && !isPowerOf2_64(Val)))
1141 return SelectCode(N);
1143 // Get the bit position.
1144 bitpos = countTrailingZeros(uint64_t(Val));
1146 // For fabs and fneg, it's always the 31st bit.
1150 unsigned BitOpc = 0;
1151 // Set the right opcode for bitwise operations.
1153 default: llvm_unreachable("Only bit-wise/abs/neg operations are allowed.");
1156 BitOpc = Hexagon::S2_clrbit_i;
1159 BitOpc = Hexagon::S2_setbit_i;
1163 BitOpc = Hexagon::S2_togglebit_i;
1168 // Get the right SDVal for the opcode.
1169 SDValue SDVal = CurDAG->getTargetConstant(bitpos, MVT::i32);
1171 if (ValueVT == MVT::i32 || ValueVT == MVT::f32) {
1172 Result = CurDAG->getMachineNode(BitOpc, dl, ValueVT,
1173 N->getOperand(0), SDVal);
1175 // 64-bit gymnastic to use REG_SEQUENCE. But it's worth it.
1177 if (ValueVT == MVT::i64)
1178 SubValueVT = MVT::i32;
1180 SubValueVT = MVT::f32;
1182 SDNode *Reg = N->getOperand(0).getNode();
1183 SDValue RegClass = CurDAG->getTargetConstant(Hexagon::DoubleRegsRegClassID,
1186 SDValue SubregHiIdx = CurDAG->getTargetConstant(Hexagon::subreg_hireg,
1188 SDValue SubregLoIdx = CurDAG->getTargetConstant(Hexagon::subreg_loreg,
1191 SDValue SubregHI = CurDAG->getTargetExtractSubreg(Hexagon::subreg_hireg, dl,
1192 MVT::i32, SDValue(Reg, 0));
1194 SDValue SubregLO = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg, dl,
1195 MVT::i32, SDValue(Reg, 0));
1197 // Clear/set/toggle hi or lo registers depending on the bit position.
1198 if (SubValueVT != MVT::f32 && bitpos < 32) {
1199 SDNode *Result0 = CurDAG->getMachineNode(BitOpc, dl, SubValueVT,
1201 const SDValue Ops[] = { RegClass, SubregHI, SubregHiIdx,
1202 SDValue(Result0, 0), SubregLoIdx };
1203 Result = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
1206 if (Opc != ISD::FABS && Opc != ISD::FNEG)
1207 SDVal = CurDAG->getTargetConstant(bitpos-32, MVT::i32);
1208 SDNode *Result0 = CurDAG->getMachineNode(BitOpc, dl, SubValueVT,
1210 const SDValue Ops[] = { RegClass, SDValue(Result0, 0), SubregHiIdx,
1211 SubregLO, SubregLoIdx };
1212 Result = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
1217 ReplaceUses(N, Result);
1222 SDNode *HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) {
1223 MachineFrameInfo *MFI = MF->getFrameInfo();
1224 const HexagonFrameLowering *HFI = HST->getFrameLowering();
1225 int FX = cast<FrameIndexSDNode>(N)->getIndex();
1226 unsigned StkA = HFI->getStackAlignment();
1227 unsigned MaxA = MFI->getMaxAlignment();
1228 SDValue FI = CurDAG->getTargetFrameIndex(FX, MVT::i32);
1229 SDValue Zero = CurDAG->getTargetConstant(0, MVT::i32);
1234 // - the object is fixed, or
1235 // - there are no objects with higher-than-default alignment, or
1236 // - there are no dynamically allocated objects.
1237 // Otherwise, use TFR_FIA.
1238 if (FX < 0 || MaxA <= StkA || !MFI->hasVarSizedObjects()) {
1239 R = CurDAG->getMachineNode(Hexagon::TFR_FI, DL, MVT::i32, FI, Zero);
1241 auto &HMFI = *MF->getInfo<HexagonMachineFunctionInfo>();
1242 unsigned AR = HMFI.getStackAlignBaseVReg();
1243 SDValue CH = CurDAG->getEntryNode();
1244 SDValue Ops[] = { CurDAG->getCopyFromReg(CH, DL, AR, MVT::i32), FI, Zero };
1245 R = CurDAG->getMachineNode(Hexagon::TFR_FIA, DL, MVT::i32, Ops);
1248 if (N->getHasDebugValue())
1249 CurDAG->TransferDbgValues(SDValue(N, 0), SDValue(R, 0));
1254 SDNode *HexagonDAGToDAGISel::Select(SDNode *N) {
1255 if (N->isMachineOpcode()) {
1257 return nullptr; // Already selected.
1260 switch (N->getOpcode()) {
1262 return SelectConstant(N);
1264 case ISD::ConstantFP:
1265 return SelectConstantFP(N);
1267 case ISD::FrameIndex:
1268 return SelectFrameIndex(N);
1271 return SelectAdd(N);
1274 return SelectSHL(N);
1277 return SelectLoad(N);
1280 return SelectStore(N);
1283 return SelectMul(N);
1290 return SelectBitOp(N);
1292 case ISD::ZERO_EXTEND:
1293 return SelectZeroExtend(N);
1295 case ISD::INTRINSIC_W_CHAIN:
1296 return SelectIntrinsicWChain(N);
1298 case ISD::INTRINSIC_WO_CHAIN:
1299 return SelectIntrinsicWOChain(N);
1302 return SelectCode(N);
1305 bool HexagonDAGToDAGISel::
1306 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
1307 std::vector<SDValue> &OutOps) {
1308 SDValue Inp = Op, Res;
1310 switch (ConstraintID) {
1313 case InlineAsm::Constraint_i:
1314 case InlineAsm::Constraint_o: // Offsetable.
1315 case InlineAsm::Constraint_v: // Not offsetable.
1316 case InlineAsm::Constraint_m: // Memory.
1317 if (SelectAddrFI(Inp, Res))
1318 OutOps.push_back(Res);
1320 OutOps.push_back(Inp);
1324 OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
1328 void HexagonDAGToDAGISel::PreprocessISelDAG() {
1329 SelectionDAG &DAG = *CurDAG;
1330 std::vector<SDNode*> Nodes;
1331 for (auto I = DAG.allnodes_begin(), E = DAG.allnodes_end(); I != E; ++I)
1334 // Simplify: (or (select c x 0) z) -> (select c (or x z) z)
1335 // (or (select c 0 y) z) -> (select c z (or y z))
1336 // This may not be the right thing for all targets, so do it here.
1337 for (auto I: Nodes) {
1338 if (I->getOpcode() != ISD::OR)
1341 auto IsZero = [] (const SDValue &V) -> bool {
1342 if (ConstantSDNode *SC = dyn_cast<ConstantSDNode>(V.getNode()))
1343 return SC->isNullValue();
1346 auto IsSelect0 = [IsZero] (const SDValue &Op) -> bool {
1347 if (Op.getOpcode() != ISD::SELECT)
1349 return IsZero(Op.getOperand(1)) || IsZero(Op.getOperand(2));
1352 SDValue N0 = I->getOperand(0), N1 = I->getOperand(1);
1353 EVT VT = I->getValueType(0);
1354 bool SelN0 = IsSelect0(N0);
1355 SDValue SOp = SelN0 ? N0 : N1;
1356 SDValue VOp = SelN0 ? N1 : N0;
1358 if (SOp.getOpcode() == ISD::SELECT && SOp.getNode()->hasOneUse()) {
1359 SDValue SC = SOp.getOperand(0);
1360 SDValue SX = SOp.getOperand(1);
1361 SDValue SY = SOp.getOperand(2);
1364 SDValue NewOr = DAG.getNode(ISD::OR, DLS, VT, SX, VOp);
1365 SDValue NewSel = DAG.getNode(ISD::SELECT, DLS, VT, SC, NewOr, VOp);
1366 DAG.ReplaceAllUsesWith(I, NewSel.getNode());
1367 } else if (IsZero(SX)) {
1368 SDValue NewOr = DAG.getNode(ISD::OR, DLS, VT, SY, VOp);
1369 SDValue NewSel = DAG.getNode(ISD::SELECT, DLS, VT, SC, VOp, NewOr);
1370 DAG.ReplaceAllUsesWith(I, NewSel.getNode());
1376 void HexagonDAGToDAGISel::EmitFunctionEntryCode() {
1377 auto &HST = static_cast<const HexagonSubtarget&>(MF->getSubtarget());
1378 auto &HFI = *HST.getFrameLowering();
1379 if (!HFI.needsAligna(*MF))
1382 MachineFrameInfo *MFI = MF->getFrameInfo();
1383 MachineBasicBlock *EntryBB = MF->begin();
1384 unsigned AR = FuncInfo->CreateReg(MVT::i32);
1385 unsigned MaxA = MFI->getMaxAlignment();
1386 auto &HII = *HST.getInstrInfo();
1387 BuildMI(EntryBB, DebugLoc(), HII.get(Hexagon::ALIGNA), AR)
1389 MF->getInfo<HexagonMachineFunctionInfo>()->setStackAlignBaseVReg(AR);
1392 // Match a frame index that can be used in an addressing mode.
1393 bool HexagonDAGToDAGISel::SelectAddrFI(SDValue& N, SDValue &R) {
1394 if (N.getOpcode() != ISD::FrameIndex)
1396 auto &HFI = *HST->getFrameLowering();
1397 MachineFrameInfo *MFI = MF->getFrameInfo();
1398 int FX = cast<FrameIndexSDNode>(N)->getIndex();
1399 if (!MFI->isFixedObjectIndex(FX) && HFI.needsAligna(*MF))
1401 R = CurDAG->getTargetFrameIndex(FX, MVT::i32);
1405 inline bool HexagonDAGToDAGISel::SelectAddrGA(SDValue &N, SDValue &R) {
1406 return SelectGlobalAddress(N, R, false);
1409 inline bool HexagonDAGToDAGISel::SelectAddrGP(SDValue &N, SDValue &R) {
1410 return SelectGlobalAddress(N, R, true);
1413 bool HexagonDAGToDAGISel::SelectGlobalAddress(SDValue &N, SDValue &R,
1415 switch (N.getOpcode()) {
1417 SDValue N0 = N.getOperand(0);
1418 SDValue N1 = N.getOperand(1);
1419 unsigned GAOpc = N0.getOpcode();
1420 if (UseGP && GAOpc != HexagonISD::CONST32_GP)
1422 if (!UseGP && GAOpc != HexagonISD::CONST32)
1424 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N1)) {
1425 SDValue Addr = N0.getOperand(0);
1426 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Addr)) {
1427 if (GA->getOpcode() == ISD::TargetGlobalAddress) {
1428 uint64_t NewOff = GA->getOffset() + (uint64_t)Const->getSExtValue();
1429 R = CurDAG->getTargetGlobalAddress(GA->getGlobal(), SDLoc(Const),
1430 N.getValueType(), NewOff);
1437 case HexagonISD::CONST32:
1438 // The operand(0) of CONST32 is TargetGlobalAddress, which is what we
1439 // want in the instruction.
1441 R = N.getOperand(0);
1443 case HexagonISD::CONST32_GP:
1445 R = N.getOperand(0);
1454 bool HexagonDAGToDAGISel::isValueExtension(const SDValue &Val,
1455 unsigned FromBits, SDValue &Src) {
1456 unsigned Opc = Val.getOpcode();
1458 case ISD::SIGN_EXTEND:
1459 case ISD::ZERO_EXTEND:
1460 case ISD::ANY_EXTEND: {
1461 SDValue const &Op0 = Val.getOperand(0);
1462 EVT T = Op0.getValueType();
1463 if (T.isInteger() && T.getSizeInBits() == FromBits) {
1469 case ISD::SIGN_EXTEND_INREG:
1470 case ISD::AssertSext:
1471 case ISD::AssertZext:
1472 if (Val.getOperand(0).getValueType().isInteger()) {
1473 VTSDNode *T = cast<VTSDNode>(Val.getOperand(1));
1474 if (T->getVT().getSizeInBits() == FromBits) {
1475 Src = Val.getOperand(0);
1481 // Check if this is an AND with "FromBits" of lower bits set to 1.
1482 uint64_t FromMask = (1 << FromBits) - 1;
1483 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) {
1484 if (C->getZExtValue() == FromMask) {
1485 Src = Val.getOperand(1);
1489 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(1))) {
1490 if (C->getZExtValue() == FromMask) {
1491 Src = Val.getOperand(0);
1499 // OR/XOR with the lower "FromBits" bits set to 0.
1500 uint64_t FromMask = (1 << FromBits) - 1;
1501 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) {
1502 if ((C->getZExtValue() & FromMask) == 0) {
1503 Src = Val.getOperand(1);
1507 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(1))) {
1508 if ((C->getZExtValue() & FromMask) == 0) {
1509 Src = Val.getOperand(0);