1 //===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the Hexagon target.
12 //===----------------------------------------------------------------------===//
15 #include "HexagonISelLowering.h"
16 #include "HexagonMachineFunctionInfo.h"
17 #include "HexagonTargetMachine.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/FunctionLoweringInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/SelectionDAGISel.h"
22 #include "llvm/IR/Intrinsics.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Compiler.h"
25 #include "llvm/Support/Debug.h"
28 #define DEBUG_TYPE "hexagon-isel"
32 MaxNumOfUsesForConstExtenders("ga-max-num-uses-for-constant-extenders",
33 cl::Hidden, cl::init(2),
34 cl::desc("Maximum number of uses of a global address such that we still us a"
35 "constant extended instruction"));
37 //===----------------------------------------------------------------------===//
38 // Instruction Selector Implementation
39 //===----------------------------------------------------------------------===//
42 void initializeHexagonDAGToDAGISelPass(PassRegistry&);
45 //===--------------------------------------------------------------------===//
46 /// HexagonDAGToDAGISel - Hexagon specific code to select Hexagon machine
47 /// instructions for SelectionDAG operations.
50 class HexagonDAGToDAGISel : public SelectionDAGISel {
51 const HexagonTargetMachine& HTM;
52 const HexagonSubtarget *HST;
53 const HexagonInstrInfo *HII;
54 const HexagonRegisterInfo *HRI;
56 explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm,
57 CodeGenOpt::Level OptLevel)
58 : SelectionDAGISel(tm, OptLevel), HTM(tm), HST(nullptr), HII(nullptr),
60 initializeHexagonDAGToDAGISelPass(*PassRegistry::getPassRegistry());
63 bool runOnMachineFunction(MachineFunction &MF) override {
64 // Reset the subtarget each time through.
65 HST = &MF.getSubtarget<HexagonSubtarget>();
66 HII = HST->getInstrInfo();
67 HRI = HST->getRegisterInfo();
68 SelectionDAGISel::runOnMachineFunction(MF);
72 virtual void PreprocessISelDAG() override;
73 virtual void EmitFunctionEntryCode() override;
75 SDNode *Select(SDNode *N) override;
77 // Complex Pattern Selectors.
78 inline bool SelectAddrGA(SDValue &N, SDValue &R);
79 inline bool SelectAddrGP(SDValue &N, SDValue &R);
80 bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP);
81 bool SelectAddrFI(SDValue &N, SDValue &R);
83 const char *getPassName() const override {
84 return "Hexagon DAG->DAG Pattern Instruction Selection";
87 SDNode *SelectFrameIndex(SDNode *N);
88 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
89 /// inline asm expressions.
90 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
91 unsigned ConstraintID,
92 std::vector<SDValue> &OutOps) override;
93 SDNode *SelectLoad(SDNode *N);
94 SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl);
95 SDNode *SelectIndexedLoad(LoadSDNode *LD, SDLoc dl);
96 SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
98 SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
100 SDNode *SelectBaseOffsetStore(StoreSDNode *ST, SDLoc dl);
101 SDNode *SelectIndexedStore(StoreSDNode *ST, SDLoc dl);
102 SDNode *SelectStore(SDNode *N);
103 SDNode *SelectSHL(SDNode *N);
104 SDNode *SelectMul(SDNode *N);
105 SDNode *SelectZeroExtend(SDNode *N);
106 SDNode *SelectIntrinsicWChain(SDNode *N);
107 SDNode *SelectIntrinsicWOChain(SDNode *N);
108 SDNode *SelectConstant(SDNode *N);
109 SDNode *SelectConstantFP(SDNode *N);
110 SDNode *SelectAdd(SDNode *N);
111 SDNode *SelectBitOp(SDNode *N);
113 // XformMskToBitPosU5Imm - Returns the bit position which
114 // the single bit 32 bit mask represents.
115 // Used in Clr and Set bit immediate memops.
116 SDValue XformMskToBitPosU5Imm(uint32_t Imm, SDLoc DL) {
118 bitPos = Log2_32(Imm);
119 assert(bitPos >= 0 && bitPos < 32 &&
120 "Constant out of range for 32 BitPos Memops");
121 return CurDAG->getTargetConstant(bitPos, DL, MVT::i32);
124 // XformMskToBitPosU4Imm - Returns the bit position which the single-bit
125 // 16 bit mask represents. Used in Clr and Set bit immediate memops.
126 SDValue XformMskToBitPosU4Imm(uint16_t Imm, SDLoc DL) {
127 return XformMskToBitPosU5Imm(Imm, DL);
130 // XformMskToBitPosU3Imm - Returns the bit position which the single-bit
131 // 8 bit mask represents. Used in Clr and Set bit immediate memops.
132 SDValue XformMskToBitPosU3Imm(uint8_t Imm, SDLoc DL) {
133 return XformMskToBitPosU5Imm(Imm, DL);
136 // Return true if there is exactly one bit set in V, i.e., if V is one of the
137 // following integers: 2^0, 2^1, ..., 2^31.
138 bool ImmIsSingleBit(uint32_t v) const {
139 return isPowerOf2_32(v);
142 // XformM5ToU5Imm - Return a target constant with the specified value, of
143 // type i32 where the negative literal is transformed into a positive literal
144 // for use in -= memops.
145 inline SDValue XformM5ToU5Imm(signed Imm, SDLoc DL) {
146 assert((Imm >= -31 && Imm <= -1) && "Constant out of range for Memops");
147 return CurDAG->getTargetConstant(-Imm, DL, MVT::i32);
150 // XformU7ToU7M1Imm - Return a target constant decremented by 1, in range
151 // [1..128], used in cmpb.gtu instructions.
152 inline SDValue XformU7ToU7M1Imm(signed Imm, SDLoc DL) {
153 assert((Imm >= 1 && Imm <= 128) && "Constant out of range for cmpb op");
154 return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i8);
157 // XformS8ToS8M1Imm - Return a target constant decremented by 1.
158 inline SDValue XformSToSM1Imm(signed Imm, SDLoc DL) {
159 return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i32);
162 // XformU8ToU8M1Imm - Return a target constant decremented by 1.
163 inline SDValue XformUToUM1Imm(unsigned Imm, SDLoc DL) {
164 assert((Imm >= 1) && "Cannot decrement unsigned int less than 1");
165 return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i32);
168 // XformSToSM2Imm - Return a target constant decremented by 2.
169 inline SDValue XformSToSM2Imm(unsigned Imm, SDLoc DL) {
170 return CurDAG->getTargetConstant(Imm - 2, DL, MVT::i32);
173 // XformSToSM3Imm - Return a target constant decremented by 3.
174 inline SDValue XformSToSM3Imm(unsigned Imm, SDLoc DL) {
175 return CurDAG->getTargetConstant(Imm - 3, DL, MVT::i32);
178 // Include the pieces autogenerated from the target description.
179 #include "HexagonGenDAGISel.inc"
182 bool isValueExtension(const SDValue &Val, unsigned FromBits, SDValue &Src);
183 }; // end HexagonDAGToDAGISel
184 } // end anonymous namespace
187 /// createHexagonISelDag - This pass converts a legalized DAG into a
188 /// Hexagon-specific DAG, ready for instruction scheduling.
191 FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
192 CodeGenOpt::Level OptLevel) {
193 return new HexagonDAGToDAGISel(TM, OptLevel);
197 static void initializePassOnce(PassRegistry &Registry) {
198 const char *Name = "Hexagon DAG->DAG Pattern Instruction Selection";
199 PassInfo *PI = new PassInfo(Name, "hexagon-isel",
200 &SelectionDAGISel::ID, nullptr, false, false);
201 Registry.registerPass(*PI, true);
204 void llvm::initializeHexagonDAGToDAGISelPass(PassRegistry &Registry) {
205 CALL_ONCE_INITIALIZATION(initializePassOnce)
209 // Intrinsics that return a a predicate.
210 static bool doesIntrinsicReturnPredicate(unsigned ID) {
214 case Intrinsic::hexagon_C2_cmpeq:
215 case Intrinsic::hexagon_C2_cmpgt:
216 case Intrinsic::hexagon_C2_cmpgtu:
217 case Intrinsic::hexagon_C2_cmpgtup:
218 case Intrinsic::hexagon_C2_cmpgtp:
219 case Intrinsic::hexagon_C2_cmpeqp:
220 case Intrinsic::hexagon_C2_bitsset:
221 case Intrinsic::hexagon_C2_bitsclr:
222 case Intrinsic::hexagon_C2_cmpeqi:
223 case Intrinsic::hexagon_C2_cmpgti:
224 case Intrinsic::hexagon_C2_cmpgtui:
225 case Intrinsic::hexagon_C2_cmpgei:
226 case Intrinsic::hexagon_C2_cmpgeui:
227 case Intrinsic::hexagon_C2_cmplt:
228 case Intrinsic::hexagon_C2_cmpltu:
229 case Intrinsic::hexagon_C2_bitsclri:
230 case Intrinsic::hexagon_C2_and:
231 case Intrinsic::hexagon_C2_or:
232 case Intrinsic::hexagon_C2_xor:
233 case Intrinsic::hexagon_C2_andn:
234 case Intrinsic::hexagon_C2_not:
235 case Intrinsic::hexagon_C2_orn:
236 case Intrinsic::hexagon_C2_pxfer_map:
237 case Intrinsic::hexagon_C2_any8:
238 case Intrinsic::hexagon_C2_all8:
239 case Intrinsic::hexagon_A2_vcmpbeq:
240 case Intrinsic::hexagon_A2_vcmpbgtu:
241 case Intrinsic::hexagon_A2_vcmpheq:
242 case Intrinsic::hexagon_A2_vcmphgt:
243 case Intrinsic::hexagon_A2_vcmphgtu:
244 case Intrinsic::hexagon_A2_vcmpweq:
245 case Intrinsic::hexagon_A2_vcmpwgt:
246 case Intrinsic::hexagon_A2_vcmpwgtu:
247 case Intrinsic::hexagon_C2_tfrrp:
248 case Intrinsic::hexagon_S2_tstbit_i:
249 case Intrinsic::hexagon_S2_tstbit_r:
254 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
257 SDValue Chain = LD->getChain();
258 EVT LoadedVT = LD->getMemoryVT();
259 SDValue Base = LD->getBasePtr();
260 SDValue Offset = LD->getOffset();
261 SDNode *OffsetNode = Offset.getNode();
262 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
264 if (HII->isValidAutoIncImm(LoadedVT, Val)) {
265 SDValue TargetConst = CurDAG->getTargetConstant(Val, dl, MVT::i32);
266 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32,
267 MVT::Other, Base, TargetConst,
269 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
270 SDValue(Result_1, 0));
271 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
272 MemOp[0] = LD->getMemOperand();
273 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
274 const SDValue Froms[] = { SDValue(LD, 0),
277 const SDValue Tos[] = { SDValue(Result_2, 0),
278 SDValue(Result_1, 1),
279 SDValue(Result_1, 2) };
280 ReplaceUses(Froms, Tos, 3);
284 SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
285 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
286 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Other,
287 Base, TargetConst0, Chain);
288 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
289 SDValue(Result_1, 0));
290 SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
291 Base, TargetConstVal,
292 SDValue(Result_1, 1));
293 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
294 MemOp[0] = LD->getMemOperand();
295 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
296 const SDValue Froms[] = { SDValue(LD, 0),
299 const SDValue Tos[] = { SDValue(Result_2, 0),
300 SDValue(Result_3, 0),
301 SDValue(Result_1, 1) };
302 ReplaceUses(Froms, Tos, 3);
307 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
310 SDValue Chain = LD->getChain();
311 EVT LoadedVT = LD->getMemoryVT();
312 SDValue Base = LD->getBasePtr();
313 SDValue Offset = LD->getOffset();
314 SDNode *OffsetNode = Offset.getNode();
315 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
317 if (HII->isValidAutoIncImm(LoadedVT, Val)) {
318 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
319 SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
320 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
321 MVT::i32, MVT::Other, Base,
322 TargetConstVal, Chain);
323 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A4_combineir, dl,
324 MVT::i64, MVT::Other,
326 SDValue(Result_1,0));
327 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
328 MemOp[0] = LD->getMemOperand();
329 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
330 const SDValue Froms[] = { SDValue(LD, 0),
333 const SDValue Tos[] = { SDValue(Result_2, 0),
334 SDValue(Result_1, 1),
335 SDValue(Result_1, 2) };
336 ReplaceUses(Froms, Tos, 3);
340 // Generate an indirect load.
341 SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
342 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
343 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
344 MVT::Other, Base, TargetConst0,
346 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A4_combineir, dl,
347 MVT::i64, MVT::Other,
349 SDValue(Result_1,0));
350 // Add offset to base.
351 SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
352 Base, TargetConstVal,
353 SDValue(Result_1, 1));
354 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
355 MemOp[0] = LD->getMemOperand();
356 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
357 const SDValue Froms[] = { SDValue(LD, 0),
360 const SDValue Tos[] = { SDValue(Result_2, 0), // Load value.
361 SDValue(Result_3, 0), // New address.
362 SDValue(Result_1, 1) };
363 ReplaceUses(Froms, Tos, 3);
368 SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
369 SDValue Chain = LD->getChain();
370 SDValue Base = LD->getBasePtr();
371 SDValue Offset = LD->getOffset();
372 SDNode *OffsetNode = Offset.getNode();
373 // Get the constant value.
374 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
375 EVT LoadedVT = LD->getMemoryVT();
378 // Check for zero extended loads. Treat any-extend loads as zero extended
380 ISD::LoadExtType ExtType = LD->getExtensionType();
381 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD);
382 bool HasVecOffset = false;
384 // Figure out the opcode.
385 if (LoadedVT == MVT::i64) {
386 if (HII->isValidAutoIncImm(LoadedVT, Val))
387 Opcode = Hexagon::L2_loadrd_pi;
389 Opcode = Hexagon::L2_loadrd_io;
390 } else if (LoadedVT == MVT::i32) {
391 if (HII->isValidAutoIncImm(LoadedVT, Val))
392 Opcode = Hexagon::L2_loadri_pi;
394 Opcode = Hexagon::L2_loadri_io;
395 } else if (LoadedVT == MVT::i16) {
396 if (HII->isValidAutoIncImm(LoadedVT, Val))
397 Opcode = IsZeroExt ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadrh_pi;
399 Opcode = IsZeroExt ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io;
400 } else if (LoadedVT == MVT::i8) {
401 if (HII->isValidAutoIncImm(LoadedVT, Val))
402 Opcode = IsZeroExt ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrb_pi;
404 Opcode = IsZeroExt ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io;
405 } else if (LoadedVT == MVT::v16i32 || LoadedVT == MVT::v8i64 ||
406 LoadedVT == MVT::v32i16 || LoadedVT == MVT::v64i8) {
408 if (HII->isValidAutoIncImm(LoadedVT, Val)) {
409 Opcode = Hexagon::V6_vL32b_pi;
412 Opcode = Hexagon::V6_vL32b_ai;
414 } else if (LoadedVT == MVT::v32i32 || LoadedVT == MVT::v16i64 ||
415 LoadedVT == MVT::v64i16 || LoadedVT == MVT::v128i8) {
417 if (HII->isValidAutoIncImm(LoadedVT, Val)) {
418 Opcode = Hexagon::V6_vL32b_pi_128B;
421 Opcode = Hexagon::V6_vL32b_ai_128B;
423 llvm_unreachable("unknown memory type");
425 // For zero extended i64 loads, we need to add combine instructions.
426 if (LD->getValueType(0) == MVT::i64 && IsZeroExt)
427 return SelectIndexedLoadZeroExtend64(LD, Opcode, dl);
428 // Handle sign extended i64 loads.
429 if (LD->getValueType(0) == MVT::i64 && ExtType == ISD::SEXTLOAD)
430 return SelectIndexedLoadSignExtend64(LD, Opcode, dl);
432 if (HII->isValidAutoIncImm(LoadedVT, Val)) {
433 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
434 SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
436 MVT::i32, MVT::Other, Base,
437 TargetConstVal, Chain);
438 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
439 MemOp[0] = LD->getMemOperand();
440 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
442 const SDValue Froms[] = { SDValue(LD, 0),
445 const SDValue Tos[] = { SDValue(Result, 0),
448 ReplaceUses(Froms, Tos, 2);
450 const SDValue Froms[] = { SDValue(LD, 0),
454 const SDValue Tos[] = { SDValue(Result, 0),
458 ReplaceUses(Froms, Tos, 3);
462 SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
463 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
464 SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl,
466 MVT::Other, Base, TargetConst0,
468 SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
469 Base, TargetConstVal,
470 SDValue(Result_1, 1));
471 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
472 MemOp[0] = LD->getMemOperand();
473 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
474 const SDValue Froms[] = { SDValue(LD, 0),
478 const SDValue Tos[] = { SDValue(Result_1, 0),
479 SDValue(Result_2, 0),
482 ReplaceUses(Froms, Tos, 3);
488 SDNode *HexagonDAGToDAGISel::SelectLoad(SDNode *N) {
491 LoadSDNode *LD = cast<LoadSDNode>(N);
492 ISD::MemIndexedMode AM = LD->getAddressingMode();
494 // Handle indexed loads.
495 if (AM != ISD::UNINDEXED) {
496 result = SelectIndexedLoad(LD, dl);
498 result = SelectCode(LD);
505 SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
506 SDValue Chain = ST->getChain();
507 SDValue Base = ST->getBasePtr();
508 SDValue Offset = ST->getOffset();
509 SDValue Value = ST->getValue();
510 SDNode *OffsetNode = Offset.getNode();
511 // Get the constant value.
512 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
513 EVT StoredVT = ST->getMemoryVT();
514 EVT ValueVT = Value.getValueType();
516 // Offset value must be within representable range
517 // and must have correct alignment properties.
518 if (HII->isValidAutoIncImm(StoredVT, Val)) {
521 // Figure out the post inc version of opcode.
522 if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_pi;
523 else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_pi;
524 else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_pi;
525 else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_pi;
526 else if (StoredVT == MVT::v16i32 || StoredVT == MVT::v8i64 ||
527 StoredVT == MVT::v32i16 || StoredVT == MVT::v64i8) {
528 Opcode = Hexagon::V6_vS32b_pi;
531 else if (StoredVT == MVT::v32i32 || StoredVT == MVT::v16i64 ||
532 StoredVT == MVT::v64i16 || StoredVT == MVT::v128i8) {
533 Opcode = Hexagon::V6_vS32b_pi_128B;
534 } else llvm_unreachable("unknown memory type");
536 if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) {
537 assert(StoredVT.getSizeInBits() < 64 && "Not a truncating store");
538 Value = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg,
539 dl, MVT::i32, Value);
541 SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, dl, MVT::i32), Value,
543 // Build post increment store.
544 SDNode* Result = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
546 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
547 MemOp[0] = ST->getMemOperand();
548 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
550 ReplaceUses(ST, Result);
551 ReplaceUses(SDValue(ST,1), SDValue(Result,1));
555 // Note: Order of operands matches the def of instruction:
557 // : STInst<(outs), (ins IntRegs:$base, imm:$offset, DoubleRegs:$src1), ...
558 // and it differs for POST_ST* for instance.
559 SDValue Ops[] = { Base, CurDAG->getTargetConstant(0, dl, MVT::i32), Value,
563 // Figure out the opcode.
564 if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_io;
565 else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_io;
566 else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_io;
567 else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_io;
568 else if (StoredVT == MVT::v16i32 || StoredVT == MVT::v8i64 ||
569 StoredVT == MVT::v32i16 || StoredVT == MVT::v64i8)
570 Opcode = Hexagon::V6_vS32b_ai;
572 else if (StoredVT == MVT::v32i32 || StoredVT == MVT::v16i64 ||
573 StoredVT == MVT::v64i16 || StoredVT == MVT::v128i8)
574 Opcode = Hexagon::V6_vS32b_ai_128B;
575 else llvm_unreachable("unknown memory type");
577 // Build regular store.
578 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
579 SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
580 // Build splitted incriment instruction.
581 SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
584 SDValue(Result_1, 0));
585 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
586 MemOp[0] = ST->getMemOperand();
587 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
589 ReplaceUses(SDValue(ST,0), SDValue(Result_2,0));
590 ReplaceUses(SDValue(ST,1), SDValue(Result_1,0));
594 SDNode *HexagonDAGToDAGISel::SelectStore(SDNode *N) {
596 StoreSDNode *ST = cast<StoreSDNode>(N);
597 ISD::MemIndexedMode AM = ST->getAddressingMode();
599 // Handle indexed stores.
600 if (AM != ISD::UNINDEXED) {
601 return SelectIndexedStore(ST, dl);
604 return SelectCode(ST);
607 SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
611 // %conv.i = sext i32 %tmp1 to i64
612 // %conv2.i = sext i32 %add to i64
613 // %mul.i = mul nsw i64 %conv2.i, %conv.i
615 // --- match with the following ---
617 // %mul.i = mpy (%tmp1, %add)
620 if (N->getValueType(0) == MVT::i64) {
621 // Shifting a i64 signed multiply.
622 SDValue MulOp0 = N->getOperand(0);
623 SDValue MulOp1 = N->getOperand(1);
628 // Handle sign_extend and sextload.
629 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
630 SDValue Sext0 = MulOp0.getOperand(0);
631 if (Sext0.getNode()->getValueType(0) != MVT::i32) {
632 return SelectCode(N);
636 } else if (MulOp0.getOpcode() == ISD::LOAD) {
637 LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
638 if (LD->getMemoryVT() != MVT::i32 ||
639 LD->getExtensionType() != ISD::SEXTLOAD ||
640 LD->getAddressingMode() != ISD::UNINDEXED) {
641 return SelectCode(N);
644 SDValue Chain = LD->getChain();
645 SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
646 OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
648 LD->getBasePtr(), TargetConst0,
651 return SelectCode(N);
654 // Same goes for the second operand.
655 if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
656 SDValue Sext1 = MulOp1.getOperand(0);
657 if (Sext1.getNode()->getValueType(0) != MVT::i32) {
658 return SelectCode(N);
662 } else if (MulOp1.getOpcode() == ISD::LOAD) {
663 LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
664 if (LD->getMemoryVT() != MVT::i32 ||
665 LD->getExtensionType() != ISD::SEXTLOAD ||
666 LD->getAddressingMode() != ISD::UNINDEXED) {
667 return SelectCode(N);
670 SDValue Chain = LD->getChain();
671 SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
672 OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
674 LD->getBasePtr(), TargetConst0,
677 return SelectCode(N);
680 // Generate a mpy instruction.
681 SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_dpmpyss_s0, dl, MVT::i64,
683 ReplaceUses(N, Result);
687 return SelectCode(N);
690 SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
692 if (N->getValueType(0) == MVT::i32) {
693 SDValue Shl_0 = N->getOperand(0);
694 SDValue Shl_1 = N->getOperand(1);
696 if (Shl_1.getOpcode() == ISD::Constant) {
697 if (Shl_0.getOpcode() == ISD::MUL) {
698 SDValue Mul_0 = Shl_0.getOperand(0); // Val
699 SDValue Mul_1 = Shl_0.getOperand(1); // Const
700 // RHS of mul is const.
701 if (Mul_1.getOpcode() == ISD::Constant) {
703 cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
705 cast<ConstantSDNode>(Mul_1.getNode())->getSExtValue();
706 int32_t ValConst = MulConst << ShlConst;
707 SDValue Val = CurDAG->getTargetConstant(ValConst, dl,
709 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val.getNode()))
710 if (isInt<9>(CN->getSExtValue())) {
712 CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl,
713 MVT::i32, Mul_0, Val);
714 ReplaceUses(N, Result);
719 } else if (Shl_0.getOpcode() == ISD::SUB) {
720 SDValue Sub_0 = Shl_0.getOperand(0); // Const 0
721 SDValue Sub_1 = Shl_0.getOperand(1); // Val
722 if (Sub_0.getOpcode() == ISD::Constant) {
724 cast<ConstantSDNode>(Sub_0.getNode())->getSExtValue();
726 if (Sub_1.getOpcode() == ISD::SHL) {
727 SDValue Shl2_0 = Sub_1.getOperand(0); // Val
728 SDValue Shl2_1 = Sub_1.getOperand(1); // Const
729 if (Shl2_1.getOpcode() == ISD::Constant) {
731 cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
733 cast<ConstantSDNode>(Shl2_1.getNode())->getSExtValue();
734 int32_t ValConst = 1 << (ShlConst+Shl2Const);
735 SDValue Val = CurDAG->getTargetConstant(-ValConst, dl,
737 if (ConstantSDNode *CN =
738 dyn_cast<ConstantSDNode>(Val.getNode()))
739 if (isInt<9>(CN->getSExtValue())) {
741 CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl, MVT::i32,
743 ReplaceUses(N, Result);
753 return SelectCode(N);
758 // If there is an zero_extend followed an intrinsic in DAG (this means - the
759 // result of the intrinsic is predicate); convert the zero_extend to
760 // transfer instruction.
762 // Zero extend -> transfer is lowered here. Otherwise, zero_extend will be
763 // converted into a MUX as predicate registers defined as 1 bit in the
764 // compiler. Architecture defines them as 8-bit registers.
765 // We want to preserve all the lower 8-bits and, not just 1 LSB bit.
767 SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
770 SDValue Op0 = N->getOperand(0);
771 EVT OpVT = Op0.getValueType();
772 unsigned OpBW = OpVT.getSizeInBits();
774 // Special handling for zero-extending a vector of booleans.
775 if (OpVT.isVector() && OpVT.getVectorElementType() == MVT::i1 && OpBW <= 64) {
776 SDNode *Mask = CurDAG->getMachineNode(Hexagon::C2_mask, dl, MVT::i64, Op0);
777 unsigned NE = OpVT.getVectorNumElements();
778 EVT ExVT = N->getValueType(0);
779 unsigned ES = ExVT.getVectorElementType().getSizeInBits();
780 uint64_t MV = 0, Bit = 1;
781 for (unsigned i = 0; i < NE; ++i) {
785 SDValue Ones = CurDAG->getTargetConstant(MV, dl, MVT::i64);
786 SDNode *OnesReg = CurDAG->getMachineNode(Hexagon::CONST64_Int_Real, dl,
788 if (ExVT.getSizeInBits() == 32) {
789 SDNode *And = CurDAG->getMachineNode(Hexagon::A2_andp, dl, MVT::i64,
790 SDValue(Mask,0), SDValue(OnesReg,0));
791 SDValue SubR = CurDAG->getTargetConstant(Hexagon::subreg_loreg, dl,
793 return CurDAG->getMachineNode(Hexagon::EXTRACT_SUBREG, dl, ExVT,
794 SDValue(And,0), SubR);
796 return CurDAG->getMachineNode(Hexagon::A2_andp, dl, ExVT,
797 SDValue(Mask,0), SDValue(OnesReg,0));
800 SDNode *IsIntrinsic = N->getOperand(0).getNode();
801 if ((IsIntrinsic->getOpcode() == ISD::INTRINSIC_WO_CHAIN)) {
803 cast<ConstantSDNode>(IsIntrinsic->getOperand(0))->getZExtValue();
804 if (doesIntrinsicReturnPredicate(ID)) {
805 // Now we need to differentiate target data types.
806 if (N->getValueType(0) == MVT::i64) {
807 // Convert the zero_extend to Rs = Pd followed by A2_combinew(0,Rs).
808 SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
809 SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
811 SDValue(IsIntrinsic, 0));
812 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl,
815 SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl,
816 MVT::i64, MVT::Other,
817 SDValue(Result_2, 0),
818 SDValue(Result_1, 0));
819 ReplaceUses(N, Result_3);
822 if (N->getValueType(0) == MVT::i32) {
823 // Convert the zero_extend to Rs = Pd
824 SDNode* RsPd = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
826 SDValue(IsIntrinsic, 0));
827 ReplaceUses(N, RsPd);
830 llvm_unreachable("Unexpected value type");
833 return SelectCode(N);
837 // Checking for intrinsics circular load/store, and bitreverse load/store
838 // instrisics in order to select the correct lowered operation.
840 SDNode *HexagonDAGToDAGISel::SelectIntrinsicWChain(SDNode *N) {
841 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
842 if (IntNo == Intrinsic::hexagon_circ_ldd ||
843 IntNo == Intrinsic::hexagon_circ_ldw ||
844 IntNo == Intrinsic::hexagon_circ_lduh ||
845 IntNo == Intrinsic::hexagon_circ_ldh ||
846 IntNo == Intrinsic::hexagon_circ_ldub ||
847 IntNo == Intrinsic::hexagon_circ_ldb) {
849 SDValue Chain = N->getOperand(0);
850 SDValue Base = N->getOperand(2);
851 SDValue Load = N->getOperand(3);
852 SDValue ModifierExpr = N->getOperand(4);
853 SDValue Offset = N->getOperand(5);
855 // We need to add the rerurn type for the load. This intrinsic has
856 // two return types, one for the load and one for the post-increment.
857 // Only the *_ld instructions push the extra return type, and bump the
858 // result node operand number correspondingly.
859 std::vector<EVT> ResTys;
861 unsigned memsize, align;
862 MVT MvtSize = MVT::i32;
864 if (IntNo == Intrinsic::hexagon_circ_ldd) {
865 ResTys.push_back(MVT::i32);
866 ResTys.push_back(MVT::i64);
867 opc = Hexagon::L2_loadrd_pci_pseudo;
870 } else if (IntNo == Intrinsic::hexagon_circ_ldw) {
871 ResTys.push_back(MVT::i32);
872 ResTys.push_back(MVT::i32);
873 opc = Hexagon::L2_loadri_pci_pseudo;
876 } else if (IntNo == Intrinsic::hexagon_circ_ldh) {
877 ResTys.push_back(MVT::i32);
878 ResTys.push_back(MVT::i32);
879 opc = Hexagon::L2_loadrh_pci_pseudo;
883 } else if (IntNo == Intrinsic::hexagon_circ_lduh) {
884 ResTys.push_back(MVT::i32);
885 ResTys.push_back(MVT::i32);
886 opc = Hexagon::L2_loadruh_pci_pseudo;
890 } else if (IntNo == Intrinsic::hexagon_circ_ldb) {
891 ResTys.push_back(MVT::i32);
892 ResTys.push_back(MVT::i32);
893 opc = Hexagon::L2_loadrb_pci_pseudo;
897 } else if (IntNo == Intrinsic::hexagon_circ_ldub) {
898 ResTys.push_back(MVT::i32);
899 ResTys.push_back(MVT::i32);
900 opc = Hexagon::L2_loadrub_pci_pseudo;
905 llvm_unreachable("no opc");
907 ResTys.push_back(MVT::Other);
909 // Copy over the arguments, which are the same mostly.
910 SmallVector<SDValue, 5> Ops;
913 Ops.push_back(ModifierExpr);
914 int32_t Val = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
915 Ops.push_back(CurDAG->getTargetConstant(Val, dl, MVT::i32));
916 Ops.push_back(Chain);
917 SDNode* Result = CurDAG->getMachineNode(opc, dl, ResTys, Ops);
920 MachineMemOperand *Mem =
921 MF->getMachineMemOperand(MachinePointerInfo(),
922 MachineMemOperand::MOStore, memsize, align);
923 if (MvtSize != MVT::i32)
924 ST = CurDAG->getTruncStore(Chain, dl, SDValue(Result, 1), Load,
927 ST = CurDAG->getStore(Chain, dl, SDValue(Result, 1), Load, Mem);
929 SDNode* Store = SelectStore(ST.getNode());
931 const SDValue Froms[] = { SDValue(N, 0),
933 const SDValue Tos[] = { SDValue(Result, 0),
935 ReplaceUses(Froms, Tos, 2);
939 if (IntNo == Intrinsic::hexagon_brev_ldd ||
940 IntNo == Intrinsic::hexagon_brev_ldw ||
941 IntNo == Intrinsic::hexagon_brev_ldh ||
942 IntNo == Intrinsic::hexagon_brev_lduh ||
943 IntNo == Intrinsic::hexagon_brev_ldb ||
944 IntNo == Intrinsic::hexagon_brev_ldub) {
946 SDValue Chain = N->getOperand(0);
947 SDValue Base = N->getOperand(2);
948 SDValue Load = N->getOperand(3);
949 SDValue ModifierExpr = N->getOperand(4);
951 // We need to add the rerurn type for the load. This intrinsic has
952 // two return types, one for the load and one for the post-increment.
953 std::vector<EVT> ResTys;
955 unsigned memsize, align;
956 MVT MvtSize = MVT::i32;
958 if (IntNo == Intrinsic::hexagon_brev_ldd) {
959 ResTys.push_back(MVT::i32);
960 ResTys.push_back(MVT::i64);
961 opc = Hexagon::L2_loadrd_pbr_pseudo;
964 } else if (IntNo == Intrinsic::hexagon_brev_ldw) {
965 ResTys.push_back(MVT::i32);
966 ResTys.push_back(MVT::i32);
967 opc = Hexagon::L2_loadri_pbr_pseudo;
970 } else if (IntNo == Intrinsic::hexagon_brev_ldh) {
971 ResTys.push_back(MVT::i32);
972 ResTys.push_back(MVT::i32);
973 opc = Hexagon::L2_loadrh_pbr_pseudo;
977 } else if (IntNo == Intrinsic::hexagon_brev_lduh) {
978 ResTys.push_back(MVT::i32);
979 ResTys.push_back(MVT::i32);
980 opc = Hexagon::L2_loadruh_pbr_pseudo;
984 } else if (IntNo == Intrinsic::hexagon_brev_ldb) {
985 ResTys.push_back(MVT::i32);
986 ResTys.push_back(MVT::i32);
987 opc = Hexagon::L2_loadrb_pbr_pseudo;
991 } else if (IntNo == Intrinsic::hexagon_brev_ldub) {
992 ResTys.push_back(MVT::i32);
993 ResTys.push_back(MVT::i32);
994 opc = Hexagon::L2_loadrub_pbr_pseudo;
999 llvm_unreachable("no opc");
1001 ResTys.push_back(MVT::Other);
1003 // Copy over the arguments, which are the same mostly.
1004 SmallVector<SDValue, 4> Ops;
1005 Ops.push_back(Base);
1006 Ops.push_back(Load);
1007 Ops.push_back(ModifierExpr);
1008 Ops.push_back(Chain);
1009 SDNode* Result = CurDAG->getMachineNode(opc, dl, ResTys, Ops);
1011 MachineMemOperand *Mem =
1012 MF->getMachineMemOperand(MachinePointerInfo(),
1013 MachineMemOperand::MOStore, memsize, align);
1014 if (MvtSize != MVT::i32)
1015 ST = CurDAG->getTruncStore(Chain, dl, SDValue(Result, 1), Load,
1018 ST = CurDAG->getStore(Chain, dl, SDValue(Result, 1), Load, Mem);
1020 SDNode* Store = SelectStore(ST.getNode());
1022 const SDValue Froms[] = { SDValue(N, 0),
1024 const SDValue Tos[] = { SDValue(Result, 0),
1025 SDValue(Store, 0) };
1026 ReplaceUses(Froms, Tos, 2);
1030 return SelectCode(N);
1034 // Checking for intrinsics which have predicate registers as operand(s)
1035 // and lowering to the actual intrinsic.
1037 SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
1038 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
1041 case Intrinsic::hexagon_S2_vsplatrb:
1044 case Intrinsic::hexagon_S2_vsplatrh:
1048 return SelectCode(N);
1051 SDValue const &V = N->getOperand(1);
1053 if (isValueExtension(V, Bits, U)) {
1054 SDValue R = CurDAG->getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
1055 N->getOperand(0), U);
1056 return SelectCode(R.getNode());
1058 return SelectCode(N);
1062 // Map floating point constant values.
1064 SDNode *HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) {
1066 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
1067 APFloat APF = CN->getValueAPF();
1068 if (N->getValueType(0) == MVT::f32) {
1069 return CurDAG->getMachineNode(Hexagon::TFRI_f, dl, MVT::f32,
1070 CurDAG->getTargetConstantFP(APF.convertToFloat(), dl, MVT::f32));
1072 else if (N->getValueType(0) == MVT::f64) {
1073 return CurDAG->getMachineNode(Hexagon::CONST64_Float_Real, dl, MVT::f64,
1074 CurDAG->getTargetConstantFP(APF.convertToDouble(), dl, MVT::f64));
1077 return SelectCode(N);
1081 // Map predicate true (encoded as -1 in LLVM) to a XOR.
1083 SDNode *HexagonDAGToDAGISel::SelectConstant(SDNode *N) {
1085 if (N->getValueType(0) == MVT::i1) {
1087 int32_t Val = cast<ConstantSDNode>(N)->getSExtValue();
1089 Result = CurDAG->getMachineNode(Hexagon::TFR_PdTrue, dl, MVT::i1);
1090 } else if (Val == 0) {
1091 Result = CurDAG->getMachineNode(Hexagon::TFR_PdFalse, dl, MVT::i1);
1094 ReplaceUses(N, Result);
1099 return SelectCode(N);
1104 // Map add followed by a asr -> asr +=.
1106 SDNode *HexagonDAGToDAGISel::SelectAdd(SDNode *N) {
1108 if (N->getValueType(0) != MVT::i32) {
1109 return SelectCode(N);
1111 // Identify nodes of the form: add(asr(...)).
1112 SDNode* Src1 = N->getOperand(0).getNode();
1113 if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse()
1114 || Src1->getValueType(0) != MVT::i32) {
1115 return SelectCode(N);
1118 // Build Rd = Rd' + asr(Rs, Rt). The machine constraints will ensure that
1119 // Rd and Rd' are assigned to the same register
1120 SDNode* Result = CurDAG->getMachineNode(Hexagon::S2_asr_r_r_acc, dl, MVT::i32,
1122 Src1->getOperand(0),
1123 Src1->getOperand(1));
1124 ReplaceUses(N, Result);
1130 // Map the following, where possible.
1131 // AND/FABS -> clrbit
1133 // XOR/FNEG ->toggle_bit.
1135 SDNode *HexagonDAGToDAGISel::SelectBitOp(SDNode *N) {
1137 EVT ValueVT = N->getValueType(0);
1139 // We handle only 32 and 64-bit bit ops.
1140 if (!(ValueVT == MVT::i32 || ValueVT == MVT::i64 ||
1141 ValueVT == MVT::f32 || ValueVT == MVT::f64))
1142 return SelectCode(N);
1144 // We handly only fabs and fneg for V5.
1145 unsigned Opc = N->getOpcode();
1146 if ((Opc == ISD::FABS || Opc == ISD::FNEG) && !HST->hasV5TOps())
1147 return SelectCode(N);
1150 if (Opc != ISD::FABS && Opc != ISD::FNEG) {
1151 if (N->getOperand(1).getOpcode() == ISD::Constant)
1152 Val = cast<ConstantSDNode>((N)->getOperand(1))->getSExtValue();
1154 return SelectCode(N);
1157 if (Opc == ISD::AND) {
1158 // Check if this is a bit-clearing AND, if not select code the usual way.
1159 if ((ValueVT == MVT::i32 && isPowerOf2_32(~Val)) ||
1160 (ValueVT == MVT::i64 && isPowerOf2_64(~Val)))
1163 return SelectCode(N);
1166 // If OR or AND is being fed by shl, srl and, sra don't do this change,
1167 // because Hexagon provide |= &= on shl, srl, and sra.
1168 // Traverse the DAG to see if there is shl, srl and sra.
1169 if (Opc == ISD::OR || Opc == ISD::AND) {
1170 switch (N->getOperand(0)->getOpcode()) {
1176 return SelectCode(N);
1180 // Make sure it's power of 2.
1181 unsigned BitPos = 0;
1182 if (Opc != ISD::FABS && Opc != ISD::FNEG) {
1183 if ((ValueVT == MVT::i32 && !isPowerOf2_32(Val)) ||
1184 (ValueVT == MVT::i64 && !isPowerOf2_64(Val)))
1185 return SelectCode(N);
1187 // Get the bit position.
1188 BitPos = countTrailingZeros(uint64_t(Val));
1190 // For fabs and fneg, it's always the 31st bit.
1194 unsigned BitOpc = 0;
1195 // Set the right opcode for bitwise operations.
1198 llvm_unreachable("Only bit-wise/abs/neg operations are allowed.");
1201 BitOpc = Hexagon::S2_clrbit_i;
1204 BitOpc = Hexagon::S2_setbit_i;
1208 BitOpc = Hexagon::S2_togglebit_i;
1213 // Get the right SDVal for the opcode.
1214 SDValue SDVal = CurDAG->getTargetConstant(BitPos, dl, MVT::i32);
1216 if (ValueVT == MVT::i32 || ValueVT == MVT::f32) {
1217 Result = CurDAG->getMachineNode(BitOpc, dl, ValueVT,
1218 N->getOperand(0), SDVal);
1220 // 64-bit gymnastic to use REG_SEQUENCE. But it's worth it.
1222 if (ValueVT == MVT::i64)
1223 SubValueVT = MVT::i32;
1225 SubValueVT = MVT::f32;
1227 SDNode *Reg = N->getOperand(0).getNode();
1228 SDValue RegClass = CurDAG->getTargetConstant(Hexagon::DoubleRegsRegClassID,
1231 SDValue SubregHiIdx = CurDAG->getTargetConstant(Hexagon::subreg_hireg, dl,
1233 SDValue SubregLoIdx = CurDAG->getTargetConstant(Hexagon::subreg_loreg, dl,
1236 SDValue SubregHI = CurDAG->getTargetExtractSubreg(Hexagon::subreg_hireg, dl,
1237 MVT::i32, SDValue(Reg, 0));
1239 SDValue SubregLO = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg, dl,
1240 MVT::i32, SDValue(Reg, 0));
1242 // Clear/set/toggle hi or lo registers depending on the bit position.
1243 if (SubValueVT != MVT::f32 && BitPos < 32) {
1244 SDNode *Result0 = CurDAG->getMachineNode(BitOpc, dl, SubValueVT,
1246 const SDValue Ops[] = { RegClass, SubregHI, SubregHiIdx,
1247 SDValue(Result0, 0), SubregLoIdx };
1248 Result = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
1251 if (Opc != ISD::FABS && Opc != ISD::FNEG)
1252 SDVal = CurDAG->getTargetConstant(BitPos-32, dl, MVT::i32);
1253 SDNode *Result0 = CurDAG->getMachineNode(BitOpc, dl, SubValueVT,
1255 const SDValue Ops[] = { RegClass, SDValue(Result0, 0), SubregHiIdx,
1256 SubregLO, SubregLoIdx };
1257 Result = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
1262 ReplaceUses(N, Result);
1267 SDNode *HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) {
1268 MachineFrameInfo *MFI = MF->getFrameInfo();
1269 const HexagonFrameLowering *HFI = HST->getFrameLowering();
1270 int FX = cast<FrameIndexSDNode>(N)->getIndex();
1271 unsigned StkA = HFI->getStackAlignment();
1272 unsigned MaxA = MFI->getMaxAlignment();
1273 SDValue FI = CurDAG->getTargetFrameIndex(FX, MVT::i32);
1275 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
1279 // - the object is fixed, or
1280 // - there are no objects with higher-than-default alignment, or
1281 // - there are no dynamically allocated objects.
1282 // Otherwise, use TFR_FIA.
1283 if (FX < 0 || MaxA <= StkA || !MFI->hasVarSizedObjects()) {
1284 R = CurDAG->getMachineNode(Hexagon::TFR_FI, DL, MVT::i32, FI, Zero);
1286 auto &HMFI = *MF->getInfo<HexagonMachineFunctionInfo>();
1287 unsigned AR = HMFI.getStackAlignBaseVReg();
1288 SDValue CH = CurDAG->getEntryNode();
1289 SDValue Ops[] = { CurDAG->getCopyFromReg(CH, DL, AR, MVT::i32), FI, Zero };
1290 R = CurDAG->getMachineNode(Hexagon::TFR_FIA, DL, MVT::i32, Ops);
1293 if (N->getHasDebugValue())
1294 CurDAG->TransferDbgValues(SDValue(N, 0), SDValue(R, 0));
1299 SDNode *HexagonDAGToDAGISel::Select(SDNode *N) {
1300 if (N->isMachineOpcode()) {
1302 return nullptr; // Already selected.
1305 switch (N->getOpcode()) {
1307 return SelectConstant(N);
1309 case ISD::ConstantFP:
1310 return SelectConstantFP(N);
1312 case ISD::FrameIndex:
1313 return SelectFrameIndex(N);
1316 return SelectAdd(N);
1319 return SelectSHL(N);
1322 return SelectLoad(N);
1325 return SelectStore(N);
1328 return SelectMul(N);
1335 return SelectBitOp(N);
1337 case ISD::ZERO_EXTEND:
1338 return SelectZeroExtend(N);
1340 case ISD::INTRINSIC_W_CHAIN:
1341 return SelectIntrinsicWChain(N);
1343 case ISD::INTRINSIC_WO_CHAIN:
1344 return SelectIntrinsicWOChain(N);
1347 return SelectCode(N);
1350 bool HexagonDAGToDAGISel::
1351 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
1352 std::vector<SDValue> &OutOps) {
1353 SDValue Inp = Op, Res;
1355 switch (ConstraintID) {
1358 case InlineAsm::Constraint_i:
1359 case InlineAsm::Constraint_o: // Offsetable.
1360 case InlineAsm::Constraint_v: // Not offsetable.
1361 case InlineAsm::Constraint_m: // Memory.
1362 if (SelectAddrFI(Inp, Res))
1363 OutOps.push_back(Res);
1365 OutOps.push_back(Inp);
1369 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1374 void HexagonDAGToDAGISel::PreprocessISelDAG() {
1375 SelectionDAG &DAG = *CurDAG;
1376 std::vector<SDNode*> Nodes;
1377 for (SDNode &Node : DAG.allnodes())
1378 Nodes.push_back(&Node);
1380 // Simplify: (or (select c x 0) z) -> (select c (or x z) z)
1381 // (or (select c 0 y) z) -> (select c z (or y z))
1382 // This may not be the right thing for all targets, so do it here.
1383 for (auto I: Nodes) {
1384 if (I->getOpcode() != ISD::OR)
1387 auto IsZero = [] (const SDValue &V) -> bool {
1388 if (ConstantSDNode *SC = dyn_cast<ConstantSDNode>(V.getNode()))
1389 return SC->isNullValue();
1392 auto IsSelect0 = [IsZero] (const SDValue &Op) -> bool {
1393 if (Op.getOpcode() != ISD::SELECT)
1395 return IsZero(Op.getOperand(1)) || IsZero(Op.getOperand(2));
1398 SDValue N0 = I->getOperand(0), N1 = I->getOperand(1);
1399 EVT VT = I->getValueType(0);
1400 bool SelN0 = IsSelect0(N0);
1401 SDValue SOp = SelN0 ? N0 : N1;
1402 SDValue VOp = SelN0 ? N1 : N0;
1404 if (SOp.getOpcode() == ISD::SELECT && SOp.getNode()->hasOneUse()) {
1405 SDValue SC = SOp.getOperand(0);
1406 SDValue SX = SOp.getOperand(1);
1407 SDValue SY = SOp.getOperand(2);
1410 SDValue NewOr = DAG.getNode(ISD::OR, DLS, VT, SX, VOp);
1411 SDValue NewSel = DAG.getNode(ISD::SELECT, DLS, VT, SC, NewOr, VOp);
1412 DAG.ReplaceAllUsesWith(I, NewSel.getNode());
1413 } else if (IsZero(SX)) {
1414 SDValue NewOr = DAG.getNode(ISD::OR, DLS, VT, SY, VOp);
1415 SDValue NewSel = DAG.getNode(ISD::SELECT, DLS, VT, SC, VOp, NewOr);
1416 DAG.ReplaceAllUsesWith(I, NewSel.getNode());
1422 void HexagonDAGToDAGISel::EmitFunctionEntryCode() {
1423 auto &HST = static_cast<const HexagonSubtarget&>(MF->getSubtarget());
1424 auto &HFI = *HST.getFrameLowering();
1425 if (!HFI.needsAligna(*MF))
1428 MachineFrameInfo *MFI = MF->getFrameInfo();
1429 MachineBasicBlock *EntryBB = &MF->front();
1430 unsigned AR = FuncInfo->CreateReg(MVT::i32);
1431 unsigned MaxA = MFI->getMaxAlignment();
1432 BuildMI(EntryBB, DebugLoc(), HII->get(Hexagon::ALIGNA), AR)
1434 MF->getInfo<HexagonMachineFunctionInfo>()->setStackAlignBaseVReg(AR);
1437 // Match a frame index that can be used in an addressing mode.
1438 bool HexagonDAGToDAGISel::SelectAddrFI(SDValue& N, SDValue &R) {
1439 if (N.getOpcode() != ISD::FrameIndex)
1441 auto &HFI = *HST->getFrameLowering();
1442 MachineFrameInfo *MFI = MF->getFrameInfo();
1443 int FX = cast<FrameIndexSDNode>(N)->getIndex();
1444 if (!MFI->isFixedObjectIndex(FX) && HFI.needsAligna(*MF))
1446 R = CurDAG->getTargetFrameIndex(FX, MVT::i32);
1450 inline bool HexagonDAGToDAGISel::SelectAddrGA(SDValue &N, SDValue &R) {
1451 return SelectGlobalAddress(N, R, false);
1454 inline bool HexagonDAGToDAGISel::SelectAddrGP(SDValue &N, SDValue &R) {
1455 return SelectGlobalAddress(N, R, true);
1458 bool HexagonDAGToDAGISel::SelectGlobalAddress(SDValue &N, SDValue &R,
1460 switch (N.getOpcode()) {
1462 SDValue N0 = N.getOperand(0);
1463 SDValue N1 = N.getOperand(1);
1464 unsigned GAOpc = N0.getOpcode();
1465 if (UseGP && GAOpc != HexagonISD::CONST32_GP)
1467 if (!UseGP && GAOpc != HexagonISD::CONST32)
1469 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N1)) {
1470 SDValue Addr = N0.getOperand(0);
1471 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Addr)) {
1472 if (GA->getOpcode() == ISD::TargetGlobalAddress) {
1473 uint64_t NewOff = GA->getOffset() + (uint64_t)Const->getSExtValue();
1474 R = CurDAG->getTargetGlobalAddress(GA->getGlobal(), SDLoc(Const),
1475 N.getValueType(), NewOff);
1482 case HexagonISD::CONST32:
1483 // The operand(0) of CONST32 is TargetGlobalAddress, which is what we
1484 // want in the instruction.
1486 R = N.getOperand(0);
1488 case HexagonISD::CONST32_GP:
1490 R = N.getOperand(0);
1499 bool HexagonDAGToDAGISel::isValueExtension(const SDValue &Val,
1500 unsigned FromBits, SDValue &Src) {
1501 unsigned Opc = Val.getOpcode();
1503 case ISD::SIGN_EXTEND:
1504 case ISD::ZERO_EXTEND:
1505 case ISD::ANY_EXTEND: {
1506 SDValue const &Op0 = Val.getOperand(0);
1507 EVT T = Op0.getValueType();
1508 if (T.isInteger() && T.getSizeInBits() == FromBits) {
1514 case ISD::SIGN_EXTEND_INREG:
1515 case ISD::AssertSext:
1516 case ISD::AssertZext:
1517 if (Val.getOperand(0).getValueType().isInteger()) {
1518 VTSDNode *T = cast<VTSDNode>(Val.getOperand(1));
1519 if (T->getVT().getSizeInBits() == FromBits) {
1520 Src = Val.getOperand(0);
1526 // Check if this is an AND with "FromBits" of lower bits set to 1.
1527 uint64_t FromMask = (1 << FromBits) - 1;
1528 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) {
1529 if (C->getZExtValue() == FromMask) {
1530 Src = Val.getOperand(1);
1534 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(1))) {
1535 if (C->getZExtValue() == FromMask) {
1536 Src = Val.getOperand(0);
1544 // OR/XOR with the lower "FromBits" bits set to 0.
1545 uint64_t FromMask = (1 << FromBits) - 1;
1546 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) {
1547 if ((C->getZExtValue() & FromMask) == 0) {
1548 Src = Val.getOperand(1);
1552 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(1))) {
1553 if ((C->getZExtValue() & FromMask) == 0) {
1554 Src = Val.getOperand(0);