1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Hexagon uses to lower LLVM code
11 // into a selection DAG.
13 //===----------------------------------------------------------------------===//
15 #include "HexagonISelLowering.h"
16 #include "HexagonMachineFunctionInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "HexagonTargetMachine.h"
19 #include "HexagonTargetObjectFile.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineJumpTableInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/CodeGen/ValueTypes.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/GlobalAlias.h"
32 #include "llvm/IR/GlobalVariable.h"
33 #include "llvm/IR/InlineAsm.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
43 EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden,
44 cl::desc("Control jump table emission on Hexagon target"));
47 class HexagonCCState : public CCState {
48 int NumNamedVarArgParams;
51 HexagonCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
52 const TargetMachine &TM, SmallVectorImpl<CCValAssign> &locs,
53 LLVMContext &C, int NumNamedVarArgParams)
54 : CCState(CC, isVarArg, MF, TM, locs, C),
55 NumNamedVarArgParams(NumNamedVarArgParams) {}
57 int getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
61 // Implement calling convention for Hexagon.
63 CC_Hexagon(unsigned ValNo, MVT ValVT,
64 MVT LocVT, CCValAssign::LocInfo LocInfo,
65 ISD::ArgFlagsTy ArgFlags, CCState &State);
68 CC_Hexagon32(unsigned ValNo, MVT ValVT,
69 MVT LocVT, CCValAssign::LocInfo LocInfo,
70 ISD::ArgFlagsTy ArgFlags, CCState &State);
73 CC_Hexagon64(unsigned ValNo, MVT ValVT,
74 MVT LocVT, CCValAssign::LocInfo LocInfo,
75 ISD::ArgFlagsTy ArgFlags, CCState &State);
78 RetCC_Hexagon(unsigned ValNo, MVT ValVT,
79 MVT LocVT, CCValAssign::LocInfo LocInfo,
80 ISD::ArgFlagsTy ArgFlags, CCState &State);
83 RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
84 MVT LocVT, CCValAssign::LocInfo LocInfo,
85 ISD::ArgFlagsTy ArgFlags, CCState &State);
88 RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
89 MVT LocVT, CCValAssign::LocInfo LocInfo,
90 ISD::ArgFlagsTy ArgFlags, CCState &State);
93 CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
94 MVT LocVT, CCValAssign::LocInfo LocInfo,
95 ISD::ArgFlagsTy ArgFlags, CCState &State) {
96 HexagonCCState &HState = static_cast<HexagonCCState &>(State);
98 // NumNamedVarArgParams can not be zero for a VarArg function.
99 assert((HState.getNumNamedVarArgParams() > 0) &&
100 "NumNamedVarArgParams is not bigger than zero.");
102 if ((int)ValNo < HState.getNumNamedVarArgParams()) {
103 // Deal with named arguments.
104 return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
107 // Deal with un-named arguments.
109 if (ArgFlags.isByVal()) {
110 // If pass-by-value, the size allocated on stack is decided
111 // by ArgFlags.getByValSize(), not by the size of LocVT.
112 assert ((ArgFlags.getByValSize() > 8) &&
113 "ByValSize must be bigger than 8 bytes");
114 ofst = State.AllocateStack(ArgFlags.getByValSize(), 4);
115 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
118 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
121 if (ArgFlags.isSExt())
122 LocInfo = CCValAssign::SExt;
123 else if (ArgFlags.isZExt())
124 LocInfo = CCValAssign::ZExt;
126 LocInfo = CCValAssign::AExt;
128 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
129 ofst = State.AllocateStack(4, 4);
130 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
133 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
134 ofst = State.AllocateStack(8, 8);
135 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
143 CC_Hexagon (unsigned ValNo, MVT ValVT,
144 MVT LocVT, CCValAssign::LocInfo LocInfo,
145 ISD::ArgFlagsTy ArgFlags, CCState &State) {
147 if (ArgFlags.isByVal()) {
149 assert ((ArgFlags.getByValSize() > 8) &&
150 "ByValSize must be bigger than 8 bytes");
151 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(), 4);
152 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
156 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
159 if (ArgFlags.isSExt())
160 LocInfo = CCValAssign::SExt;
161 else if (ArgFlags.isZExt())
162 LocInfo = CCValAssign::ZExt;
164 LocInfo = CCValAssign::AExt;
167 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
168 if (!CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
172 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
173 if (!CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
177 return true; // CC didn't match.
181 static bool CC_Hexagon32(unsigned ValNo, MVT ValVT,
182 MVT LocVT, CCValAssign::LocInfo LocInfo,
183 ISD::ArgFlagsTy ArgFlags, CCState &State) {
185 static const MCPhysReg RegList[] = {
186 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
189 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
190 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
194 unsigned Offset = State.AllocateStack(4, 4);
195 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
199 static bool CC_Hexagon64(unsigned ValNo, MVT ValVT,
200 MVT LocVT, CCValAssign::LocInfo LocInfo,
201 ISD::ArgFlagsTy ArgFlags, CCState &State) {
203 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
204 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
208 static const MCPhysReg RegList1[] = {
209 Hexagon::D1, Hexagon::D2
211 static const MCPhysReg RegList2[] = {
212 Hexagon::R1, Hexagon::R3
214 if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 2)) {
215 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
219 unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2);
220 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
224 static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT,
225 MVT LocVT, CCValAssign::LocInfo LocInfo,
226 ISD::ArgFlagsTy ArgFlags, CCState &State) {
229 if (LocVT == MVT::i1 ||
234 if (ArgFlags.isSExt())
235 LocInfo = CCValAssign::SExt;
236 else if (ArgFlags.isZExt())
237 LocInfo = CCValAssign::ZExt;
239 LocInfo = CCValAssign::AExt;
242 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
243 if (!RetCC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
247 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
248 if (!RetCC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
252 return true; // CC didn't match.
255 static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
256 MVT LocVT, CCValAssign::LocInfo LocInfo,
257 ISD::ArgFlagsTy ArgFlags, CCState &State) {
259 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
260 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) {
261 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
266 unsigned Offset = State.AllocateStack(4, 4);
267 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
271 static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
272 MVT LocVT, CCValAssign::LocInfo LocInfo,
273 ISD::ArgFlagsTy ArgFlags, CCState &State) {
274 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
275 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
276 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
281 unsigned Offset = State.AllocateStack(8, 8);
282 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
287 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
292 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
293 /// by "Src" to address "Dst" of size "Size". Alignment information is
294 /// specified by the specific parameter attribute. The copy will be passed as
295 /// a byval function parameter. Sometimes what we are copying is the end of a
296 /// larger object, the part that does not fit in registers.
298 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
299 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
302 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
303 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
304 /*isVolatile=*/false, /*AlwaysInline=*/false,
305 MachinePointerInfo(), MachinePointerInfo());
309 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
310 // passed by value, the function prototype is modified to return void and
311 // the value is stored in memory pointed by a pointer passed by caller.
313 HexagonTargetLowering::LowerReturn(SDValue Chain,
314 CallingConv::ID CallConv, bool isVarArg,
315 const SmallVectorImpl<ISD::OutputArg> &Outs,
316 const SmallVectorImpl<SDValue> &OutVals,
317 SDLoc dl, SelectionDAG &DAG) const {
319 // CCValAssign - represent the assignment of the return value to locations.
320 SmallVector<CCValAssign, 16> RVLocs;
322 // CCState - Info about the registers and stack slot.
323 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
324 getTargetMachine(), RVLocs, *DAG.getContext());
326 // Analyze return values of ISD::RET
327 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
330 SmallVector<SDValue, 4> RetOps(1, Chain);
332 // Copy the result values into the output registers.
333 for (unsigned i = 0; i != RVLocs.size(); ++i) {
334 CCValAssign &VA = RVLocs[i];
336 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
338 // Guarantee that all emitted copies are stuck together with flags.
339 Flag = Chain.getValue(1);
340 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
343 RetOps[0] = Chain; // Update chain.
345 // Add the flag if we have it.
347 RetOps.push_back(Flag);
349 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other,
350 &RetOps[0], RetOps.size());
356 /// LowerCallResult - Lower the result values of an ISD::CALL into the
357 /// appropriate copies out of appropriate physical registers. This assumes that
358 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
359 /// being lowered. Returns a SDNode with the same number of values as the
362 HexagonTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
363 CallingConv::ID CallConv, bool isVarArg,
365 SmallVectorImpl<ISD::InputArg> &Ins,
366 SDLoc dl, SelectionDAG &DAG,
367 SmallVectorImpl<SDValue> &InVals,
368 const SmallVectorImpl<SDValue> &OutVals,
369 SDValue Callee) const {
371 // Assign locations to each value returned by this call.
372 SmallVector<CCValAssign, 16> RVLocs;
374 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
375 getTargetMachine(), RVLocs, *DAG.getContext());
377 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
379 // Copy all of the result registers out of their specified physreg.
380 for (unsigned i = 0; i != RVLocs.size(); ++i) {
381 Chain = DAG.getCopyFromReg(Chain, dl,
382 RVLocs[i].getLocReg(),
383 RVLocs[i].getValVT(), InFlag).getValue(1);
384 InFlag = Chain.getValue(2);
385 InVals.push_back(Chain.getValue(0));
391 /// LowerCall - Functions arguments are copied from virtual regs to
392 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
394 HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
395 SmallVectorImpl<SDValue> &InVals) const {
396 SelectionDAG &DAG = CLI.DAG;
398 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
399 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
400 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
401 SDValue Chain = CLI.Chain;
402 SDValue Callee = CLI.Callee;
403 bool &isTailCall = CLI.IsTailCall;
404 CallingConv::ID CallConv = CLI.CallConv;
405 bool isVarArg = CLI.IsVarArg;
407 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
409 // Check for varargs.
410 int NumNamedVarArgParams = -1;
411 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Callee))
413 const Function* CalleeFn = NULL;
414 Callee = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, MVT::i32);
415 if ((CalleeFn = dyn_cast<Function>(GA->getGlobal())))
417 // If a function has zero args and is a vararg function, that's
418 // disallowed so it must be an undeclared function. Do not assume
419 // varargs if the callee is undefined.
420 if (CalleeFn->isVarArg() &&
421 CalleeFn->getFunctionType()->getNumParams() != 0) {
422 NumNamedVarArgParams = CalleeFn->getFunctionType()->getNumParams();
427 // Analyze operands of the call, assigning locations to each operand.
428 SmallVector<CCValAssign, 16> ArgLocs;
429 HexagonCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
430 getTargetMachine(), ArgLocs, *DAG.getContext(),
431 NumNamedVarArgParams);
433 if (NumNamedVarArgParams > 0)
434 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
436 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
440 bool StructAttrFlag =
441 DAG.getMachineFunction().getFunction()->hasStructRetAttr();
442 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
443 isVarArg, IsStructRet,
445 Outs, OutVals, Ins, DAG);
446 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i){
447 CCValAssign &VA = ArgLocs[i];
454 DEBUG(dbgs () << "Eligible for Tail Call\n");
457 "Argument must be passed on stack. Not eligible for Tail Call\n");
460 // Get a count of how many bytes are to be pushed on the stack.
461 unsigned NumBytes = CCInfo.getNextStackOffset();
462 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
463 SmallVector<SDValue, 8> MemOpChains;
466 DAG.getCopyFromReg(Chain, dl, TM.getRegisterInfo()->getStackRegister(),
469 // Walk the register/memloc assignments, inserting copies/loads.
470 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
471 CCValAssign &VA = ArgLocs[i];
472 SDValue Arg = OutVals[i];
473 ISD::ArgFlagsTy Flags = Outs[i].Flags;
475 // Promote the value if needed.
476 switch (VA.getLocInfo()) {
478 // Loc info must be one of Full, SExt, ZExt, or AExt.
479 llvm_unreachable("Unknown loc info!");
480 case CCValAssign::Full:
482 case CCValAssign::SExt:
483 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
485 case CCValAssign::ZExt:
486 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
488 case CCValAssign::AExt:
489 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
494 unsigned LocMemOffset = VA.getLocMemOffset();
495 SDValue PtrOff = DAG.getConstant(LocMemOffset, StackPtr.getValueType());
496 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
498 if (Flags.isByVal()) {
499 // The argument is a struct passed by value. According to LLVM, "Arg"
501 MemOpChains.push_back(CreateCopyOfByValArgument(Arg, PtrOff, Chain,
504 // The argument is not passed by value. "Arg" is a buildin type. It is
506 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
507 MachinePointerInfo(),false, false,
513 // Arguments that can be passed on register must be kept at RegsToPass
516 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
520 // Transform all store nodes into one single node because all store
521 // nodes are independent of each other.
522 if (!MemOpChains.empty()) {
523 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0],
528 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes,
529 getPointerTy(), true),
532 // Build a sequence of copy-to-reg nodes chained together with token
533 // chain and flag operands which copy the outgoing args into registers.
534 // The InFlag in necessary since all emitted instructions must be
538 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
539 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
540 RegsToPass[i].second, InFlag);
541 InFlag = Chain.getValue(1);
545 // For tail calls lower the arguments to the 'real' stack slot.
547 // Force all the incoming stack arguments to be loaded from the stack
548 // before any new outgoing arguments are stored to the stack, because the
549 // outgoing stack slots may alias the incoming argument stack slots, and
550 // the alias isn't otherwise explicit. This is slightly more conservative
551 // than necessary, because it means that each store effectively depends
552 // on every argument instead of just those arguments it would clobber.
554 // Do not flag preceding copytoreg stuff together with the following stuff.
556 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
557 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
558 RegsToPass[i].second, InFlag);
559 InFlag = Chain.getValue(1);
564 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
565 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
566 // node so that legalize doesn't hack it.
567 if (flag_aligned_memcpy) {
568 const char *MemcpyName =
569 "__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes";
571 DAG.getTargetExternalSymbol(MemcpyName, getPointerTy());
572 flag_aligned_memcpy = false;
573 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
574 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy());
575 } else if (ExternalSymbolSDNode *S =
576 dyn_cast<ExternalSymbolSDNode>(Callee)) {
577 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
580 // Returns a chain & a flag for retval copy to use.
581 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
582 SmallVector<SDValue, 8> Ops;
583 Ops.push_back(Chain);
584 Ops.push_back(Callee);
586 // Add argument registers to the end of the list so that they are
587 // known live into the call.
588 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
589 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
590 RegsToPass[i].second.getValueType()));
593 if (InFlag.getNode()) {
594 Ops.push_back(InFlag);
598 return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
600 Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
601 InFlag = Chain.getValue(1);
603 // Create the CALLSEQ_END node.
604 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
605 DAG.getIntPtrConstant(0, true), InFlag, dl);
606 InFlag = Chain.getValue(1);
608 // Handle result values, copying them out of physregs into vregs that we
610 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
611 InVals, OutVals, Callee);
614 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
615 bool isSEXTLoad, SDValue &Base,
616 SDValue &Offset, bool &isInc,
618 if (Ptr->getOpcode() != ISD::ADD)
621 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
622 isInc = (Ptr->getOpcode() == ISD::ADD);
623 Base = Ptr->getOperand(0);
624 Offset = Ptr->getOperand(1);
625 // Ensure that Offset is a constant.
626 return (isa<ConstantSDNode>(Offset));
632 // TODO: Put this function along with the other isS* functions in
633 // HexagonISelDAGToDAG.cpp into a common file. Or better still, use the
634 // functions defined in HexagonOperands.td.
635 static bool Is_PostInc_S4_Offset(SDNode * S, int ShiftAmount) {
636 ConstantSDNode *N = cast<ConstantSDNode>(S);
638 // immS4 predicate - True if the immediate fits in a 4-bit sign extended.
640 int64_t v = (int64_t)N->getSExtValue();
642 if (ShiftAmount > 0) {
644 v = v >> ShiftAmount;
646 return (v <= 7) && (v >= -8) && (m == 0);
649 /// getPostIndexedAddressParts - returns true by value, base pointer and
650 /// offset pointer and addressing mode by reference if this node can be
651 /// combined with a load / store to form a post-indexed load / store.
652 bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
655 ISD::MemIndexedMode &AM,
656 SelectionDAG &DAG) const
660 bool isSEXTLoad = false;
662 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
663 VT = LD->getMemoryVT();
664 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
665 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
666 VT = ST->getMemoryVT();
667 if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore()) {
675 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
677 // ShiftAmount = number of left-shifted bits in the Hexagon instruction.
678 int ShiftAmount = VT.getSizeInBits() / 16;
679 if (isLegal && Is_PostInc_S4_Offset(Offset.getNode(), ShiftAmount)) {
680 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
687 SDValue HexagonTargetLowering::LowerINLINEASM(SDValue Op,
688 SelectionDAG &DAG) const {
689 SDNode *Node = Op.getNode();
690 MachineFunction &MF = DAG.getMachineFunction();
691 HexagonMachineFunctionInfo *FuncInfo =
692 MF.getInfo<HexagonMachineFunctionInfo>();
693 switch (Node->getOpcode()) {
694 case ISD::INLINEASM: {
695 unsigned NumOps = Node->getNumOperands();
696 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
697 --NumOps; // Ignore the flag operand.
699 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
700 if (FuncInfo->hasClobberLR())
703 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
704 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
705 ++i; // Skip the ID value.
707 switch (InlineAsm::getKind(Flags)) {
708 default: llvm_unreachable("Bad flags!");
709 case InlineAsm::Kind_RegDef:
710 case InlineAsm::Kind_RegUse:
711 case InlineAsm::Kind_Imm:
712 case InlineAsm::Kind_Clobber:
713 case InlineAsm::Kind_Mem: {
714 for (; NumVals; --NumVals, ++i) {}
717 case InlineAsm::Kind_RegDefEarlyClobber: {
718 for (; NumVals; --NumVals, ++i) {
720 cast<RegisterSDNode>(Node->getOperand(i))->getReg();
723 if (Reg == TM.getRegisterInfo()->getRARegister()) {
724 FuncInfo->setHasClobberLR(true);
739 // Taken from the XCore backend.
741 SDValue HexagonTargetLowering::
742 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
744 SDValue Chain = Op.getOperand(0);
745 SDValue Table = Op.getOperand(1);
746 SDValue Index = Op.getOperand(2);
748 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
749 unsigned JTI = JT->getIndex();
750 MachineFunction &MF = DAG.getMachineFunction();
751 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
752 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
754 // Mark all jump table targets as address taken.
755 const std::vector<MachineJumpTableEntry> &JTE = MJTI->getJumpTables();
756 const std::vector<MachineBasicBlock*> &JTBBs = JTE[JTI].MBBs;
757 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
758 MachineBasicBlock *MBB = JTBBs[i];
759 MBB->setHasAddressTaken();
760 // This line is needed to set the hasAddressTaken flag on the BasicBlock
762 BlockAddress::get(const_cast<BasicBlock *>(MBB->getBasicBlock()));
765 SDValue JumpTableBase = DAG.getNode(HexagonISD::WrapperJT, dl,
766 getPointerTy(), TargetJT);
767 SDValue ShiftIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
768 DAG.getConstant(2, MVT::i32));
769 SDValue JTAddress = DAG.getNode(ISD::ADD, dl, MVT::i32, JumpTableBase,
771 SDValue LoadTarget = DAG.getLoad(MVT::i32, dl, Chain, JTAddress,
772 MachinePointerInfo(), false, false, false,
774 return DAG.getNode(HexagonISD::BR_JT, dl, MVT::Other, Chain, LoadTarget);
779 HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
780 SelectionDAG &DAG) const {
781 SDValue Chain = Op.getOperand(0);
782 SDValue Size = Op.getOperand(1);
785 unsigned SPReg = getStackPointerRegisterToSaveRestore();
787 // Get a reference to the stack pointer.
788 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
790 // Subtract the dynamic size from the actual stack size to
791 // obtain the new stack size.
792 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
795 // For Hexagon, the outgoing memory arguments area should be on top of the
796 // alloca area on the stack i.e., the outgoing memory arguments should be
797 // at a lower address than the alloca area. Move the alloca area down the
798 // stack by adding back the space reserved for outgoing arguments to SP
801 // We do not know what the size of the outgoing args is at this point.
802 // So, we add a pseudo instruction ADJDYNALLOC that will adjust the
803 // stack pointer. We patch this instruction with the correct, known
804 // offset in emitPrologue().
806 // Use a placeholder immediate (zero) for now. This will be patched up
807 // by emitPrologue().
808 SDValue ArgAdjust = DAG.getNode(HexagonISD::ADJDYNALLOC, dl,
811 DAG.getConstant(0, MVT::i32));
813 // The Sub result contains the new stack start address, so it
814 // must be placed in the stack pointer register.
815 SDValue CopyChain = DAG.getCopyToReg(Chain, dl,
816 TM.getRegisterInfo()->getStackRegister(),
819 SDValue Ops[2] = { ArgAdjust, CopyChain };
820 return DAG.getMergeValues(Ops, 2, dl);
824 HexagonTargetLowering::LowerFormalArguments(SDValue Chain,
825 CallingConv::ID CallConv,
828 SmallVectorImpl<ISD::InputArg> &Ins,
829 SDLoc dl, SelectionDAG &DAG,
830 SmallVectorImpl<SDValue> &InVals)
833 MachineFunction &MF = DAG.getMachineFunction();
834 MachineFrameInfo *MFI = MF.getFrameInfo();
835 MachineRegisterInfo &RegInfo = MF.getRegInfo();
836 HexagonMachineFunctionInfo *FuncInfo =
837 MF.getInfo<HexagonMachineFunctionInfo>();
840 // Assign locations to all of the incoming arguments.
841 SmallVector<CCValAssign, 16> ArgLocs;
842 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
843 getTargetMachine(), ArgLocs, *DAG.getContext());
845 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
847 // For LLVM, in the case when returning a struct by value (>8byte),
848 // the first argument is a pointer that points to the location on caller's
849 // stack where the return value will be stored. For Hexagon, the location on
850 // caller's stack is passed only when the struct size is smaller than (and
851 // equal to) 8 bytes. If not, no address will be passed into callee and
852 // callee return the result direclty through R0/R1.
854 SmallVector<SDValue, 4> MemOps;
856 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
857 CCValAssign &VA = ArgLocs[i];
858 ISD::ArgFlagsTy Flags = Ins[i].Flags;
860 unsigned StackLocation;
863 if ( (VA.isRegLoc() && !Flags.isByVal())
864 || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) {
865 // Arguments passed in registers
866 // 1. int, long long, ptr args that get allocated in register.
867 // 2. Large struct that gets an register to put its address in.
868 EVT RegVT = VA.getLocVT();
869 if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
870 RegVT == MVT::i32 || RegVT == MVT::f32) {
872 RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
873 RegInfo.addLiveIn(VA.getLocReg(), VReg);
874 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
875 } else if (RegVT == MVT::i64) {
877 RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
878 RegInfo.addLiveIn(VA.getLocReg(), VReg);
879 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
883 } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) {
884 assert (0 && "ByValSize must be bigger than 8 bytes");
887 assert(VA.isMemLoc());
889 if (Flags.isByVal()) {
890 // If it's a byval parameter, then we need to compute the
891 // "real" size, not the size of the pointer.
892 ObjSize = Flags.getByValSize();
894 ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3;
897 StackLocation = HEXAGON_LRFP_SIZE + VA.getLocMemOffset();
898 // Create the frame index object for this incoming parameter...
899 FI = MFI->CreateFixedObject(ObjSize, StackLocation, true);
901 // Create the SelectionDAG nodes cordl, responding to a load
902 // from this parameter.
903 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
905 if (Flags.isByVal()) {
906 // If it's a pass-by-value aggregate, then do not dereference the stack
907 // location. Instead, we should generate a reference to the stack
909 InVals.push_back(FIN);
911 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
912 MachinePointerInfo(), false, false,
919 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0],
923 // This will point to the next argument passed via stack.
924 int FrameIndex = MFI->CreateFixedObject(Hexagon_PointerSize,
926 CCInfo.getNextStackOffset(),
928 FuncInfo->setVarArgsFrameIndex(FrameIndex);
935 HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
936 // VASTART stores the address of the VarArgsFrameIndex slot into the
937 // memory location argument.
938 MachineFunction &MF = DAG.getMachineFunction();
939 HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>();
940 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32);
941 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
942 return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr,
943 Op.getOperand(1), MachinePointerInfo(SV), false,
948 HexagonTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
949 SDValue LHS = Op.getOperand(0);
950 SDValue RHS = Op.getOperand(1);
951 SDValue CC = Op.getOperand(4);
952 SDValue TrueVal = Op.getOperand(2);
953 SDValue FalseVal = Op.getOperand(3);
955 SDNode* OpNode = Op.getNode();
956 EVT SVT = OpNode->getValueType(0);
958 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i1, LHS, RHS, CC);
959 return DAG.getNode(ISD::SELECT, dl, SVT, Cond, TrueVal, FalseVal);
963 HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
964 EVT ValTy = Op.getValueType();
966 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
968 if (CP->isMachineConstantPoolEntry())
969 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), ValTy,
972 Res = DAG.getTargetConstantPool(CP->getConstVal(), ValTy,
974 return DAG.getNode(HexagonISD::CONST32, dl, ValTy, Res);
978 HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
979 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
980 MachineFunction &MF = DAG.getMachineFunction();
981 MachineFrameInfo *MFI = MF.getFrameInfo();
982 MFI->setReturnAddressIsTaken(true);
984 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
987 EVT VT = Op.getValueType();
989 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
991 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
992 SDValue Offset = DAG.getConstant(4, MVT::i32);
993 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
994 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
995 MachinePointerInfo(), false, false, false, 0);
998 // Return LR, which contains the return address. Mark it an implicit live-in.
999 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
1000 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
1004 HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1005 const HexagonRegisterInfo *TRI = TM.getRegisterInfo();
1006 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1007 MFI->setFrameAddressIsTaken(true);
1009 EVT VT = Op.getValueType();
1011 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1012 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1013 TRI->getFrameRegister(), VT);
1015 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1016 MachinePointerInfo(),
1017 false, false, false, 0);
1021 SDValue HexagonTargetLowering::LowerATOMIC_FENCE(SDValue Op,
1022 SelectionDAG& DAG) const {
1024 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1028 SDValue HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op,
1029 SelectionDAG &DAG) const {
1031 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1032 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1034 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
1036 const HexagonTargetObjectFile &TLOF =
1037 static_cast<const HexagonTargetObjectFile &>(getObjFileLowering());
1038 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1039 return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), Result);
1042 return DAG.getNode(HexagonISD::CONST32, dl, getPointerTy(), Result);
1046 HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
1047 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1048 SDValue BA_SD = DAG.getTargetBlockAddress(BA, MVT::i32);
1050 return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), BA_SD);
1053 //===----------------------------------------------------------------------===//
1054 // TargetLowering Implementation
1055 //===----------------------------------------------------------------------===//
1057 HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine
1059 : TargetLowering(targetmachine, new HexagonTargetObjectFile()),
1062 const HexagonRegisterInfo* QRI = TM.getRegisterInfo();
1064 // Set up the register classes.
1065 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1066 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1068 if (QRI->Subtarget.hasV5TOps()) {
1069 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1070 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1073 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1075 computeRegisterProperties();
1078 setPrefLoopAlignment(4);
1080 // Limits for inline expansion of memcpy/memmove
1081 MaxStoresPerMemcpy = 6;
1082 MaxStoresPerMemmove = 6;
1085 // Library calls for unsupported operations
1088 setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
1089 setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
1091 setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
1092 setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
1094 setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
1095 setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
1097 setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
1098 setOperationAction(ISD::SDIV, MVT::i32, Expand);
1099 setLibcallName(RTLIB::SREM_I32, "__hexagon_umodsi3");
1100 setOperationAction(ISD::SREM, MVT::i32, Expand);
1102 setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
1103 setOperationAction(ISD::SDIV, MVT::i64, Expand);
1104 setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
1105 setOperationAction(ISD::SREM, MVT::i64, Expand);
1107 setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
1108 setOperationAction(ISD::UDIV, MVT::i32, Expand);
1110 setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
1111 setOperationAction(ISD::UDIV, MVT::i64, Expand);
1113 setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
1114 setOperationAction(ISD::UREM, MVT::i32, Expand);
1116 setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
1117 setOperationAction(ISD::UREM, MVT::i64, Expand);
1119 setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
1120 setOperationAction(ISD::FDIV, MVT::f32, Expand);
1122 setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
1123 setOperationAction(ISD::FDIV, MVT::f64, Expand);
1125 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
1126 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
1127 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1128 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1130 if (QRI->Subtarget.hasV5TOps()) {
1131 // Hexagon V5 Support.
1132 setOperationAction(ISD::FADD, MVT::f32, Legal);
1133 setOperationAction(ISD::FADD, MVT::f64, Legal);
1134 setOperationAction(ISD::FP_EXTEND, MVT::f32, Legal);
1135 setCondCodeAction(ISD::SETOEQ, MVT::f32, Legal);
1136 setCondCodeAction(ISD::SETOEQ, MVT::f64, Legal);
1137 setCondCodeAction(ISD::SETUEQ, MVT::f32, Legal);
1138 setCondCodeAction(ISD::SETUEQ, MVT::f64, Legal);
1140 setCondCodeAction(ISD::SETOGE, MVT::f32, Legal);
1141 setCondCodeAction(ISD::SETOGE, MVT::f64, Legal);
1142 setCondCodeAction(ISD::SETUGE, MVT::f32, Legal);
1143 setCondCodeAction(ISD::SETUGE, MVT::f64, Legal);
1145 setCondCodeAction(ISD::SETOGT, MVT::f32, Legal);
1146 setCondCodeAction(ISD::SETOGT, MVT::f64, Legal);
1147 setCondCodeAction(ISD::SETUGT, MVT::f32, Legal);
1148 setCondCodeAction(ISD::SETUGT, MVT::f64, Legal);
1150 setCondCodeAction(ISD::SETOLE, MVT::f32, Legal);
1151 setCondCodeAction(ISD::SETOLE, MVT::f64, Legal);
1152 setCondCodeAction(ISD::SETOLT, MVT::f32, Legal);
1153 setCondCodeAction(ISD::SETOLT, MVT::f64, Legal);
1155 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
1156 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
1158 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
1159 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
1160 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
1161 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
1163 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
1164 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
1165 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
1166 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
1168 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
1169 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
1170 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
1171 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
1173 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1174 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1175 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1176 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1178 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1179 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1180 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1181 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1183 setOperationAction(ISD::FABS, MVT::f32, Legal);
1184 setOperationAction(ISD::FABS, MVT::f64, Expand);
1186 setOperationAction(ISD::FNEG, MVT::f32, Legal);
1187 setOperationAction(ISD::FNEG, MVT::f64, Expand);
1190 // Expand fp<->uint.
1191 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand);
1192 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
1194 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
1195 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
1197 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf");
1198 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf");
1200 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf");
1201 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf");
1203 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf");
1204 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf");
1206 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf");
1207 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf");
1209 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi");
1210 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi");
1212 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi");
1213 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi");
1215 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi");
1216 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi");
1218 setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
1219 setOperationAction(ISD::FADD, MVT::f64, Expand);
1221 setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
1222 setOperationAction(ISD::FADD, MVT::f32, Expand);
1224 setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2");
1225 setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand);
1227 setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2");
1228 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
1230 setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2");
1231 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
1233 setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2");
1234 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
1236 setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2");
1237 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
1239 setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2");
1240 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
1242 setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
1243 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand);
1245 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi");
1246 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand);
1248 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi");
1249 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand);
1251 setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2");
1252 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
1254 setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2");
1255 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
1257 setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2");
1258 setCondCodeAction(ISD::SETOLT, MVT::f64, Expand);
1260 setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2");
1261 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
1263 setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
1264 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1266 setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3");
1267 setOperationAction(ISD::MUL, MVT::f32, Expand);
1269 setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2");
1270 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
1272 setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2");
1274 setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
1275 setOperationAction(ISD::SUB, MVT::f64, Expand);
1277 setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3");
1278 setOperationAction(ISD::SUB, MVT::f32, Expand);
1280 setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2");
1281 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand);
1283 setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2");
1284 setCondCodeAction(ISD::SETUO, MVT::f64, Expand);
1286 setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2");
1287 setCondCodeAction(ISD::SETO, MVT::f64, Expand);
1289 setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2");
1290 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
1292 setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2");
1293 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
1295 setOperationAction(ISD::FABS, MVT::f32, Expand);
1296 setOperationAction(ISD::FABS, MVT::f64, Expand);
1297 setOperationAction(ISD::FNEG, MVT::f32, Expand);
1298 setOperationAction(ISD::FNEG, MVT::f64, Expand);
1301 setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
1302 setOperationAction(ISD::SREM, MVT::i32, Expand);
1304 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
1305 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
1306 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
1307 setIndexedLoadAction(ISD::POST_INC, MVT::i64, Legal);
1309 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal);
1310 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal);
1311 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
1312 setIndexedStoreAction(ISD::POST_INC, MVT::i64, Legal);
1314 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
1316 // Turn FP extload into load/fextend.
1317 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
1318 // Hexagon has a i1 sign extending load.
1319 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand);
1320 // Turn FP truncstore into trunc + store.
1321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1323 // Custom legalize GlobalAddress nodes into CONST32.
1324 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1325 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
1326 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1328 setOperationAction(ISD::TRUNCATE, MVT::i64, Expand);
1330 // Hexagon doesn't have sext_inreg, replace them with shl/sra.
1331 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
1333 // Hexagon has no REM or DIVREM operations.
1334 setOperationAction(ISD::UREM, MVT::i32, Expand);
1335 setOperationAction(ISD::SREM, MVT::i32, Expand);
1336 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1337 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1338 setOperationAction(ISD::SREM, MVT::i64, Expand);
1339 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
1340 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
1342 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
1344 // Lower SELECT_CC to SETCC and SELECT.
1345 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1346 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
1348 if (QRI->Subtarget.hasV5TOps()) {
1350 // We need to make the operation type of SELECT node to be Custom,
1351 // such that we don't go into the infinite loop of
1352 // select -> setcc -> select_cc -> select loop.
1353 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1354 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1356 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
1357 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
1358 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
1362 // Hexagon has no select or setcc: expand to SELECT_CC.
1363 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1364 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1366 // This is a workaround documented in DAGCombiner.cpp:2892 We don't
1367 // support SELECT_CC on every type.
1368 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
1372 if (EmitJumpTables) {
1373 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1375 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1377 // Increase jump tables cutover to 5, was 4.
1378 setMinimumJumpTableEntries(5);
1380 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
1381 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
1382 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1383 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
1384 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
1386 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1388 setOperationAction(ISD::FSIN , MVT::f64, Expand);
1389 setOperationAction(ISD::FCOS , MVT::f64, Expand);
1390 setOperationAction(ISD::FREM , MVT::f64, Expand);
1391 setOperationAction(ISD::FSIN , MVT::f32, Expand);
1392 setOperationAction(ISD::FCOS , MVT::f32, Expand);
1393 setOperationAction(ISD::FREM , MVT::f32, Expand);
1394 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1395 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1397 // In V4, we have double word add/sub with carry. The problem with
1398 // modelling this instruction is that it produces 2 results - Rdd and Px.
1399 // To model update of Px, we will have to use Defs[p0..p3] which will
1400 // cause any predicate live range to spill. So, we pretend we dont't
1401 // have these instructions.
1402 setOperationAction(ISD::ADDE, MVT::i8, Expand);
1403 setOperationAction(ISD::ADDE, MVT::i16, Expand);
1404 setOperationAction(ISD::ADDE, MVT::i32, Expand);
1405 setOperationAction(ISD::ADDE, MVT::i64, Expand);
1406 setOperationAction(ISD::SUBE, MVT::i8, Expand);
1407 setOperationAction(ISD::SUBE, MVT::i16, Expand);
1408 setOperationAction(ISD::SUBE, MVT::i32, Expand);
1409 setOperationAction(ISD::SUBE, MVT::i64, Expand);
1410 setOperationAction(ISD::ADDC, MVT::i8, Expand);
1411 setOperationAction(ISD::ADDC, MVT::i16, Expand);
1412 setOperationAction(ISD::ADDC, MVT::i32, Expand);
1413 setOperationAction(ISD::ADDC, MVT::i64, Expand);
1414 setOperationAction(ISD::SUBC, MVT::i8, Expand);
1415 setOperationAction(ISD::SUBC, MVT::i16, Expand);
1416 setOperationAction(ISD::SUBC, MVT::i32, Expand);
1417 setOperationAction(ISD::SUBC, MVT::i64, Expand);
1419 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1420 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
1421 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1422 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
1423 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
1424 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
1425 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1426 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
1427 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
1428 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
1429 setOperationAction(ISD::ROTL , MVT::i32, Expand);
1430 setOperationAction(ISD::ROTR , MVT::i32, Expand);
1431 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1432 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1433 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1434 setOperationAction(ISD::FPOW , MVT::f64, Expand);
1435 setOperationAction(ISD::FPOW , MVT::f32, Expand);
1437 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1438 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1439 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1441 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1442 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1444 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
1445 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
1447 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
1449 if (TM.getSubtargetImpl()->isSubtargetV2()) {
1450 setExceptionPointerRegister(Hexagon::R20);
1451 setExceptionSelectorRegister(Hexagon::R21);
1453 setExceptionPointerRegister(Hexagon::R0);
1454 setExceptionSelectorRegister(Hexagon::R1);
1457 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1458 setOperationAction(ISD::VASTART , MVT::Other, Custom);
1460 // Use the default implementation.
1461 setOperationAction(ISD::VAARG , MVT::Other, Expand);
1462 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
1463 setOperationAction(ISD::VAEND , MVT::Other, Expand);
1464 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
1465 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
1468 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
1469 setOperationAction(ISD::INLINEASM , MVT::Other, Custom);
1471 setMinFunctionAlignment(2);
1473 // Needed for DYNAMIC_STACKALLOC expansion.
1474 unsigned StackRegister = TM.getRegisterInfo()->getStackRegister();
1475 setStackPointerRegisterToSaveRestore(StackRegister);
1476 setSchedulingPreference(Sched::VLIW);
1481 HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
1484 case HexagonISD::CONST32: return "HexagonISD::CONST32";
1485 case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
1486 case HexagonISD::CONST32_Int_Real: return "HexagonISD::CONST32_Int_Real";
1487 case HexagonISD::ADJDYNALLOC: return "HexagonISD::ADJDYNALLOC";
1488 case HexagonISD::CMPICC: return "HexagonISD::CMPICC";
1489 case HexagonISD::CMPFCC: return "HexagonISD::CMPFCC";
1490 case HexagonISD::BRICC: return "HexagonISD::BRICC";
1491 case HexagonISD::BRFCC: return "HexagonISD::BRFCC";
1492 case HexagonISD::SELECT_ICC: return "HexagonISD::SELECT_ICC";
1493 case HexagonISD::SELECT_FCC: return "HexagonISD::SELECT_FCC";
1494 case HexagonISD::Hi: return "HexagonISD::Hi";
1495 case HexagonISD::Lo: return "HexagonISD::Lo";
1496 case HexagonISD::FTOI: return "HexagonISD::FTOI";
1497 case HexagonISD::ITOF: return "HexagonISD::ITOF";
1498 case HexagonISD::CALL: return "HexagonISD::CALL";
1499 case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
1500 case HexagonISD::BR_JT: return "HexagonISD::BR_JT";
1501 case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
1502 case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
1507 HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
1508 EVT MTy1 = EVT::getEVT(Ty1);
1509 EVT MTy2 = EVT::getEVT(Ty2);
1510 if (!MTy1.isSimple() || !MTy2.isSimple()) {
1513 return ((MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32));
1516 bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1517 if (!VT1.isSimple() || !VT2.isSimple()) {
1520 return ((VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32));
1524 HexagonTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
1525 // Assuming the caller does not have either a signext or zeroext modifier, and
1526 // only one value is accepted, any reasonable truncation is allowed.
1527 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
1530 // FIXME: in principle up to 64-bit could be made safe, but it would be very
1531 // fragile at the moment: any support for multiple value returns would be
1532 // liable to disallow tail calls involving i64 -> iN truncation in many cases.
1533 return Ty1->getPrimitiveSizeInBits() <= 32;
1537 HexagonTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
1538 SDValue Chain = Op.getOperand(0);
1539 SDValue Offset = Op.getOperand(1);
1540 SDValue Handler = Op.getOperand(2);
1543 // Mark function as containing a call to EH_RETURN.
1544 HexagonMachineFunctionInfo *FuncInfo =
1545 DAG.getMachineFunction().getInfo<HexagonMachineFunctionInfo>();
1546 FuncInfo->setHasEHReturn();
1548 unsigned OffsetReg = Hexagon::R28;
1550 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(),
1551 DAG.getRegister(Hexagon::R30, getPointerTy()),
1552 DAG.getIntPtrConstant(4));
1553 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
1555 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
1557 // Not needed we already use it as explict input to EH_RETURN.
1558 // MF.getRegInfo().addLiveOut(OffsetReg);
1560 return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
1564 HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1565 switch (Op.getOpcode()) {
1566 default: llvm_unreachable("Should not custom lower this!");
1567 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1568 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
1569 // Frame & Return address. Currently unimplemented.
1570 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
1571 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
1572 case ISD::GlobalTLSAddress:
1573 llvm_unreachable("TLS not implemented for Hexagon.");
1574 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
1575 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
1576 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
1577 case ISD::VASTART: return LowerVASTART(Op, DAG);
1578 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
1580 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
1581 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
1582 case ISD::SELECT: return Op;
1583 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1584 case ISD::INLINEASM: return LowerINLINEASM(Op, DAG);
1591 //===----------------------------------------------------------------------===//
1592 // Hexagon Scheduler Hooks
1593 //===----------------------------------------------------------------------===//
1595 HexagonTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1596 MachineBasicBlock *BB)
1598 switch (MI->getOpcode()) {
1599 case Hexagon::ADJDYNALLOC: {
1600 MachineFunction *MF = BB->getParent();
1601 HexagonMachineFunctionInfo *FuncInfo =
1602 MF->getInfo<HexagonMachineFunctionInfo>();
1603 FuncInfo->addAllocaAdjustInst(MI);
1606 default: llvm_unreachable("Unexpected instr type to insert");
1610 //===----------------------------------------------------------------------===//
1611 // Inline Assembly Support
1612 //===----------------------------------------------------------------------===//
1614 std::pair<unsigned, const TargetRegisterClass*>
1615 HexagonTargetLowering::getRegForInlineAsmConstraint(const
1616 std::string &Constraint,
1618 if (Constraint.size() == 1) {
1619 switch (Constraint[0]) {
1621 switch (VT.SimpleTy) {
1623 llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
1628 return std::make_pair(0U, &Hexagon::IntRegsRegClass);
1631 return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
1634 llvm_unreachable("Unknown asm register class");
1638 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1641 /// isFPImmLegal - Returns true if the target can instruction select the
1642 /// specified FP immediate natively. If false, the legalizer will
1643 /// materialize the FP immediate as a load from a constant pool.
1644 bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
1645 const HexagonRegisterInfo* QRI = TM.getRegisterInfo();
1646 return QRI->Subtarget.hasV5TOps();
1649 /// isLegalAddressingMode - Return true if the addressing mode represented by
1650 /// AM is legal for this target, for a load/store of the specified type.
1651 bool HexagonTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1653 // Allows a signed-extended 11-bit immediate field.
1654 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1) {
1658 // No global is ever allowed as a base.
1663 int Scale = AM.Scale;
1664 if (Scale < 0) Scale = -Scale;
1666 case 0: // No scale reg, "r+i", "r", or just "i".
1668 default: // No scaled addressing mode.
1674 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1675 /// icmp immediate, that is the target has icmp instructions which can compare
1676 /// a register against the immediate without having to materialize the
1677 /// immediate into a register.
1678 bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
1679 return Imm >= -512 && Imm <= 511;
1682 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1683 /// for tail call optimization. Targets which want to do tail call
1684 /// optimization should implement this function.
1685 bool HexagonTargetLowering::IsEligibleForTailCallOptimization(
1687 CallingConv::ID CalleeCC,
1689 bool isCalleeStructRet,
1690 bool isCallerStructRet,
1691 const SmallVectorImpl<ISD::OutputArg> &Outs,
1692 const SmallVectorImpl<SDValue> &OutVals,
1693 const SmallVectorImpl<ISD::InputArg> &Ins,
1694 SelectionDAG& DAG) const {
1695 const Function *CallerF = DAG.getMachineFunction().getFunction();
1696 CallingConv::ID CallerCC = CallerF->getCallingConv();
1697 bool CCMatch = CallerCC == CalleeCC;
1699 // ***************************************************************************
1700 // Look for obvious safe cases to perform tail call optimization that do not
1701 // require ABI changes.
1702 // ***************************************************************************
1704 // If this is a tail call via a function pointer, then don't do it!
1705 if (!(dyn_cast<GlobalAddressSDNode>(Callee))
1706 && !(dyn_cast<ExternalSymbolSDNode>(Callee))) {
1710 // Do not optimize if the calling conventions do not match.
1714 // Do not tail call optimize vararg calls.
1718 // Also avoid tail call optimization if either caller or callee uses struct
1719 // return semantics.
1720 if (isCalleeStructRet || isCallerStructRet)
1723 // In addition to the cases above, we also disable Tail Call Optimization if
1724 // the calling convention code that at least one outgoing argument needs to
1725 // go on the stack. We cannot check that here because at this point that
1726 // information is not available.