1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Hexagon uses to lower LLVM code
11 // into a selection DAG.
13 //===----------------------------------------------------------------------===//
15 #include "HexagonISelLowering.h"
16 #include "HexagonMachineFunctionInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "HexagonTargetMachine.h"
19 #include "HexagonTargetObjectFile.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineJumpTableInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/CodeGen/ValueTypes.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/GlobalAlias.h"
32 #include "llvm/IR/GlobalVariable.h"
33 #include "llvm/IR/InlineAsm.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
42 #define DEBUG_TYPE "hexagon-lowering"
45 EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden,
46 cl::desc("Control jump table emission on Hexagon target"));
48 static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
49 cl::Hidden, cl::ZeroOrMore, cl::init(false),
50 cl::desc("Enable Hexagon SDNode scheduling"));
52 static cl::opt<bool> EnableFastMath("ffast-math",
53 cl::Hidden, cl::ZeroOrMore, cl::init(false),
54 cl::desc("Enable Fast Math processing"));
56 static cl::opt<int> MinimumJumpTables("minimum-jump-tables",
57 cl::Hidden, cl::ZeroOrMore, cl::init(5),
58 cl::desc("Set minimum jump tables"));
60 static cl::opt<int> MaxStoresPerMemcpyCL("max-store-memcpy",
61 cl::Hidden, cl::ZeroOrMore, cl::init(6),
62 cl::desc("Max #stores to inline memcpy"));
64 static cl::opt<int> MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os",
65 cl::Hidden, cl::ZeroOrMore, cl::init(4),
66 cl::desc("Max #stores to inline memcpy"));
68 static cl::opt<int> MaxStoresPerMemmoveCL("max-store-memmove",
69 cl::Hidden, cl::ZeroOrMore, cl::init(6),
70 cl::desc("Max #stores to inline memmove"));
72 static cl::opt<int> MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os",
73 cl::Hidden, cl::ZeroOrMore, cl::init(4),
74 cl::desc("Max #stores to inline memmove"));
76 static cl::opt<int> MaxStoresPerMemsetCL("max-store-memset",
77 cl::Hidden, cl::ZeroOrMore, cl::init(8),
78 cl::desc("Max #stores to inline memset"));
80 static cl::opt<int> MaxStoresPerMemsetOptSizeCL("max-store-memset-Os",
81 cl::Hidden, cl::ZeroOrMore, cl::init(4),
82 cl::desc("Max #stores to inline memset"));
86 class HexagonCCState : public CCState {
87 unsigned NumNamedVarArgParams;
90 HexagonCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
91 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
92 int NumNamedVarArgParams)
93 : CCState(CC, isVarArg, MF, locs, C),
94 NumNamedVarArgParams(NumNamedVarArgParams) {}
96 unsigned getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
100 // Implement calling convention for Hexagon.
102 CC_Hexagon(unsigned ValNo, MVT ValVT,
103 MVT LocVT, CCValAssign::LocInfo LocInfo,
104 ISD::ArgFlagsTy ArgFlags, CCState &State);
107 CC_Hexagon32(unsigned ValNo, MVT ValVT,
108 MVT LocVT, CCValAssign::LocInfo LocInfo,
109 ISD::ArgFlagsTy ArgFlags, CCState &State);
112 CC_Hexagon64(unsigned ValNo, MVT ValVT,
113 MVT LocVT, CCValAssign::LocInfo LocInfo,
114 ISD::ArgFlagsTy ArgFlags, CCState &State);
117 RetCC_Hexagon(unsigned ValNo, MVT ValVT,
118 MVT LocVT, CCValAssign::LocInfo LocInfo,
119 ISD::ArgFlagsTy ArgFlags, CCState &State);
122 RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
123 MVT LocVT, CCValAssign::LocInfo LocInfo,
124 ISD::ArgFlagsTy ArgFlags, CCState &State);
127 RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
128 MVT LocVT, CCValAssign::LocInfo LocInfo,
129 ISD::ArgFlagsTy ArgFlags, CCState &State);
132 CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
133 MVT LocVT, CCValAssign::LocInfo LocInfo,
134 ISD::ArgFlagsTy ArgFlags, CCState &State) {
135 HexagonCCState &HState = static_cast<HexagonCCState &>(State);
137 if (ValNo < HState.getNumNamedVarArgParams()) {
138 // Deal with named arguments.
139 return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
142 // Deal with un-named arguments.
144 if (ArgFlags.isByVal()) {
145 // If pass-by-value, the size allocated on stack is decided
146 // by ArgFlags.getByValSize(), not by the size of LocVT.
147 ofst = State.AllocateStack(ArgFlags.getByValSize(),
148 ArgFlags.getByValAlign());
149 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
152 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
155 if (ArgFlags.isSExt())
156 LocInfo = CCValAssign::SExt;
157 else if (ArgFlags.isZExt())
158 LocInfo = CCValAssign::ZExt;
160 LocInfo = CCValAssign::AExt;
162 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
163 ofst = State.AllocateStack(4, 4);
164 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
167 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
168 ofst = State.AllocateStack(8, 8);
169 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
172 llvm_unreachable(nullptr);
177 CC_Hexagon (unsigned ValNo, MVT ValVT,
178 MVT LocVT, CCValAssign::LocInfo LocInfo,
179 ISD::ArgFlagsTy ArgFlags, CCState &State) {
181 if (ArgFlags.isByVal()) {
183 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(),
184 ArgFlags.getByValAlign());
185 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
189 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
192 if (ArgFlags.isSExt())
193 LocInfo = CCValAssign::SExt;
194 else if (ArgFlags.isZExt())
195 LocInfo = CCValAssign::ZExt;
197 LocInfo = CCValAssign::AExt;
198 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
200 LocInfo = CCValAssign::BCvt;
201 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
203 LocInfo = CCValAssign::BCvt;
206 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
207 if (!CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
211 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
212 if (!CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
216 return true; // CC didn't match.
220 static bool CC_Hexagon32(unsigned ValNo, MVT ValVT,
221 MVT LocVT, CCValAssign::LocInfo LocInfo,
222 ISD::ArgFlagsTy ArgFlags, CCState &State) {
224 static const MCPhysReg RegList[] = {
225 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
228 if (unsigned Reg = State.AllocateReg(RegList)) {
229 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
233 unsigned Offset = State.AllocateStack(4, 4);
234 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
238 static bool CC_Hexagon64(unsigned ValNo, MVT ValVT,
239 MVT LocVT, CCValAssign::LocInfo LocInfo,
240 ISD::ArgFlagsTy ArgFlags, CCState &State) {
242 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
243 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
247 static const MCPhysReg RegList1[] = {
248 Hexagon::D1, Hexagon::D2
250 static const MCPhysReg RegList2[] = {
251 Hexagon::R1, Hexagon::R3
253 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
254 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
258 unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2);
259 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
263 static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT,
264 MVT LocVT, CCValAssign::LocInfo LocInfo,
265 ISD::ArgFlagsTy ArgFlags, CCState &State) {
268 if (LocVT == MVT::i1 ||
273 if (ArgFlags.isSExt())
274 LocInfo = CCValAssign::SExt;
275 else if (ArgFlags.isZExt())
276 LocInfo = CCValAssign::ZExt;
278 LocInfo = CCValAssign::AExt;
279 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
281 LocInfo = CCValAssign::BCvt;
282 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
284 LocInfo = CCValAssign::BCvt;
287 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
288 if (!RetCC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
292 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
293 if (!RetCC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
297 return true; // CC didn't match.
300 static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
301 MVT LocVT, CCValAssign::LocInfo LocInfo,
302 ISD::ArgFlagsTy ArgFlags, CCState &State) {
304 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
305 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) {
306 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
311 unsigned Offset = State.AllocateStack(4, 4);
312 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
316 static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
317 MVT LocVT, CCValAssign::LocInfo LocInfo,
318 ISD::ArgFlagsTy ArgFlags, CCState &State) {
319 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
320 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
321 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
326 unsigned Offset = State.AllocateStack(8, 8);
327 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
332 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
337 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
338 /// by "Src" to address "Dst" of size "Size". Alignment information is
339 /// specified by the specific parameter attribute. The copy will be passed as
340 /// a byval function parameter. Sometimes what we are copying is the end of a
341 /// larger object, the part that does not fit in registers.
343 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
344 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
347 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
348 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
349 /*isVolatile=*/false, /*AlwaysInline=*/false,
350 /*isTailCall=*/false,
351 MachinePointerInfo(), MachinePointerInfo());
355 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
356 // passed by value, the function prototype is modified to return void and
357 // the value is stored in memory pointed by a pointer passed by caller.
359 HexagonTargetLowering::LowerReturn(SDValue Chain,
360 CallingConv::ID CallConv, bool isVarArg,
361 const SmallVectorImpl<ISD::OutputArg> &Outs,
362 const SmallVectorImpl<SDValue> &OutVals,
363 SDLoc dl, SelectionDAG &DAG) const {
365 // CCValAssign - represent the assignment of the return value to locations.
366 SmallVector<CCValAssign, 16> RVLocs;
368 // CCState - Info about the registers and stack slot.
369 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
372 // Analyze return values of ISD::RET
373 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
376 SmallVector<SDValue, 4> RetOps(1, Chain);
378 // Copy the result values into the output registers.
379 for (unsigned i = 0; i != RVLocs.size(); ++i) {
380 CCValAssign &VA = RVLocs[i];
382 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
384 // Guarantee that all emitted copies are stuck together with flags.
385 Flag = Chain.getValue(1);
386 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
389 RetOps[0] = Chain; // Update chain.
391 // Add the flag if we have it.
393 RetOps.push_back(Flag);
395 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
398 bool HexagonTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
399 // If either no tail call or told not to tail call at all, don't.
400 if (!CI->isTailCall() || HTM.Options.DisableTailCalls)
406 /// LowerCallResult - Lower the result values of an ISD::CALL into the
407 /// appropriate copies out of appropriate physical registers. This assumes that
408 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
409 /// being lowered. Returns a SDNode with the same number of values as the
412 HexagonTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
413 CallingConv::ID CallConv, bool isVarArg,
415 SmallVectorImpl<ISD::InputArg> &Ins,
416 SDLoc dl, SelectionDAG &DAG,
417 SmallVectorImpl<SDValue> &InVals,
418 const SmallVectorImpl<SDValue> &OutVals,
419 SDValue Callee) const {
421 // Assign locations to each value returned by this call.
422 SmallVector<CCValAssign, 16> RVLocs;
424 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
427 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
429 // Copy all of the result registers out of their specified physreg.
430 for (unsigned i = 0; i != RVLocs.size(); ++i) {
431 Chain = DAG.getCopyFromReg(Chain, dl,
432 RVLocs[i].getLocReg(),
433 RVLocs[i].getValVT(), InFlag).getValue(1);
434 InFlag = Chain.getValue(2);
435 InVals.push_back(Chain.getValue(0));
441 /// LowerCall - Functions arguments are copied from virtual regs to
442 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
444 HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
445 SmallVectorImpl<SDValue> &InVals) const {
446 SelectionDAG &DAG = CLI.DAG;
448 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
449 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
450 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
451 SDValue Chain = CLI.Chain;
452 SDValue Callee = CLI.Callee;
453 bool &isTailCall = CLI.IsTailCall;
454 CallingConv::ID CallConv = CLI.CallConv;
455 bool isVarArg = CLI.IsVarArg;
456 bool doesNotReturn = CLI.DoesNotReturn;
458 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
459 MachineFunction &MF = DAG.getMachineFunction();
461 // Check for varargs.
462 int NumNamedVarArgParams = -1;
463 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Callee))
465 const Function* CalleeFn = nullptr;
466 Callee = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, MVT::i32);
467 if ((CalleeFn = dyn_cast<Function>(GA->getGlobal())))
469 // If a function has zero args and is a vararg function, that's
470 // disallowed so it must be an undeclared function. Do not assume
471 // varargs if the callee is undefined.
472 if (CalleeFn->isVarArg() &&
473 CalleeFn->getFunctionType()->getNumParams() != 0) {
474 NumNamedVarArgParams = CalleeFn->getFunctionType()->getNumParams();
479 // Analyze operands of the call, assigning locations to each operand.
480 SmallVector<CCValAssign, 16> ArgLocs;
481 HexagonCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
482 *DAG.getContext(), NumNamedVarArgParams);
485 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
487 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
489 if (DAG.getTarget().Options.DisableTailCalls)
493 bool StructAttrFlag = MF.getFunction()->hasStructRetAttr();
494 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
495 isVarArg, IsStructRet,
497 Outs, OutVals, Ins, DAG);
498 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
499 CCValAssign &VA = ArgLocs[i];
505 DEBUG(dbgs() << (isTailCall ? "Eligible for Tail Call\n"
506 : "Argument must be passed on stack. "
507 "Not eligible for Tail Call\n"));
509 // Get a count of how many bytes are to be pushed on the stack.
510 unsigned NumBytes = CCInfo.getNextStackOffset();
511 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
512 SmallVector<SDValue, 8> MemOpChains;
514 auto &HRI = *Subtarget.getRegisterInfo();
515 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(),
518 // Walk the register/memloc assignments, inserting copies/loads.
519 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
520 CCValAssign &VA = ArgLocs[i];
521 SDValue Arg = OutVals[i];
522 ISD::ArgFlagsTy Flags = Outs[i].Flags;
524 // Promote the value if needed.
525 switch (VA.getLocInfo()) {
527 // Loc info must be one of Full, SExt, ZExt, or AExt.
528 llvm_unreachable("Unknown loc info!");
529 case CCValAssign::BCvt:
530 case CCValAssign::Full:
532 case CCValAssign::SExt:
533 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
535 case CCValAssign::ZExt:
536 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
538 case CCValAssign::AExt:
539 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
544 unsigned LocMemOffset = VA.getLocMemOffset();
545 SDValue MemAddr = DAG.getConstant(LocMemOffset, StackPtr.getValueType());
546 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
547 if (Flags.isByVal()) {
548 // The argument is a struct passed by value. According to LLVM, "Arg"
550 MemOpChains.push_back(CreateCopyOfByValArgument(Arg, MemAddr, Chain,
553 MachinePointerInfo LocPI = MachinePointerInfo::getStack(LocMemOffset);
554 SDValue S = DAG.getStore(Chain, dl, Arg, MemAddr, LocPI, false,
556 MemOpChains.push_back(S);
561 // Arguments that can be passed on register must be kept at RegsToPass
564 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
567 // Transform all store nodes into one single node because all store
568 // nodes are independent of each other.
569 if (!MemOpChains.empty())
570 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
573 SDValue C = DAG.getConstant(NumBytes, getPointerTy(), true);
574 Chain = DAG.getCALLSEQ_START(Chain, C, dl);
577 // Build a sequence of copy-to-reg nodes chained together with token
578 // chain and flag operands which copy the outgoing args into registers.
579 // The InFlag in necessary since all emitted instructions must be
583 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
584 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
585 RegsToPass[i].second, InFlag);
586 InFlag = Chain.getValue(1);
589 // For tail calls lower the arguments to the 'real' stack slot.
591 // Force all the incoming stack arguments to be loaded from the stack
592 // before any new outgoing arguments are stored to the stack, because the
593 // outgoing stack slots may alias the incoming argument stack slots, and
594 // the alias isn't otherwise explicit. This is slightly more conservative
595 // than necessary, because it means that each store effectively depends
596 // on every argument instead of just those arguments it would clobber.
598 // Do not flag preceding copytoreg stuff together with the following stuff.
600 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
601 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
602 RegsToPass[i].second, InFlag);
603 InFlag = Chain.getValue(1);
608 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
609 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
610 // node so that legalize doesn't hack it.
611 if (flag_aligned_memcpy) {
612 const char *MemcpyName =
613 "__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes";
614 Callee = DAG.getTargetExternalSymbol(MemcpyName, getPointerTy());
615 flag_aligned_memcpy = false;
616 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
617 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy());
618 } else if (ExternalSymbolSDNode *S =
619 dyn_cast<ExternalSymbolSDNode>(Callee)) {
620 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
623 // Returns a chain & a flag for retval copy to use.
624 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
625 SmallVector<SDValue, 8> Ops;
626 Ops.push_back(Chain);
627 Ops.push_back(Callee);
629 // Add argument registers to the end of the list so that they are
630 // known live into the call.
631 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
632 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
633 RegsToPass[i].second.getValueType()));
636 if (InFlag.getNode())
637 Ops.push_back(InFlag);
640 return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
642 int OpCode = doesNotReturn ? HexagonISD::CALLv3nr : HexagonISD::CALLv3;
643 Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
644 InFlag = Chain.getValue(1);
646 // Create the CALLSEQ_END node.
647 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
648 DAG.getIntPtrConstant(0, true), InFlag, dl);
649 InFlag = Chain.getValue(1);
651 // Handle result values, copying them out of physregs into vregs that we
653 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
654 InVals, OutVals, Callee);
657 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
658 bool isSEXTLoad, SDValue &Base,
659 SDValue &Offset, bool &isInc,
661 if (Ptr->getOpcode() != ISD::ADD)
664 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
665 isInc = (Ptr->getOpcode() == ISD::ADD);
666 Base = Ptr->getOperand(0);
667 Offset = Ptr->getOperand(1);
668 // Ensure that Offset is a constant.
669 return (isa<ConstantSDNode>(Offset));
675 // TODO: Put this function along with the other isS* functions in
676 // HexagonISelDAGToDAG.cpp into a common file. Or better still, use the
677 // functions defined in HexagonOperands.td.
678 static bool Is_PostInc_S4_Offset(SDNode * S, int ShiftAmount) {
679 ConstantSDNode *N = cast<ConstantSDNode>(S);
681 // immS4 predicate - True if the immediate fits in a 4-bit sign extended.
683 int64_t v = (int64_t)N->getSExtValue();
685 if (ShiftAmount > 0) {
687 v = v >> ShiftAmount;
689 return (v <= 7) && (v >= -8) && (m == 0);
692 /// getPostIndexedAddressParts - returns true by value, base pointer and
693 /// offset pointer and addressing mode by reference if this node can be
694 /// combined with a load / store to form a post-indexed load / store.
695 bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
698 ISD::MemIndexedMode &AM,
699 SelectionDAG &DAG) const
703 bool isSEXTLoad = false;
705 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
706 VT = LD->getMemoryVT();
707 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
708 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
709 VT = ST->getMemoryVT();
710 if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore()) {
718 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
720 // ShiftAmount = number of left-shifted bits in the Hexagon instruction.
721 int ShiftAmount = VT.getSizeInBits() / 16;
722 if (isLegal && Is_PostInc_S4_Offset(Offset.getNode(), ShiftAmount)) {
723 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
730 SDValue HexagonTargetLowering::LowerINLINEASM(SDValue Op,
731 SelectionDAG &DAG) const {
732 SDNode *Node = Op.getNode();
733 MachineFunction &MF = DAG.getMachineFunction();
734 auto &FuncInfo = *MF.getInfo<HexagonMachineFunctionInfo>();
735 switch (Node->getOpcode()) {
736 case ISD::INLINEASM: {
737 unsigned NumOps = Node->getNumOperands();
738 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
739 --NumOps; // Ignore the flag operand.
741 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
742 if (FuncInfo.hasClobberLR())
745 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
746 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
747 ++i; // Skip the ID value.
749 switch (InlineAsm::getKind(Flags)) {
750 default: llvm_unreachable("Bad flags!");
751 case InlineAsm::Kind_RegDef:
752 case InlineAsm::Kind_RegUse:
753 case InlineAsm::Kind_Imm:
754 case InlineAsm::Kind_Clobber:
755 case InlineAsm::Kind_Mem: {
756 for (; NumVals; --NumVals, ++i) {}
759 case InlineAsm::Kind_RegDefEarlyClobber: {
760 for (; NumVals; --NumVals, ++i) {
762 cast<RegisterSDNode>(Node->getOperand(i))->getReg();
765 const HexagonRegisterInfo *QRI = Subtarget.getRegisterInfo();
766 if (Reg == QRI->getRARegister()) {
767 FuncInfo.setHasClobberLR(true);
782 // Taken from the XCore backend.
784 SDValue HexagonTargetLowering::
785 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
787 SDValue Chain = Op.getOperand(0);
788 SDValue Table = Op.getOperand(1);
789 SDValue Index = Op.getOperand(2);
791 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
792 unsigned JTI = JT->getIndex();
793 MachineFunction &MF = DAG.getMachineFunction();
794 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
795 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
797 // Mark all jump table targets as address taken.
798 const std::vector<MachineJumpTableEntry> &JTE = MJTI->getJumpTables();
799 const std::vector<MachineBasicBlock*> &JTBBs = JTE[JTI].MBBs;
800 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
801 MachineBasicBlock *MBB = JTBBs[i];
802 MBB->setHasAddressTaken();
803 // This line is needed to set the hasAddressTaken flag on the BasicBlock
805 BlockAddress::get(const_cast<BasicBlock *>(MBB->getBasicBlock()));
808 SDValue JumpTableBase = DAG.getNode(HexagonISD::JT, dl,
809 getPointerTy(), TargetJT);
810 SDValue ShiftIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
811 DAG.getConstant(2, MVT::i32));
812 SDValue JTAddress = DAG.getNode(ISD::ADD, dl, MVT::i32, JumpTableBase,
814 SDValue LoadTarget = DAG.getLoad(MVT::i32, dl, Chain, JTAddress,
815 MachinePointerInfo(), false, false, false,
817 return DAG.getNode(HexagonISD::BR_JT, dl, MVT::Other, Chain, LoadTarget);
822 HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
823 SelectionDAG &DAG) const {
824 SDValue Chain = Op.getOperand(0);
825 SDValue Size = Op.getOperand(1);
826 SDValue Align = Op.getOperand(2);
829 ConstantSDNode *AlignConst = dyn_cast<ConstantSDNode>(Align);
830 assert(AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC");
832 unsigned A = AlignConst->getSExtValue();
833 auto &HFI = *Subtarget.getFrameLowering();
834 // "Zero" means natural stack alignment.
836 A = HFI.getStackAlignment();
839 dbgs () << LLVM_FUNCTION_NAME << " Align: " << A << " Size: ";
840 Size.getNode()->dump(&DAG);
844 SDValue AC = DAG.getConstant(A, MVT::i32);
845 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
846 return DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
850 HexagonTargetLowering::LowerFormalArguments(SDValue Chain,
851 CallingConv::ID CallConv,
854 SmallVectorImpl<ISD::InputArg> &Ins,
855 SDLoc dl, SelectionDAG &DAG,
856 SmallVectorImpl<SDValue> &InVals)
859 MachineFunction &MF = DAG.getMachineFunction();
860 MachineFrameInfo *MFI = MF.getFrameInfo();
861 MachineRegisterInfo &RegInfo = MF.getRegInfo();
862 auto &FuncInfo = *MF.getInfo<HexagonMachineFunctionInfo>();
864 // Assign locations to all of the incoming arguments.
865 SmallVector<CCValAssign, 16> ArgLocs;
866 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
869 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
871 // For LLVM, in the case when returning a struct by value (>8byte),
872 // the first argument is a pointer that points to the location on caller's
873 // stack where the return value will be stored. For Hexagon, the location on
874 // caller's stack is passed only when the struct size is smaller than (and
875 // equal to) 8 bytes. If not, no address will be passed into callee and
876 // callee return the result direclty through R0/R1.
878 SmallVector<SDValue, 4> MemOps;
880 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
881 CCValAssign &VA = ArgLocs[i];
882 ISD::ArgFlagsTy Flags = Ins[i].Flags;
884 unsigned StackLocation;
887 if ( (VA.isRegLoc() && !Flags.isByVal())
888 || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) {
889 // Arguments passed in registers
890 // 1. int, long long, ptr args that get allocated in register.
891 // 2. Large struct that gets an register to put its address in.
892 EVT RegVT = VA.getLocVT();
893 if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
894 RegVT == MVT::i32 || RegVT == MVT::f32) {
896 RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
897 RegInfo.addLiveIn(VA.getLocReg(), VReg);
898 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
899 } else if (RegVT == MVT::i64 || RegVT == MVT::f64) {
901 RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
902 RegInfo.addLiveIn(VA.getLocReg(), VReg);
903 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
907 } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) {
908 assert (0 && "ByValSize must be bigger than 8 bytes");
911 assert(VA.isMemLoc());
913 if (Flags.isByVal()) {
914 // If it's a byval parameter, then we need to compute the
915 // "real" size, not the size of the pointer.
916 ObjSize = Flags.getByValSize();
918 ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3;
921 StackLocation = HEXAGON_LRFP_SIZE + VA.getLocMemOffset();
922 // Create the frame index object for this incoming parameter...
923 FI = MFI->CreateFixedObject(ObjSize, StackLocation, true);
925 // Create the SelectionDAG nodes cordl, responding to a load
926 // from this parameter.
927 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
929 if (Flags.isByVal()) {
930 // If it's a pass-by-value aggregate, then do not dereference the stack
931 // location. Instead, we should generate a reference to the stack
933 InVals.push_back(FIN);
935 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
936 MachinePointerInfo(), false, false,
943 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
946 // This will point to the next argument passed via stack.
947 int FrameIndex = MFI->CreateFixedObject(Hexagon_PointerSize,
949 CCInfo.getNextStackOffset(),
951 FuncInfo.setVarArgsFrameIndex(FrameIndex);
958 HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
959 // VASTART stores the address of the VarArgsFrameIndex slot into the
960 // memory location argument.
961 MachineFunction &MF = DAG.getMachineFunction();
962 HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>();
963 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32);
964 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
965 return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr,
966 Op.getOperand(1), MachinePointerInfo(SV), false,
970 // Creates a SPLAT instruction for a constant value VAL.
971 static SDValue createSplat(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue Val) {
972 if (VT.getSimpleVT() == MVT::v4i8)
973 return DAG.getNode(HexagonISD::VSPLATB, dl, VT, Val);
975 if (VT.getSimpleVT() == MVT::v4i16)
976 return DAG.getNode(HexagonISD::VSPLATH, dl, VT, Val);
981 static bool isSExtFree(SDValue N) {
982 // A sign-extend of a truncate of a sign-extend is free.
983 if (N.getOpcode() == ISD::TRUNCATE &&
984 N.getOperand(0).getOpcode() == ISD::AssertSext)
986 // We have sign-extended loads.
987 if (N.getOpcode() == ISD::LOAD)
992 SDValue HexagonTargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
994 SDValue InpVal = Op.getOperand(0);
995 if (isa<ConstantSDNode>(InpVal)) {
996 uint64_t V = cast<ConstantSDNode>(InpVal)->getZExtValue();
997 return DAG.getTargetConstant(countPopulation(V), MVT::i64);
999 SDValue PopOut = DAG.getNode(HexagonISD::POPCOUNT, dl, MVT::i32, InpVal);
1000 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, PopOut);
1003 SDValue HexagonTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1006 SDValue LHS = Op.getOperand(0);
1007 SDValue RHS = Op.getOperand(1);
1008 SDValue Cmp = Op.getOperand(2);
1009 ISD::CondCode CC = cast<CondCodeSDNode>(Cmp)->get();
1011 EVT VT = Op.getValueType();
1012 EVT LHSVT = LHS.getValueType();
1013 EVT RHSVT = RHS.getValueType();
1015 if (LHSVT == MVT::v2i16) {
1016 assert(ISD::isSignedIntSetCC(CC) || ISD::isUnsignedIntSetCC(CC));
1017 unsigned ExtOpc = ISD::isSignedIntSetCC(CC) ? ISD::SIGN_EXTEND
1019 SDValue LX = DAG.getNode(ExtOpc, dl, MVT::v2i32, LHS);
1020 SDValue RX = DAG.getNode(ExtOpc, dl, MVT::v2i32, RHS);
1021 SDValue SC = DAG.getNode(ISD::SETCC, dl, MVT::v2i1, LX, RX, Cmp);
1025 // Treat all other vector types as legal.
1029 // Equals and not equals should use sign-extend, not zero-extend, since
1030 // we can represent small negative values in the compare instructions.
1031 // The LLVM default is to use zero-extend arbitrarily in these cases.
1032 if ((CC == ISD::SETEQ || CC == ISD::SETNE) &&
1033 (RHSVT == MVT::i8 || RHSVT == MVT::i16) &&
1034 (LHSVT == MVT::i8 || LHSVT == MVT::i16)) {
1035 ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);
1036 if (C && C->getAPIntValue().isNegative()) {
1037 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1038 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1039 return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1040 LHS, RHS, Op.getOperand(2));
1042 if (isSExtFree(LHS) || isSExtFree(RHS)) {
1043 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1044 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1045 return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1046 LHS, RHS, Op.getOperand(2));
1052 SDValue HexagonTargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG)
1054 SDValue PredOp = Op.getOperand(0);
1055 SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2);
1056 EVT OpVT = Op1.getValueType();
1059 if (OpVT == MVT::v2i16) {
1060 SDValue X1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op1);
1061 SDValue X2 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op2);
1062 SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2);
1063 SDValue TR = DAG.getNode(ISD::TRUNCATE, DL, MVT::v2i16, SL);
1070 // Handle only specific vector loads.
1071 SDValue HexagonTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1072 EVT VT = Op.getValueType();
1074 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1075 SDValue Chain = LoadNode->getChain();
1076 SDValue Ptr = Op.getOperand(1);
1077 SDValue LoweredLoad;
1079 SDValue Base = LoadNode->getBasePtr();
1080 ISD::LoadExtType Ext = LoadNode->getExtensionType();
1081 unsigned Alignment = LoadNode->getAlignment();
1084 if(Ext == ISD::NON_EXTLOAD)
1085 Ext = ISD::ZEXTLOAD;
1087 if (VT == MVT::v4i16) {
1088 if (Alignment == 2) {
1091 Loads[0] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Base,
1092 LoadNode->getPointerInfo(), MVT::i16,
1093 LoadNode->isVolatile(),
1094 LoadNode->isNonTemporal(),
1095 LoadNode->isInvariant(),
1098 SDValue Increment = DAG.getConstant(2, MVT::i32);
1099 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1100 Loads[1] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1101 LoadNode->getPointerInfo(), MVT::i16,
1102 LoadNode->isVolatile(),
1103 LoadNode->isNonTemporal(),
1104 LoadNode->isInvariant(),
1106 // SHL 16, then OR base and base+2.
1107 SDValue ShiftAmount = DAG.getConstant(16, MVT::i32);
1108 SDValue Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[1], ShiftAmount);
1109 SDValue Tmp2 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[0]);
1111 Increment = DAG.getConstant(4, MVT::i32);
1112 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1113 Loads[2] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1114 LoadNode->getPointerInfo(), MVT::i16,
1115 LoadNode->isVolatile(),
1116 LoadNode->isNonTemporal(),
1117 LoadNode->isInvariant(),
1120 Increment = DAG.getConstant(6, MVT::i32);
1121 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1122 Loads[3] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1123 LoadNode->getPointerInfo(), MVT::i16,
1124 LoadNode->isVolatile(),
1125 LoadNode->isNonTemporal(),
1126 LoadNode->isInvariant(),
1128 // SHL 16, then OR base+4 and base+6.
1129 Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[3], ShiftAmount);
1130 SDValue Tmp4 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[2]);
1131 // Combine to i64. This could be optimised out later if we can
1132 // affect reg allocation of this code.
1133 Result = DAG.getNode(HexagonISD::COMBINE, DL, MVT::i64, Tmp4, Tmp2);
1134 LoadChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
1135 Loads[0].getValue(1), Loads[1].getValue(1),
1136 Loads[2].getValue(1), Loads[3].getValue(1));
1138 // Perform default type expansion.
1139 Result = DAG.getLoad(MVT::i64, DL, Chain, Ptr, LoadNode->getPointerInfo(),
1140 LoadNode->isVolatile(), LoadNode->isNonTemporal(),
1141 LoadNode->isInvariant(), LoadNode->getAlignment());
1142 LoadChain = Result.getValue(1);
1145 llvm_unreachable("Custom lowering unsupported load");
1147 Result = DAG.getNode(ISD::BITCAST, DL, VT, Result);
1148 // Since we pretend to lower a load, we need the original chain
1149 // info attached to the result.
1150 SDValue Ops[] = { Result, LoadChain };
1152 return DAG.getMergeValues(Ops, DL);
1157 HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
1158 EVT ValTy = Op.getValueType();
1160 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1162 if (CP->isMachineConstantPoolEntry())
1163 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), ValTy,
1164 CP->getAlignment());
1166 Res = DAG.getTargetConstantPool(CP->getConstVal(), ValTy,
1167 CP->getAlignment());
1168 return DAG.getNode(HexagonISD::CP, dl, ValTy, Res);
1172 HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
1173 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1174 MachineFunction &MF = DAG.getMachineFunction();
1175 MachineFrameInfo &MFI = *MF.getFrameInfo();
1176 MFI.setReturnAddressIsTaken(true);
1178 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1181 EVT VT = Op.getValueType();
1183 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1185 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1186 SDValue Offset = DAG.getConstant(4, MVT::i32);
1187 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
1188 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
1189 MachinePointerInfo(), false, false, false, 0);
1192 // Return LR, which contains the return address. Mark it an implicit live-in.
1193 unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
1194 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
1198 HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1199 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1200 MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo();
1201 MFI.setFrameAddressIsTaken(true);
1203 EVT VT = Op.getValueType();
1205 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1206 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1207 HRI.getFrameRegister(), VT);
1209 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1210 MachinePointerInfo(),
1211 false, false, false, 0);
1215 SDValue HexagonTargetLowering::LowerATOMIC_FENCE(SDValue Op,
1216 SelectionDAG& DAG) const {
1218 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1222 SDValue HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op,
1223 SelectionDAG &DAG) const {
1225 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1226 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1228 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
1230 const HexagonTargetObjectFile *TLOF =
1231 static_cast<const HexagonTargetObjectFile *>(
1232 getTargetMachine().getObjFileLowering());
1233 if (TLOF->IsGlobalInSmallSection(GV, getTargetMachine())) {
1234 return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), Result);
1237 return DAG.getNode(HexagonISD::CONST32, dl, getPointerTy(), Result);
1240 // Specifies that for loads and stores VT can be promoted to PromotedLdStVT.
1241 void HexagonTargetLowering::promoteLdStType(EVT VT, EVT PromotedLdStVT) {
1242 if (VT != PromotedLdStVT) {
1243 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
1244 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(),
1245 PromotedLdStVT.getSimpleVT());
1247 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
1248 AddPromotedToType(ISD::STORE, VT.getSimpleVT(),
1249 PromotedLdStVT.getSimpleVT());
1254 HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
1255 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1256 SDValue BA_SD = DAG.getTargetBlockAddress(BA, MVT::i32);
1258 return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), BA_SD);
1261 //===----------------------------------------------------------------------===//
1262 // TargetLowering Implementation
1263 //===----------------------------------------------------------------------===//
1265 HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
1266 const HexagonSubtarget &STI)
1267 : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
1269 bool IsV4 = !Subtarget.hasV5TOps();
1270 auto &HRI = *Subtarget.getRegisterInfo();
1272 setPrefLoopAlignment(4);
1273 setPrefFunctionAlignment(4);
1274 setMinFunctionAlignment(2);
1275 setInsertFencesForAtomic(false);
1276 setExceptionPointerRegister(Hexagon::R0);
1277 setExceptionSelectorRegister(Hexagon::R1);
1278 setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
1280 if (EnableHexSDNodeSched)
1281 setSchedulingPreference(Sched::VLIW);
1283 setSchedulingPreference(Sched::Source);
1285 // Limits for inline expansion of memcpy/memmove
1286 MaxStoresPerMemcpy = MaxStoresPerMemcpyCL;
1287 MaxStoresPerMemcpyOptSize = MaxStoresPerMemcpyOptSizeCL;
1288 MaxStoresPerMemmove = MaxStoresPerMemmoveCL;
1289 MaxStoresPerMemmoveOptSize = MaxStoresPerMemmoveOptSizeCL;
1290 MaxStoresPerMemset = MaxStoresPerMemsetCL;
1291 MaxStoresPerMemsetOptSize = MaxStoresPerMemsetOptSizeCL;
1294 // Set up register classes.
1297 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1298 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1299 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1300 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1301 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1302 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1303 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1304 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1305 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1306 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1307 addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1309 if (Subtarget.hasV5TOps()) {
1310 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1311 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1314 // Generic action function (for use in std::for_each).
1315 auto ExpandOp = [this] (MVT VT) -> std::function<void(unsigned)> {
1316 HexagonTargetLowering *T = this;
1317 return [T, VT] (unsigned Op) { T->setOperationAction(Op, VT, Expand); };
1321 // Handling of scalar operations.
1323 // All operations default to "legal", except:
1324 // - indexed loads and stores (pre-/post-incremented),
1325 // - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
1326 // ConstantFP, DEBUGTRAP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
1327 // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
1328 // FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
1329 // which default to "expand" for at least one type.
1332 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); // Default: expand
1333 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); // Default: expand
1335 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1336 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
1337 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1338 setOperationAction(ISD::INLINEASM, MVT::Other, Custom);
1339 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
1340 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1342 // Custom legalize GlobalAddress nodes into CONST32.
1343 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1344 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
1345 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1347 // Hexagon needs to optimize cases with negative constants.
1348 setOperationAction(ISD::SETCC, MVT::i8, Custom);
1349 setOperationAction(ISD::SETCC, MVT::i16, Custom);
1351 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1352 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1353 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1354 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1356 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1357 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1358 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1361 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1363 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1364 // Increase jump tables cutover to 5, was 4.
1365 setMinimumJumpTableEntries(MinimumJumpTables);
1367 // Hexagon has instructions for add/sub with carry. The problem with
1368 // modeling these instructions is that they produce 2 results: Rdd and Px.
1369 // To model the update of Px, we will have to use Defs[p0..p3] which will
1370 // cause any predicate live range to spill. So, we pretend we dont't have
1371 // these instructions.
1372 setOperationAction(ISD::ADDE, MVT::i8, Expand);
1373 setOperationAction(ISD::ADDE, MVT::i16, Expand);
1374 setOperationAction(ISD::ADDE, MVT::i32, Expand);
1375 setOperationAction(ISD::ADDE, MVT::i64, Expand);
1376 setOperationAction(ISD::SUBE, MVT::i8, Expand);
1377 setOperationAction(ISD::SUBE, MVT::i16, Expand);
1378 setOperationAction(ISD::SUBE, MVT::i32, Expand);
1379 setOperationAction(ISD::SUBE, MVT::i64, Expand);
1380 setOperationAction(ISD::ADDC, MVT::i8, Expand);
1381 setOperationAction(ISD::ADDC, MVT::i16, Expand);
1382 setOperationAction(ISD::ADDC, MVT::i32, Expand);
1383 setOperationAction(ISD::ADDC, MVT::i64, Expand);
1384 setOperationAction(ISD::SUBC, MVT::i8, Expand);
1385 setOperationAction(ISD::SUBC, MVT::i16, Expand);
1386 setOperationAction(ISD::SUBC, MVT::i32, Expand);
1387 setOperationAction(ISD::SUBC, MVT::i64, Expand);
1389 // Only add and sub that detect overflow are the saturating ones.
1390 for (MVT VT : MVT::integer_valuetypes()) {
1391 setOperationAction(ISD::UADDO, VT, Expand);
1392 setOperationAction(ISD::SADDO, VT, Expand);
1393 setOperationAction(ISD::USUBO, VT, Expand);
1394 setOperationAction(ISD::SSUBO, VT, Expand);
1397 setOperationAction(ISD::CTLZ, MVT::i8, Promote);
1398 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
1399 setOperationAction(ISD::CTTZ, MVT::i8, Promote);
1400 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
1401 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8, Promote);
1402 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Promote);
1403 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i8, Promote);
1404 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Promote);
1406 // In V5, popcount can count # of 1s in i64 but returns i32.
1407 // On V4 it will be expanded (set later).
1408 setOperationAction(ISD::CTPOP, MVT::i8, Promote);
1409 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
1410 setOperationAction(ISD::CTPOP, MVT::i32, Promote);
1411 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
1413 // We custom lower i64 to i64 mul, so that it is not considered as a legal
1414 // operation. There is a pattern that will match i64 mul and transform it
1415 // to a series of instructions.
1416 setOperationAction(ISD::MUL, MVT::i64, Expand);
1417 setOperationAction(ISD::MULHS, MVT::i64, Expand);
1419 static unsigned IntExpOps[] = {
1420 ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM,
1421 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR,
1422 ISD::BSWAP, ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS,
1423 ISD::SMUL_LOHI, ISD::UMUL_LOHI
1425 static unsigned IntExpOpsLen = array_lengthof(IntExpOps);
1426 std::for_each(IntExpOps, IntExpOps+IntExpOpsLen, ExpandOp(MVT::i32));
1427 std::for_each(IntExpOps, IntExpOps+IntExpOpsLen, ExpandOp(MVT::i64));
1429 static unsigned FPExpOps[] = {
1430 ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
1431 ISD::FPOW, ISD::FCOPYSIGN
1433 static unsigned FPExpOpsLen = array_lengthof(FPExpOps);
1434 std::for_each(FPExpOps, FPExpOps+FPExpOpsLen, ExpandOp(MVT::f32));
1435 std::for_each(FPExpOps, FPExpOps+FPExpOpsLen, ExpandOp(MVT::f64));
1437 // No extending loads from i32.
1438 for (MVT VT : MVT::integer_valuetypes()) {
1439 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
1440 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
1441 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
1443 // Turn FP truncstore into trunc + store.
1444 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1445 // Turn FP extload into load/fextend.
1446 for (MVT VT : MVT::fp_valuetypes())
1447 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1449 // Expand BR_CC and SELECT_CC for all integer and fp types.
1450 for (MVT VT : MVT::integer_valuetypes()) {
1451 setOperationAction(ISD::BR_CC, VT, Expand);
1452 setOperationAction(ISD::SELECT_CC, VT, Expand);
1454 for (MVT VT : MVT::fp_valuetypes()) {
1455 setOperationAction(ISD::BR_CC, VT, Expand);
1456 setOperationAction(ISD::SELECT_CC, VT, Expand);
1458 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
1461 // Handling of vector operations.
1464 // Custom lower v4i16 load only. Let v4i16 store to be
1465 // promoted for now.
1466 promoteLdStType(MVT::v4i8, MVT::i32);
1467 promoteLdStType(MVT::v2i16, MVT::i32);
1468 promoteLdStType(MVT::v8i8, MVT::i64);
1469 promoteLdStType(MVT::v2i32, MVT::i64);
1471 setOperationAction(ISD::LOAD, MVT::v4i16, Custom);
1472 setOperationAction(ISD::STORE, MVT::v4i16, Promote);
1473 AddPromotedToType(ISD::LOAD, MVT::v4i16, MVT::i64);
1474 AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::i64);
1476 // Set the action for vector operations to "expand", then override it with
1477 // either "custom" or "legal" for specific cases.
1478 static unsigned VectExpOps[] = {
1479 // Integer arithmetic:
1480 ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV,
1481 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::ADDC,
1482 ISD::SUBC, ISD::SADDO, ISD::UADDO, ISD::SSUBO, ISD::USUBO,
1483 ISD::SMUL_LOHI, ISD::UMUL_LOHI,
1485 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR,
1486 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ, ISD::CTLZ_ZERO_UNDEF,
1487 ISD::CTTZ_ZERO_UNDEF,
1488 // Floating point arithmetic/math functions:
1489 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV,
1490 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN,
1491 ISD::FCOS, ISD::FPOWI, ISD::FPOW, ISD::FLOG, ISD::FLOG2,
1492 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC,
1493 ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR,
1494 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS,
1496 ISD::SELECT, ISD::ConstantPool,
1498 ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR,
1499 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT,
1500 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR,
1501 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE
1503 static unsigned VectExpOpsLen = array_lengthof(VectExpOps);
1505 for (MVT VT : MVT::vector_valuetypes()) {
1506 std::for_each(VectExpOps, VectExpOps+VectExpOpsLen, ExpandOp(VT));
1508 // Expand all extended loads and truncating stores:
1509 for (MVT TargetVT : MVT::vector_valuetypes()) {
1510 setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
1511 setTruncStoreAction(VT, TargetVT, Expand);
1514 setOperationAction(ISD::SRA, VT, Custom);
1515 setOperationAction(ISD::SHL, VT, Custom);
1516 setOperationAction(ISD::SRL, VT, Custom);
1519 // Types natively supported:
1520 static MVT NativeVT[] = {
1521 MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v32i1, MVT::v64i1,
1522 MVT::v4i8, MVT::v8i8,
1523 MVT::v2i16, MVT::v4i16,
1524 MVT::v1i32, MVT::v2i32,
1527 static unsigned NativeVTLen = array_lengthof(NativeVT);
1528 for (auto I = NativeVT, E = NativeVT+NativeVTLen; I != E; ++I) {
1529 setOperationAction(ISD::BUILD_VECTOR, *I, Custom);
1530 setOperationAction(ISD::EXTRACT_VECTOR_ELT, *I, Custom);
1531 setOperationAction(ISD::INSERT_VECTOR_ELT, *I, Custom);
1532 setOperationAction(ISD::EXTRACT_SUBVECTOR, *I, Custom);
1533 setOperationAction(ISD::INSERT_SUBVECTOR, *I, Custom);
1534 setOperationAction(ISD::CONCAT_VECTORS, *I, Custom);
1536 setOperationAction(ISD::ADD, *I, Legal);
1537 setOperationAction(ISD::SUB, *I, Legal);
1538 setOperationAction(ISD::MUL, *I, Legal);
1539 setOperationAction(ISD::AND, *I, Legal);
1540 setOperationAction(ISD::OR, *I, Legal);
1541 setOperationAction(ISD::XOR, *I, Legal);
1544 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
1545 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom);
1546 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
1547 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
1549 // Subtarget-specific operation actions.
1551 if (Subtarget.hasV5TOps()) {
1552 setOperationAction(ISD::FMA, MVT::f64, Expand);
1553 setOperationAction(ISD::FADD, MVT::f64, Expand);
1554 setOperationAction(ISD::FSUB, MVT::f64, Expand);
1555 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1557 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
1558 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
1559 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
1560 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
1561 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
1562 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
1563 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
1564 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
1565 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
1566 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
1567 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
1568 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
1571 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
1572 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Expand);
1573 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
1574 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
1575 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand);
1576 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand);
1577 setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand);
1578 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand);
1579 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
1581 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
1582 setOperationAction(ISD::CTPOP, MVT::i16, Expand);
1583 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1584 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
1586 // Expand these operations for both f32 and f64:
1587 static unsigned FPExpOpsV4[] = {
1588 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FABS, ISD::FNEG, ISD::FMA
1590 static unsigned FPExpOpsV4Len = array_lengthof(FPExpOpsV4);
1591 std::for_each(FPExpOpsV4, FPExpOpsV4+FPExpOpsV4Len, ExpandOp(MVT::f32));
1592 std::for_each(FPExpOpsV4, FPExpOpsV4+FPExpOpsV4Len, ExpandOp(MVT::f64));
1594 static ISD::CondCode FPExpCCV4[] = {
1595 ISD::SETOEQ, ISD::SETOGT, ISD::SETOLT, ISD::SETOGE, ISD::SETOLE,
1596 ISD::SETUO, ISD::SETO
1598 static unsigned FPExpCCV4Len = array_lengthof(FPExpCCV4);
1599 for (auto I = FPExpCCV4, E = FPExpCCV4+FPExpCCV4Len; I != E; ++I) {
1600 setCondCodeAction(*I, MVT::f32, Expand);
1601 setCondCodeAction(*I, MVT::f64, Expand);
1605 // Handling of indexed loads/stores: default is "expand".
1607 static MVT LSXTys[] = {
1608 MVT::i8, MVT::i16, MVT::i32, MVT::i64,
1610 static unsigned LSXTysLen = array_lengthof(LSXTys);
1612 for (auto I = LSXTys, E = LSXTys+LSXTysLen; I != E; ++I) {
1613 setIndexedLoadAction(ISD::POST_INC, *I, Legal);
1614 setIndexedStoreAction(ISD::POST_INC, *I, Legal);
1617 computeRegisterProperties(&HRI);
1620 // Library calls for unsupported operations
1622 bool FastMath = EnableFastMath;
1624 setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
1625 setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
1626 setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
1627 setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
1628 setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
1629 setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
1630 setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
1631 setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
1633 setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
1634 setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
1635 setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
1636 setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
1637 setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
1638 setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
1641 // Handle single-precision floating point operations on V4.
1643 setLibcallName(RTLIB::ADD_F32, "__hexagon_fast_addsf3");
1644 setLibcallName(RTLIB::SUB_F32, "__hexagon_fast_subsf3");
1645 setLibcallName(RTLIB::MUL_F32, "__hexagon_fast_mulsf3");
1646 setLibcallName(RTLIB::OGT_F32, "__hexagon_fast_gtsf2");
1647 setLibcallName(RTLIB::OLT_F32, "__hexagon_fast_ltsf2");
1648 // Double-precision compares.
1649 setLibcallName(RTLIB::OGT_F64, "__hexagon_fast_gtdf2");
1650 setLibcallName(RTLIB::OLT_F64, "__hexagon_fast_ltdf2");
1652 setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
1653 setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3");
1654 setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3");
1655 setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2");
1656 setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2");
1657 // Double-precision compares.
1658 setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
1659 setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2");
1663 // This is the only fast library function for sqrtd.
1665 setLibcallName(RTLIB::SQRT_F64, "__hexagon_fast2_sqrtdf2");
1667 // Prefix is: nothing for "slow-math",
1668 // "fast2_" for V4 fast-math and V5+ fast-math double-precision
1669 // (actually, keep fast-math and fast-math2 separate for now)
1671 setLibcallName(RTLIB::ADD_F64, "__hexagon_fast_adddf3");
1672 setLibcallName(RTLIB::SUB_F64, "__hexagon_fast_subdf3");
1673 setLibcallName(RTLIB::MUL_F64, "__hexagon_fast_muldf3");
1674 setLibcallName(RTLIB::DIV_F64, "__hexagon_fast_divdf3");
1675 // Calling __hexagon_fast2_divsf3 with fast-math on V5 (ok).
1676 setLibcallName(RTLIB::DIV_F32, "__hexagon_fast_divsf3");
1678 setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
1679 setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
1680 setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
1681 setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
1682 setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
1685 if (Subtarget.hasV5TOps()) {
1687 setLibcallName(RTLIB::SQRT_F32, "__hexagon_fast2_sqrtf");
1689 setLibcallName(RTLIB::SQRT_F32, "__hexagon_sqrtf");
1692 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf");
1693 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf");
1694 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf");
1695 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf");
1696 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf");
1697 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf");
1698 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf");
1699 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf");
1700 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi");
1701 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi");
1702 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi");
1703 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi");
1704 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi");
1705 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi");
1706 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi");
1707 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi");
1708 setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2");
1709 setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2");
1710 setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2");
1711 setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2");
1712 setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2");
1713 setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2");
1714 setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2");
1715 setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2");
1716 setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2");
1717 setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2");
1718 setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2");
1719 setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2");
1720 setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2");
1721 setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2");
1724 // These cause problems when the shift amount is non-constant.
1725 setLibcallName(RTLIB::SHL_I128, nullptr);
1726 setLibcallName(RTLIB::SRL_I128, nullptr);
1727 setLibcallName(RTLIB::SRA_I128, nullptr);
1731 const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
1733 default: return nullptr;
1734 case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
1735 case HexagonISD::ARGEXTEND: return "HexagonISD::ARGEXTEND";
1736 case HexagonISD::AT_GOT: return "HexagonISD::AT_GOT";
1737 case HexagonISD::AT_PCREL: return "HexagonISD::AT_PCREL";
1738 case HexagonISD::BARRIER: return "HexagonISD::BARRIER";
1739 case HexagonISD::BR_JT: return "HexagonISD::BR_JT";
1740 case HexagonISD::CALLR: return "HexagonISD::CALLR";
1741 case HexagonISD::CALLv3nr: return "HexagonISD::CALLv3nr";
1742 case HexagonISD::CALLv3: return "HexagonISD::CALLv3";
1743 case HexagonISD::COMBINE: return "HexagonISD::COMBINE";
1744 case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
1745 case HexagonISD::CONST32: return "HexagonISD::CONST32";
1746 case HexagonISD::CP: return "HexagonISD::CP";
1747 case HexagonISD::DCFETCH: return "HexagonISD::DCFETCH";
1748 case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
1749 case HexagonISD::EXTRACTU: return "HexagonISD::EXTRACTU";
1750 case HexagonISD::EXTRACTURP: return "HexagonISD::EXTRACTURP";
1751 case HexagonISD::FCONST32: return "HexagonISD::FCONST32";
1752 case HexagonISD::INSERT: return "HexagonISD::INSERT";
1753 case HexagonISD::INSERTRP: return "HexagonISD::INSERTRP";
1754 case HexagonISD::JT: return "HexagonISD::JT";
1755 case HexagonISD::PACKHL: return "HexagonISD::PACKHL";
1756 case HexagonISD::PIC_ADD: return "HexagonISD::PIC_ADD";
1757 case HexagonISD::POPCOUNT: return "HexagonISD::POPCOUNT";
1758 case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
1759 case HexagonISD::SHUFFEB: return "HexagonISD::SHUFFEB";
1760 case HexagonISD::SHUFFEH: return "HexagonISD::SHUFFEH";
1761 case HexagonISD::SHUFFOB: return "HexagonISD::SHUFFOB";
1762 case HexagonISD::SHUFFOH: return "HexagonISD::SHUFFOH";
1763 case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
1764 case HexagonISD::VCMPBEQ: return "HexagonISD::VCMPBEQ";
1765 case HexagonISD::VCMPBGT: return "HexagonISD::VCMPBGT";
1766 case HexagonISD::VCMPBGTU: return "HexagonISD::VCMPBGTU";
1767 case HexagonISD::VCMPHEQ: return "HexagonISD::VCMPHEQ";
1768 case HexagonISD::VCMPHGT: return "HexagonISD::VCMPHGT";
1769 case HexagonISD::VCMPHGTU: return "HexagonISD::VCMPHGTU";
1770 case HexagonISD::VCMPWEQ: return "HexagonISD::VCMPWEQ";
1771 case HexagonISD::VCMPWGT: return "HexagonISD::VCMPWGT";
1772 case HexagonISD::VCMPWGTU: return "HexagonISD::VCMPWGTU";
1773 case HexagonISD::VSHLH: return "HexagonISD::VSHLH";
1774 case HexagonISD::VSHLW: return "HexagonISD::VSHLW";
1775 case HexagonISD::VSPLATB: return "HexagonISD::VSPLTB";
1776 case HexagonISD::VSPLATH: return "HexagonISD::VSPLATH";
1777 case HexagonISD::VSRAH: return "HexagonISD::VSRAH";
1778 case HexagonISD::VSRAW: return "HexagonISD::VSRAW";
1779 case HexagonISD::VSRLH: return "HexagonISD::VSRLH";
1780 case HexagonISD::VSRLW: return "HexagonISD::VSRLW";
1781 case HexagonISD::VSXTBH: return "HexagonISD::VSXTBH";
1782 case HexagonISD::VSXTBW: return "HexagonISD::VSXTBW";
1786 bool HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
1787 EVT MTy1 = EVT::getEVT(Ty1);
1788 EVT MTy2 = EVT::getEVT(Ty2);
1789 if (!MTy1.isSimple() || !MTy2.isSimple())
1791 return (MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32);
1794 bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1795 if (!VT1.isSimple() || !VT2.isSimple())
1797 return (VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32);
1800 // shouldExpandBuildVectorWithShuffles
1801 // Should we expand the build vector with shuffles?
1803 HexagonTargetLowering::shouldExpandBuildVectorWithShuffles(EVT VT,
1804 unsigned DefinedValues) const {
1806 // Hexagon vector shuffle operates on element sizes of bytes or halfwords
1807 EVT EltVT = VT.getVectorElementType();
1808 int EltBits = EltVT.getSizeInBits();
1809 if ((EltBits != 8) && (EltBits != 16))
1812 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
1815 // LowerVECTOR_SHUFFLE - Lower a vector shuffle (V1, V2, V3). V1 and
1816 // V2 are the two vectors to select data from, V3 is the permutation.
1817 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
1818 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
1819 SDValue V1 = Op.getOperand(0);
1820 SDValue V2 = Op.getOperand(1);
1822 EVT VT = Op.getValueType();
1824 if (V2.getOpcode() == ISD::UNDEF)
1827 if (SVN->isSplat()) {
1828 int Lane = SVN->getSplatIndex();
1829 if (Lane == -1) Lane = 0;
1831 // Test if V1 is a SCALAR_TO_VECTOR.
1832 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
1833 return createSplat(DAG, dl, VT, V1.getOperand(0));
1835 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
1836 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
1838 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
1839 !isa<ConstantSDNode>(V1.getOperand(0))) {
1840 bool IsScalarToVector = true;
1841 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
1842 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
1843 IsScalarToVector = false;
1846 if (IsScalarToVector)
1847 return createSplat(DAG, dl, VT, V1.getOperand(0));
1849 return createSplat(DAG, dl, VT, DAG.getConstant(Lane, MVT::i32));
1852 // FIXME: We need to support more general vector shuffles. See
1853 // below the comment from the ARM backend that deals in the general
1854 // case with the vector shuffles. For now, let expand handle these.
1857 // If the shuffle is not directly supported and it has 4 elements, use
1858 // the PerfectShuffle-generated table to synthesize it from other shuffles.
1861 // If BUILD_VECTOR has same base element repeated several times,
1863 static bool isCommonSplatElement(BuildVectorSDNode *BVN) {
1864 unsigned NElts = BVN->getNumOperands();
1865 SDValue V0 = BVN->getOperand(0);
1867 for (unsigned i = 1, e = NElts; i != e; ++i) {
1868 if (BVN->getOperand(i) != V0)
1874 // LowerVECTOR_SHIFT - Lower a vector shift. Try to convert
1875 // <VT> = SHL/SRA/SRL <VT> by <VT> to Hexagon specific
1876 // <VT> = SHL/SRA/SRL <VT> by <IT/i32>.
1877 static SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) {
1878 BuildVectorSDNode *BVN = 0;
1879 SDValue V1 = Op.getOperand(0);
1880 SDValue V2 = Op.getOperand(1);
1883 EVT VT = Op.getValueType();
1885 if ((BVN = dyn_cast<BuildVectorSDNode>(V1.getNode())) &&
1886 isCommonSplatElement(BVN))
1888 else if ((BVN = dyn_cast<BuildVectorSDNode>(V2.getNode())) &&
1889 isCommonSplatElement(BVN))
1894 SDValue CommonSplat = BVN->getOperand(0);
1897 if (VT.getSimpleVT() == MVT::v4i16) {
1898 switch (Op.getOpcode()) {
1900 Result = DAG.getNode(HexagonISD::VSRAH, dl, VT, V3, CommonSplat);
1903 Result = DAG.getNode(HexagonISD::VSHLH, dl, VT, V3, CommonSplat);
1906 Result = DAG.getNode(HexagonISD::VSRLH, dl, VT, V3, CommonSplat);
1911 } else if (VT.getSimpleVT() == MVT::v2i32) {
1912 switch (Op.getOpcode()) {
1914 Result = DAG.getNode(HexagonISD::VSRAW, dl, VT, V3, CommonSplat);
1917 Result = DAG.getNode(HexagonISD::VSHLW, dl, VT, V3, CommonSplat);
1920 Result = DAG.getNode(HexagonISD::VSRLW, dl, VT, V3, CommonSplat);
1929 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
1933 HexagonTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
1934 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
1936 EVT VT = Op.getValueType();
1938 unsigned Size = VT.getSizeInBits();
1940 // A vector larger than 64 bits cannot be represented in Hexagon.
1941 // Expand will split the vector.
1945 APInt APSplatBits, APSplatUndef;
1946 unsigned SplatBitSize;
1948 unsigned NElts = BVN->getNumOperands();
1950 // Try to generate a SPLAT instruction.
1951 if ((VT.getSimpleVT() == MVT::v4i8 || VT.getSimpleVT() == MVT::v4i16) &&
1952 (BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
1953 HasAnyUndefs, 0, true) && SplatBitSize <= 16)) {
1954 unsigned SplatBits = APSplatBits.getZExtValue();
1955 int32_t SextVal = ((int32_t) (SplatBits << (32 - SplatBitSize)) >>
1956 (32 - SplatBitSize));
1957 return createSplat(DAG, dl, VT, DAG.getConstant(SextVal, MVT::i32));
1960 // Try to generate COMBINE to build v2i32 vectors.
1961 if (VT.getSimpleVT() == MVT::v2i32) {
1962 SDValue V0 = BVN->getOperand(0);
1963 SDValue V1 = BVN->getOperand(1);
1965 if (V0.getOpcode() == ISD::UNDEF)
1966 V0 = DAG.getConstant(0, MVT::i32);
1967 if (V1.getOpcode() == ISD::UNDEF)
1968 V1 = DAG.getConstant(0, MVT::i32);
1970 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(V0);
1971 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(V1);
1972 // If the element isn't a constant, it is in a register:
1973 // generate a COMBINE Register Register instruction.
1975 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
1977 // If one of the operands is an 8 bit integer constant, generate
1978 // a COMBINE Immediate Immediate instruction.
1979 if (isInt<8>(C0->getSExtValue()) ||
1980 isInt<8>(C1->getSExtValue()))
1981 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
1984 // Try to generate a S2_packhl to build v2i16 vectors.
1985 if (VT.getSimpleVT() == MVT::v2i16) {
1986 for (unsigned i = 0, e = NElts; i != e; ++i) {
1987 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF)
1989 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(BVN->getOperand(i));
1990 // If the element isn't a constant, it is in a register:
1991 // generate a S2_packhl instruction.
1993 SDValue pack = DAG.getNode(HexagonISD::PACKHL, dl, MVT::v4i16,
1994 BVN->getOperand(1), BVN->getOperand(0));
1996 return DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::v2i16,
2002 // In the general case, generate a CONST32 or a CONST64 for constant vectors,
2003 // and insert_vector_elt for all the other cases.
2005 unsigned EltSize = Size / NElts;
2007 uint64_t Mask = ~uint64_t(0ULL) >> (64 - EltSize);
2008 bool HasNonConstantElements = false;
2010 for (unsigned i = 0, e = NElts; i != e; ++i) {
2011 // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon's
2012 // combine, const64, etc. are Big Endian.
2013 unsigned OpIdx = NElts - i - 1;
2014 SDValue Operand = BVN->getOperand(OpIdx);
2015 if (Operand.getOpcode() == ISD::UNDEF)
2019 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Operand))
2020 Val = Cst->getSExtValue();
2022 HasNonConstantElements = true;
2025 Res = (Res << EltSize) | Val;
2029 ConstVal = DAG.getConstant(Res, MVT::i64);
2031 ConstVal = DAG.getConstant(Res, MVT::i32);
2033 // When there are non constant operands, add them with INSERT_VECTOR_ELT to
2034 // ConstVal, the constant part of the vector.
2035 if (HasNonConstantElements) {
2036 EVT EltVT = VT.getVectorElementType();
2037 SDValue Width = DAG.getConstant(EltVT.getSizeInBits(), MVT::i64);
2038 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2039 DAG.getConstant(32, MVT::i64));
2041 for (unsigned i = 0, e = NElts; i != e; ++i) {
2042 // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon
2044 unsigned OpIdx = NElts - i - 1;
2045 SDValue Operand = BVN->getOperand(OpIdx);
2046 if (isa<ConstantSDNode>(Operand))
2047 // This operand is already in ConstVal.
2050 if (VT.getSizeInBits() == 64 &&
2051 Operand.getValueType().getSizeInBits() == 32) {
2052 SDValue C = DAG.getConstant(0, MVT::i32);
2053 Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand);
2056 SDValue Idx = DAG.getConstant(OpIdx, MVT::i64);
2057 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width);
2058 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2059 const SDValue Ops[] = {ConstVal, Operand, Combined};
2061 if (VT.getSizeInBits() == 32)
2062 ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2064 ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2068 return DAG.getNode(ISD::BITCAST, dl, VT, ConstVal);
2072 HexagonTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
2073 SelectionDAG &DAG) const {
2075 EVT VT = Op.getValueType();
2076 unsigned NElts = Op.getNumOperands();
2077 SDValue Vec = Op.getOperand(0);
2078 EVT VecVT = Vec.getValueType();
2079 SDValue Width = DAG.getConstant(VecVT.getSizeInBits(), MVT::i64);
2080 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2081 DAG.getConstant(32, MVT::i64));
2082 SDValue ConstVal = DAG.getConstant(0, MVT::i64);
2084 ConstantSDNode *W = dyn_cast<ConstantSDNode>(Width);
2085 ConstantSDNode *S = dyn_cast<ConstantSDNode>(Shifted);
2087 if ((VecVT.getSimpleVT() == MVT::v2i16) && (NElts == 2) && W && S) {
2088 if ((W->getZExtValue() == 32) && ((S->getZExtValue() >> 32) == 32)) {
2089 // We are trying to concat two v2i16 to a single v4i16.
2090 SDValue Vec0 = Op.getOperand(1);
2091 SDValue Combined = DAG.getNode(HexagonISD::COMBINE, dl, VT, Vec0, Vec);
2092 return DAG.getNode(ISD::BITCAST, dl, VT, Combined);
2096 if ((VecVT.getSimpleVT() == MVT::v4i8) && (NElts == 2) && W && S) {
2097 if ((W->getZExtValue() == 32) && ((S->getZExtValue() >> 32) == 32)) {
2098 // We are trying to concat two v4i8 to a single v8i8.
2099 SDValue Vec0 = Op.getOperand(1);
2100 SDValue Combined = DAG.getNode(HexagonISD::COMBINE, dl, VT, Vec0, Vec);
2101 return DAG.getNode(ISD::BITCAST, dl, VT, Combined);
2105 for (unsigned i = 0, e = NElts; i != e; ++i) {
2106 unsigned OpIdx = NElts - i - 1;
2107 SDValue Operand = Op.getOperand(OpIdx);
2109 if (VT.getSizeInBits() == 64 &&
2110 Operand.getValueType().getSizeInBits() == 32) {
2111 SDValue C = DAG.getConstant(0, MVT::i32);
2112 Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand);
2115 SDValue Idx = DAG.getConstant(OpIdx, MVT::i64);
2116 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width);
2117 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2118 const SDValue Ops[] = {ConstVal, Operand, Combined};
2120 if (VT.getSizeInBits() == 32)
2121 ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2123 ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2126 return DAG.getNode(ISD::BITCAST, dl, VT, ConstVal);
2130 HexagonTargetLowering::LowerEXTRACT_VECTOR(SDValue Op,
2131 SelectionDAG &DAG) const {
2132 EVT VT = Op.getValueType();
2133 int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
2135 SDValue Idx = Op.getOperand(1);
2136 SDValue Vec = Op.getOperand(0);
2137 EVT VecVT = Vec.getValueType();
2138 EVT EltVT = VecVT.getVectorElementType();
2139 int EltSize = EltVT.getSizeInBits();
2140 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT ?
2141 EltSize : VTN * EltSize, MVT::i64);
2143 // Constant element number.
2144 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Idx)) {
2145 uint64_t X = CI->getZExtValue();
2146 SDValue Offset = DAG.getConstant(X * EltSize, MVT::i32);
2147 const SDValue Ops[] = {Vec, Width, Offset};
2149 ConstantSDNode *CW = dyn_cast<ConstantSDNode>(Width);
2150 assert(CW && "Non constant width in LowerEXTRACT_VECTOR");
2153 MVT SVT = VecVT.getSimpleVT();
2154 uint64_t W = CW->getZExtValue();
2157 // Translate this node into EXTRACT_SUBREG.
2158 unsigned Subreg = (X == 0) ? Hexagon::subreg_loreg : 0;
2161 Subreg = Hexagon::subreg_loreg;
2162 else if (SVT == MVT::v2i32 && X == 1)
2163 Subreg = Hexagon::subreg_hireg;
2164 else if (SVT == MVT::v4i16 && X == 2)
2165 Subreg = Hexagon::subreg_hireg;
2166 else if (SVT == MVT::v8i8 && X == 4)
2167 Subreg = Hexagon::subreg_hireg;
2169 llvm_unreachable("Bad offset");
2170 N = DAG.getTargetExtractSubreg(Subreg, dl, MVT::i32, Vec);
2172 } else if (VecVT.getSizeInBits() == 32) {
2173 N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i32, Ops);
2175 N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i64, Ops);
2176 if (VT.getSizeInBits() == 32)
2177 N = DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::i32, N);
2180 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2183 // Variable element number.
2184 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2185 DAG.getConstant(EltSize, MVT::i32));
2186 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2187 DAG.getConstant(32, MVT::i64));
2188 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2190 const SDValue Ops[] = {Vec, Combined};
2193 if (VecVT.getSizeInBits() == 32) {
2194 N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i32, Ops);
2196 N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i64, Ops);
2197 if (VT.getSizeInBits() == 32)
2198 N = DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::i32, N);
2200 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2204 HexagonTargetLowering::LowerINSERT_VECTOR(SDValue Op,
2205 SelectionDAG &DAG) const {
2206 EVT VT = Op.getValueType();
2207 int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
2209 SDValue Vec = Op.getOperand(0);
2210 SDValue Val = Op.getOperand(1);
2211 SDValue Idx = Op.getOperand(2);
2212 EVT VecVT = Vec.getValueType();
2213 EVT EltVT = VecVT.getVectorElementType();
2214 int EltSize = EltVT.getSizeInBits();
2215 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::INSERT_VECTOR_ELT ?
2216 EltSize : VTN * EltSize, MVT::i64);
2218 if (ConstantSDNode *C = cast<ConstantSDNode>(Idx)) {
2219 SDValue Offset = DAG.getConstant(C->getSExtValue() * EltSize, MVT::i32);
2220 const SDValue Ops[] = {Vec, Val, Width, Offset};
2223 if (VT.getSizeInBits() == 32)
2224 N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i32, Ops);
2226 N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i64, Ops);
2228 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2231 // Variable element number.
2232 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2233 DAG.getConstant(EltSize, MVT::i32));
2234 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2235 DAG.getConstant(32, MVT::i64));
2236 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2238 if (VT.getSizeInBits() == 64 &&
2239 Val.getValueType().getSizeInBits() == 32) {
2240 SDValue C = DAG.getConstant(0, MVT::i32);
2241 Val = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Val);
2244 const SDValue Ops[] = {Vec, Val, Combined};
2247 if (VT.getSizeInBits() == 32)
2248 N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2250 N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2252 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2256 HexagonTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
2257 // Assuming the caller does not have either a signext or zeroext modifier, and
2258 // only one value is accepted, any reasonable truncation is allowed.
2259 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
2262 // FIXME: in principle up to 64-bit could be made safe, but it would be very
2263 // fragile at the moment: any support for multiple value returns would be
2264 // liable to disallow tail calls involving i64 -> iN truncation in many cases.
2265 return Ty1->getPrimitiveSizeInBits() <= 32;
2269 HexagonTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
2270 SDValue Chain = Op.getOperand(0);
2271 SDValue Offset = Op.getOperand(1);
2272 SDValue Handler = Op.getOperand(2);
2275 // Mark function as containing a call to EH_RETURN.
2276 HexagonMachineFunctionInfo *FuncInfo =
2277 DAG.getMachineFunction().getInfo<HexagonMachineFunctionInfo>();
2278 FuncInfo->setHasEHReturn();
2280 unsigned OffsetReg = Hexagon::R28;
2282 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(),
2283 DAG.getRegister(Hexagon::R30, getPointerTy()),
2284 DAG.getIntPtrConstant(4));
2285 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
2287 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
2289 // Not needed we already use it as explict input to EH_RETURN.
2290 // MF.getRegInfo().addLiveOut(OffsetReg);
2292 return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
2296 HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2297 unsigned Opc = Op.getOpcode();
2301 Op.getNode()->dumpr(&DAG);
2302 if (Opc > HexagonISD::OP_BEGIN && Opc < HexagonISD::OP_END)
2303 errs() << "Check for a non-legal type in this operation\n";
2305 llvm_unreachable("Should not custom lower this!");
2306 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2307 case ISD::INSERT_SUBVECTOR: return LowerINSERT_VECTOR(Op, DAG);
2308 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR(Op, DAG);
2309 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_VECTOR(Op, DAG);
2310 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR(Op, DAG);
2311 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2312 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2315 case ISD::SRL: return LowerVECTOR_SHIFT(Op, DAG);
2316 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2317 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
2318 // Frame & Return address. Currently unimplemented.
2319 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
2320 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2321 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
2322 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
2323 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2324 case ISD::VASTART: return LowerVASTART(Op, DAG);
2325 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
2326 // Custom lower some vector loads.
2327 case ISD::LOAD: return LowerLOAD(Op, DAG);
2328 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2329 case ISD::SETCC: return LowerSETCC(Op, DAG);
2330 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
2331 case ISD::CTPOP: return LowerCTPOP(Op, DAG);
2332 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2333 case ISD::INLINEASM: return LowerINLINEASM(Op, DAG);
2338 HexagonTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2339 MachineBasicBlock *BB)
2341 switch (MI->getOpcode()) {
2342 case Hexagon::ALLOCA: {
2343 MachineFunction *MF = BB->getParent();
2344 auto *FuncInfo = MF->getInfo<HexagonMachineFunctionInfo>();
2345 FuncInfo->addAllocaAdjustInst(MI);
2348 default: llvm_unreachable("Unexpected instr type to insert");
2352 //===----------------------------------------------------------------------===//
2353 // Inline Assembly Support
2354 //===----------------------------------------------------------------------===//
2356 std::pair<unsigned, const TargetRegisterClass *>
2357 HexagonTargetLowering::getRegForInlineAsmConstraint(
2358 const TargetRegisterInfo *TRI, const std::string &Constraint,
2360 if (Constraint.size() == 1) {
2361 switch (Constraint[0]) {
2363 switch (VT.SimpleTy) {
2365 llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
2370 return std::make_pair(0U, &Hexagon::IntRegsRegClass);
2373 return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
2376 llvm_unreachable("Unknown asm register class");
2380 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
2383 /// isFPImmLegal - Returns true if the target can instruction select the
2384 /// specified FP immediate natively. If false, the legalizer will
2385 /// materialize the FP immediate as a load from a constant pool.
2386 bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2387 return Subtarget.hasV5TOps();
2390 /// isLegalAddressingMode - Return true if the addressing mode represented by
2391 /// AM is legal for this target, for a load/store of the specified type.
2392 bool HexagonTargetLowering::isLegalAddressingMode(const AddrMode &AM,
2394 // Allows a signed-extended 11-bit immediate field.
2395 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1)
2398 // No global is ever allowed as a base.
2402 int Scale = AM.Scale;
2403 if (Scale < 0) Scale = -Scale;
2405 case 0: // No scale reg, "r+i", "r", or just "i".
2407 default: // No scaled addressing mode.
2413 /// isLegalICmpImmediate - Return true if the specified immediate is legal
2414 /// icmp immediate, that is the target has icmp instructions which can compare
2415 /// a register against the immediate without having to materialize the
2416 /// immediate into a register.
2417 bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
2418 return Imm >= -512 && Imm <= 511;
2421 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2422 /// for tail call optimization. Targets which want to do tail call
2423 /// optimization should implement this function.
2424 bool HexagonTargetLowering::IsEligibleForTailCallOptimization(
2426 CallingConv::ID CalleeCC,
2428 bool isCalleeStructRet,
2429 bool isCallerStructRet,
2430 const SmallVectorImpl<ISD::OutputArg> &Outs,
2431 const SmallVectorImpl<SDValue> &OutVals,
2432 const SmallVectorImpl<ISD::InputArg> &Ins,
2433 SelectionDAG& DAG) const {
2434 const Function *CallerF = DAG.getMachineFunction().getFunction();
2435 CallingConv::ID CallerCC = CallerF->getCallingConv();
2436 bool CCMatch = CallerCC == CalleeCC;
2438 // ***************************************************************************
2439 // Look for obvious safe cases to perform tail call optimization that do not
2440 // require ABI changes.
2441 // ***************************************************************************
2443 // If this is a tail call via a function pointer, then don't do it!
2444 if (!(dyn_cast<GlobalAddressSDNode>(Callee))
2445 && !(dyn_cast<ExternalSymbolSDNode>(Callee))) {
2449 // Do not optimize if the calling conventions do not match.
2453 // Do not tail call optimize vararg calls.
2457 // Also avoid tail call optimization if either caller or callee uses struct
2458 // return semantics.
2459 if (isCalleeStructRet || isCallerStructRet)
2462 // In addition to the cases above, we also disable Tail Call Optimization if
2463 // the calling convention code that at least one outgoing argument needs to
2464 // go on the stack. We cannot check that here because at this point that
2465 // information is not available.
2469 // Return true when the given node fits in a positive half word.
2470 bool llvm::isPositiveHalfWord(SDNode *N) {
2471 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
2472 if (CN && CN->getSExtValue() > 0 && isInt<16>(CN->getSExtValue()))
2475 switch (N->getOpcode()) {
2478 case ISD::SIGN_EXTEND_INREG: