1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Hexagon uses to lower LLVM code
11 // into a selection DAG.
13 //===----------------------------------------------------------------------===//
15 #include "HexagonISelLowering.h"
16 #include "HexagonTargetMachine.h"
17 #include "HexagonMachineFunctionInfo.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonSubtarget.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/InlineAsm.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/GlobalAlias.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/CodeGen/CallingConvLower.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/CodeGen/MachineJumpTableInfo.h"
37 #include "HexagonMachineFunctionInfo.h"
38 #include "llvm/Support/CommandLine.h"
40 const unsigned Hexagon_MAX_RET_SIZE = 64;
44 EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden,
45 cl::desc("Control jump table emission on Hexagon target"));
47 int NumNamedVarArgParams = -1;
49 // Implement calling convention for Hexagon.
51 CC_Hexagon(unsigned ValNo, MVT ValVT,
52 MVT LocVT, CCValAssign::LocInfo LocInfo,
53 ISD::ArgFlagsTy ArgFlags, CCState &State);
56 CC_Hexagon32(unsigned ValNo, MVT ValVT,
57 MVT LocVT, CCValAssign::LocInfo LocInfo,
58 ISD::ArgFlagsTy ArgFlags, CCState &State);
61 CC_Hexagon64(unsigned ValNo, MVT ValVT,
62 MVT LocVT, CCValAssign::LocInfo LocInfo,
63 ISD::ArgFlagsTy ArgFlags, CCState &State);
66 RetCC_Hexagon(unsigned ValNo, MVT ValVT,
67 MVT LocVT, CCValAssign::LocInfo LocInfo,
68 ISD::ArgFlagsTy ArgFlags, CCState &State);
71 RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
72 MVT LocVT, CCValAssign::LocInfo LocInfo,
73 ISD::ArgFlagsTy ArgFlags, CCState &State);
76 RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
77 MVT LocVT, CCValAssign::LocInfo LocInfo,
78 ISD::ArgFlagsTy ArgFlags, CCState &State);
81 CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
82 MVT LocVT, CCValAssign::LocInfo LocInfo,
83 ISD::ArgFlagsTy ArgFlags, CCState &State) {
85 // NumNamedVarArgParams can not be zero for a VarArg function.
86 assert ( (NumNamedVarArgParams > 0) &&
87 "NumNamedVarArgParams is not bigger than zero.");
89 if ( (int)ValNo < NumNamedVarArgParams ) {
90 // Deal with named arguments.
91 return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
94 // Deal with un-named arguments.
96 if (ArgFlags.isByVal()) {
97 // If pass-by-value, the size allocated on stack is decided
98 // by ArgFlags.getByValSize(), not by the size of LocVT.
99 assert ((ArgFlags.getByValSize() > 8) &&
100 "ByValSize must be bigger than 8 bytes");
101 ofst = State.AllocateStack(ArgFlags.getByValSize(), 4);
102 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
105 if (LocVT == MVT::i32) {
106 ofst = State.AllocateStack(4, 4);
107 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
110 if (LocVT == MVT::i64) {
111 ofst = State.AllocateStack(8, 8);
112 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
120 CC_Hexagon (unsigned ValNo, MVT ValVT,
121 MVT LocVT, CCValAssign::LocInfo LocInfo,
122 ISD::ArgFlagsTy ArgFlags, CCState &State) {
124 if (ArgFlags.isByVal()) {
126 assert ((ArgFlags.getByValSize() > 8) &&
127 "ByValSize must be bigger than 8 bytes");
128 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(), 4);
129 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
133 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
136 if (ArgFlags.isSExt())
137 LocInfo = CCValAssign::SExt;
138 else if (ArgFlags.isZExt())
139 LocInfo = CCValAssign::ZExt;
141 LocInfo = CCValAssign::AExt;
144 if (LocVT == MVT::i32) {
145 if (!CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
149 if (LocVT == MVT::i64) {
150 if (!CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
154 return true; // CC didn't match.
158 static bool CC_Hexagon32(unsigned ValNo, MVT ValVT,
159 MVT LocVT, CCValAssign::LocInfo LocInfo,
160 ISD::ArgFlagsTy ArgFlags, CCState &State) {
162 static const unsigned RegList[] = {
163 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
166 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
167 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
171 unsigned Offset = State.AllocateStack(4, 4);
172 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
176 static bool CC_Hexagon64(unsigned ValNo, MVT ValVT,
177 MVT LocVT, CCValAssign::LocInfo LocInfo,
178 ISD::ArgFlagsTy ArgFlags, CCState &State) {
180 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
181 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
185 static const unsigned RegList1[] = {
186 Hexagon::D1, Hexagon::D2
188 static const unsigned RegList2[] = {
189 Hexagon::R1, Hexagon::R3
191 if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 2)) {
192 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
196 unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2);
197 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
201 static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT,
202 MVT LocVT, CCValAssign::LocInfo LocInfo,
203 ISD::ArgFlagsTy ArgFlags, CCState &State) {
206 if (LocVT == MVT::i1 ||
211 if (ArgFlags.isSExt())
212 LocInfo = CCValAssign::SExt;
213 else if (ArgFlags.isZExt())
214 LocInfo = CCValAssign::ZExt;
216 LocInfo = CCValAssign::AExt;
219 if (LocVT == MVT::i32) {
220 if (!RetCC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
224 if (LocVT == MVT::i64) {
225 if (!RetCC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
229 return true; // CC didn't match.
232 static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
233 MVT LocVT, CCValAssign::LocInfo LocInfo,
234 ISD::ArgFlagsTy ArgFlags, CCState &State) {
236 if (LocVT == MVT::i32) {
237 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) {
238 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
243 unsigned Offset = State.AllocateStack(4, 4);
244 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
248 static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
249 MVT LocVT, CCValAssign::LocInfo LocInfo,
250 ISD::ArgFlagsTy ArgFlags, CCState &State) {
251 if (LocVT == MVT::i64) {
252 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
253 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
258 unsigned Offset = State.AllocateStack(8, 8);
259 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
264 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
269 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
270 /// by "Src" to address "Dst" of size "Size". Alignment information is
271 /// specified by the specific parameter attribute. The copy will be passed as
272 /// a byval function parameter. Sometimes what we are copying is the end of a
273 /// larger object, the part that does not fit in registers.
275 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
276 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
279 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
280 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
281 /*isVolatile=*/false, /*AlwaysInline=*/false,
282 MachinePointerInfo(), MachinePointerInfo());
286 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
287 // passed by value, the function prototype is modified to return void and
288 // the value is stored in memory pointed by a pointer passed by caller.
290 HexagonTargetLowering::LowerReturn(SDValue Chain,
291 CallingConv::ID CallConv, bool isVarArg,
292 const SmallVectorImpl<ISD::OutputArg> &Outs,
293 const SmallVectorImpl<SDValue> &OutVals,
294 DebugLoc dl, SelectionDAG &DAG) const {
296 // CCValAssign - represent the assignment of the return value to locations.
297 SmallVector<CCValAssign, 16> RVLocs;
299 // CCState - Info about the registers and stack slot.
300 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
301 getTargetMachine(), RVLocs, *DAG.getContext());
303 // Analyze return values of ISD::RET
304 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
306 // If this is the first return lowered for this function, add the regs to the
307 // liveout set for the function.
308 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
309 for (unsigned i = 0; i != RVLocs.size(); ++i)
310 if (RVLocs[i].isRegLoc())
311 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
315 // Copy the result values into the output registers.
316 for (unsigned i = 0; i != RVLocs.size(); ++i) {
317 CCValAssign &VA = RVLocs[i];
319 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
321 // Guarantee that all emitted copies are stuck together with flags.
322 Flag = Chain.getValue(1);
326 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
328 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, Chain);
334 /// LowerCallResult - Lower the result values of an ISD::CALL into the
335 /// appropriate copies out of appropriate physical registers. This assumes that
336 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
337 /// being lowered. Returns a SDNode with the same number of values as the
340 HexagonTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
341 CallingConv::ID CallConv, bool isVarArg,
343 SmallVectorImpl<ISD::InputArg> &Ins,
344 DebugLoc dl, SelectionDAG &DAG,
345 SmallVectorImpl<SDValue> &InVals,
346 const SmallVectorImpl<SDValue> &OutVals,
347 SDValue Callee) const {
349 // Assign locations to each value returned by this call.
350 SmallVector<CCValAssign, 16> RVLocs;
352 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
353 getTargetMachine(), RVLocs, *DAG.getContext());
355 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
357 // Copy all of the result registers out of their specified physreg.
358 for (unsigned i = 0; i != RVLocs.size(); ++i) {
359 Chain = DAG.getCopyFromReg(Chain, dl,
360 RVLocs[i].getLocReg(),
361 RVLocs[i].getValVT(), InFlag).getValue(1);
362 InFlag = Chain.getValue(2);
363 InVals.push_back(Chain.getValue(0));
369 /// LowerCall - Functions arguments are copied from virtual regs to
370 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
372 HexagonTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
373 CallingConv::ID CallConv, bool isVarArg,
375 const SmallVectorImpl<ISD::OutputArg> &Outs,
376 const SmallVectorImpl<SDValue> &OutVals,
377 const SmallVectorImpl<ISD::InputArg> &Ins,
378 DebugLoc dl, SelectionDAG &DAG,
379 SmallVectorImpl<SDValue> &InVals) const {
381 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
383 // Analyze operands of the call, assigning locations to each operand.
384 SmallVector<CCValAssign, 16> ArgLocs;
385 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
386 getTargetMachine(), ArgLocs, *DAG.getContext());
388 // Check for varargs.
389 NumNamedVarArgParams = -1;
390 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Callee))
392 const Function* CalleeFn = NULL;
393 Callee = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, MVT::i32);
394 if ((CalleeFn = dyn_cast<Function>(GA->getGlobal())))
396 // If a function has zero args and is a vararg function, that's
397 // disallowed so it must be an undeclared function. Do not assume
398 // varargs if the callee is undefined.
399 if (CalleeFn->isVarArg() &&
400 CalleeFn->getFunctionType()->getNumParams() != 0) {
401 NumNamedVarArgParams = CalleeFn->getFunctionType()->getNumParams();
406 if (NumNamedVarArgParams > 0)
407 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
409 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
413 bool StructAttrFlag =
414 DAG.getMachineFunction().getFunction()->hasStructRetAttr();
415 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
416 isVarArg, IsStructRet,
418 Outs, OutVals, Ins, DAG);
419 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i){
420 CCValAssign &VA = ArgLocs[i];
427 DEBUG(dbgs () << "Eligible for Tail Call\n");
430 "Argument must be passed on stack. Not eligible for Tail Call\n");
433 // Get a count of how many bytes are to be pushed on the stack.
434 unsigned NumBytes = CCInfo.getNextStackOffset();
435 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
436 SmallVector<SDValue, 8> MemOpChains;
439 DAG.getCopyFromReg(Chain, dl, TM.getRegisterInfo()->getStackRegister(),
442 // Walk the register/memloc assignments, inserting copies/loads.
443 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
444 CCValAssign &VA = ArgLocs[i];
445 SDValue Arg = OutVals[i];
446 ISD::ArgFlagsTy Flags = Outs[i].Flags;
448 // Promote the value if needed.
449 switch (VA.getLocInfo()) {
451 // Loc info must be one of Full, SExt, ZExt, or AExt.
452 assert(0 && "Unknown loc info!");
453 case CCValAssign::Full:
455 case CCValAssign::SExt:
456 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
458 case CCValAssign::ZExt:
459 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
461 case CCValAssign::AExt:
462 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
467 unsigned LocMemOffset = VA.getLocMemOffset();
468 SDValue PtrOff = DAG.getConstant(LocMemOffset, StackPtr.getValueType());
469 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
471 if (Flags.isByVal()) {
472 // The argument is a struct passed by value. According to LLVM, "Arg"
474 MemOpChains.push_back(CreateCopyOfByValArgument(Arg, PtrOff, Chain,
477 // The argument is not passed by value. "Arg" is a buildin type. It is
479 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
480 MachinePointerInfo(),false, false,
486 // Arguments that can be passed on register must be kept at RegsToPass
489 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
493 // Transform all store nodes into one single node because all store
494 // nodes are independent of each other.
495 if (!MemOpChains.empty()) {
496 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0],
501 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes,
502 getPointerTy(), true));
504 // Build a sequence of copy-to-reg nodes chained together with token
505 // chain and flag operands which copy the outgoing args into registers.
506 // The InFlag in necessary since all emited instructions must be
510 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
511 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
512 RegsToPass[i].second, InFlag);
513 InFlag = Chain.getValue(1);
517 // For tail calls lower the arguments to the 'real' stack slot.
519 // Force all the incoming stack arguments to be loaded from the stack
520 // before any new outgoing arguments are stored to the stack, because the
521 // outgoing stack slots may alias the incoming argument stack slots, and
522 // the alias isn't otherwise explicit. This is slightly more conservative
523 // than necessary, because it means that each store effectively depends
524 // on every argument instead of just those arguments it would clobber.
526 // Do not flag preceeding copytoreg stuff together with the following stuff.
528 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
529 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
530 RegsToPass[i].second, InFlag);
531 InFlag = Chain.getValue(1);
536 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
537 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
538 // node so that legalize doesn't hack it.
539 if (flag_aligned_memcpy) {
540 const char *MemcpyName =
541 "__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes";
543 DAG.getTargetExternalSymbol(MemcpyName, getPointerTy());
544 flag_aligned_memcpy = false;
545 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
546 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy());
547 } else if (ExternalSymbolSDNode *S =
548 dyn_cast<ExternalSymbolSDNode>(Callee)) {
549 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
552 // Returns a chain & a flag for retval copy to use.
553 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
554 SmallVector<SDValue, 8> Ops;
555 Ops.push_back(Chain);
556 Ops.push_back(Callee);
558 // Add argument registers to the end of the list so that they are
559 // known live into the call.
560 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
561 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
562 RegsToPass[i].second.getValueType()));
565 if (InFlag.getNode()) {
566 Ops.push_back(InFlag);
570 return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
572 Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
573 InFlag = Chain.getValue(1);
575 // Create the CALLSEQ_END node.
576 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
577 DAG.getIntPtrConstant(0, true), InFlag);
578 InFlag = Chain.getValue(1);
580 // Handle result values, copying them out of physregs into vregs that we
582 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
583 InVals, OutVals, Callee);
586 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
587 bool isSEXTLoad, SDValue &Base,
588 SDValue &Offset, bool &isInc,
590 if (Ptr->getOpcode() != ISD::ADD)
593 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
594 isInc = (Ptr->getOpcode() == ISD::ADD);
595 Base = Ptr->getOperand(0);
596 Offset = Ptr->getOperand(1);
597 // Ensure that Offset is a constant.
598 return (isa<ConstantSDNode>(Offset));
604 // TODO: Put this function along with the other isS* functions in
605 // HexagonISelDAGToDAG.cpp into a common file. Or better still, use the
606 // functions defined in HexagonImmediates.td.
607 static bool Is_PostInc_S4_Offset(SDNode * S, int ShiftAmount) {
608 ConstantSDNode *N = cast<ConstantSDNode>(S);
610 // immS4 predicate - True if the immediate fits in a 4-bit sign extended.
612 int64_t v = (int64_t)N->getSExtValue();
614 if (ShiftAmount > 0) {
616 v = v >> ShiftAmount;
618 return (v <= 7) && (v >= -8) && (m == 0);
621 /// getPostIndexedAddressParts - returns true by value, base pointer and
622 /// offset pointer and addressing mode by reference if this node can be
623 /// combined with a load / store to form a post-indexed load / store.
624 bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
627 ISD::MemIndexedMode &AM,
628 SelectionDAG &DAG) const
632 bool isSEXTLoad = false;
634 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
635 VT = LD->getMemoryVT();
636 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
637 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
638 VT = ST->getMemoryVT();
639 if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore()) {
647 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
649 // ShiftAmount = number of left-shifted bits in the Hexagon instruction.
650 int ShiftAmount = VT.getSizeInBits() / 16;
651 if (isLegal && Is_PostInc_S4_Offset(Offset.getNode(), ShiftAmount)) {
652 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
659 SDValue HexagonTargetLowering::LowerINLINEASM(SDValue Op,
660 SelectionDAG &DAG) const {
661 SDNode *Node = Op.getNode();
662 MachineFunction &MF = DAG.getMachineFunction();
663 HexagonMachineFunctionInfo *FuncInfo =
664 MF.getInfo<HexagonMachineFunctionInfo>();
665 switch (Node->getOpcode()) {
666 case ISD::INLINEASM: {
667 unsigned NumOps = Node->getNumOperands();
668 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
669 --NumOps; // Ignore the flag operand.
671 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
672 if (FuncInfo->hasClobberLR())
675 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
676 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
677 ++i; // Skip the ID value.
679 switch (InlineAsm::getKind(Flags)) {
680 default: llvm_unreachable("Bad flags!");
681 case InlineAsm::Kind_RegDef:
682 case InlineAsm::Kind_RegUse:
683 case InlineAsm::Kind_Imm:
684 case InlineAsm::Kind_Clobber:
685 case InlineAsm::Kind_Mem: {
686 for (; NumVals; --NumVals, ++i) {}
689 case InlineAsm::Kind_RegDefEarlyClobber: {
690 for (; NumVals; --NumVals, ++i) {
692 cast<RegisterSDNode>(Node->getOperand(i))->getReg();
695 if (Reg == TM.getRegisterInfo()->getRARegister()) {
696 FuncInfo->setHasClobberLR(true);
711 // Taken from the XCore backend.
713 SDValue HexagonTargetLowering::
714 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
716 SDValue Chain = Op.getOperand(0);
717 SDValue Table = Op.getOperand(1);
718 SDValue Index = Op.getOperand(2);
719 DebugLoc dl = Op.getDebugLoc();
720 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
721 unsigned JTI = JT->getIndex();
722 MachineFunction &MF = DAG.getMachineFunction();
723 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
724 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
726 // Mark all jump table targets as address taken.
727 const std::vector<MachineJumpTableEntry> &JTE = MJTI->getJumpTables();
728 const std::vector<MachineBasicBlock*> &JTBBs = JTE[JTI].MBBs;
729 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
730 MachineBasicBlock *MBB = JTBBs[i];
731 MBB->setHasAddressTaken();
732 // This line is needed to set the hasAddressTaken flag on the BasicBlock
734 BlockAddress::get(const_cast<BasicBlock *>(MBB->getBasicBlock()));
737 SDValue JumpTableBase = DAG.getNode(HexagonISD::WrapperJT, dl,
738 getPointerTy(), TargetJT);
739 SDValue ShiftIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
740 DAG.getConstant(2, MVT::i32));
741 SDValue JTAddress = DAG.getNode(ISD::ADD, dl, MVT::i32, JumpTableBase,
743 SDValue LoadTarget = DAG.getLoad(MVT::i32, dl, Chain, JTAddress,
744 MachinePointerInfo(), false, false, false,
746 return DAG.getNode(HexagonISD::BR_JT, dl, MVT::Other, Chain, LoadTarget);
751 HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
752 SelectionDAG &DAG) const {
753 SDValue Chain = Op.getOperand(0);
754 SDValue Size = Op.getOperand(1);
755 DebugLoc dl = Op.getDebugLoc();
757 unsigned SPReg = getStackPointerRegisterToSaveRestore();
759 // Get a reference to the stack pointer.
760 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
762 // Subtract the dynamic size from the actual stack size to
763 // obtain the new stack size.
764 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
767 // For Hexagon, the outgoing memory arguments area should be on top of the
768 // alloca area on the stack i.e., the outgoing memory arguments should be
769 // at a lower address than the alloca area. Move the alloca area down the
770 // stack by adding back the space reserved for outgoing arguments to SP
773 // We do not know what the size of the outgoing args is at this point.
774 // So, we add a pseudo instruction ADJDYNALLOC that will adjust the
775 // stack pointer. We patch this instruction with the correct, known
776 // offset in emitPrologue().
778 // Use a placeholder immediate (zero) for now. This will be patched up
779 // by emitPrologue().
780 SDValue ArgAdjust = DAG.getNode(HexagonISD::ADJDYNALLOC, dl,
783 DAG.getConstant(0, MVT::i32));
785 // The Sub result contains the new stack start address, so it
786 // must be placed in the stack pointer register.
787 SDValue CopyChain = DAG.getCopyToReg(Chain, dl,
788 TM.getRegisterInfo()->getStackRegister(),
791 SDValue Ops[2] = { ArgAdjust, CopyChain };
792 return DAG.getMergeValues(Ops, 2, dl);
796 HexagonTargetLowering::LowerFormalArguments(SDValue Chain,
797 CallingConv::ID CallConv,
800 SmallVectorImpl<ISD::InputArg> &Ins,
801 DebugLoc dl, SelectionDAG &DAG,
802 SmallVectorImpl<SDValue> &InVals)
805 MachineFunction &MF = DAG.getMachineFunction();
806 MachineFrameInfo *MFI = MF.getFrameInfo();
807 MachineRegisterInfo &RegInfo = MF.getRegInfo();
808 HexagonMachineFunctionInfo *FuncInfo =
809 MF.getInfo<HexagonMachineFunctionInfo>();
812 // Assign locations to all of the incoming arguments.
813 SmallVector<CCValAssign, 16> ArgLocs;
814 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
815 getTargetMachine(), ArgLocs, *DAG.getContext());
817 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
819 // For LLVM, in the case when returning a struct by value (>8byte),
820 // the first argument is a pointer that points to the location on caller's
821 // stack where the return value will be stored. For Hexagon, the location on
822 // caller's stack is passed only when the struct size is smaller than (and
823 // equal to) 8 bytes. If not, no address will be passed into callee and
824 // callee return the result direclty through R0/R1.
826 SmallVector<SDValue, 4> MemOps;
828 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
829 CCValAssign &VA = ArgLocs[i];
830 ISD::ArgFlagsTy Flags = Ins[i].Flags;
832 unsigned StackLocation;
835 if ( (VA.isRegLoc() && !Flags.isByVal())
836 || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) {
837 // Arguments passed in registers
838 // 1. int, long long, ptr args that get allocated in register.
839 // 2. Large struct that gets an register to put its address in.
840 EVT RegVT = VA.getLocVT();
841 if (RegVT == MVT::i8 || RegVT == MVT::i16 || RegVT == MVT::i32) {
843 RegInfo.createVirtualRegister(Hexagon::IntRegsRegisterClass);
844 RegInfo.addLiveIn(VA.getLocReg(), VReg);
845 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
846 } else if (RegVT == MVT::i64) {
848 RegInfo.createVirtualRegister(Hexagon::DoubleRegsRegisterClass);
849 RegInfo.addLiveIn(VA.getLocReg(), VReg);
850 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
854 } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) {
855 assert (0 && "ByValSize must be bigger than 8 bytes");
858 assert(VA.isMemLoc());
860 if (Flags.isByVal()) {
861 // If it's a byval parameter, then we need to compute the
862 // "real" size, not the size of the pointer.
863 ObjSize = Flags.getByValSize();
865 ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3;
868 StackLocation = HEXAGON_LRFP_SIZE + VA.getLocMemOffset();
869 // Create the frame index object for this incoming parameter...
870 FI = MFI->CreateFixedObject(ObjSize, StackLocation, true);
872 // Create the SelectionDAG nodes cordl, responding to a load
873 // from this parameter.
874 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
876 if (Flags.isByVal()) {
877 // If it's a pass-by-value aggregate, then do not dereference the stack
878 // location. Instead, we should generate a reference to the stack
880 InVals.push_back(FIN);
882 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
883 MachinePointerInfo(), false, false,
890 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0],
894 // This will point to the next argument passed via stack.
895 int FrameIndex = MFI->CreateFixedObject(Hexagon_PointerSize,
897 CCInfo.getNextStackOffset(),
899 FuncInfo->setVarArgsFrameIndex(FrameIndex);
906 HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
907 // VASTART stores the address of the VarArgsFrameIndex slot into the
908 // memory location argument.
909 MachineFunction &MF = DAG.getMachineFunction();
910 HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>();
911 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32);
912 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
913 return DAG.getStore(Op.getOperand(0), Op.getDebugLoc(), Addr,
914 Op.getOperand(1), MachinePointerInfo(SV), false,
919 HexagonTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
920 SDNode* OpNode = Op.getNode();
922 SDValue Cond = DAG.getNode(ISD::SETCC, Op.getDebugLoc(), MVT::i1,
923 Op.getOperand(2), Op.getOperand(3),
925 return DAG.getNode(ISD::SELECT, Op.getDebugLoc(), OpNode->getValueType(0),
926 Cond, Op.getOperand(0),
931 HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
932 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
933 MachineFunction &MF = DAG.getMachineFunction();
934 MachineFrameInfo *MFI = MF.getFrameInfo();
935 MFI->setReturnAddressIsTaken(true);
937 EVT VT = Op.getValueType();
938 DebugLoc dl = Op.getDebugLoc();
939 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
941 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
942 SDValue Offset = DAG.getConstant(4, MVT::i32);
943 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
944 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
945 MachinePointerInfo(), false, false, false, 0);
948 // Return LR, which contains the return address. Mark it an implicit live-in.
949 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
950 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
954 HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
955 const HexagonRegisterInfo *TRI = TM.getRegisterInfo();
956 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
957 MFI->setFrameAddressIsTaken(true);
959 EVT VT = Op.getValueType();
960 DebugLoc dl = Op.getDebugLoc();
961 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
962 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
963 TRI->getFrameRegister(), VT);
965 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
966 MachinePointerInfo(),
967 false, false, false, 0);
972 SDValue HexagonTargetLowering::LowerMEMBARRIER(SDValue Op,
973 SelectionDAG& DAG) const {
974 DebugLoc dl = Op.getDebugLoc();
975 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
979 SDValue HexagonTargetLowering::LowerATOMIC_FENCE(SDValue Op,
980 SelectionDAG& DAG) const {
981 DebugLoc dl = Op.getDebugLoc();
982 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
986 SDValue HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op,
987 SelectionDAG &DAG) const {
989 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
990 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
991 DebugLoc dl = Op.getDebugLoc();
992 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
994 HexagonTargetObjectFile &TLOF =
995 (HexagonTargetObjectFile&)getObjFileLowering();
996 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
997 return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), Result);
1000 return DAG.getNode(HexagonISD::CONST32, dl, getPointerTy(), Result);
1003 //===----------------------------------------------------------------------===//
1004 // TargetLowering Implementation
1005 //===----------------------------------------------------------------------===//
1007 HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine
1009 : TargetLowering(targetmachine, new HexagonTargetObjectFile()),
1012 // Set up the register classes.
1013 addRegisterClass(MVT::i32, Hexagon::IntRegsRegisterClass);
1014 addRegisterClass(MVT::i64, Hexagon::DoubleRegsRegisterClass);
1016 addRegisterClass(MVT::i1, Hexagon::PredRegsRegisterClass);
1018 computeRegisterProperties();
1021 setPrefLoopAlignment(4);
1023 // Limits for inline expansion of memcpy/memmove
1024 maxStoresPerMemcpy = 6;
1025 maxStoresPerMemmove = 6;
1028 // Library calls for unsupported operations
1030 setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
1032 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf");
1033 setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
1034 setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
1035 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf");
1036 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf");
1037 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf");
1038 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf");
1040 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi");
1041 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi");
1042 setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
1044 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi");
1045 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi");
1046 setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
1048 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf");
1049 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi");
1050 setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
1051 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi");
1052 setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
1054 setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
1056 setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
1057 setOperationAction(ISD::SDIV, MVT::i32, Expand);
1058 setLibcallName(RTLIB::SREM_I32, "__hexagon_umodsi3");
1059 setOperationAction(ISD::SREM, MVT::i32, Expand);
1061 setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
1062 setOperationAction(ISD::SDIV, MVT::i64, Expand);
1063 setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
1064 setOperationAction(ISD::SREM, MVT::i64, Expand);
1066 setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
1067 setOperationAction(ISD::UDIV, MVT::i32, Expand);
1069 setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
1070 setOperationAction(ISD::UDIV, MVT::i64, Expand);
1072 setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
1073 setOperationAction(ISD::UREM, MVT::i32, Expand);
1075 setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
1076 setOperationAction(ISD::UREM, MVT::i64, Expand);
1078 setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
1079 setOperationAction(ISD::FDIV, MVT::f32, Expand);
1081 setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
1082 setOperationAction(ISD::FDIV, MVT::f64, Expand);
1084 setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2");
1085 setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand);
1087 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf");
1088 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
1090 setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
1091 setOperationAction(ISD::FADD, MVT::f64, Expand);
1093 setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
1094 setOperationAction(ISD::FADD, MVT::f32, Expand);
1096 setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
1097 setOperationAction(ISD::FADD, MVT::f32, Expand);
1099 setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2");
1100 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
1102 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi");
1103 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand);
1105 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi");
1106 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand);
1108 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf");
1109 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
1111 setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2");
1112 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
1114 setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2");
1115 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
1117 setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2");
1118 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
1120 setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2");
1121 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
1123 setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2");
1124 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
1126 setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2");
1127 setCondCodeAction(ISD::SETOLT, MVT::f64, Expand);
1129 setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2");
1130 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
1132 setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
1133 setOperationAction(ISD::SREM, MVT::i32, Expand);
1135 setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
1136 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1138 setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3");
1139 setOperationAction(ISD::MUL, MVT::f32, Expand);
1141 setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2");
1142 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
1144 setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2");
1147 setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
1148 setOperationAction(ISD::SUB, MVT::f64, Expand);
1150 setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3");
1151 setOperationAction(ISD::SUB, MVT::f32, Expand);
1153 setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2");
1154 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand);
1156 setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2");
1157 setCondCodeAction(ISD::SETUO, MVT::f64, Expand);
1159 setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2");
1160 setCondCodeAction(ISD::SETO, MVT::f64, Expand);
1162 setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2");
1163 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
1165 setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2");
1166 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
1168 setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2");
1169 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
1171 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
1172 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
1173 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
1174 setIndexedLoadAction(ISD::POST_INC, MVT::i64, Legal);
1176 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal);
1177 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal);
1178 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
1179 setIndexedStoreAction(ISD::POST_INC, MVT::i64, Legal);
1181 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
1183 // Turn FP extload into load/fextend.
1184 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
1185 // Hexagon has a i1 sign extending load.
1186 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand);
1187 // Turn FP truncstore into trunc + store.
1188 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1190 // Custom legalize GlobalAddress nodes into CONST32.
1191 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1192 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
1194 setOperationAction(ISD::TRUNCATE, MVT::i64, Expand);
1196 // Hexagon doesn't have sext_inreg, replace them with shl/sra.
1197 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
1199 // Hexagon has no REM or DIVREM operations.
1200 setOperationAction(ISD::UREM, MVT::i32, Expand);
1201 setOperationAction(ISD::SREM, MVT::i32, Expand);
1202 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1203 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1204 setOperationAction(ISD::SREM, MVT::i64, Expand);
1205 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
1206 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
1208 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
1210 // Expand fp<->uint.
1211 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
1212 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
1214 // Hexagon has no select or setcc: expand to SELECT_CC.
1215 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1216 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1218 // Lower SELECT_CC to SETCC and SELECT.
1219 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1220 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
1221 // This is a workaround documented in DAGCombiner.cpp:2892 We don't
1222 // support SELECT_CC on every type.
1223 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
1225 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
1226 setOperationAction(ISD::BRIND, MVT::Other, Expand);
1227 if (EmitJumpTables) {
1228 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1230 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1233 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
1235 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
1236 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1238 setOperationAction(ISD::FSIN , MVT::f64, Expand);
1239 setOperationAction(ISD::FCOS , MVT::f64, Expand);
1240 setOperationAction(ISD::FREM , MVT::f64, Expand);
1241 setOperationAction(ISD::FSIN , MVT::f32, Expand);
1242 setOperationAction(ISD::FCOS , MVT::f32, Expand);
1243 setOperationAction(ISD::FREM , MVT::f32, Expand);
1244 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1245 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1246 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
1247 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1248 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
1249 setOperationAction(ISD::ROTL , MVT::i32, Expand);
1250 setOperationAction(ISD::ROTR , MVT::i32, Expand);
1251 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1252 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1253 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1254 setOperationAction(ISD::FPOW , MVT::f64, Expand);
1255 setOperationAction(ISD::FPOW , MVT::f32, Expand);
1257 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1258 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1259 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1261 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1262 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1264 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
1265 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
1267 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
1268 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
1269 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
1270 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
1272 setOperationAction(ISD::EH_RETURN, MVT::Other, Expand);
1274 if (TM.getSubtargetImpl()->isSubtargetV2()) {
1275 setExceptionPointerRegister(Hexagon::R20);
1276 setExceptionSelectorRegister(Hexagon::R21);
1278 setExceptionPointerRegister(Hexagon::R0);
1279 setExceptionSelectorRegister(Hexagon::R1);
1282 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1283 setOperationAction(ISD::VASTART , MVT::Other, Custom);
1285 // Use the default implementation.
1286 setOperationAction(ISD::VAARG , MVT::Other, Expand);
1287 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
1288 setOperationAction(ISD::VAEND , MVT::Other, Expand);
1289 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
1290 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
1293 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
1294 setOperationAction(ISD::INLINEASM , MVT::Other, Custom);
1296 setMinFunctionAlignment(2);
1298 // Needed for DYNAMIC_STACKALLOC expansion.
1299 unsigned StackRegister = TM.getRegisterInfo()->getStackRegister();
1300 setStackPointerRegisterToSaveRestore(StackRegister);
1305 HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
1308 case HexagonISD::CONST32: return "HexagonISD::CONST32";
1309 case HexagonISD::ADJDYNALLOC: return "HexagonISD::ADJDYNALLOC";
1310 case HexagonISD::CMPICC: return "HexagonISD::CMPICC";
1311 case HexagonISD::CMPFCC: return "HexagonISD::CMPFCC";
1312 case HexagonISD::BRICC: return "HexagonISD::BRICC";
1313 case HexagonISD::BRFCC: return "HexagonISD::BRFCC";
1314 case HexagonISD::SELECT_ICC: return "HexagonISD::SELECT_ICC";
1315 case HexagonISD::SELECT_FCC: return "HexagonISD::SELECT_FCC";
1316 case HexagonISD::Hi: return "HexagonISD::Hi";
1317 case HexagonISD::Lo: return "HexagonISD::Lo";
1318 case HexagonISD::FTOI: return "HexagonISD::FTOI";
1319 case HexagonISD::ITOF: return "HexagonISD::ITOF";
1320 case HexagonISD::CALL: return "HexagonISD::CALL";
1321 case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
1322 case HexagonISD::BR_JT: return "HexagonISD::BR_JT";
1323 case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
1328 HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
1329 EVT MTy1 = EVT::getEVT(Ty1);
1330 EVT MTy2 = EVT::getEVT(Ty2);
1331 if (!MTy1.isSimple() || !MTy2.isSimple()) {
1334 return ((MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32));
1337 bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1338 if (!VT1.isSimple() || !VT2.isSimple()) {
1341 return ((VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32));
1345 HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1346 switch (Op.getOpcode()) {
1347 default: assert(0 && "Should not custom lower this!");
1348 // Frame & Return address. Currently unimplemented.
1349 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
1350 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
1351 case ISD::GlobalTLSAddress:
1352 assert(0 && "TLS not implemented for Hexagon.");
1353 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
1354 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
1355 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
1356 case ISD::VASTART: return LowerVASTART(Op, DAG);
1357 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
1359 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
1360 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
1361 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1362 case ISD::INLINEASM: return LowerINLINEASM(Op, DAG);
1369 //===----------------------------------------------------------------------===//
1370 // Hexagon Scheduler Hooks
1371 //===----------------------------------------------------------------------===//
1373 HexagonTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1374 MachineBasicBlock *BB)
1376 switch (MI->getOpcode()) {
1377 case Hexagon::ADJDYNALLOC: {
1378 MachineFunction *MF = BB->getParent();
1379 HexagonMachineFunctionInfo *FuncInfo =
1380 MF->getInfo<HexagonMachineFunctionInfo>();
1381 FuncInfo->addAllocaAdjustInst(MI);
1385 assert(false && "Unexpected instr type to insert");
1390 //===----------------------------------------------------------------------===//
1391 // Inline Assembly Support
1392 //===----------------------------------------------------------------------===//
1394 std::pair<unsigned, const TargetRegisterClass*>
1395 HexagonTargetLowering::getRegForInlineAsmConstraint(const
1396 std::string &Constraint,
1398 if (Constraint.size() == 1) {
1399 switch (Constraint[0]) {
1401 switch (VT.getSimpleVT().SimpleTy) {
1403 assert(0 && "getRegForInlineAsmConstraint Unhandled data type");
1407 return std::make_pair(0U, Hexagon::IntRegsRegisterClass);
1409 return std::make_pair(0U, Hexagon::DoubleRegsRegisterClass);
1412 assert(0 && "Unknown asm register class");
1416 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1419 /// isLegalAddressingMode - Return true if the addressing mode represented by
1420 /// AM is legal for this target, for a load/store of the specified type.
1421 bool HexagonTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1423 // Allows a signed-extended 11-bit immediate field.
1424 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1) {
1428 // No global is ever allowed as a base.
1433 int Scale = AM.Scale;
1434 if (Scale < 0) Scale = -Scale;
1436 case 0: // No scale reg, "r+i", "r", or just "i".
1438 default: // No scaled addressing mode.
1444 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1445 /// icmp immediate, that is the target has icmp instructions which can compare
1446 /// a register against the immediate without having to materialize the
1447 /// immediate into a register.
1448 bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
1449 return Imm >= -512 && Imm <= 511;
1452 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1453 /// for tail call optimization. Targets which want to do tail call
1454 /// optimization should implement this function.
1455 bool HexagonTargetLowering::IsEligibleForTailCallOptimization(
1457 CallingConv::ID CalleeCC,
1459 bool isCalleeStructRet,
1460 bool isCallerStructRet,
1461 const SmallVectorImpl<ISD::OutputArg> &Outs,
1462 const SmallVectorImpl<SDValue> &OutVals,
1463 const SmallVectorImpl<ISD::InputArg> &Ins,
1464 SelectionDAG& DAG) const {
1465 const Function *CallerF = DAG.getMachineFunction().getFunction();
1466 CallingConv::ID CallerCC = CallerF->getCallingConv();
1467 bool CCMatch = CallerCC == CalleeCC;
1469 // ***************************************************************************
1470 // Look for obvious safe cases to perform tail call optimization that do not
1471 // require ABI changes.
1472 // ***************************************************************************
1474 // If this is a tail call via a function pointer, then don't do it!
1475 if (!(dyn_cast<GlobalAddressSDNode>(Callee))
1476 && !(dyn_cast<ExternalSymbolSDNode>(Callee))) {
1480 // Do not optimize if the calling conventions do not match.
1484 // Do not tail call optimize vararg calls.
1488 // Also avoid tail call optimization if either caller or callee uses struct
1489 // return semantics.
1490 if (isCalleeStructRet || isCallerStructRet)
1493 // In addition to the cases above, we also disable Tail Call Optimization if
1494 // the calling convention code that at least one outgoing argument needs to
1495 // go on the stack. We cannot check that here because at this point that
1496 // information is not available.