1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Hexagon uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef Hexagon_ISELLOWERING_H
16 #define Hexagon_ISELLOWERING_H
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/IR/CallingConv.h"
21 #include "llvm/Target/TargetLowering.h"
24 namespace HexagonISD {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 CONST32_GP, // For marking data present in GP.
36 CMPICC, // Compare two GPR operands, set icc.
37 CMPFCC, // Compare two FP operands, set fcc.
38 BRICC, // Branch to dest on icc condition
39 BRFCC, // Branch to dest on fcc condition
40 SELECT_ICC, // Select between two values using the current ICC flags.
41 SELECT_FCC, // Select between two values using the current FCC flags.
43 Hi, Lo, // Hi/Lo operations, typically on a global address.
45 FTOI, // FP to Int within a FP register.
46 ITOF, // Int to FP within a FP register.
48 CALL, // A call instruction.
49 RET_FLAG, // Return with a flag operand.
51 BARRIER, // Memory barrier.
70 class HexagonTargetLowering : public TargetLowering {
71 int VarArgsFrameOffset; // Frame offset to start of varargs area.
73 bool CanReturnSmallStruct(const Function* CalleeFn,
74 unsigned& RetSize) const;
77 HexagonTargetMachine &TM;
78 explicit HexagonTargetLowering(HexagonTargetMachine &targetmachine);
80 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
81 /// for tail call optimization. Targets which want to do tail call
82 /// optimization should implement this function.
84 IsEligibleForTailCallOptimization(SDValue Callee,
85 CallingConv::ID CalleeCC,
87 bool isCalleeStructRet,
88 bool isCallerStructRet,
90 SmallVectorImpl<ISD::OutputArg> &Outs,
91 const SmallVectorImpl<SDValue> &OutVals,
92 const SmallVectorImpl<ISD::InputArg> &Ins,
93 SelectionDAG& DAG) const;
95 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
96 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
98 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
100 virtual const char *getTargetNodeName(unsigned Opcode) const;
101 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
102 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
103 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
104 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
105 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
106 SDValue LowerFormalArguments(SDValue Chain,
107 CallingConv::ID CallConv, bool isVarArg,
108 const SmallVectorImpl<ISD::InputArg> &Ins,
109 DebugLoc dl, SelectionDAG &DAG,
110 SmallVectorImpl<SDValue> &InVals) const;
111 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
112 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
114 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
115 SmallVectorImpl<SDValue> &InVals) const;
117 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
118 CallingConv::ID CallConv, bool isVarArg,
119 const SmallVectorImpl<ISD::InputArg> &Ins,
120 DebugLoc dl, SelectionDAG &DAG,
121 SmallVectorImpl<SDValue> &InVals,
122 const SmallVectorImpl<SDValue> &OutVals,
123 SDValue Callee) const;
125 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
126 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
127 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
128 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
130 SDValue LowerReturn(SDValue Chain,
131 CallingConv::ID CallConv, bool isVarArg,
132 const SmallVectorImpl<ISD::OutputArg> &Outs,
133 const SmallVectorImpl<SDValue> &OutVals,
134 DebugLoc dl, SelectionDAG &DAG) const;
136 virtual MachineBasicBlock
137 *EmitInstrWithCustomInserter(MachineInstr *MI,
138 MachineBasicBlock *BB) const;
140 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
141 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
142 virtual EVT getSetCCResultType(EVT VT) const {
146 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
147 SDValue &Base, SDValue &Offset,
148 ISD::MemIndexedMode &AM,
149 SelectionDAG &DAG) const;
151 std::pair<unsigned, const TargetRegisterClass*>
152 getRegForInlineAsmConstraint(const std::string &Constraint,
156 virtual SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op,
157 SelectionDAG &DAG) const;
158 /// isLegalAddressingMode - Return true if the addressing mode represented
159 /// by AM is legal for this target, for a load/store of the specified type.
160 /// The type may be VoidTy, in which case only return true if the addressing
161 /// mode is legal for a load/store of any legal type.
162 /// TODO: Handle pre/postinc as well.
163 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
164 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
166 /// isLegalICmpImmediate - Return true if the specified immediate is legal
167 /// icmp immediate, that is the target has icmp instructions which can
168 /// compare a register against the immediate without having to materialize
169 /// the immediate into a register.
170 virtual bool isLegalICmpImmediate(int64_t Imm) const;
172 } // end namespace llvm
174 #endif // Hexagon_ISELLOWERING_H