1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Hexagon uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/IR/CallingConv.h"
21 #include "llvm/Target/TargetLowering.h"
25 // Return true when the given node fits in a positive half word.
26 bool isPositiveHalfWord(SDNode *N);
28 namespace HexagonISD {
30 OP_BEGIN = ISD::BUILTIN_OP_END,
33 CONST32_GP, // For marking data present in GP.
42 CALLv3, // A V3+ call instruction.
43 CALLv3nr, // A V3+ call instruction that doesn't return.
46 RET_FLAG, // Return with a flag operand.
47 BR_JT, // Branch through jump table.
48 BARRIER, // Memory barrier.
91 class HexagonSubtarget;
93 class HexagonTargetLowering : public TargetLowering {
94 int VarArgsFrameOffset; // Frame offset to start of varargs area.
96 bool CanReturnSmallStruct(const Function* CalleeFn, unsigned& RetSize)
98 void promoteLdStType(EVT VT, EVT PromotedLdStVT);
99 const HexagonTargetMachine &HTM;
100 const HexagonSubtarget &Subtarget;
103 explicit HexagonTargetLowering(const TargetMachine &TM,
104 const HexagonSubtarget &ST);
106 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
107 /// for tail call optimization. Targets which want to do tail call
108 /// optimization should implement this function.
109 bool IsEligibleForTailCallOptimization(SDValue Callee,
110 CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet,
111 bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,
112 const SmallVectorImpl<SDValue> &OutVals,
113 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
115 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
116 bool isTruncateFree(EVT VT1, EVT VT2) const override;
118 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
120 // Should we expand the build vector with shuffles?
121 bool shouldExpandBuildVectorWithShuffles(EVT VT,
122 unsigned DefinedValues) const override;
124 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
125 const char *getTargetNodeName(unsigned Opcode) const override;
126 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
127 SDValue LowerEXTRACT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
128 SDValue LowerINSERT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
129 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
130 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
131 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
132 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
133 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
134 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
135 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
136 bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
137 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const override;
138 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
139 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
141 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
142 SmallVectorImpl<SDValue> &InVals) const override;
143 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
144 CallingConv::ID CallConv, bool isVarArg,
145 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
146 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
147 const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const;
149 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
150 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
151 SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
152 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
153 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
154 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
155 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
157 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
158 bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs,
159 const SmallVectorImpl<SDValue> &OutVals, SDLoc dl,
160 SelectionDAG &DAG) const override;
162 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
163 MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI,
164 MachineBasicBlock *BB) const override;
166 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
167 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
168 EVT getSetCCResultType(LLVMContext &C, EVT VT) const override {
172 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
175 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
176 SDValue &Base, SDValue &Offset,
177 ISD::MemIndexedMode &AM,
178 SelectionDAG &DAG) const override;
180 std::pair<unsigned, const TargetRegisterClass *>
181 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
182 const std::string &Constraint,
183 MVT VT) const override;
185 unsigned getInlineAsmMemConstraint(
186 const std::string &ConstraintCode) const override {
187 if (ConstraintCode == "o")
188 return InlineAsm::Constraint_o;
189 else if (ConstraintCode == "v")
190 return InlineAsm::Constraint_v;
191 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
195 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
196 /// isLegalAddressingMode - Return true if the addressing mode represented
197 /// by AM is legal for this target, for a load/store of the specified type.
198 /// The type may be VoidTy, in which case only return true if the addressing
199 /// mode is legal for a load/store of any legal type.
200 /// TODO: Handle pre/postinc as well.
201 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
202 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
204 /// isLegalICmpImmediate - Return true if the specified immediate is legal
205 /// icmp immediate, that is the target has icmp instructions which can
206 /// compare a register against the immediate without having to materialize
207 /// the immediate into a register.
208 bool isLegalICmpImmediate(int64_t Imm) const override;
211 void setHexLibcallName(RTLIB::Libcall Call, Twine Name);
213 } // end namespace llvm
215 #endif // Hexagon_ISELLOWERING_H