1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Hexagon Instruction Flags +
13 // *** Must match HexagonBaseInfo.h ***
14 //===----------------------------------------------------------------------===//
16 class IType<bits<5> t> {
19 def TypePSEUDO : IType<0>;
20 def TypeALU32 : IType<1>;
21 def TypeCR : IType<2>;
22 def TypeJR : IType<3>;
24 def TypeLD : IType<5>;
25 def TypeST : IType<6>;
26 def TypeSYSTEM : IType<7>;
27 def TypeXTYPE : IType<8>;
28 def TypeENDLOOP: IType<31>;
30 // Maintain list of valid subtargets for each instruction.
31 class SubTarget<bits<4> value> {
32 bits<4> Value = value;
35 def HasV2SubT : SubTarget<0xf>;
36 def HasV2SubTOnly : SubTarget<0x1>;
37 def NoV2SubT : SubTarget<0x0>;
38 def HasV3SubT : SubTarget<0xe>;
39 def HasV3SubTOnly : SubTarget<0x2>;
40 def NoV3SubT : SubTarget<0x1>;
41 def HasV4SubT : SubTarget<0xc>;
42 def NoV4SubT : SubTarget<0x3>;
43 def HasV5SubT : SubTarget<0x8>;
44 def NoV5SubT : SubTarget<0x7>;
46 // Addressing modes for load/store instructions
47 class AddrModeType<bits<3> value> {
48 bits<3> Value = value;
51 def NoAddrMode : AddrModeType<0>; // No addressing mode
52 def Absolute : AddrModeType<1>; // Absolute addressing mode
53 def AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode
54 def BaseImmOffset : AddrModeType<3>; // Indirect with offset
55 def BaseLongOffset : AddrModeType<4>; // Indirect with long offset
56 def BaseRegOffset : AddrModeType<5>; // Indirect with register offset
57 def PostInc : AddrModeType<6>; // Post increment addressing mode
59 class MemAccessSize<bits<3> value> {
60 bits<3> Value = value;
63 def NoMemAccess : MemAccessSize<0>;// Not a memory acces instruction.
64 def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb).
65 def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh).
66 def WordAccess : MemAccessSize<3>;// Word access instruction (memw).
67 def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd)
70 //===----------------------------------------------------------------------===//
71 // Instruction Class Declaration +
72 //===----------------------------------------------------------------------===//
75 field bits<32> Inst = ?; // Default to an invalid insn.
76 bits<4> IClass = 0; // ICLASS
77 bits<2> IParse = 0; // Parse bits.
79 let Inst{31-28} = IClass;
80 let Inst{15-14} = IParse;
85 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
86 string cstr, InstrItinClass itin, IType type>
87 : Instruction, OpcodeHexagon {
88 let Namespace = "Hexagon";
90 dag OutOperandList = outs;
91 dag InOperandList = ins;
92 let AsmString = asmstr;
93 let Pattern = pattern;
94 let Constraints = cstr;
98 // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
100 // Instruction type according to the ISA.
102 let TSFlags{4-0} = Type.Value;
104 // Solo instructions, i.e., those that cannot be in a packet with others.
106 let TSFlags{5} = isSolo;
107 // Packed only with A or X-type instructions.
108 bits<1> isSoloAX = 0;
109 let TSFlags{6} = isSoloAX;
110 // Only A-type instruction in first slot or nothing.
111 bits<1> isSoloAin1 = 0;
112 let TSFlags{7} = isSoloAin1;
114 // Predicated instructions.
115 bits<1> isPredicated = 0;
116 let TSFlags{8} = isPredicated;
117 bits<1> isPredicatedFalse = 0;
118 let TSFlags{9} = isPredicatedFalse;
119 bits<1> isPredicatedNew = 0;
120 let TSFlags{10} = isPredicatedNew;
121 bits<1> isPredicateLate = 0;
122 let TSFlags{11} = isPredicateLate; // Late predicate producer insn.
124 // New-value insn helper fields.
125 bits<1> isNewValue = 0;
126 let TSFlags{12} = isNewValue; // New-value consumer insn.
127 bits<1> hasNewValue = 0;
128 let TSFlags{13} = hasNewValue; // New-value producer insn.
129 bits<3> opNewValue = 0;
130 let TSFlags{16-14} = opNewValue; // New-value produced operand.
131 bits<1> isNVStorable = 0;
132 let TSFlags{17} = isNVStorable; // Store that can become new-value store.
133 bits<1> isNVStore = 0;
134 let TSFlags{18} = isNVStore; // New-value store insn.
135 bits<1> isCVLoadable = 0;
136 let TSFlags{19} = isCVLoadable; // Load that can become cur-value load.
137 bits<1> isCVLoad = 0;
138 let TSFlags{20} = isCVLoad; // Cur-value load insn.
140 // Immediate extender helper fields.
141 bits<1> isExtendable = 0;
142 let TSFlags{21} = isExtendable; // Insn may be extended.
143 bits<1> isExtended = 0;
144 let TSFlags{22} = isExtended; // Insn must be extended.
145 bits<3> opExtendable = 0;
146 let TSFlags{25-23} = opExtendable; // Which operand may be extended.
147 bits<1> isExtentSigned = 0;
148 let TSFlags{26} = isExtentSigned; // Signed or unsigned range.
149 bits<5> opExtentBits = 0;
150 let TSFlags{31-27} = opExtentBits; //Number of bits of range before extending.
151 bits<2> opExtentAlign = 0;
152 let TSFlags{33-32} = opExtentAlign; // Alignment exponent before extending.
154 // If an instruction is valid on a subtarget (v2-v5), set the corresponding
155 // bit from validSubTargets. v2 is the least significant bit.
156 // By default, instruction is valid on all subtargets.
157 SubTarget validSubTargets = HasV2SubT;
158 let TSFlags{37-34} = validSubTargets.Value;
160 // Addressing mode for load/store instructions.
161 AddrModeType addrMode = NoAddrMode;
162 let TSFlags{42-40} = addrMode.Value;
164 // Memory access size for mem access instructions (load/store)
165 MemAccessSize accessSize = NoMemAccess;
166 let TSFlags{45-43} = accessSize.Value;
169 let TSFlags {47} = isTaken; // Branch prediction.
172 let TSFlags {48} = isFP; // Floating-point.
174 // Fields used for relation models.
175 string BaseOpcode = "";
176 string CextOpcode = "";
177 string PredSense = "";
178 string PNewValue = "";
179 string NValueST = ""; // Set to "true" for new-value stores.
180 string InputType = ""; // Input is "imm" or "reg" type.
181 string isMEMri = "false"; // Set to "true" for load/store with MEMri operand.
182 string isFloat = "false"; // Set to "true" for the floating-point load/store.
183 string isBrTaken = ""; // Set to "true"/"false" for jump instructions
185 let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
187 let PNewValue = !if(isPredicatedNew, "new", "");
188 let NValueST = !if(isNVStore, "true", "false");
190 // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
193 //===----------------------------------------------------------------------===//
194 // Instruction Classes Definitions +
195 //===----------------------------------------------------------------------===//
197 // LD Instruction Class in V2/V3/V4.
198 // Definition of the instruction class NOT CHANGED.
199 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
200 string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
201 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>;
204 class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
206 : LDInst<outs, ins, asmstr, pattern, cstr>;
208 class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
210 : LDInst<outs, ins, asmstr, pattern, cstr>;
212 // LD Instruction Class in V2/V3/V4.
213 // Definition of the instruction class NOT CHANGED.
214 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
216 : LDInst<outs, ins, asmstr, pattern, cstr>;
219 class LD0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
220 string cstr = "", InstrItinClass itin=LD_tc_ld_SLOT0>
221 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>;
223 // ST Instruction Class in V2/V3 can take SLOT0 only.
224 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
225 // Definition of the instruction class CHANGED from V2/V3 to V4.
227 class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
228 string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
229 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>;
231 class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
233 : STInst<outs, ins, asmstr, pattern, cstr>;
236 class ST0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
237 string cstr = "", InstrItinClass itin = ST_tc_ld_SLOT0>
238 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>;
240 // ST Instruction Class in V2/V3 can take SLOT0 only.
241 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
242 // Definition of the instruction class CHANGED from V2/V3 to V4.
243 class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
244 string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
245 : STInst<outs, ins, asmstr, pattern, cstr, itin>;
247 // SYSTEM Instruction Class in V4 can take SLOT0 only
248 // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
249 class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
250 string cstr = "", InstrItinClass itin = ST_tc_3stall_SLOT0>
251 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeSYSTEM>;
253 // ALU32 Instruction Class in V2/V3/V4.
254 // Definition of the instruction class NOT CHANGED.
255 class ALU32Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
256 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
257 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU32>;
259 // ALU64 Instruction Class in V2/V3.
260 // XTYPE Instruction Class in V4.
261 // Definition of the instruction class NOT CHANGED.
262 // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
263 class ALU64Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
264 string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
265 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
267 class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
268 string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
269 : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
272 // M Instruction Class in V2/V3.
273 // XTYPE Instruction Class in V4.
274 // Definition of the instruction class NOT CHANGED.
275 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
276 class MInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
277 string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23>
278 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
280 // M Instruction Class in V2/V3.
281 // XTYPE Instruction Class in V4.
282 // Definition of the instruction class NOT CHANGED.
283 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
284 class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
285 string cstr = "", InstrItinClass itin = M_tc_2_SLOT23>
286 : MInst<outs, ins, asmstr, pattern, cstr, itin>;
288 // S Instruction Class in V2/V3.
289 // XTYPE Instruction Class in V4.
290 // Definition of the instruction class NOT CHANGED.
291 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
292 class SInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
293 string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23>
294 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
296 // S Instruction Class in V2/V3.
297 // XTYPE Instruction Class in V4.
298 // Definition of the instruction class NOT CHANGED.
299 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
300 class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
301 string cstr = "", InstrItinClass itin = S_3op_tc_1_SLOT23>
302 : SInst<outs, ins, asmstr, pattern, cstr, itin>;
304 // J Instruction Class in V2/V3/V4.
305 // Definition of the instruction class NOT CHANGED.
306 class JInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
307 string cstr = "", InstrItinClass itin = J_tc_2early_SLOT23>
308 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJ>;
310 // JR Instruction Class in V2/V3/V4.
311 // Definition of the instruction class NOT CHANGED.
312 class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
313 string cstr = "", InstrItinClass itin = J_tc_2early_SLOT2>
314 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJR>;
316 // CR Instruction Class in V2/V3/V4.
317 // Definition of the instruction class NOT CHANGED.
318 class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
319 string cstr = "", InstrItinClass itin = CR_tc_2early_SLOT3>
320 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCR>;
322 let isCodeGenOnly = 1, isPseudo = 1 in
323 class Endloop<dag outs, dag ins, string asmstr, list<dag> pattern = [],
324 string cstr = "", InstrItinClass itin = J_tc_2early_SLOT0123>
325 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeENDLOOP>;
327 let isCodeGenOnly = 1, isPseudo = 1 in
328 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = [],
330 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDO, TypePSEUDO>;
332 let isCodeGenOnly = 1, isPseudo = 1 in
333 class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [],
335 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDOM, TypePSEUDO>;
337 //===----------------------------------------------------------------------===//
338 // Instruction Classes Definitions -
339 //===----------------------------------------------------------------------===//
345 class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [],
346 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
347 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
349 class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern = [],
350 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
351 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
353 class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [],
354 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
355 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
357 class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern = [],
358 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
359 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
365 class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [],
366 string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23>
367 : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
369 class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [],
370 string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23>
371 : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
373 // Post increment ST Instruction.
374 class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
376 : STInst<outs, ins, asmstr, pattern, cstr>;
379 class STInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
381 : STInst<outs, ins, asmstr, pattern, cstr>;
383 // Post increment LD Instruction.
384 class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
386 : LDInst<outs, ins, asmstr, pattern, cstr>;
389 class LDInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
391 : LDInst<outs, ins, asmstr, pattern, cstr>;
393 //===----------------------------------------------------------------------===//
394 // V4 Instruction Format Definitions +
395 //===----------------------------------------------------------------------===//
397 include "HexagonInstrFormatsV4.td"
399 //===----------------------------------------------------------------------===//
400 // V4 Instruction Format Definitions +
401 //===----------------------------------------------------------------------===//