1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Hexagon Instruction Flags +
13 // *** Must match HexagonBaseInfo.h ***
14 //===----------------------------------------------------------------------===//
16 class IType<bits<5> t> {
19 def TypePSEUDO : IType<0>;
20 def TypeALU32 : IType<1>;
21 def TypeCR : IType<2>;
22 def TypeJR : IType<3>;
24 def TypeLD : IType<5>;
25 def TypeST : IType<6>;
26 def TypeSYSTEM : IType<7>;
27 def TypeXTYPE : IType<8>;
28 def TypeENDLOOP: IType<31>;
30 // Maintain list of valid subtargets for each instruction.
31 class SubTarget<bits<6> value> {
32 bits<6> Value = value;
35 def HasAnySubT : SubTarget<0x3f>; // 111111
36 def HasV5SubT : SubTarget<0x3e>; // 111110
37 def HasV55SubT : SubTarget<0x3c>; // 111100
38 def HasV60SubT : SubTarget<0x38>; // 111000
40 // Addressing modes for load/store instructions
41 class AddrModeType<bits<3> value> {
42 bits<3> Value = value;
45 def NoAddrMode : AddrModeType<0>; // No addressing mode
46 def Absolute : AddrModeType<1>; // Absolute addressing mode
47 def AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode
48 def BaseImmOffset : AddrModeType<3>; // Indirect with offset
49 def BaseLongOffset : AddrModeType<4>; // Indirect with long offset
50 def BaseRegOffset : AddrModeType<5>; // Indirect with register offset
51 def PostInc : AddrModeType<6>; // Post increment addressing mode
53 class MemAccessSize<bits<4> value> {
54 bits<4> Value = value;
57 def NoMemAccess : MemAccessSize<0>;// Not a memory acces instruction.
58 def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb).
59 def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh).
60 def WordAccess : MemAccessSize<3>;// Word access instruction (memw).
61 def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd)
62 def Vector64Access : MemAccessSize<7>;// Vector access instruction (memv)
63 def Vector128Access : MemAccessSize<8>;// Vector access instruction (memv)
66 //===----------------------------------------------------------------------===//
67 // Instruction Class Declaration +
68 //===----------------------------------------------------------------------===//
71 field bits<32> Inst = ?; // Default to an invalid insn.
72 bits<4> IClass = 0; // ICLASS
74 let Inst{31-28} = IClass;
79 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
80 string cstr, InstrItinClass itin, IType type>
82 let Namespace = "Hexagon";
84 dag OutOperandList = outs;
85 dag InOperandList = ins;
86 let AsmString = asmstr;
87 let Pattern = pattern;
88 let Constraints = cstr;
92 // SoftFail is a field the disassembler can use to provide a way for
93 // instructions to not match without killing the whole decode process. It is
94 // mainly used for ARM, but Tablegen expects this field to exist or it fails
95 // to build the decode table.
96 field bits<32> SoftFail = 0;
98 // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
100 // Instruction type according to the ISA.
102 let TSFlags{4-0} = Type.Value;
104 // Solo instructions, i.e., those that cannot be in a packet with others.
106 let TSFlags{5} = isSolo;
107 // Packed only with A or X-type instructions.
108 bits<1> isSoloAX = 0;
109 let TSFlags{6} = isSoloAX;
110 // Only A-type instruction in first slot or nothing.
111 bits<1> isSoloAin1 = 0;
112 let TSFlags{7} = isSoloAin1;
114 // Predicated instructions.
115 bits<1> isPredicated = 0;
116 let TSFlags{8} = isPredicated;
117 bits<1> isPredicatedFalse = 0;
118 let TSFlags{9} = isPredicatedFalse;
119 bits<1> isPredicatedNew = 0;
120 let TSFlags{10} = isPredicatedNew;
121 bits<1> isPredicateLate = 0;
122 let TSFlags{11} = isPredicateLate; // Late predicate producer insn.
124 // New-value insn helper fields.
125 bits<1> isNewValue = 0;
126 let TSFlags{12} = isNewValue; // New-value consumer insn.
127 bits<1> hasNewValue = 0;
128 let TSFlags{13} = hasNewValue; // New-value producer insn.
129 bits<3> opNewValue = 0;
130 let TSFlags{16-14} = opNewValue; // New-value produced operand.
131 bits<1> isNVStorable = 0;
132 let TSFlags{17} = isNVStorable; // Store that can become new-value store.
133 bits<1> isNVStore = 0;
134 let TSFlags{18} = isNVStore; // New-value store insn.
135 bits<1> isCVLoadable = 0;
136 let TSFlags{19} = isCVLoadable; // Load that can become cur-value load.
137 bits<1> isCVLoad = 0;
138 let TSFlags{20} = isCVLoad; // Cur-value load insn.
140 // Immediate extender helper fields.
141 bits<1> isExtendable = 0;
142 let TSFlags{21} = isExtendable; // Insn may be extended.
143 bits<1> isExtended = 0;
144 let TSFlags{22} = isExtended; // Insn must be extended.
145 bits<3> opExtendable = 0;
146 let TSFlags{25-23} = opExtendable; // Which operand may be extended.
147 bits<1> isExtentSigned = 0;
148 let TSFlags{26} = isExtentSigned; // Signed or unsigned range.
149 bits<5> opExtentBits = 0;
150 let TSFlags{31-27} = opExtentBits; //Number of bits of range before extending.
151 bits<2> opExtentAlign = 0;
152 let TSFlags{33-32} = opExtentAlign; // Alignment exponent before extending.
154 // If an instruction is valid on a subtarget, set the corresponding
155 // bit from validSubTargets.
156 // By default, instruction is valid on all subtargets.
157 SubTarget validSubTargets = HasAnySubT;
158 let TSFlags{39-34} = validSubTargets.Value;
160 // Addressing mode for load/store instructions.
161 AddrModeType addrMode = NoAddrMode;
162 let TSFlags{42-40} = addrMode.Value;
164 // Memory access size for mem access instructions (load/store)
165 MemAccessSize accessSize = NoMemAccess;
166 let TSFlags{46-43} = accessSize.Value;
169 let TSFlags {47} = isTaken; // Branch prediction.
172 let TSFlags {48} = isFP; // Floating-point.
174 bits<1> hasNewValue2 = 0;
175 let TSFlags{50} = hasNewValue2; // Second New-value producer insn.
176 bits<3> opNewValue2 = 0;
177 let TSFlags{53-51} = opNewValue2; // Second New-value produced operand.
179 bits<1> isAccumulator = 0;
180 let TSFlags{54} = isAccumulator;
182 // Fields used for relation models.
183 bit isNonTemporal = 0;
184 string isNT = ""; // set to "true" for non-temporal vector stores.
185 string BaseOpcode = "";
186 string CextOpcode = "";
187 string PredSense = "";
188 string PNewValue = "";
189 string NValueST = ""; // Set to "true" for new-value stores.
190 string InputType = ""; // Input is "imm" or "reg" type.
191 string isFloat = "false"; // Set to "true" for the floating-point load/store.
192 string isBrTaken = !if(isTaken, "true", "false"); // Set to "true"/"false" for jump instructions
194 let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
196 let PNewValue = !if(isPredicatedNew, "new", "");
197 let NValueST = !if(isNVStore, "true", "false");
198 let isNT = !if(isNonTemporal, "true", "false");
200 // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
203 //===----------------------------------------------------------------------===//
204 // Instruction Classes Definitions +
205 //===----------------------------------------------------------------------===//
207 // LD Instruction Class in V2/V3/V4.
208 // Definition of the instruction class NOT CHANGED.
210 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
211 string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
212 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
215 class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
217 : LDInst<outs, ins, asmstr, pattern, cstr>;
219 class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
221 : LDInst<outs, ins, asmstr, pattern, cstr>;
223 // LD Instruction Class in V2/V3/V4.
224 // Definition of the instruction class NOT CHANGED.
225 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
227 : LDInst<outs, ins, asmstr, pattern, cstr>;
230 class LD0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
231 string cstr = "", InstrItinClass itin=LD_tc_ld_SLOT0>
232 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
235 class LD1Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
236 string cstr = "", InstrItinClass itin=LD_tc_ld_SLOT0>
237 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>;
239 // ST Instruction Class in V2/V3 can take SLOT0 only.
240 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
241 // Definition of the instruction class CHANGED from V2/V3 to V4.
243 class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
244 string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
245 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon;
247 class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
249 : STInst<outs, ins, asmstr, pattern, cstr>;
252 class ST0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
253 string cstr = "", InstrItinClass itin = ST_tc_ld_SLOT0>
254 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon;
256 // Same as ST0Inst but doesn't derive from OpcodeHexagon.
258 class ST1Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
259 string cstr = "", InstrItinClass itin = ST_tc_st_SLOT0>
260 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>;
262 // ST Instruction Class in V2/V3 can take SLOT0 only.
263 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
264 // Definition of the instruction class CHANGED from V2/V3 to V4.
265 class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
266 string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
267 : STInst<outs, ins, asmstr, pattern, cstr, itin>;
269 // SYSTEM Instruction Class in V4 can take SLOT0 only
270 // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
271 class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
272 string cstr = "", InstrItinClass itin = ST_tc_3stall_SLOT0>
273 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeSYSTEM>,
276 // ALU32 Instruction Class in V2/V3/V4.
277 // Definition of the instruction class NOT CHANGED.
278 class ALU32Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
279 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
280 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU32>, OpcodeHexagon;
282 // ALU64 Instruction Class in V2/V3.
283 // XTYPE Instruction Class in V4.
284 // Definition of the instruction class NOT CHANGED.
285 // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
286 class ALU64Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
287 string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
288 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>,
291 class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
292 string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
293 : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
296 // M Instruction Class in V2/V3.
297 // XTYPE Instruction Class in V4.
298 // Definition of the instruction class NOT CHANGED.
299 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
300 class MInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
301 string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23>
302 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>,
305 // Same as above but doesn't derive from OpcodeHexagon
306 class MInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
307 string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23>
308 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
310 // M Instruction Class in V2/V3.
311 // XTYPE Instruction Class in V4.
312 // Definition of the instruction class NOT CHANGED.
313 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
314 class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
315 string cstr = "", InstrItinClass itin = M_tc_2_SLOT23>
316 : MInst<outs, ins, asmstr, pattern, cstr, itin>;
318 // S Instruction Class in V2/V3.
319 // XTYPE Instruction Class in V4.
320 // Definition of the instruction class NOT CHANGED.
321 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
322 class SInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
323 string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23>
324 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>,
327 class SInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
328 string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23>
329 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
331 // S Instruction Class in V2/V3.
332 // XTYPE Instruction Class in V4.
333 // Definition of the instruction class NOT CHANGED.
334 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
335 class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
336 string cstr = "", InstrItinClass itin = S_3op_tc_1_SLOT23>
337 : SInst<outs, ins, asmstr, pattern, cstr, itin>;
339 // J Instruction Class in V2/V3/V4.
340 // Definition of the instruction class NOT CHANGED.
341 class JInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
342 string cstr = "", InstrItinClass itin = J_tc_2early_SLOT23>
343 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJ>, OpcodeHexagon;
345 // JR Instruction Class in V2/V3/V4.
346 // Definition of the instruction class NOT CHANGED.
347 class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
348 string cstr = "", InstrItinClass itin = J_tc_2early_SLOT2>
349 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJR>, OpcodeHexagon;
351 // CR Instruction Class in V2/V3/V4.
352 // Definition of the instruction class NOT CHANGED.
353 class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
354 string cstr = "", InstrItinClass itin = CR_tc_2early_SLOT3>
355 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCR>, OpcodeHexagon;
357 let isCodeGenOnly = 1, isPseudo = 1 in
358 class Endloop<dag outs, dag ins, string asmstr, list<dag> pattern = [],
359 string cstr = "", InstrItinClass itin = J_tc_2early_SLOT0123>
360 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeENDLOOP>,
363 let isCodeGenOnly = 1, isPseudo = 1 in
364 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = [],
366 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDO, TypePSEUDO>,
369 let isCodeGenOnly = 1, isPseudo = 1 in
370 class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [],
372 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDOM, TypePSEUDO>,
375 //===----------------------------------------------------------------------===//
376 // Instruction Classes Definitions -
377 //===----------------------------------------------------------------------===//
383 class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [],
384 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
385 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
387 class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern = [],
388 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
389 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
391 class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [],
392 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
393 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
395 class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern = [],
396 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
397 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
402 class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [],
403 string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23>
404 : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
406 class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [],
407 string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23>
408 : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
410 // Post increment ST Instruction.
411 class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
413 : STInst<outs, ins, asmstr, pattern, cstr>;
416 class STInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
418 : STInst<outs, ins, asmstr, pattern, cstr>;
420 // Post increment LD Instruction.
421 class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
423 : LDInst<outs, ins, asmstr, pattern, cstr>;
426 class LDInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
428 : LDInst<outs, ins, asmstr, pattern, cstr>;
430 //===----------------------------------------------------------------------===//
431 // V4 Instruction Format Definitions +
432 //===----------------------------------------------------------------------===//
434 include "HexagonInstrFormatsV4.td"
436 //===----------------------------------------------------------------------===//
437 // V4 Instruction Format Definitions +
438 //===----------------------------------------------------------------------===//
440 //===----------------------------------------------------------------------===//
441 // V60 Instruction Format Definitions +
442 //===----------------------------------------------------------------------===//
444 include "HexagonInstrFormatsV60.td"
446 //===----------------------------------------------------------------------===//
447 // V60 Instruction Format Definitions +
448 //===----------------------------------------------------------------------===//