1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Hexagon Intruction Flags +
13 // *** Must match HexagonBaseInfo.h ***
14 //===----------------------------------------------------------------------===//
16 class IType<bits<5> t> {
19 def TypePSEUDO : IType<0>;
20 def TypeALU32 : IType<1>;
21 def TypeCR : IType<2>;
22 def TypeJR : IType<3>;
24 def TypeLD : IType<5>;
25 def TypeST : IType<6>;
26 def TypeSYSTEM : IType<7>;
27 def TypeXTYPE : IType<8>;
28 def TypeENDLOOP: IType<31>;
30 // Maintain list of valid subtargets for each instruction.
31 class SubTarget<bits<4> value> {
32 bits<4> Value = value;
35 def HasV2SubT : SubTarget<0xf>;
36 def HasV2SubTOnly : SubTarget<0x1>;
37 def NoV2SubT : SubTarget<0x0>;
38 def HasV3SubT : SubTarget<0xe>;
39 def HasV3SubTOnly : SubTarget<0x2>;
40 def NoV3SubT : SubTarget<0x1>;
41 def HasV4SubT : SubTarget<0xc>;
42 def NoV4SubT : SubTarget<0x3>;
43 def HasV5SubT : SubTarget<0x8>;
44 def NoV5SubT : SubTarget<0x7>;
46 // Addressing modes for load/store instructions
47 class AddrModeType<bits<3> value> {
48 bits<3> Value = value;
51 def NoAddrMode : AddrModeType<0>; // No addressing mode
52 def Absolute : AddrModeType<1>; // Absolute addressing mode
53 def AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode
54 def BaseImmOffset : AddrModeType<3>; // Indirect with offset
55 def BaseLongOffset : AddrModeType<4>; // Indirect with long offset
56 def BaseRegOffset : AddrModeType<5>; // Indirect with register offset
58 class MemAccessSize<bits<3> value> {
59 bits<3> Value = value;
62 def NoMemAccess : MemAccessSize<0>;// Not a memory acces instruction.
63 def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb).
64 def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh).
65 def WordAccess : MemAccessSize<3>;// Word access instrution (memw).
66 def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd)
69 //===----------------------------------------------------------------------===//
70 // Intruction Class Declaration +
71 //===----------------------------------------------------------------------===//
74 field bits<32> Inst = ?; // Default to an invalid insn.
75 bits<4> IClass = 0; // ICLASS
76 bits<2> IParse = 0; // Parse bits.
78 let Inst{31-28} = IClass;
79 let Inst{15-14} = IParse;
84 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
85 string cstr, InstrItinClass itin, IType type>
86 : Instruction, OpcodeHexagon {
87 let Namespace = "Hexagon";
89 dag OutOperandList = outs;
90 dag InOperandList = ins;
91 let AsmString = asmstr;
92 let Pattern = pattern;
93 let Constraints = cstr;
97 // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
99 // Instruction type according to the ISA.
101 let TSFlags{4-0} = Type.Value;
103 // Solo instructions, i.e., those that cannot be in a packet with others.
105 let TSFlags{5} = isSolo;
107 // Predicated instructions.
108 bits<1> isPredicated = 0;
109 let TSFlags{6} = isPredicated;
110 bits<1> isPredicatedFalse = 0;
111 let TSFlags{7} = isPredicatedFalse;
112 bits<1> isPredicatedNew = 0;
113 let TSFlags{8} = isPredicatedNew;
115 // New-value insn helper fields.
116 bits<1> isNewValue = 0;
117 let TSFlags{9} = isNewValue; // New-value consumer insn.
118 bits<1> hasNewValue = 0;
119 let TSFlags{10} = hasNewValue; // New-value producer insn.
120 bits<3> opNewValue = 0;
121 let TSFlags{13-11} = opNewValue; // New-value produced operand.
122 bits<2> opNewBits = 0;
123 let TSFlags{15-14} = opNewBits; // New-value opcode bits location: 0, 8, 16.
124 bits<1> isNVStorable = 0;
125 let TSFlags{16} = isNVStorable; // Store that can become new-value store.
126 bits<1> isNVStore = 0;
127 let TSFlags{17} = isNVStore; // New-value store insn.
129 // Immediate extender helper fields.
130 bits<1> isExtendable = 0;
131 let TSFlags{18} = isExtendable; // Insn may be extended.
132 bits<1> isExtended = 0;
133 let TSFlags{19} = isExtended; // Insn must be extended.
134 bits<3> opExtendable = 0;
135 let TSFlags{22-20} = opExtendable; // Which operand may be extended.
136 bits<1> isExtentSigned = 0;
137 let TSFlags{23} = isExtentSigned; // Signed or unsigned range.
138 bits<5> opExtentBits = 0;
139 let TSFlags{28-24} = opExtentBits; //Number of bits of range before extending.
141 // If an instruction is valid on a subtarget (v2-v5), set the corresponding
142 // bit from validSubTargets. v2 is the least significant bit.
143 // By default, instruction is valid on all subtargets.
144 SubTarget validSubTargets = HasV2SubT;
145 let TSFlags{32-29} = validSubTargets.Value;
147 // Addressing mode for load/store instructions.
148 AddrModeType addrMode = NoAddrMode;
149 let TSFlags{35-33} = addrMode.Value;
151 // Memory access size for mem access instructions (load/store)
152 MemAccessSize accessSize = NoMemAccess;
153 let TSFlags{38-36} = accessSize.Value;
155 // Fields used for relation models.
156 string BaseOpcode = "";
157 string CextOpcode = "";
158 string PredSense = "";
159 string PNewValue = "";
160 string InputType = ""; // Input is "imm" or "reg" type.
161 string isMEMri = "false"; // Set to "true" for load/store with MEMri operand.
162 string isFloat = "false"; // Set to "true" for the floating-point load/store.
163 string isBrTaken = ""; // Set to "true"/"false" for jump instructions
165 let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
167 let PNewValue = !if(isPredicatedNew, "new", "");
169 // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
172 //===----------------------------------------------------------------------===//
173 // Intruction Classes Definitions +
174 //===----------------------------------------------------------------------===//
176 // LD Instruction Class in V2/V3/V4.
177 // Definition of the instruction class NOT CHANGED.
178 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
180 : InstHexagon<outs, ins, asmstr, pattern, cstr, LD, TypeLD>;
183 class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
185 : LDInst<outs, ins, asmstr, pattern, cstr>;
187 class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
189 : LDInst<outs, ins, asmstr, pattern, cstr>;
191 // LD Instruction Class in V2/V3/V4.
192 // Definition of the instruction class NOT CHANGED.
193 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
195 : LDInst<outs, ins, asmstr, pattern, cstr>;
198 class LD0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
200 : LDInst<outs, ins, asmstr, pattern, cstr>;
202 // ST Instruction Class in V2/V3 can take SLOT0 only.
203 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
204 // Definition of the instruction class CHANGED from V2/V3 to V4.
206 class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
208 : InstHexagon<outs, ins, asmstr, pattern, cstr, ST, TypeST>;
210 class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
212 : STInst<outs, ins, asmstr, pattern, cstr>;
215 class ST0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
217 : InstHexagon<outs, ins, asmstr, pattern, cstr, ST0, TypeST>;
219 // ST Instruction Class in V2/V3 can take SLOT0 only.
220 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
221 // Definition of the instruction class CHANGED from V2/V3 to V4.
222 class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
224 : STInst<outs, ins, asmstr, pattern, cstr>;
226 // SYSTEM Instruction Class in V4 can take SLOT0 only
227 // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
228 class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
230 : InstHexagon<outs, ins, asmstr, pattern, cstr, SYS, TypeSYSTEM>;
232 // ALU32 Instruction Class in V2/V3/V4.
233 // Definition of the instruction class NOT CHANGED.
234 class ALU32Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
236 : InstHexagon<outs, ins, asmstr, pattern, cstr, ALU32, TypeALU32>;
238 // ALU64 Instruction Class in V2/V3.
239 // XTYPE Instruction Class in V4.
240 // Definition of the instruction class NOT CHANGED.
241 // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
242 class ALU64Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
244 : InstHexagon<outs, ins, asmstr, pattern, cstr, ALU64, TypeXTYPE>;
246 class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
248 : ALU64Inst<outs, ins, asmstr, pattern, cstr>;
251 // M Instruction Class in V2/V3.
252 // XTYPE Instruction Class in V4.
253 // Definition of the instruction class NOT CHANGED.
254 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
255 class MInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
257 : InstHexagon<outs, ins, asmstr, pattern, cstr, M, TypeXTYPE>;
259 // M Instruction Class in V2/V3.
260 // XTYPE Instruction Class in V4.
261 // Definition of the instruction class NOT CHANGED.
262 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
263 class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
265 : MInst<outs, ins, asmstr, pattern, cstr>;
267 // S Instruction Class in V2/V3.
268 // XTYPE Instruction Class in V4.
269 // Definition of the instruction class NOT CHANGED.
270 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
271 class SInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
273 : InstHexagon<outs, ins, asmstr, pattern, cstr, S, TypeXTYPE>;
275 // S Instruction Class in V2/V3.
276 // XTYPE Instruction Class in V4.
277 // Definition of the instruction class NOT CHANGED.
278 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
279 class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
281 : SInst<outs, ins, asmstr, pattern, cstr>;
283 // J Instruction Class in V2/V3/V4.
284 // Definition of the instruction class NOT CHANGED.
285 class JInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
287 : InstHexagon<outs, ins, asmstr, pattern, cstr, J, TypeJ>;
289 // JR Instruction Class in V2/V3/V4.
290 // Definition of the instruction class NOT CHANGED.
291 class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
293 : InstHexagon<outs, ins, asmstr, pattern, cstr, JR, TypeJR>;
295 // CR Instruction Class in V2/V3/V4.
296 // Definition of the instruction class NOT CHANGED.
297 class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
299 : InstHexagon<outs, ins, asmstr, pattern, cstr, CR, TypeCR>;
301 let isCodeGenOnly = 1, isPseudo = 1 in
302 class Endloop<dag outs, dag ins, string asmstr, list<dag> pattern = [],
304 : InstHexagon<outs, ins, asmstr, pattern, cstr, ENDLOOP, TypeENDLOOP>;
306 let isCodeGenOnly = 1, isPseudo = 1 in
307 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = [],
309 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDO, TypePSEUDO>;
311 let isCodeGenOnly = 1, isPseudo = 1 in
312 class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [],
314 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDOM, TypePSEUDO>;
316 //===----------------------------------------------------------------------===//
317 // Intruction Classes Definitions -
318 //===----------------------------------------------------------------------===//
324 class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern,
326 : ALU32Inst<outs, ins, asmstr, pattern, cstr>;
328 class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern,
330 : ALU32Inst<outs, ins, asmstr, pattern, cstr>;
332 class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern,
334 : ALU32Inst<outs, ins, asmstr, pattern, cstr>;
336 class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern,
338 : ALU32Inst<outs, ins, asmstr, pattern, cstr>;
343 class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern,
345 : ALU64Inst<outs, ins, asmstr, pattern, cstr>;
347 class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern,
349 : ALU64Inst<outs, ins, asmstr, pattern, cstr>;
351 // Post increment ST Instruction.
352 class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
354 : STInst<outs, ins, asmstr, pattern, cstr>;
357 class STInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
359 : STInst<outs, ins, asmstr, pattern, cstr>;
361 // Post increment LD Instruction.
362 class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
364 : LDInst<outs, ins, asmstr, pattern, cstr>;
367 class LDInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
369 : LDInst<outs, ins, asmstr, pattern, cstr>;
371 //===----------------------------------------------------------------------===//
372 // V4 Instruction Format Definitions +
373 //===----------------------------------------------------------------------===//
375 include "HexagonInstrFormatsV4.td"
377 //===----------------------------------------------------------------------===//
378 // V4 Instruction Format Definitions +
379 //===----------------------------------------------------------------------===//