1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
12 InstrItinClass itin> : Instruction {
15 let Namespace = "Hexagon";
17 /* Commented out for Hexagon
19 let Inst{31-30} = op; */ // Top two bits are the 'op' field
21 dag OutOperandList = outs;
22 dag InOperandList = ins;
23 let AsmString = asmstr;
24 let Pattern = pattern;
25 let Constraints = cstr;
29 //----------------------------------------------------------------------------//
30 // Intruction Classes Definitions +
31 //----------------------------------------------------------------------------//
33 // LD Instruction Class in V2/V3/V4.
34 // Definition of the instruction class NOT CHANGED.
35 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern>
36 : InstHexagon<outs, ins, asmstr, pattern, "", LD> {
42 // LD Instruction Class in V2/V3/V4.
43 // Definition of the instruction class NOT CHANGED.
44 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
46 : InstHexagon<outs, ins, asmstr, pattern, cstr, LD> {
53 // ST Instruction Class in V2/V3 can take SLOT0 only.
54 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
55 // Definition of the instruction class CHANGED from V2/V3 to V4.
56 class STInst<dag outs, dag ins, string asmstr, list<dag> pattern>
57 : InstHexagon<outs, ins, asmstr, pattern, "", ST> {
63 // ST Instruction Class in V2/V3 can take SLOT0 only.
64 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
65 // Definition of the instruction class CHANGED from V2/V3 to V4.
66 class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
68 : InstHexagon<outs, ins, asmstr, pattern, cstr, ST> {
75 // ALU32 Instruction Class in V2/V3/V4.
76 // Definition of the instruction class NOT CHANGED.
77 class ALU32Type<dag outs, dag ins, string asmstr, list<dag> pattern>
78 : InstHexagon<outs, ins, asmstr, pattern, "", ALU32> {
86 // ALU64 Instruction Class in V2/V3.
87 // XTYPE Instruction Class in V4.
88 // Definition of the instruction class NOT CHANGED.
89 // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
90 class ALU64Type<dag outs, dag ins, string asmstr, list<dag> pattern>
91 : InstHexagon<outs, ins, asmstr, pattern, "", ALU64> {
99 // M Instruction Class in V2/V3.
100 // XTYPE Instruction Class in V4.
101 // Definition of the instruction class NOT CHANGED.
102 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
103 class MInst<dag outs, dag ins, string asmstr, list<dag> pattern>
104 : InstHexagon<outs, ins, asmstr, pattern, "", M> {
110 // M Instruction Class in V2/V3.
111 // XTYPE Instruction Class in V4.
112 // Definition of the instruction class NOT CHANGED.
113 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
114 class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
116 : InstHexagon<outs, ins, asmstr, pattern, cstr, M> {
122 // S Instruction Class in V2/V3.
123 // XTYPE Instruction Class in V4.
124 // Definition of the instruction class NOT CHANGED.
125 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
126 class SInst<dag outs, dag ins, string asmstr, list<dag> pattern>
127 //: InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, M)> {
128 : InstHexagon<outs, ins, asmstr, pattern, "", S> {
129 // : InstHexagon<outs, ins, asmstr, pattern, "", S> {
135 // S Instruction Class in V2/V3.
136 // XTYPE Instruction Class in V4.
137 // Definition of the instruction class NOT CHANGED.
138 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
139 class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
141 : InstHexagon<outs, ins, asmstr, pattern, cstr, S> {
142 // : InstHexagon<outs, ins, asmstr, pattern, cstr, S> {
143 // : InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, S)> {
149 // J Instruction Class in V2/V3/V4.
150 // Definition of the instruction class NOT CHANGED.
151 class JType<dag outs, dag ins, string asmstr, list<dag> pattern>
152 : InstHexagon<outs, ins, asmstr, pattern, "", J> {
156 // JR Instruction Class in V2/V3/V4.
157 // Definition of the instruction class NOT CHANGED.
158 class JRType<dag outs, dag ins, string asmstr, list<dag> pattern>
159 : InstHexagon<outs, ins, asmstr, pattern, "", JR> {
161 bits<5> pu; // Predicate register
164 // CR Instruction Class in V2/V3/V4.
165 // Definition of the instruction class NOT CHANGED.
166 class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
167 : InstHexagon<outs, ins, asmstr, pattern, "", CR> {
173 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
174 : InstHexagon<outs, ins, asmstr, pattern, "", PSEUDO>;
177 //----------------------------------------------------------------------------//
178 // Intruction Classes Definitions -
179 //----------------------------------------------------------------------------//
185 class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern>
186 : ALU32Type<outs, ins, asmstr, pattern> {
189 class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern>
190 : ALU32Type<outs, ins, asmstr, pattern> {
194 class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern>
195 : ALU32Type<outs, ins, asmstr, pattern> {
199 class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern>
200 : ALU32Type<outs, ins, asmstr, pattern> {
207 class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern>
208 : ALU64Type<outs, ins, asmstr, pattern> {
211 // J Type Instructions.
212 class JInst<dag outs, dag ins, string asmstr, list<dag> pattern>
213 : JType<outs, ins, asmstr, pattern> {
216 // JR type Instructions.
217 class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
218 : JRType<outs, ins, asmstr, pattern> {
222 // Post increment ST Instruction.
223 class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr>
224 : STInstPost<outs, ins, asmstr, pattern, cstr> {
228 // Post increment LD Instruction.
229 class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr>
230 : LDInstPost<outs, ins, asmstr, pattern, cstr> {
234 //===----------------------------------------------------------------------===//
235 // V4 Instruction Format Definitions +
236 //===----------------------------------------------------------------------===//
238 include "HexagonInstrFormatsV4.td"
240 //===----------------------------------------------------------------------===//
241 // V4 Instruction Format Definitions +
242 //===----------------------------------------------------------------------===//