1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Hexagon Intruction Flags +
13 // *** Must match HexagonBaseInfo.h ***
14 //===----------------------------------------------------------------------===//
16 class IType<bits<5> t> {
19 def TypePSEUDO : IType<0>;
20 def TypeALU32 : IType<1>;
21 def TypeCR : IType<2>;
22 def TypeJR : IType<3>;
24 def TypeLD : IType<5>;
25 def TypeST : IType<6>;
26 def TypeSYSTEM : IType<7>;
27 def TypeXTYPE : IType<8>;
28 def TypeENDLOOP: IType<31>;
30 // Maintain list of valid subtargets for each instruction.
31 class SubTarget<bits<4> value> {
32 bits<4> Value = value;
35 def HasV2SubT : SubTarget<0xf>;
36 def HasV2SubTOnly : SubTarget<0x1>;
37 def NoV2SubT : SubTarget<0x0>;
38 def HasV3SubT : SubTarget<0xe>;
39 def HasV3SubTOnly : SubTarget<0x2>;
40 def NoV3SubT : SubTarget<0x1>;
41 def HasV4SubT : SubTarget<0xc>;
42 def NoV4SubT : SubTarget<0x3>;
43 def HasV5SubT : SubTarget<0x8>;
44 def NoV5SubT : SubTarget<0x7>;
46 // Addressing modes for load/store instructions
47 class AddrModeType<bits<3> value> {
48 bits<3> Value = value;
51 def NoAddrMode : AddrModeType<0>; // No addressing mode
52 def Absolute : AddrModeType<1>; // Absolute addressing mode
53 def AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode
54 def BaseImmOffset : AddrModeType<3>; // Indirect with offset
55 def BaseLongOffset : AddrModeType<4>; // Indirect with long offset
56 def BaseRegOffset : AddrModeType<5>; // Indirect with register offset
57 def PostInc : AddrModeType<6>; // Post increment addressing mode
59 class MemAccessSize<bits<3> value> {
60 bits<3> Value = value;
63 def NoMemAccess : MemAccessSize<0>;// Not a memory acces instruction.
64 def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb).
65 def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh).
66 def WordAccess : MemAccessSize<3>;// Word access instruction (memw).
67 def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd)
70 //===----------------------------------------------------------------------===//
71 // Intruction Class Declaration +
72 //===----------------------------------------------------------------------===//
75 field bits<32> Inst = ?; // Default to an invalid insn.
76 bits<4> IClass = 0; // ICLASS
77 bits<2> IParse = 0; // Parse bits.
79 let Inst{31-28} = IClass;
80 let Inst{15-14} = IParse;
85 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
86 string cstr, InstrItinClass itin, IType type>
87 : Instruction, OpcodeHexagon {
88 let Namespace = "Hexagon";
90 dag OutOperandList = outs;
91 dag InOperandList = ins;
92 let AsmString = asmstr;
93 let Pattern = pattern;
94 let Constraints = cstr;
98 // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
100 // Instruction type according to the ISA.
102 let TSFlags{4-0} = Type.Value;
104 // Solo instructions, i.e., those that cannot be in a packet with others.
106 let TSFlags{5} = isSolo;
108 // Predicated instructions.
109 bits<1> isPredicated = 0;
110 let TSFlags{6} = isPredicated;
111 bits<1> isPredicatedFalse = 0;
112 let TSFlags{7} = isPredicatedFalse;
113 bits<1> isPredicatedNew = 0;
114 let TSFlags{8} = isPredicatedNew;
116 // New-value insn helper fields.
117 bits<1> isNewValue = 0;
118 let TSFlags{9} = isNewValue; // New-value consumer insn.
119 bits<1> hasNewValue = 0;
120 let TSFlags{10} = hasNewValue; // New-value producer insn.
121 bits<3> opNewValue = 0;
122 let TSFlags{13-11} = opNewValue; // New-value produced operand.
123 bits<2> opNewBits = 0;
124 let TSFlags{15-14} = opNewBits; // New-value opcode bits location: 0, 8, 16.
125 bits<1> isNVStorable = 0;
126 let TSFlags{16} = isNVStorable; // Store that can become new-value store.
127 bits<1> isNVStore = 0;
128 let TSFlags{17} = isNVStore; // New-value store insn.
130 // Immediate extender helper fields.
131 bits<1> isExtendable = 0;
132 let TSFlags{18} = isExtendable; // Insn may be extended.
133 bits<1> isExtended = 0;
134 let TSFlags{19} = isExtended; // Insn must be extended.
135 bits<3> opExtendable = 0;
136 let TSFlags{22-20} = opExtendable; // Which operand may be extended.
137 bits<1> isExtentSigned = 0;
138 let TSFlags{23} = isExtentSigned; // Signed or unsigned range.
139 bits<5> opExtentBits = 0;
140 let TSFlags{28-24} = opExtentBits; //Number of bits of range before extending.
142 // If an instruction is valid on a subtarget (v2-v5), set the corresponding
143 // bit from validSubTargets. v2 is the least significant bit.
144 // By default, instruction is valid on all subtargets.
145 SubTarget validSubTargets = HasV2SubT;
146 let TSFlags{32-29} = validSubTargets.Value;
148 // Addressing mode for load/store instructions.
149 AddrModeType addrMode = NoAddrMode;
150 let TSFlags{35-33} = addrMode.Value;
152 // Memory access size for mem access instructions (load/store)
153 MemAccessSize accessSize = NoMemAccess;
154 let TSFlags{38-36} = accessSize.Value;
156 // Fields used for relation models.
157 string BaseOpcode = "";
158 string CextOpcode = "";
159 string PredSense = "";
160 string PNewValue = "";
161 string NValueST = ""; // Set to "true" for new-value stores.
162 string InputType = ""; // Input is "imm" or "reg" type.
163 string isMEMri = "false"; // Set to "true" for load/store with MEMri operand.
164 string isFloat = "false"; // Set to "true" for the floating-point load/store.
165 string isBrTaken = ""; // Set to "true"/"false" for jump instructions
167 let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
169 let PNewValue = !if(isPredicatedNew, "new", "");
170 let NValueST = !if(isNVStore, "true", "false");
172 // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
175 //===----------------------------------------------------------------------===//
176 // Intruction Classes Definitions +
177 //===----------------------------------------------------------------------===//
179 // LD Instruction Class in V2/V3/V4.
180 // Definition of the instruction class NOT CHANGED.
181 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
183 : InstHexagon<outs, ins, asmstr, pattern, cstr, LD, TypeLD>;
186 class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
188 : LDInst<outs, ins, asmstr, pattern, cstr>;
190 class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
192 : LDInst<outs, ins, asmstr, pattern, cstr>;
194 // LD Instruction Class in V2/V3/V4.
195 // Definition of the instruction class NOT CHANGED.
196 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
198 : LDInst<outs, ins, asmstr, pattern, cstr>;
201 class LD0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
203 : LDInst<outs, ins, asmstr, pattern, cstr>;
205 // ST Instruction Class in V2/V3 can take SLOT0 only.
206 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
207 // Definition of the instruction class CHANGED from V2/V3 to V4.
209 class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
211 : InstHexagon<outs, ins, asmstr, pattern, cstr, ST, TypeST>;
213 class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
215 : STInst<outs, ins, asmstr, pattern, cstr>;
218 class ST0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
220 : InstHexagon<outs, ins, asmstr, pattern, cstr, ST0, TypeST>;
222 // ST Instruction Class in V2/V3 can take SLOT0 only.
223 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
224 // Definition of the instruction class CHANGED from V2/V3 to V4.
225 class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
227 : STInst<outs, ins, asmstr, pattern, cstr>;
229 // SYSTEM Instruction Class in V4 can take SLOT0 only
230 // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
231 class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
233 : InstHexagon<outs, ins, asmstr, pattern, cstr, SYS, TypeSYSTEM>;
235 // ALU32 Instruction Class in V2/V3/V4.
236 // Definition of the instruction class NOT CHANGED.
237 class ALU32Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
239 : InstHexagon<outs, ins, asmstr, pattern, cstr, ALU32, TypeALU32>;
241 // ALU64 Instruction Class in V2/V3.
242 // XTYPE Instruction Class in V4.
243 // Definition of the instruction class NOT CHANGED.
244 // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
245 class ALU64Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
247 : InstHexagon<outs, ins, asmstr, pattern, cstr, ALU64, TypeXTYPE>;
249 class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
251 : ALU64Inst<outs, ins, asmstr, pattern, cstr>;
254 // M Instruction Class in V2/V3.
255 // XTYPE Instruction Class in V4.
256 // Definition of the instruction class NOT CHANGED.
257 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
258 class MInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
260 : InstHexagon<outs, ins, asmstr, pattern, cstr, M, TypeXTYPE>;
262 // M Instruction Class in V2/V3.
263 // XTYPE Instruction Class in V4.
264 // Definition of the instruction class NOT CHANGED.
265 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
266 class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
268 : MInst<outs, ins, asmstr, pattern, cstr>;
270 // S Instruction Class in V2/V3.
271 // XTYPE Instruction Class in V4.
272 // Definition of the instruction class NOT CHANGED.
273 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
274 class SInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
276 : InstHexagon<outs, ins, asmstr, pattern, cstr, S, TypeXTYPE>;
278 // S Instruction Class in V2/V3.
279 // XTYPE Instruction Class in V4.
280 // Definition of the instruction class NOT CHANGED.
281 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
282 class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
284 : SInst<outs, ins, asmstr, pattern, cstr>;
286 // J Instruction Class in V2/V3/V4.
287 // Definition of the instruction class NOT CHANGED.
288 class JInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
290 : InstHexagon<outs, ins, asmstr, pattern, cstr, J, TypeJ>;
292 // JR Instruction Class in V2/V3/V4.
293 // Definition of the instruction class NOT CHANGED.
294 class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
296 : InstHexagon<outs, ins, asmstr, pattern, cstr, JR, TypeJR>;
298 // CR Instruction Class in V2/V3/V4.
299 // Definition of the instruction class NOT CHANGED.
300 class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
302 : InstHexagon<outs, ins, asmstr, pattern, cstr, CR, TypeCR>;
304 let isCodeGenOnly = 1, isPseudo = 1 in
305 class Endloop<dag outs, dag ins, string asmstr, list<dag> pattern = [],
307 : InstHexagon<outs, ins, asmstr, pattern, cstr, ENDLOOP, TypeENDLOOP>;
309 let isCodeGenOnly = 1, isPseudo = 1 in
310 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = [],
312 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDO, TypePSEUDO>;
314 let isCodeGenOnly = 1, isPseudo = 1 in
315 class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [],
317 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDOM, TypePSEUDO>;
319 //===----------------------------------------------------------------------===//
320 // Intruction Classes Definitions -
321 //===----------------------------------------------------------------------===//
327 class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern,
329 : ALU32Inst<outs, ins, asmstr, pattern, cstr>;
331 class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern,
333 : ALU32Inst<outs, ins, asmstr, pattern, cstr>;
335 class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern,
337 : ALU32Inst<outs, ins, asmstr, pattern, cstr>;
339 class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern,
341 : ALU32Inst<outs, ins, asmstr, pattern, cstr>;
346 class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern,
348 : ALU64Inst<outs, ins, asmstr, pattern, cstr>;
350 class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern,
352 : ALU64Inst<outs, ins, asmstr, pattern, cstr>;
354 // Post increment ST Instruction.
355 class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
357 : STInst<outs, ins, asmstr, pattern, cstr>;
360 class STInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
362 : STInst<outs, ins, asmstr, pattern, cstr>;
364 // Post increment LD Instruction.
365 class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
367 : LDInst<outs, ins, asmstr, pattern, cstr>;
370 class LDInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
372 : LDInst<outs, ins, asmstr, pattern, cstr>;
374 //===----------------------------------------------------------------------===//
375 // V4 Instruction Format Definitions +
376 //===----------------------------------------------------------------------===//
378 include "HexagonInstrFormatsV4.td"
380 //===----------------------------------------------------------------------===//
381 // V4 Instruction Format Definitions +
382 //===----------------------------------------------------------------------===//