1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Hexagon Intruction Flags +
13 // *** Must match HexagonBaseInfo.h ***
14 //===----------------------------------------------------------------------===//
16 class Type<bits<5> t> {
19 def TypePSEUDO : Type<0>;
20 def TypeALU32 : Type<1>;
26 def TypeSYSTEM : Type<7>;
27 def TypeXTYPE : Type<8>;
28 def TypeMARKER : Type<31>;
30 //===----------------------------------------------------------------------===//
31 // Intruction Class Declaration +
32 //===----------------------------------------------------------------------===//
34 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
35 string cstr, InstrItinClass itin, Type type> : Instruction {
38 let Namespace = "Hexagon";
40 dag OutOperandList = outs;
41 dag InOperandList = ins;
42 let AsmString = asmstr;
43 let Pattern = pattern;
44 let Constraints = cstr;
47 // *** Must match HexagonBaseInfo.h ***
48 Type HexagonType = type;
49 let TSFlags{4-0} = HexagonType.Value;
50 bits<1> isHexagonSolo = 0;
51 let TSFlags{5} = isHexagonSolo;
53 // Predicated instructions.
54 bits<1> isPredicated = 0;
55 let TSFlags{6} = isPredicated;
57 // *** The code above must match HexagonBaseInfo.h ***
60 //===----------------------------------------------------------------------===//
61 // Intruction Classes Definitions +
62 //===----------------------------------------------------------------------===//
64 // LD Instruction Class in V2/V3/V4.
65 // Definition of the instruction class NOT CHANGED.
66 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern>
67 : InstHexagon<outs, ins, asmstr, pattern, "", LD, TypeLD> {
74 // LD Instruction Class in V2/V3/V4.
75 // Definition of the instruction class NOT CHANGED.
76 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
78 : InstHexagon<outs, ins, asmstr, pattern, cstr, LD, TypeLD> {
86 // ST Instruction Class in V2/V3 can take SLOT0 only.
87 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
88 // Definition of the instruction class CHANGED from V2/V3 to V4.
89 class STInst<dag outs, dag ins, string asmstr, list<dag> pattern>
90 : InstHexagon<outs, ins, asmstr, pattern, "", ST, TypeST> {
97 // SYSTEM Instruction Class in V4 can take SLOT0 only
98 // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
99 class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern>
100 : InstHexagon<outs, ins, asmstr, pattern, "", SYS, TypeSYSTEM> {
106 // ST Instruction Class in V2/V3 can take SLOT0 only.
107 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
108 // Definition of the instruction class CHANGED from V2/V3 to V4.
109 class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
111 : InstHexagon<outs, ins, asmstr, pattern, cstr, ST, TypeST> {
119 // ALU32 Instruction Class in V2/V3/V4.
120 // Definition of the instruction class NOT CHANGED.
121 class ALU32Type<dag outs, dag ins, string asmstr, list<dag> pattern>
122 : InstHexagon<outs, ins, asmstr, pattern, "", ALU32, TypeALU32> {
130 // ALU64 Instruction Class in V2/V3.
131 // XTYPE Instruction Class in V4.
132 // Definition of the instruction class NOT CHANGED.
133 // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
134 class ALU64Type<dag outs, dag ins, string asmstr, list<dag> pattern>
135 : InstHexagon<outs, ins, asmstr, pattern, "", ALU64, TypeXTYPE> {
143 class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
145 : InstHexagon<outs, ins, asmstr, pattern, cstr, ALU64, TypeXTYPE> {
153 // M Instruction Class in V2/V3.
154 // XTYPE Instruction Class in V4.
155 // Definition of the instruction class NOT CHANGED.
156 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
157 class MInst<dag outs, dag ins, string asmstr, list<dag> pattern>
158 : InstHexagon<outs, ins, asmstr, pattern, "", M, TypeXTYPE> {
164 // M Instruction Class in V2/V3.
165 // XTYPE Instruction Class in V4.
166 // Definition of the instruction class NOT CHANGED.
167 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
168 class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
170 : InstHexagon<outs, ins, asmstr, pattern, cstr, M, TypeXTYPE> {
176 // S Instruction Class in V2/V3.
177 // XTYPE Instruction Class in V4.
178 // Definition of the instruction class NOT CHANGED.
179 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
180 class SInst<dag outs, dag ins, string asmstr, list<dag> pattern>
181 : InstHexagon<outs, ins, asmstr, pattern, "", S, TypeXTYPE> {
187 // S Instruction Class in V2/V3.
188 // XTYPE Instruction Class in V4.
189 // Definition of the instruction class NOT CHANGED.
190 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
191 class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
193 : InstHexagon<outs, ins, asmstr, pattern, cstr, S, TypeXTYPE> {
194 // : InstHexagon<outs, ins, asmstr, pattern, cstr, S> {
195 // : InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, S)> {
201 // J Instruction Class in V2/V3/V4.
202 // Definition of the instruction class NOT CHANGED.
203 class JType<dag outs, dag ins, string asmstr, list<dag> pattern>
204 : InstHexagon<outs, ins, asmstr, pattern, "", J, TypeJ> {
208 // JR Instruction Class in V2/V3/V4.
209 // Definition of the instruction class NOT CHANGED.
210 class JRType<dag outs, dag ins, string asmstr, list<dag> pattern>
211 : InstHexagon<outs, ins, asmstr, pattern, "", JR, TypeJR> {
213 bits<5> pu; // Predicate register
216 // CR Instruction Class in V2/V3/V4.
217 // Definition of the instruction class NOT CHANGED.
218 class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
219 : InstHexagon<outs, ins, asmstr, pattern, "", CR, TypeCR> {
224 class Marker<dag outs, dag ins, string asmstr, list<dag> pattern>
225 : InstHexagon<outs, ins, asmstr, pattern, "", MARKER, TypeMARKER> {
226 let isCodeGenOnly = 1;
230 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
231 : InstHexagon<outs, ins, asmstr, pattern, "", PSEUDO, TypePSEUDO> {
232 let isCodeGenOnly = 1;
236 //===----------------------------------------------------------------------===//
237 // Intruction Classes Definitions -
238 //===----------------------------------------------------------------------===//
244 class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern>
245 : ALU32Type<outs, ins, asmstr, pattern> {
248 class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern>
249 : ALU32Type<outs, ins, asmstr, pattern> {
253 class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern>
254 : ALU32Type<outs, ins, asmstr, pattern> {
258 class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern>
259 : ALU32Type<outs, ins, asmstr, pattern> {
266 class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern>
267 : ALU64Type<outs, ins, asmstr, pattern> {
270 class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern>
271 : ALU64Type<outs, ins, asmstr, pattern> {
275 // J Type Instructions.
276 class JInst<dag outs, dag ins, string asmstr, list<dag> pattern>
277 : JType<outs, ins, asmstr, pattern> {
280 // JR type Instructions.
281 class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
282 : JRType<outs, ins, asmstr, pattern> {
286 // Post increment ST Instruction.
287 class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr>
288 : STInstPost<outs, ins, asmstr, pattern, cstr> {
293 // Post increment LD Instruction.
294 class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr>
295 : LDInstPost<outs, ins, asmstr, pattern, cstr> {
300 //===----------------------------------------------------------------------===//
301 // V4 Instruction Format Definitions +
302 //===----------------------------------------------------------------------===//
304 include "HexagonInstrFormatsV4.td"
306 //===----------------------------------------------------------------------===//
307 // V4 Instruction Format Definitions +
308 //===----------------------------------------------------------------------===//