1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Hexagon Intruction Flags +
13 // *** Must match HexagonBaseInfo.h ***
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // Intruction Class Declaration +
19 //===----------------------------------------------------------------------===//
21 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
22 string cstr, InstrItinClass itin> : Instruction {
25 let Namespace = "Hexagon";
27 dag OutOperandList = outs;
28 dag InOperandList = ins;
29 let AsmString = asmstr;
30 let Pattern = pattern;
31 let Constraints = cstr;
34 // *** The code below must match HexagonBaseInfo.h ***
36 // Predicated instructions.
37 bits<1> isPredicated = 0;
38 let TSFlags{1} = isPredicated;
40 // *** The code above must match HexagonBaseInfo.h ***
43 //===----------------------------------------------------------------------===//
44 // Intruction Classes Definitions +
45 //===----------------------------------------------------------------------===//
47 // LD Instruction Class in V2/V3/V4.
48 // Definition of the instruction class NOT CHANGED.
49 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern>
50 : InstHexagon<outs, ins, asmstr, pattern, "", LD> {
56 // LD Instruction Class in V2/V3/V4.
57 // Definition of the instruction class NOT CHANGED.
58 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
60 : InstHexagon<outs, ins, asmstr, pattern, cstr, LD> {
67 // ST Instruction Class in V2/V3 can take SLOT0 only.
68 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
69 // Definition of the instruction class CHANGED from V2/V3 to V4.
70 class STInst<dag outs, dag ins, string asmstr, list<dag> pattern>
71 : InstHexagon<outs, ins, asmstr, pattern, "", ST> {
77 // ST Instruction Class in V2/V3 can take SLOT0 only.
78 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
79 // Definition of the instruction class CHANGED from V2/V3 to V4.
80 class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
82 : InstHexagon<outs, ins, asmstr, pattern, cstr, ST> {
89 // ALU32 Instruction Class in V2/V3/V4.
90 // Definition of the instruction class NOT CHANGED.
91 class ALU32Type<dag outs, dag ins, string asmstr, list<dag> pattern>
92 : InstHexagon<outs, ins, asmstr, pattern, "", ALU32> {
100 // ALU64 Instruction Class in V2/V3.
101 // XTYPE Instruction Class in V4.
102 // Definition of the instruction class NOT CHANGED.
103 // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
104 class ALU64Type<dag outs, dag ins, string asmstr, list<dag> pattern>
105 : InstHexagon<outs, ins, asmstr, pattern, "", ALU64> {
113 // M Instruction Class in V2/V3.
114 // XTYPE Instruction Class in V4.
115 // Definition of the instruction class NOT CHANGED.
116 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
117 class MInst<dag outs, dag ins, string asmstr, list<dag> pattern>
118 : InstHexagon<outs, ins, asmstr, pattern, "", M> {
124 // M Instruction Class in V2/V3.
125 // XTYPE Instruction Class in V4.
126 // Definition of the instruction class NOT CHANGED.
127 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
128 class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
130 : InstHexagon<outs, ins, asmstr, pattern, cstr, M> {
136 // S Instruction Class in V2/V3.
137 // XTYPE Instruction Class in V4.
138 // Definition of the instruction class NOT CHANGED.
139 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
140 class SInst<dag outs, dag ins, string asmstr, list<dag> pattern>
141 //: InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, M)> {
142 : InstHexagon<outs, ins, asmstr, pattern, "", S> {
143 // : InstHexagon<outs, ins, asmstr, pattern, "", S> {
149 // S Instruction Class in V2/V3.
150 // XTYPE Instruction Class in V4.
151 // Definition of the instruction class NOT CHANGED.
152 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
153 class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
155 : InstHexagon<outs, ins, asmstr, pattern, cstr, S> {
156 // : InstHexagon<outs, ins, asmstr, pattern, cstr, S> {
157 // : InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, S)> {
163 // J Instruction Class in V2/V3/V4.
164 // Definition of the instruction class NOT CHANGED.
165 class JType<dag outs, dag ins, string asmstr, list<dag> pattern>
166 : InstHexagon<outs, ins, asmstr, pattern, "", J> {
170 // JR Instruction Class in V2/V3/V4.
171 // Definition of the instruction class NOT CHANGED.
172 class JRType<dag outs, dag ins, string asmstr, list<dag> pattern>
173 : InstHexagon<outs, ins, asmstr, pattern, "", JR> {
175 bits<5> pu; // Predicate register
178 // CR Instruction Class in V2/V3/V4.
179 // Definition of the instruction class NOT CHANGED.
180 class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
181 : InstHexagon<outs, ins, asmstr, pattern, "", CR> {
187 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
188 : InstHexagon<outs, ins, asmstr, pattern, "", PSEUDO>;
191 //===----------------------------------------------------------------------===//
192 // Intruction Classes Definitions -
193 //===----------------------------------------------------------------------===//
199 class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern>
200 : ALU32Type<outs, ins, asmstr, pattern> {
203 class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern>
204 : ALU32Type<outs, ins, asmstr, pattern> {
208 class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern>
209 : ALU32Type<outs, ins, asmstr, pattern> {
213 class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern>
214 : ALU32Type<outs, ins, asmstr, pattern> {
221 class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern>
222 : ALU64Type<outs, ins, asmstr, pattern> {
225 // J Type Instructions.
226 class JInst<dag outs, dag ins, string asmstr, list<dag> pattern>
227 : JType<outs, ins, asmstr, pattern> {
230 // JR type Instructions.
231 class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
232 : JRType<outs, ins, asmstr, pattern> {
236 // Post increment ST Instruction.
237 class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr>
238 : STInstPost<outs, ins, asmstr, pattern, cstr> {
242 // Post increment LD Instruction.
243 class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr>
244 : LDInstPost<outs, ins, asmstr, pattern, cstr> {
248 //===----------------------------------------------------------------------===//
249 // V4 Instruction Format Definitions +
250 //===----------------------------------------------------------------------===//
252 include "HexagonInstrFormatsV4.td"
254 //===----------------------------------------------------------------------===//
255 // V4 Instruction Format Definitions +
256 //===----------------------------------------------------------------------===//