1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Hexagon Instruction Flags +
13 // *** Must match HexagonBaseInfo.h ***
14 //===----------------------------------------------------------------------===//
16 class IType<bits<5> t> {
19 def TypePSEUDO : IType<0>;
20 def TypeALU32 : IType<1>;
21 def TypeCR : IType<2>;
22 def TypeJR : IType<3>;
24 def TypeLD : IType<5>;
25 def TypeST : IType<6>;
26 def TypeSYSTEM : IType<7>;
27 def TypeXTYPE : IType<8>;
28 def TypeENDLOOP: IType<31>;
30 // Maintain list of valid subtargets for each instruction.
31 class SubTarget<bits<6> value> {
32 bits<6> Value = value;
35 def HasAnySubT : SubTarget<0x3f>; // 111111
36 def HasV5SubT : SubTarget<0x3e>; // 111110
38 // Addressing modes for load/store instructions
39 class AddrModeType<bits<3> value> {
40 bits<3> Value = value;
43 def NoAddrMode : AddrModeType<0>; // No addressing mode
44 def Absolute : AddrModeType<1>; // Absolute addressing mode
45 def AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode
46 def BaseImmOffset : AddrModeType<3>; // Indirect with offset
47 def BaseLongOffset : AddrModeType<4>; // Indirect with long offset
48 def BaseRegOffset : AddrModeType<5>; // Indirect with register offset
49 def PostInc : AddrModeType<6>; // Post increment addressing mode
51 class MemAccessSize<bits<4> value> {
52 bits<4> Value = value;
55 def NoMemAccess : MemAccessSize<0>;// Not a memory acces instruction.
56 def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb).
57 def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh).
58 def WordAccess : MemAccessSize<3>;// Word access instruction (memw).
59 def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd)
62 //===----------------------------------------------------------------------===//
63 // Instruction Class Declaration +
64 //===----------------------------------------------------------------------===//
67 field bits<32> Inst = ?; // Default to an invalid insn.
68 bits<4> IClass = 0; // ICLASS
69 bits<2> IParse = 0; // Parse bits.
71 let Inst{31-28} = IClass;
72 let Inst{15-14} = IParse;
77 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
78 string cstr, InstrItinClass itin, IType type>
79 : Instruction, OpcodeHexagon {
80 let Namespace = "Hexagon";
82 dag OutOperandList = outs;
83 dag InOperandList = ins;
84 let AsmString = asmstr;
85 let Pattern = pattern;
86 let Constraints = cstr;
87 let Itinerary = itin;
\r
90 // SoftFail is a field the disassembler can use to provide a way for
\r
91 // instructions to not match without killing the whole decode process. It is
\r
92 // mainly used for ARM, but Tablegen expects this field to exist or it fails
\r
93 // to build the decode table.
\r
94 field bits<32> SoftFail = 0;
\r
96 // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
\r
98 // Instruction type according to the ISA.
\r
100 let TSFlags{4-0} = Type.Value;
102 // Solo instructions, i.e., those that cannot be in a packet with others.
104 let TSFlags{5} = isSolo;
105 // Packed only with A or X-type instructions.
106 bits<1> isSoloAX = 0;
107 let TSFlags{6} = isSoloAX;
108 // Only A-type instruction in first slot or nothing.
109 bits<1> isSoloAin1 = 0;
110 let TSFlags{7} = isSoloAin1;
112 // Predicated instructions.
113 bits<1> isPredicated = 0;
114 let TSFlags{8} = isPredicated;
115 bits<1> isPredicatedFalse = 0;
116 let TSFlags{9} = isPredicatedFalse;
117 bits<1> isPredicatedNew = 0;
118 let TSFlags{10} = isPredicatedNew;
119 bits<1> isPredicateLate = 0;
120 let TSFlags{11} = isPredicateLate; // Late predicate producer insn.
122 // New-value insn helper fields.
123 bits<1> isNewValue = 0;
124 let TSFlags{12} = isNewValue; // New-value consumer insn.
125 bits<1> hasNewValue = 0;
126 let TSFlags{13} = hasNewValue; // New-value producer insn.
127 bits<3> opNewValue = 0;
128 let TSFlags{16-14} = opNewValue; // New-value produced operand.
129 bits<1> isNVStorable = 0;
130 let TSFlags{17} = isNVStorable; // Store that can become new-value store.
131 bits<1> isNVStore = 0;
132 let TSFlags{18} = isNVStore; // New-value store insn.
133 bits<1> isCVLoadable = 0;
134 let TSFlags{19} = isCVLoadable; // Load that can become cur-value load.
135 bits<1> isCVLoad = 0;
136 let TSFlags{20} = isCVLoad; // Cur-value load insn.
138 // Immediate extender helper fields.
139 bits<1> isExtendable = 0;
140 let TSFlags{21} = isExtendable; // Insn may be extended.
141 bits<1> isExtended = 0;
142 let TSFlags{22} = isExtended; // Insn must be extended.
143 bits<3> opExtendable = 0;
144 let TSFlags{25-23} = opExtendable; // Which operand may be extended.
145 bits<1> isExtentSigned = 0;
146 let TSFlags{26} = isExtentSigned; // Signed or unsigned range.
147 bits<5> opExtentBits = 0;
148 let TSFlags{31-27} = opExtentBits; //Number of bits of range before extending.
149 bits<2> opExtentAlign = 0;
150 let TSFlags{33-32} = opExtentAlign; // Alignment exponent before extending.
152 // If an instruction is valid on a subtarget, set the corresponding
153 // bit from validSubTargets.
154 // By default, instruction is valid on all subtargets.
155 SubTarget validSubTargets = HasAnySubT;
156 let TSFlags{39-34} = validSubTargets.Value;
158 // Addressing mode for load/store instructions.
159 AddrModeType addrMode = NoAddrMode;
160 let TSFlags{42-40} = addrMode.Value;
162 // Memory access size for mem access instructions (load/store)
163 MemAccessSize accessSize = NoMemAccess;
164 let TSFlags{46-43} = accessSize.Value;
167 let TSFlags {47} = isTaken; // Branch prediction.
170 let TSFlags {48} = isFP; // Floating-point.
172 // Fields used for relation models.
173 string BaseOpcode = "";
174 string CextOpcode = "";
175 string PredSense = "";
176 string PNewValue = "";
177 string NValueST = ""; // Set to "true" for new-value stores.
178 string InputType = ""; // Input is "imm" or "reg" type.
179 string isMEMri = "false"; // Set to "true" for load/store with MEMri operand.
180 string isFloat = "false"; // Set to "true" for the floating-point load/store.
181 string isBrTaken = !if(isTaken, "true", "false"); // Set to "true"/"false" for jump instructions
183 let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
185 let PNewValue = !if(isPredicatedNew, "new", "");
186 let NValueST = !if(isNVStore, "true", "false");
188 // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
191 //===----------------------------------------------------------------------===//
192 // Instruction Classes Definitions +
193 //===----------------------------------------------------------------------===//
195 // LD Instruction Class in V2/V3/V4.
196 // Definition of the instruction class NOT CHANGED.
198 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
199 string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
200 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>;
203 class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
205 : LDInst<outs, ins, asmstr, pattern, cstr>;
207 class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
209 : LDInst<outs, ins, asmstr, pattern, cstr>;
211 // LD Instruction Class in V2/V3/V4.
212 // Definition of the instruction class NOT CHANGED.
213 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
215 : LDInst<outs, ins, asmstr, pattern, cstr>;
218 class LD0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
219 string cstr = "", InstrItinClass itin=LD_tc_ld_SLOT0>
220 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>;
222 // ST Instruction Class in V2/V3 can take SLOT0 only.
223 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
224 // Definition of the instruction class CHANGED from V2/V3 to V4.
226 class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
227 string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
228 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>;
230 class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
232 : STInst<outs, ins, asmstr, pattern, cstr>;
235 class ST0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
236 string cstr = "", InstrItinClass itin = ST_tc_ld_SLOT0>
237 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>;
239 // ST Instruction Class in V2/V3 can take SLOT0 only.
240 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
241 // Definition of the instruction class CHANGED from V2/V3 to V4.
242 class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
243 string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
244 : STInst<outs, ins, asmstr, pattern, cstr, itin>;
246 // SYSTEM Instruction Class in V4 can take SLOT0 only
247 // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
248 class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
249 string cstr = "", InstrItinClass itin = ST_tc_3stall_SLOT0>
250 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeSYSTEM>;
252 // ALU32 Instruction Class in V2/V3/V4.
253 // Definition of the instruction class NOT CHANGED.
254 class ALU32Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
255 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
256 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU32>;
258 // ALU64 Instruction Class in V2/V3.
259 // XTYPE Instruction Class in V4.
260 // Definition of the instruction class NOT CHANGED.
261 // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
262 class ALU64Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
263 string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
264 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
266 class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
267 string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
268 : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
271 // M Instruction Class in V2/V3.
272 // XTYPE Instruction Class in V4.
273 // Definition of the instruction class NOT CHANGED.
274 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
275 class MInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
276 string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23>
277 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
279 // M Instruction Class in V2/V3.
280 // XTYPE Instruction Class in V4.
281 // Definition of the instruction class NOT CHANGED.
282 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
283 class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
284 string cstr = "", InstrItinClass itin = M_tc_2_SLOT23>
285 : MInst<outs, ins, asmstr, pattern, cstr, itin>;
287 // S Instruction Class in V2/V3.
288 // XTYPE Instruction Class in V4.
289 // Definition of the instruction class NOT CHANGED.
290 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
291 class SInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
292 string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23>
293 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
295 // S Instruction Class in V2/V3.
296 // XTYPE Instruction Class in V4.
297 // Definition of the instruction class NOT CHANGED.
298 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
299 class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
300 string cstr = "", InstrItinClass itin = S_3op_tc_1_SLOT23>
301 : SInst<outs, ins, asmstr, pattern, cstr, itin>;
303 // J Instruction Class in V2/V3/V4.
304 // Definition of the instruction class NOT CHANGED.
305 class JInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
306 string cstr = "", InstrItinClass itin = J_tc_2early_SLOT23>
307 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJ>;
309 // JR Instruction Class in V2/V3/V4.
310 // Definition of the instruction class NOT CHANGED.
311 class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
312 string cstr = "", InstrItinClass itin = J_tc_2early_SLOT2>
313 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJR>;
315 // CR Instruction Class in V2/V3/V4.
316 // Definition of the instruction class NOT CHANGED.
317 class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
318 string cstr = "", InstrItinClass itin = CR_tc_2early_SLOT3>
319 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCR>;
321 let isCodeGenOnly = 1, isPseudo = 1 in
322 class Endloop<dag outs, dag ins, string asmstr, list<dag> pattern = [],
323 string cstr = "", InstrItinClass itin = J_tc_2early_SLOT0123>
324 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeENDLOOP>;
326 let isCodeGenOnly = 1, isPseudo = 1 in
327 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = [],
329 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDO, TypePSEUDO>;
331 let isCodeGenOnly = 1, isPseudo = 1 in
332 class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [],
334 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDOM, TypePSEUDO>;
336 //===----------------------------------------------------------------------===//
337 // Instruction Classes Definitions -
338 //===----------------------------------------------------------------------===//
344 class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [],
345 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
346 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
348 class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern = [],
349 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
350 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
352 class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [],
353 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
354 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
356 class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern = [],
357 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
358 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
363 class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [],
364 string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23>
365 : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
367 class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [],
368 string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23>
369 : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
371 // Post increment ST Instruction.
372 class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
374 : STInst<outs, ins, asmstr, pattern, cstr>;
377 class STInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
379 : STInst<outs, ins, asmstr, pattern, cstr>;
381 // Post increment LD Instruction.
382 class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
384 : LDInst<outs, ins, asmstr, pattern, cstr>;
387 class LDInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
389 : LDInst<outs, ins, asmstr, pattern, cstr>;
391 //===----------------------------------------------------------------------===//
392 // V4 Instruction Format Definitions +
393 //===----------------------------------------------------------------------===//
395 include "HexagonInstrFormatsV4.td"
397 //===----------------------------------------------------------------------===//
398 // V4 Instruction Format Definitions +
399 //===----------------------------------------------------------------------===//