1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Hexagon Intruction Flags +
13 // *** Must match HexagonBaseInfo.h ***
14 //===----------------------------------------------------------------------===//
16 class Type<bits<5> t> {
19 def TypePSEUDO : Type<0>;
20 def TypeALU32 : Type<1>;
26 def TypeSYSTEM : Type<7>;
27 def TypeXTYPE : Type<8>;
28 def TypeMARKER : Type<31>;
30 //===----------------------------------------------------------------------===//
31 // Intruction Class Declaration +
32 //===----------------------------------------------------------------------===//
34 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
35 string cstr, InstrItinClass itin, Type type> : Instruction {
38 let Namespace = "Hexagon";
40 dag OutOperandList = outs;
41 dag InOperandList = ins;
42 let AsmString = asmstr;
43 let Pattern = pattern;
44 let Constraints = cstr;
48 // *** Must match HexagonBaseInfo.h ***
49 // Instruction type according to the ISA.
50 Type HexagonType = type;
51 let TSFlags{4-0} = HexagonType.Value;
52 // Solo instructions, i.e., those that cannot be in a packet with others.
53 bits<1> isHexagonSolo = 0;
54 let TSFlags{5} = isHexagonSolo;
55 // Predicated instructions.
56 bits<1> isPredicated = 0;
57 let TSFlags{6} = isPredicated;
59 // *** The code above must match HexagonBaseInfo.h ***
62 //===----------------------------------------------------------------------===//
63 // Intruction Classes Definitions +
64 //===----------------------------------------------------------------------===//
66 // LD Instruction Class in V2/V3/V4.
67 // Definition of the instruction class NOT CHANGED.
68 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern>
69 : InstHexagon<outs, ins, asmstr, pattern, "", LD, TypeLD> {
75 class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern>
76 : InstHexagon<outs, ins, asmstr, pattern, "", LD, TypeLD> {
83 // LD Instruction Class in V2/V3/V4.
84 // Definition of the instruction class NOT CHANGED.
85 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
87 : InstHexagon<outs, ins, asmstr, pattern, cstr, LD, TypeLD> {
94 // ST Instruction Class in V2/V3 can take SLOT0 only.
95 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
96 // Definition of the instruction class CHANGED from V2/V3 to V4.
97 class STInst<dag outs, dag ins, string asmstr, list<dag> pattern>
98 : InstHexagon<outs, ins, asmstr, pattern, "", ST, TypeST> {
104 class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern>
105 : InstHexagon<outs, ins, asmstr, pattern, "", ST, TypeST> {
112 // SYSTEM Instruction Class in V4 can take SLOT0 only
113 // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
114 class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern>
115 : InstHexagon<outs, ins, asmstr, pattern, "", SYS, TypeSYSTEM> {
121 // ST Instruction Class in V2/V3 can take SLOT0 only.
122 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
123 // Definition of the instruction class CHANGED from V2/V3 to V4.
124 class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
126 : InstHexagon<outs, ins, asmstr, pattern, cstr, ST, TypeST> {
133 // ALU32 Instruction Class in V2/V3/V4.
134 // Definition of the instruction class NOT CHANGED.
135 class ALU32Type<dag outs, dag ins, string asmstr, list<dag> pattern>
136 : InstHexagon<outs, ins, asmstr, pattern, "", ALU32, TypeALU32> {
144 // ALU64 Instruction Class in V2/V3.
145 // XTYPE Instruction Class in V4.
146 // Definition of the instruction class NOT CHANGED.
147 // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
148 class ALU64Type<dag outs, dag ins, string asmstr, list<dag> pattern>
149 : InstHexagon<outs, ins, asmstr, pattern, "", ALU64, TypeXTYPE> {
157 class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
159 : InstHexagon<outs, ins, asmstr, pattern, cstr, ALU64, TypeXTYPE> {
167 // M Instruction Class in V2/V3.
168 // XTYPE Instruction Class in V4.
169 // Definition of the instruction class NOT CHANGED.
170 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
171 class MInst<dag outs, dag ins, string asmstr, list<dag> pattern>
172 : InstHexagon<outs, ins, asmstr, pattern, "", M, TypeXTYPE> {
178 // M Instruction Class in V2/V3.
179 // XTYPE Instruction Class in V4.
180 // Definition of the instruction class NOT CHANGED.
181 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
182 class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
184 : InstHexagon<outs, ins, asmstr, pattern, cstr, M, TypeXTYPE> {
190 // S Instruction Class in V2/V3.
191 // XTYPE Instruction Class in V4.
192 // Definition of the instruction class NOT CHANGED.
193 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
194 class SInst<dag outs, dag ins, string asmstr, list<dag> pattern>
195 : InstHexagon<outs, ins, asmstr, pattern, "", S, TypeXTYPE> {
201 // S Instruction Class in V2/V3.
202 // XTYPE Instruction Class in V4.
203 // Definition of the instruction class NOT CHANGED.
204 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
205 class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
207 : InstHexagon<outs, ins, asmstr, pattern, cstr, S, TypeXTYPE> {
208 // : InstHexagon<outs, ins, asmstr, pattern, cstr, S> {
209 // : InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, S)> {
215 // J Instruction Class in V2/V3/V4.
216 // Definition of the instruction class NOT CHANGED.
217 class JType<dag outs, dag ins, string asmstr, list<dag> pattern>
218 : InstHexagon<outs, ins, asmstr, pattern, "", J, TypeJ> {
222 // JR Instruction Class in V2/V3/V4.
223 // Definition of the instruction class NOT CHANGED.
224 class JRType<dag outs, dag ins, string asmstr, list<dag> pattern>
225 : InstHexagon<outs, ins, asmstr, pattern, "", JR, TypeJR> {
227 bits<5> pu; // Predicate register
230 // CR Instruction Class in V2/V3/V4.
231 // Definition of the instruction class NOT CHANGED.
232 class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
233 : InstHexagon<outs, ins, asmstr, pattern, "", CR, TypeCR> {
238 class Marker<dag outs, dag ins, string asmstr, list<dag> pattern>
239 : InstHexagon<outs, ins, asmstr, pattern, "", MARKER, TypeMARKER> {
240 let isCodeGenOnly = 1;
244 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
245 : InstHexagon<outs, ins, asmstr, pattern, "", PSEUDO, TypePSEUDO> {
246 let isCodeGenOnly = 1;
250 //===----------------------------------------------------------------------===//
251 // Intruction Classes Definitions -
252 //===----------------------------------------------------------------------===//
258 class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern>
259 : ALU32Type<outs, ins, asmstr, pattern> {
262 class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern>
263 : ALU32Type<outs, ins, asmstr, pattern> {
267 class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern>
268 : ALU32Type<outs, ins, asmstr, pattern> {
272 class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern>
273 : ALU32Type<outs, ins, asmstr, pattern> {
280 class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern>
281 : ALU64Type<outs, ins, asmstr, pattern> {
284 class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern>
285 : ALU64Type<outs, ins, asmstr, pattern> {
289 // J Type Instructions.
290 class JInst<dag outs, dag ins, string asmstr, list<dag> pattern>
291 : JType<outs, ins, asmstr, pattern> {
294 // JR type Instructions.
295 class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
296 : JRType<outs, ins, asmstr, pattern> {
300 // Post increment ST Instruction.
301 class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern,
303 : STInstPost<outs, ins, asmstr, pattern, cstr> {
307 class STInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern,
309 : STInstPost<outs, ins, asmstr, pattern, cstr> {
314 // Post increment LD Instruction.
315 class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern,
317 : LDInstPost<outs, ins, asmstr, pattern, cstr> {
321 class LDInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern,
323 : LDInstPost<outs, ins, asmstr, pattern, cstr> {
328 //===----------------------------------------------------------------------===//
329 // V4 Instruction Format Definitions +
330 //===----------------------------------------------------------------------===//
332 include "HexagonInstrFormatsV4.td"
334 //===----------------------------------------------------------------------===//
335 // V4 Instruction Format Definitions +
336 //===----------------------------------------------------------------------===//