1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Hexagon Instruction Flags +
13 // *** Must match HexagonBaseInfo.h ***
14 //===----------------------------------------------------------------------===//
16 class IType<bits<5> t> {
19 def TypePSEUDO : IType<0>;
20 def TypeALU32 : IType<1>;
21 def TypeCR : IType<2>;
22 def TypeJR : IType<3>;
24 def TypeLD : IType<5>;
25 def TypeST : IType<6>;
26 def TypeSYSTEM : IType<7>;
27 def TypeXTYPE : IType<8>;
28 def TypeENDLOOP: IType<31>;
30 // Maintain list of valid subtargets for each instruction.
31 class SubTarget<bits<4> value> {
32 bits<4> Value = value;
35 def HasV2SubT : SubTarget<0xf>;
36 def HasV2SubTOnly : SubTarget<0x1>;
37 def NoV2SubT : SubTarget<0x0>;
38 def HasV3SubT : SubTarget<0xe>;
39 def HasV3SubTOnly : SubTarget<0x2>;
40 def NoV3SubT : SubTarget<0x1>;
41 def HasV4SubT : SubTarget<0xc>;
42 def NoV4SubT : SubTarget<0x3>;
43 def HasV5SubT : SubTarget<0x8>;
44 def NoV5SubT : SubTarget<0x7>;
46 // Addressing modes for load/store instructions
47 class AddrModeType<bits<3> value> {
48 bits<3> Value = value;
51 def NoAddrMode : AddrModeType<0>; // No addressing mode
52 def Absolute : AddrModeType<1>; // Absolute addressing mode
53 def AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode
54 def BaseImmOffset : AddrModeType<3>; // Indirect with offset
55 def BaseLongOffset : AddrModeType<4>; // Indirect with long offset
56 def BaseRegOffset : AddrModeType<5>; // Indirect with register offset
57 def PostInc : AddrModeType<6>; // Post increment addressing mode
59 class MemAccessSize<bits<3> value> {
60 bits<3> Value = value;
63 def NoMemAccess : MemAccessSize<0>;// Not a memory acces instruction.
64 def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb).
65 def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh).
66 def WordAccess : MemAccessSize<3>;// Word access instruction (memw).
67 def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd)
70 //===----------------------------------------------------------------------===//
71 // Instruction Class Declaration +
72 //===----------------------------------------------------------------------===//
75 field bits<32> Inst = ?; // Default to an invalid insn.
76 bits<4> IClass = 0; // ICLASS
77 bits<2> IParse = 0; // Parse bits.
79 let Inst{31-28} = IClass;
80 let Inst{15-14} = IParse;
85 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
86 string cstr, InstrItinClass itin, IType type>
87 : Instruction, OpcodeHexagon {
88 let Namespace = "Hexagon";
90 dag OutOperandList = outs;
91 dag InOperandList = ins;
92 let AsmString = asmstr;
93 let Pattern = pattern;
94 let Constraints = cstr;
95 let Itinerary = itin;
\r
98 // SoftFail is a field the disassembler can use to provide a way for
\r
99 // instructions to not match without killing the whole decode process. It is
\r
100 // mainly used for ARM, but Tablegen expects this field to exist or it fails
\r
101 // to build the decode table.
\r
102 field bits<32> SoftFail = 0;
\r
104 // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
\r
106 // Instruction type according to the ISA.
\r
108 let TSFlags{4-0} = Type.Value;
110 // Solo instructions, i.e., those that cannot be in a packet with others.
112 let TSFlags{5} = isSolo;
113 // Packed only with A or X-type instructions.
114 bits<1> isSoloAX = 0;
115 let TSFlags{6} = isSoloAX;
116 // Only A-type instruction in first slot or nothing.
117 bits<1> isSoloAin1 = 0;
118 let TSFlags{7} = isSoloAin1;
120 // Predicated instructions.
121 bits<1> isPredicated = 0;
122 let TSFlags{8} = isPredicated;
123 bits<1> isPredicatedFalse = 0;
124 let TSFlags{9} = isPredicatedFalse;
125 bits<1> isPredicatedNew = 0;
126 let TSFlags{10} = isPredicatedNew;
127 bits<1> isPredicateLate = 0;
128 let TSFlags{11} = isPredicateLate; // Late predicate producer insn.
130 // New-value insn helper fields.
131 bits<1> isNewValue = 0;
132 let TSFlags{12} = isNewValue; // New-value consumer insn.
133 bits<1> hasNewValue = 0;
134 let TSFlags{13} = hasNewValue; // New-value producer insn.
135 bits<3> opNewValue = 0;
136 let TSFlags{16-14} = opNewValue; // New-value produced operand.
137 bits<1> isNVStorable = 0;
138 let TSFlags{17} = isNVStorable; // Store that can become new-value store.
139 bits<1> isNVStore = 0;
140 let TSFlags{18} = isNVStore; // New-value store insn.
141 bits<1> isCVLoadable = 0;
142 let TSFlags{19} = isCVLoadable; // Load that can become cur-value load.
143 bits<1> isCVLoad = 0;
144 let TSFlags{20} = isCVLoad; // Cur-value load insn.
146 // Immediate extender helper fields.
147 bits<1> isExtendable = 0;
148 let TSFlags{21} = isExtendable; // Insn may be extended.
149 bits<1> isExtended = 0;
150 let TSFlags{22} = isExtended; // Insn must be extended.
151 bits<3> opExtendable = 0;
152 let TSFlags{25-23} = opExtendable; // Which operand may be extended.
153 bits<1> isExtentSigned = 0;
154 let TSFlags{26} = isExtentSigned; // Signed or unsigned range.
155 bits<5> opExtentBits = 0;
156 let TSFlags{31-27} = opExtentBits; //Number of bits of range before extending.
157 bits<2> opExtentAlign = 0;
158 let TSFlags{33-32} = opExtentAlign; // Alignment exponent before extending.
160 // If an instruction is valid on a subtarget (v2-v5), set the corresponding
161 // bit from validSubTargets. v2 is the least significant bit.
162 // By default, instruction is valid on all subtargets.
163 SubTarget validSubTargets = HasV2SubT;
164 let TSFlags{37-34} = validSubTargets.Value;
166 // Addressing mode for load/store instructions.
167 AddrModeType addrMode = NoAddrMode;
168 let TSFlags{42-40} = addrMode.Value;
170 // Memory access size for mem access instructions (load/store)
171 MemAccessSize accessSize = NoMemAccess;
172 let TSFlags{45-43} = accessSize.Value;
175 let TSFlags {47} = isTaken; // Branch prediction.
178 let TSFlags {48} = isFP; // Floating-point.
180 // Fields used for relation models.
181 string BaseOpcode = "";
182 string CextOpcode = "";
183 string PredSense = "";
184 string PNewValue = "";
185 string NValueST = ""; // Set to "true" for new-value stores.
186 string InputType = ""; // Input is "imm" or "reg" type.
187 string isMEMri = "false"; // Set to "true" for load/store with MEMri operand.
188 string isFloat = "false"; // Set to "true" for the floating-point load/store.
189 string isBrTaken = !if(isTaken, "true", "false"); // Set to "true"/"false" for jump instructions
191 let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
193 let PNewValue = !if(isPredicatedNew, "new", "");
194 let NValueST = !if(isNVStore, "true", "false");
196 // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
199 //===----------------------------------------------------------------------===//
200 // Instruction Classes Definitions +
201 //===----------------------------------------------------------------------===//
203 // LD Instruction Class in V2/V3/V4.
204 // Definition of the instruction class NOT CHANGED.
206 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
207 string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
208 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>;
211 class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
213 : LDInst<outs, ins, asmstr, pattern, cstr>;
215 class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
217 : LDInst<outs, ins, asmstr, pattern, cstr>;
219 // LD Instruction Class in V2/V3/V4.
220 // Definition of the instruction class NOT CHANGED.
221 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
223 : LDInst<outs, ins, asmstr, pattern, cstr>;
226 class LD0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
227 string cstr = "", InstrItinClass itin=LD_tc_ld_SLOT0>
228 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>;
230 // ST Instruction Class in V2/V3 can take SLOT0 only.
231 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
232 // Definition of the instruction class CHANGED from V2/V3 to V4.
234 class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
235 string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
236 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>;
238 class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
240 : STInst<outs, ins, asmstr, pattern, cstr>;
243 class ST0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
244 string cstr = "", InstrItinClass itin = ST_tc_ld_SLOT0>
245 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>;
247 // ST Instruction Class in V2/V3 can take SLOT0 only.
248 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
249 // Definition of the instruction class CHANGED from V2/V3 to V4.
250 class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
251 string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
252 : STInst<outs, ins, asmstr, pattern, cstr, itin>;
254 // SYSTEM Instruction Class in V4 can take SLOT0 only
255 // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
256 class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
257 string cstr = "", InstrItinClass itin = ST_tc_3stall_SLOT0>
258 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeSYSTEM>;
260 // ALU32 Instruction Class in V2/V3/V4.
261 // Definition of the instruction class NOT CHANGED.
262 class ALU32Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
263 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
264 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU32>;
266 // ALU64 Instruction Class in V2/V3.
267 // XTYPE Instruction Class in V4.
268 // Definition of the instruction class NOT CHANGED.
269 // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
270 class ALU64Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
271 string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
272 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
274 class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
275 string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
276 : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
279 // M Instruction Class in V2/V3.
280 // XTYPE Instruction Class in V4.
281 // Definition of the instruction class NOT CHANGED.
282 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
283 class MInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
284 string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23>
285 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
287 // M Instruction Class in V2/V3.
288 // XTYPE Instruction Class in V4.
289 // Definition of the instruction class NOT CHANGED.
290 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
291 class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
292 string cstr = "", InstrItinClass itin = M_tc_2_SLOT23>
293 : MInst<outs, ins, asmstr, pattern, cstr, itin>;
295 // S Instruction Class in V2/V3.
296 // XTYPE Instruction Class in V4.
297 // Definition of the instruction class NOT CHANGED.
298 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
299 class SInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
300 string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23>
301 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
303 // S Instruction Class in V2/V3.
304 // XTYPE Instruction Class in V4.
305 // Definition of the instruction class NOT CHANGED.
306 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
307 class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
308 string cstr = "", InstrItinClass itin = S_3op_tc_1_SLOT23>
309 : SInst<outs, ins, asmstr, pattern, cstr, itin>;
311 // J Instruction Class in V2/V3/V4.
312 // Definition of the instruction class NOT CHANGED.
313 class JInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
314 string cstr = "", InstrItinClass itin = J_tc_2early_SLOT23>
315 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJ>;
317 // JR Instruction Class in V2/V3/V4.
318 // Definition of the instruction class NOT CHANGED.
319 class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
320 string cstr = "", InstrItinClass itin = J_tc_2early_SLOT2>
321 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJR>;
323 // CR Instruction Class in V2/V3/V4.
324 // Definition of the instruction class NOT CHANGED.
325 class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
326 string cstr = "", InstrItinClass itin = CR_tc_2early_SLOT3>
327 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCR>;
329 let isCodeGenOnly = 1, isPseudo = 1 in
330 class Endloop<dag outs, dag ins, string asmstr, list<dag> pattern = [],
331 string cstr = "", InstrItinClass itin = J_tc_2early_SLOT0123>
332 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeENDLOOP>;
334 let isCodeGenOnly = 1, isPseudo = 1 in
335 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = [],
337 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDO, TypePSEUDO>;
339 let isCodeGenOnly = 1, isPseudo = 1 in
340 class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [],
342 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDOM, TypePSEUDO>;
344 //===----------------------------------------------------------------------===//
345 // Instruction Classes Definitions -
346 //===----------------------------------------------------------------------===//
352 class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [],
353 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
354 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
356 class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern = [],
357 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
358 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
360 class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [],
361 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
362 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
364 class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern = [],
365 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
366 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
372 class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [],
373 string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23>
374 : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
376 class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [],
377 string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23>
378 : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
380 // Post increment ST Instruction.
381 class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
383 : STInst<outs, ins, asmstr, pattern, cstr>;
386 class STInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
388 : STInst<outs, ins, asmstr, pattern, cstr>;
390 // Post increment LD Instruction.
391 class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
393 : LDInst<outs, ins, asmstr, pattern, cstr>;
396 class LDInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
398 : LDInst<outs, ins, asmstr, pattern, cstr>;
400 //===----------------------------------------------------------------------===//
401 // V4 Instruction Format Definitions +
402 //===----------------------------------------------------------------------===//
404 include "HexagonInstrFormatsV4.td"
406 //===----------------------------------------------------------------------===//
407 // V4 Instruction Format Definitions +
408 //===----------------------------------------------------------------------===//