1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instruction classes in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //----------------------------------------------------------------------------//
15 // Hexagon Intruction Flags +
17 // *** Must match BaseInfo.h ***
18 //----------------------------------------------------------------------------//
20 def TypeMEMOP : Type<9>;
21 def TypeNV : Type<10>;
22 def TypePREFIX : Type<30>;
24 //----------------------------------------------------------------------------//
25 // Intruction Classes Definitions +
26 //----------------------------------------------------------------------------//
29 // NV type instructions.
31 class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern>
32 : InstHexagon<outs, ins, asmstr, pattern, "", NV_V4, TypeNV> {
38 // Definition of Post increment new value store.
39 class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern,
41 : InstHexagon<outs, ins, asmstr, pattern, cstr, NV_V4, TypeNV> {
48 // Post increment ST Instruction.
49 class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern,
51 : NVInstPost_V4<outs, ins, asmstr, pattern, cstr> {
55 class MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern>
56 : InstHexagon<outs, ins, asmstr, pattern, "", MEM_V4, TypeMEMOP> {
62 let isCodeGenOnly = 1 in
63 class EXTENDERInst<dag outs, dag ins, string asmstr, list<dag> pattern = []>
64 : InstHexagon<outs, ins, asmstr, pattern, "", PREFIX, TypePREFIX>;