1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instruction classes in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //----------------------------------------------------------------------------//
15 // Hexagon Instruction Flags
17 // *** Must match BaseInfo.h ***
18 //----------------------------------------------------------------------------//
20 def TypeMEMOP : IType<9>;
21 def TypeNV : IType<10>;
22 def TypeDUPLEX : IType<11>;
23 def TypeCOMPOUND : IType<12>;
24 def TypePREFIX : IType<30>;
26 // Duplex Instruction Class Declaration
27 //===----------------------------------------------------------------------===//
30 field bits<32> Inst = ?; // Default to an invalid insn.
31 bits<4> IClass = 0; // ICLASS
32 bits<13> ISubHi = 0; // Low sub-insn
33 bits<13> ISubLo = 0; // High sub-insn
35 let Inst{31-29} = IClass{3-1};
36 let Inst{13} = IClass{0};
38 let Inst{28-16} = ISubHi;
39 let Inst{12-0} = ISubLo;
42 class InstDuplex<bits<4> iClass, list<dag> pattern = [],
44 : Instruction, OpcodeDuplex {
45 let Namespace = "Hexagon";
46 IType Type = TypeDUPLEX; // uses slot 0,1
47 let isCodeGenOnly = 1;
48 let hasSideEffects = 0;
49 dag OutOperandList = (outs);
50 dag InOperandList = (ins);
52 let Constraints = cstr;
53 let Itinerary = DUPLEX;
56 // SoftFail is a field the disassembler can use to provide a way for
57 // instructions to not match without killing the whole decode process. It is
58 // mainly used for ARM, but Tablegen expects this field to exist or it fails
59 // to build the decode table.
60 field bits<32> SoftFail = 0;
62 // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
64 let TSFlags{4-0} = Type.Value;
66 // Predicated instructions.
67 bits<1> isPredicated = 0;
68 let TSFlags{6} = isPredicated;
69 bits<1> isPredicatedFalse = 0;
70 let TSFlags{7} = isPredicatedFalse;
71 bits<1> isPredicatedNew = 0;
72 let TSFlags{8} = isPredicatedNew;
74 // New-value insn helper fields.
75 bits<1> isNewValue = 0;
76 let TSFlags{9} = isNewValue; // New-value consumer insn.
77 bits<1> hasNewValue = 0;
78 let TSFlags{10} = hasNewValue; // New-value producer insn.
79 bits<3> opNewValue = 0;
80 let TSFlags{13-11} = opNewValue; // New-value produced operand.
81 bits<1> isNVStorable = 0;
82 let TSFlags{14} = isNVStorable; // Store that can become new-value store.
83 bits<1> isNVStore = 0;
84 let TSFlags{15} = isNVStore; // New-value store insn.
86 // Immediate extender helper fields.
87 bits<1> isExtendable = 0;
88 let TSFlags{16} = isExtendable; // Insn may be extended.
89 bits<1> isExtended = 0;
90 let TSFlags{17} = isExtended; // Insn must be extended.
91 bits<3> opExtendable = 0;
92 let TSFlags{20-18} = opExtendable; // Which operand may be extended.
93 bits<1> isExtentSigned = 0;
94 let TSFlags{21} = isExtentSigned; // Signed or unsigned range.
95 bits<5> opExtentBits = 0;
96 let TSFlags{26-22} = opExtentBits; //Number of bits of range before extending.
97 bits<2> opExtentAlign = 0;
98 let TSFlags{28-27} = opExtentAlign; // Alignment exponent before extending.
101 //----------------------------------------------------------------------------//
102 // Instruction Classes Definitions
103 //----------------------------------------------------------------------------//
106 // NV type instructions.
108 class NVInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
109 string cstr = "", InstrItinClass itin = NCJ_tc_3or4stall_SLOT0>
110 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeNV>, OpcodeHexagon;
112 class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
113 string cstr = "", InstrItinClass itin = NCJ_tc_3or4stall_SLOT0>
114 : NVInst<outs, ins, asmstr, pattern, cstr, itin>;
116 // Definition of Post increment new value store.
117 class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
118 string cstr = "", InstrItinClass itin = ST_tc_st_SLOT0>
119 : NVInst<outs, ins, asmstr, pattern, cstr, itin>;
121 // Post increment ST Instruction.
123 class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
124 string cstr = "", InstrItinClass itin = ST_tc_st_SLOT0>
125 : NVInst<outs, ins, asmstr, pattern, cstr, itin>;
127 // New-value conditional branch.
128 class NCJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
130 : NVInst<outs, ins, asmstr, pattern, cstr>;
132 let mayLoad = 1, mayStore = 1 in
133 class MEMInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
134 string cstr = "", InstrItinClass itin = V4LDST_tc_st_SLOT0>
135 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeMEMOP>,
138 class MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
139 string cstr = "", InstrItinClass itin = V4LDST_tc_st_SLOT0>
140 : MEMInst<outs, ins, asmstr, pattern, cstr, itin>;
142 let isCodeGenOnly = 1 in
143 class EXTENDERInst<dag outs, dag ins, string asmstr, list<dag> pattern = []>
144 : InstHexagon<outs, ins, asmstr, pattern, "", EXTENDER_tc_1_SLOT0123,
145 TypePREFIX>, OpcodeHexagon;
147 class SUBInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
149 : InstHexagon<outs, ins, asmstr, pattern, "", PREFIX, TypeDUPLEX>,
152 class CJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
154 : InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND, TypeCOMPOUND>,