1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/raw_ostream.h"
29 #define GET_INSTRINFO_CTOR_DTOR
30 #define GET_INSTRMAP_INFO
31 #include "HexagonGenInstrInfo.inc"
32 #include "HexagonGenDFAPacketizer.inc"
37 /// Constants for Hexagon instructions.
39 const int Hexagon_MEMW_OFFSET_MAX = 4095;
40 const int Hexagon_MEMW_OFFSET_MIN = -4096;
41 const int Hexagon_MEMD_OFFSET_MAX = 8191;
42 const int Hexagon_MEMD_OFFSET_MIN = -8192;
43 const int Hexagon_MEMH_OFFSET_MAX = 2047;
44 const int Hexagon_MEMH_OFFSET_MIN = -2048;
45 const int Hexagon_MEMB_OFFSET_MAX = 1023;
46 const int Hexagon_MEMB_OFFSET_MIN = -1024;
47 const int Hexagon_ADDI_OFFSET_MAX = 32767;
48 const int Hexagon_ADDI_OFFSET_MIN = -32768;
49 const int Hexagon_MEMD_AUTOINC_MAX = 56;
50 const int Hexagon_MEMD_AUTOINC_MIN = -64;
51 const int Hexagon_MEMW_AUTOINC_MAX = 28;
52 const int Hexagon_MEMW_AUTOINC_MIN = -32;
53 const int Hexagon_MEMH_AUTOINC_MAX = 14;
54 const int Hexagon_MEMH_AUTOINC_MIN = -16;
55 const int Hexagon_MEMB_AUTOINC_MAX = 7;
56 const int Hexagon_MEMB_AUTOINC_MIN = -8;
58 // Pin the vtable to this file.
59 void HexagonInstrInfo::anchor() {}
61 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
62 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
63 RI(ST), Subtarget(ST) {
67 /// isLoadFromStackSlot - If the specified machine instruction is a direct
68 /// load from a stack slot, return the virtual or physical register number of
69 /// the destination along with the FrameIndex of the loaded stack slot. If
70 /// not, return 0. This predicate must return 0 if the instruction has
71 /// any side effects other than loading from the stack slot.
72 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
73 int &FrameIndex) const {
76 switch (MI->getOpcode()) {
83 if (MI->getOperand(2).isFI() &&
84 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
85 FrameIndex = MI->getOperand(2).getIndex();
86 return MI->getOperand(0).getReg();
94 /// isStoreToStackSlot - If the specified machine instruction is a direct
95 /// store to a stack slot, return the virtual or physical register number of
96 /// the source reg along with the FrameIndex of the loaded stack slot. If
97 /// not, return 0. This predicate must return 0 if the instruction has
98 /// any side effects other than storing to the stack slot.
99 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
100 int &FrameIndex) const {
101 switch (MI->getOpcode()) {
107 if (MI->getOperand(2).isFI() &&
108 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
109 FrameIndex = MI->getOperand(0).getIndex();
110 return MI->getOperand(2).getReg();
119 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
120 MachineBasicBlock *FBB,
121 const SmallVectorImpl<MachineOperand> &Cond,
124 int BOpc = Hexagon::JMP;
125 int BccOpc = Hexagon::JMP_t;
127 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
130 // Check if ReverseBranchCondition has asked to reverse this branch
131 // If we want to reverse the branch an odd number of times, we want
133 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
134 BccOpc = Hexagon::JMP_f;
140 // Due to a bug in TailMerging/CFG Optimization, we need to add a
141 // special case handling of a predicated jump followed by an
142 // unconditional jump. If not, Tail Merging and CFG Optimization go
143 // into an infinite loop.
144 MachineBasicBlock *NewTBB, *NewFBB;
145 SmallVector<MachineOperand, 4> Cond;
146 MachineInstr *Term = MBB.getFirstTerminator();
147 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
149 MachineBasicBlock *NextBB =
150 std::next(MachineFunction::iterator(&MBB));
151 if (NewTBB == NextBB) {
152 ReverseBranchCondition(Cond);
154 return InsertBranch(MBB, TBB, 0, Cond, DL);
157 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
160 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
165 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
166 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
172 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
173 MachineBasicBlock *&TBB,
174 MachineBasicBlock *&FBB,
175 SmallVectorImpl<MachineOperand> &Cond,
176 bool AllowModify) const {
180 // If the block has no terminators, it just falls into the block after it.
181 MachineBasicBlock::instr_iterator I = MBB.instr_end();
182 if (I == MBB.instr_begin())
185 // A basic block may looks like this:
195 // It has two succs but does not have a terminator
196 // Don't know how to handle it.
201 } while (I != MBB.instr_begin());
206 while (I->isDebugValue()) {
207 if (I == MBB.instr_begin())
212 // Delete the JMP if it's equivalent to a fall-through.
213 if (AllowModify && I->getOpcode() == Hexagon::JMP &&
214 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
215 DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
216 I->eraseFromParent();
218 if (I == MBB.instr_begin())
222 if (!isUnpredicatedTerminator(I))
225 // Get the last instruction in the block.
226 MachineInstr *LastInst = I;
227 MachineInstr *SecondLastInst = NULL;
228 // Find one more terminator if present.
230 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(I)) {
234 // This is a third branch.
237 if (I == MBB.instr_begin())
242 int LastOpcode = LastInst->getOpcode();
244 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
245 bool LastOpcodeHasNot = PredOpcodeHasNot(LastOpcode);
247 // If there is only one terminator instruction, process it.
248 if (LastInst && !SecondLastInst) {
249 if (LastOpcode == Hexagon::JMP) {
250 TBB = LastInst->getOperand(0).getMBB();
253 if (LastOpcode == Hexagon::ENDLOOP0) {
254 TBB = LastInst->getOperand(0).getMBB();
255 Cond.push_back(LastInst->getOperand(0));
258 if (LastOpcodeHasJMP_c) {
259 TBB = LastInst->getOperand(1).getMBB();
260 if (LastOpcodeHasNot) {
261 Cond.push_back(MachineOperand::CreateImm(0));
263 Cond.push_back(LastInst->getOperand(0));
266 // Otherwise, don't know what this is.
270 int SecLastOpcode = SecondLastInst->getOpcode();
272 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
273 bool SecLastOpcodeHasNot = PredOpcodeHasNot(SecLastOpcode);
274 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::JMP)) {
275 TBB = SecondLastInst->getOperand(1).getMBB();
276 if (SecLastOpcodeHasNot)
277 Cond.push_back(MachineOperand::CreateImm(0));
278 Cond.push_back(SecondLastInst->getOperand(0));
279 FBB = LastInst->getOperand(0).getMBB();
283 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
284 // executed, so remove it.
285 if (SecLastOpcode == Hexagon::JMP && LastOpcode == Hexagon::JMP) {
286 TBB = SecondLastInst->getOperand(0).getMBB();
289 I->eraseFromParent();
293 // If the block ends with an ENDLOOP, and JMP, handle it.
294 if (SecLastOpcode == Hexagon::ENDLOOP0 &&
295 LastOpcode == Hexagon::JMP) {
296 TBB = SecondLastInst->getOperand(0).getMBB();
297 Cond.push_back(SecondLastInst->getOperand(0));
298 FBB = LastInst->getOperand(0).getMBB();
302 // Otherwise, can't handle this.
307 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
308 int BOpc = Hexagon::JMP;
309 int BccOpc = Hexagon::JMP_t;
310 int BccOpcNot = Hexagon::JMP_f;
312 MachineBasicBlock::iterator I = MBB.end();
313 if (I == MBB.begin()) return 0;
315 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
316 I->getOpcode() != BccOpcNot)
319 // Remove the branch.
320 I->eraseFromParent();
324 if (I == MBB.begin()) return 1;
326 if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
329 // Remove the branch.
330 I->eraseFromParent();
335 /// \brief For a comparison instruction, return the source registers in
336 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
337 /// compares against in CmpValue. Return true if the comparison instruction
339 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
340 unsigned &SrcReg, unsigned &SrcReg2,
341 int &Mask, int &Value) const {
342 unsigned Opc = MI->getOpcode();
344 // Set mask and the first source register.
346 case Hexagon::CMPEHexagon4rr:
347 case Hexagon::CMPEQri:
348 case Hexagon::CMPEQrr:
349 case Hexagon::CMPGT64rr:
350 case Hexagon::CMPGTU64rr:
351 case Hexagon::CMPGTUri:
352 case Hexagon::CMPGTUrr:
353 case Hexagon::CMPGTri:
354 case Hexagon::CMPGTrr:
355 SrcReg = MI->getOperand(1).getReg();
358 case Hexagon::CMPbEQri_V4:
359 case Hexagon::CMPbEQrr_sbsb_V4:
360 case Hexagon::CMPbEQrr_ubub_V4:
361 case Hexagon::CMPbGTUri_V4:
362 case Hexagon::CMPbGTUrr_V4:
363 case Hexagon::CMPbGTrr_V4:
364 SrcReg = MI->getOperand(1).getReg();
367 case Hexagon::CMPhEQri_V4:
368 case Hexagon::CMPhEQrr_shl_V4:
369 case Hexagon::CMPhEQrr_xor_V4:
370 case Hexagon::CMPhGTUri_V4:
371 case Hexagon::CMPhGTUrr_V4:
372 case Hexagon::CMPhGTrr_shl_V4:
373 SrcReg = MI->getOperand(1).getReg();
378 // Set the value/second source register.
380 case Hexagon::CMPEHexagon4rr:
381 case Hexagon::CMPEQrr:
382 case Hexagon::CMPGT64rr:
383 case Hexagon::CMPGTU64rr:
384 case Hexagon::CMPGTUrr:
385 case Hexagon::CMPGTrr:
386 case Hexagon::CMPbEQrr_sbsb_V4:
387 case Hexagon::CMPbEQrr_ubub_V4:
388 case Hexagon::CMPbGTUrr_V4:
389 case Hexagon::CMPbGTrr_V4:
390 case Hexagon::CMPhEQrr_shl_V4:
391 case Hexagon::CMPhEQrr_xor_V4:
392 case Hexagon::CMPhGTUrr_V4:
393 case Hexagon::CMPhGTrr_shl_V4:
394 SrcReg2 = MI->getOperand(2).getReg();
397 case Hexagon::CMPEQri:
398 case Hexagon::CMPGTUri:
399 case Hexagon::CMPGTri:
400 case Hexagon::CMPbEQri_V4:
401 case Hexagon::CMPbGTUri_V4:
402 case Hexagon::CMPhEQri_V4:
403 case Hexagon::CMPhGTUri_V4:
405 Value = MI->getOperand(2).getImm();
413 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
414 MachineBasicBlock::iterator I, DebugLoc DL,
415 unsigned DestReg, unsigned SrcReg,
416 bool KillSrc) const {
417 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
418 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
421 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
422 BuildMI(MBB, I, DL, get(Hexagon::TFR64), DestReg).addReg(SrcReg);
425 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
426 // Map Pd = Ps to Pd = or(Ps, Ps).
427 BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
428 DestReg).addReg(SrcReg).addReg(SrcReg);
431 if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
432 Hexagon::IntRegsRegClass.contains(SrcReg)) {
433 // We can have an overlap between single and double reg: r1:0 = r0.
434 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
436 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
437 Hexagon::subreg_hireg))).addImm(0);
439 // r1:0 = r1 or no overlap.
440 BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
441 Hexagon::subreg_loreg))).addReg(SrcReg);
442 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
443 Hexagon::subreg_hireg))).addImm(0);
447 if (Hexagon::CRRegsRegClass.contains(DestReg) &&
448 Hexagon::IntRegsRegClass.contains(SrcReg)) {
449 BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
452 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
453 Hexagon::IntRegsRegClass.contains(DestReg)) {
454 BuildMI(MBB, I, DL, get(Hexagon::TFR_RsPd), DestReg).
455 addReg(SrcReg, getKillRegState(KillSrc));
458 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
459 Hexagon::PredRegsRegClass.contains(DestReg)) {
460 BuildMI(MBB, I, DL, get(Hexagon::TFR_PdRs), DestReg).
461 addReg(SrcReg, getKillRegState(KillSrc));
465 llvm_unreachable("Unimplemented");
469 void HexagonInstrInfo::
470 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
471 unsigned SrcReg, bool isKill, int FI,
472 const TargetRegisterClass *RC,
473 const TargetRegisterInfo *TRI) const {
475 DebugLoc DL = MBB.findDebugLoc(I);
476 MachineFunction &MF = *MBB.getParent();
477 MachineFrameInfo &MFI = *MF.getFrameInfo();
478 unsigned Align = MFI.getObjectAlignment(FI);
480 MachineMemOperand *MMO =
481 MF.getMachineMemOperand(
482 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
483 MachineMemOperand::MOStore,
484 MFI.getObjectSize(FI),
487 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
488 BuildMI(MBB, I, DL, get(Hexagon::STriw))
489 .addFrameIndex(FI).addImm(0)
490 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
491 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
492 BuildMI(MBB, I, DL, get(Hexagon::STrid))
493 .addFrameIndex(FI).addImm(0)
494 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
495 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
496 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
497 .addFrameIndex(FI).addImm(0)
498 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
500 llvm_unreachable("Unimplemented");
505 void HexagonInstrInfo::storeRegToAddr(
506 MachineFunction &MF, unsigned SrcReg,
508 SmallVectorImpl<MachineOperand> &Addr,
509 const TargetRegisterClass *RC,
510 SmallVectorImpl<MachineInstr*> &NewMIs) const
512 llvm_unreachable("Unimplemented");
516 void HexagonInstrInfo::
517 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
518 unsigned DestReg, int FI,
519 const TargetRegisterClass *RC,
520 const TargetRegisterInfo *TRI) const {
521 DebugLoc DL = MBB.findDebugLoc(I);
522 MachineFunction &MF = *MBB.getParent();
523 MachineFrameInfo &MFI = *MF.getFrameInfo();
524 unsigned Align = MFI.getObjectAlignment(FI);
526 MachineMemOperand *MMO =
527 MF.getMachineMemOperand(
528 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
529 MachineMemOperand::MOLoad,
530 MFI.getObjectSize(FI),
532 if (RC == &Hexagon::IntRegsRegClass) {
533 BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)
534 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
535 } else if (RC == &Hexagon::DoubleRegsRegClass) {
536 BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
537 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
538 } else if (RC == &Hexagon::PredRegsRegClass) {
539 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
540 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
542 llvm_unreachable("Can't store this register to stack slot");
547 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
548 SmallVectorImpl<MachineOperand> &Addr,
549 const TargetRegisterClass *RC,
550 SmallVectorImpl<MachineInstr*> &NewMIs) const {
551 llvm_unreachable("Unimplemented");
555 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
557 const SmallVectorImpl<unsigned> &Ops,
559 // Hexagon_TODO: Implement.
563 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
565 MachineRegisterInfo &RegInfo = MF->getRegInfo();
566 const TargetRegisterClass *TRC;
568 TRC = &Hexagon::PredRegsRegClass;
569 } else if (VT == MVT::i32 || VT == MVT::f32) {
570 TRC = &Hexagon::IntRegsRegClass;
571 } else if (VT == MVT::i64 || VT == MVT::f64) {
572 TRC = &Hexagon::DoubleRegsRegClass;
574 llvm_unreachable("Cannot handle this register class");
577 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
581 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
582 // Constant extenders are allowed only for V4 and above.
583 if (!Subtarget.hasV4TOps())
586 const MCInstrDesc &MID = MI->getDesc();
587 const uint64_t F = MID.TSFlags;
588 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
591 // TODO: This is largely obsolete now. Will need to be removed
592 // in consecutive patches.
593 switch(MI->getOpcode()) {
594 // TFR_FI Remains a special case.
595 case Hexagon::TFR_FI:
603 // This returns true in two cases:
604 // - The OP code itself indicates that this is an extended instruction.
605 // - One of MOs has been marked with HMOTF_ConstExtended flag.
606 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
607 // First check if this is permanently extended op code.
608 const uint64_t F = MI->getDesc().TSFlags;
609 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
611 // Use MO operand flags to determine if one of MI's operands
612 // has HMOTF_ConstExtended flag set.
613 for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
614 E = MI->operands_end(); I != E; ++I) {
615 if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
621 bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
622 return MI->getDesc().isBranch();
625 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
626 if (isNewValueJump(MI))
629 if (isNewValueStore(MI))
635 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
636 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
639 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
640 bool isPred = MI->getDesc().isPredicable();
645 const int Opc = MI->getOpcode();
649 return isInt<12>(MI->getOperand(1).getImm());
652 case Hexagon::STrid_indexed:
653 return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
656 case Hexagon::STriw_indexed:
657 case Hexagon::STriw_nv_V4:
658 return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
661 case Hexagon::STrih_indexed:
662 case Hexagon::STrih_nv_V4:
663 return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
666 case Hexagon::STrib_indexed:
667 case Hexagon::STrib_nv_V4:
668 return isUInt<6>(MI->getOperand(1).getImm());
671 case Hexagon::LDrid_indexed:
672 return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
675 case Hexagon::LDriw_indexed:
676 return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
679 case Hexagon::LDriuh:
680 case Hexagon::LDrih_indexed:
681 case Hexagon::LDriuh_indexed:
682 return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
685 case Hexagon::LDriub:
686 case Hexagon::LDrib_indexed:
687 case Hexagon::LDriub_indexed:
688 return isUInt<6>(MI->getOperand(2).getImm());
690 case Hexagon::POST_LDrid:
691 return isShiftedInt<4,3>(MI->getOperand(3).getImm());
693 case Hexagon::POST_LDriw:
694 return isShiftedInt<4,2>(MI->getOperand(3).getImm());
696 case Hexagon::POST_LDrih:
697 case Hexagon::POST_LDriuh:
698 return isShiftedInt<4,1>(MI->getOperand(3).getImm());
700 case Hexagon::POST_LDrib:
701 case Hexagon::POST_LDriub:
702 return isInt<4>(MI->getOperand(3).getImm());
704 case Hexagon::STrib_imm_V4:
705 case Hexagon::STrih_imm_V4:
706 case Hexagon::STriw_imm_V4:
707 return (isUInt<6>(MI->getOperand(1).getImm()) &&
708 isInt<6>(MI->getOperand(2).getImm()));
710 case Hexagon::ADD_ri:
711 return isInt<8>(MI->getOperand(2).getImm());
719 return Subtarget.hasV4TOps();
725 // This function performs the following inversiones:
730 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
732 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
733 : Hexagon::getTruePredOpcode(Opc);
734 if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
735 return InvPredOpcode;
738 default: llvm_unreachable("Unexpected predicated instruction");
739 case Hexagon::COMBINE_rr_cPt:
740 return Hexagon::COMBINE_rr_cNotPt;
741 case Hexagon::COMBINE_rr_cNotPt:
742 return Hexagon::COMBINE_rr_cPt;
745 case Hexagon::DEALLOC_RET_cPt_V4:
746 return Hexagon::DEALLOC_RET_cNotPt_V4;
747 case Hexagon::DEALLOC_RET_cNotPt_V4:
748 return Hexagon::DEALLOC_RET_cPt_V4;
752 // New Value Store instructions.
753 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
754 const uint64_t F = MI->getDesc().TSFlags;
756 return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
759 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
760 const uint64_t F = get(Opcode).TSFlags;
762 return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
765 int HexagonInstrInfo::
766 getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
767 enum Hexagon::PredSense inPredSense;
768 inPredSense = invertPredicate ? Hexagon::PredSense_false :
769 Hexagon::PredSense_true;
770 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
771 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
774 // This switch case will be removed once all the instructions have been
775 // modified to use relation maps.
777 case Hexagon::TFRI_f:
778 return !invertPredicate ? Hexagon::TFRI_cPt_f :
779 Hexagon::TFRI_cNotPt_f;
780 case Hexagon::COMBINE_rr:
781 return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
782 Hexagon::COMBINE_rr_cNotPt;
785 case Hexagon::STriw_f:
786 return !invertPredicate ? Hexagon::STriw_cPt :
787 Hexagon::STriw_cNotPt;
788 case Hexagon::STriw_indexed_f:
789 return !invertPredicate ? Hexagon::STriw_indexed_cPt :
790 Hexagon::STriw_indexed_cNotPt;
793 case Hexagon::DEALLOC_RET_V4:
794 return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
795 Hexagon::DEALLOC_RET_cNotPt_V4;
797 llvm_unreachable("Unexpected predicable instruction");
801 bool HexagonInstrInfo::
802 PredicateInstruction(MachineInstr *MI,
803 const SmallVectorImpl<MachineOperand> &Cond) const {
804 int Opc = MI->getOpcode();
805 assert (isPredicable(MI) && "Expected predicable instruction");
806 bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
807 (Cond[0].getImm() == 0));
809 // This will change MI's opcode to its predicate version.
810 // However, its operand list is still the old one, i.e. the
811 // non-predicate one.
812 MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
815 unsigned int GAIdx = 0;
817 // Indicates whether the current MI has a GlobalAddress operand
818 bool hasGAOpnd = false;
819 std::vector<MachineOperand> tmpOpnds;
821 // Indicates whether we need to shift operands to right.
822 bool needShift = true;
824 // The predicate is ALWAYS the FIRST input operand !!!
825 if (MI->getNumOperands() == 0) {
826 // The non-predicate version of MI does not take any operands,
827 // i.e. no outs and no ins. In this condition, the predicate
828 // operand will be directly placed at Operands[0]. No operand
834 else if ( MI->getOperand(MI->getNumOperands()-1).isReg()
835 && MI->getOperand(MI->getNumOperands()-1).isDef()
836 && !MI->getOperand(MI->getNumOperands()-1).isImplicit()) {
837 // The non-predicate version of MI does not have any input operands.
838 // In this condition, we extend the length of Operands[] by one and
839 // copy the original last operand to the newly allocated slot.
840 // At this moment, it is just a place holder. Later, we will put
841 // predicate operand directly into it. No operand shift is needed.
842 // Example: r0=BARRIER (this is a faked insn used here for illustration)
843 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
845 oper = MI->getNumOperands() - 2;
848 // We need to right shift all input operands by one. Duplicate the
849 // last operand into the newly allocated slot.
850 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
855 // Operands[ MI->getNumOperands() - 2 ] has been copied into
856 // Operands[ MI->getNumOperands() - 1 ], so we start from
857 // Operands[ MI->getNumOperands() - 3 ].
858 // oper is a signed int.
859 // It is ok if "MI->getNumOperands()-3" is -3, -2, or -1.
860 for (oper = MI->getNumOperands() - 3; oper >= 0; --oper)
862 MachineOperand &MO = MI->getOperand(oper);
864 // Opnd[0] Opnd[1] Opnd[2] Opnd[3] Opnd[4] Opnd[5] Opnd[6] Opnd[7]
865 // <Def0> <Def1> <Use0> <Use1> <ImpDef0> <ImpDef1> <ImpUse0> <ImpUse1>
869 // Predicate Operand here
870 if (MO.isReg() && !MO.isUse() && !MO.isImplicit()) {
874 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
875 MO.isImplicit(), MO.isKill(),
876 MO.isDead(), MO.isUndef(),
879 else if (MO.isImm()) {
880 MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
882 else if (MO.isGlobal()) {
883 // MI can not have more than one GlobalAddress operand.
884 assert(hasGAOpnd == false && "MI can only have one GlobalAddress opnd");
886 // There is no member function called "ChangeToGlobalAddress" in the
887 // MachineOperand class (not like "ChangeToRegister" and
888 // "ChangeToImmediate"). So we have to remove them from Operands[] list
889 // first, and then add them back after we have inserted the predicate
890 // operand. tmpOpnds[] is to remember these operands before we remove
892 tmpOpnds.push_back(MO);
894 // Operands[oper] is a GlobalAddress operand;
895 // Operands[oper+1] has been copied into Operands[oper+2];
901 assert(false && "Unexpected operand type");
906 int regPos = invertJump ? 1 : 0;
907 MachineOperand PredMO = Cond[regPos];
909 // [oper] now points to the last explicit Def. Predicate operand must be
910 // located at [oper+1]. See diagram above.
911 // This assumes that the predicate is always the first operand,
912 // i.e. Operands[0+numResults], in the set of inputs
913 // It is better to have an assert here to check this. But I don't know how
914 // to write this assert because findFirstPredOperandIdx() would return -1
915 if (oper < -1) oper = -1;
917 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
918 PredMO.isImplicit(), false,
919 PredMO.isDead(), PredMO.isUndef(),
922 MachineRegisterInfo &RegInfo = MI->getParent()->getParent()->getRegInfo();
923 RegInfo.clearKillFlags(PredMO.getReg());
929 // Operands[GAIdx] is the original GlobalAddress operand, which is
930 // already copied into tmpOpnds[0].
931 // Operands[GAIdx] now stores a copy of Operands[GAIdx-1]
932 // Operands[GAIdx+1] has already been copied into Operands[GAIdx+2],
933 // so we start from [GAIdx+2]
934 for (i = GAIdx + 2; i < MI->getNumOperands(); ++i)
935 tmpOpnds.push_back(MI->getOperand(i));
937 // Remove all operands in range [ (GAIdx+1) ... (MI->getNumOperands()-1) ]
938 // It is very important that we always remove from the end of Operands[]
939 // MI->getNumOperands() is at least 2 if program goes to here.
940 for (i = MI->getNumOperands() - 1; i > GAIdx; --i)
941 MI->RemoveOperand(i);
943 for (i = 0; i < tmpOpnds.size(); ++i)
944 MI->addOperand(tmpOpnds[i]);
953 isProfitableToIfCvt(MachineBasicBlock &MBB,
955 unsigned ExtraPredCycles,
956 const BranchProbability &Probability) const {
963 isProfitableToIfCvt(MachineBasicBlock &TMBB,
965 unsigned ExtraTCycles,
966 MachineBasicBlock &FMBB,
968 unsigned ExtraFCycles,
969 const BranchProbability &Probability) const {
973 // Returns true if an instruction is predicated irrespective of the predicate
974 // sense. For example, all of the following will return true.
975 // if (p0) R1 = add(R2, R3)
976 // if (!p0) R1 = add(R2, R3)
977 // if (p0.new) R1 = add(R2, R3)
978 // if (!p0.new) R1 = add(R2, R3)
979 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
980 const uint64_t F = MI->getDesc().TSFlags;
982 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
985 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
986 const uint64_t F = get(Opcode).TSFlags;
988 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
991 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
992 const uint64_t F = MI->getDesc().TSFlags;
994 assert(isPredicated(MI));
995 return (!((F >> HexagonII::PredicatedFalsePos) &
996 HexagonII::PredicatedFalseMask));
999 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
1000 const uint64_t F = get(Opcode).TSFlags;
1002 // Make sure that the instruction is predicated.
1003 assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1004 return (!((F >> HexagonII::PredicatedFalsePos) &
1005 HexagonII::PredicatedFalseMask));
1008 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
1009 const uint64_t F = MI->getDesc().TSFlags;
1011 assert(isPredicated(MI));
1012 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1015 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
1016 const uint64_t F = get(Opcode).TSFlags;
1018 assert(isPredicated(Opcode));
1019 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1022 // Returns true, if a ST insn can be promoted to a new-value store.
1023 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
1024 const HexagonRegisterInfo& QRI = getRegisterInfo();
1025 const uint64_t F = MI->getDesc().TSFlags;
1027 return ((F >> HexagonII::mayNVStorePos) &
1028 HexagonII::mayNVStoreMask &
1029 QRI.Subtarget.hasV4TOps());
1033 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
1034 std::vector<MachineOperand> &Pred) const {
1035 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
1036 MachineOperand MO = MI->getOperand(oper);
1037 if (MO.isReg() && MO.isDef()) {
1038 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
1039 if (RC == &Hexagon::PredRegsRegClass) {
1051 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
1052 const SmallVectorImpl<MachineOperand> &Pred2) const {
1059 // We indicate that we want to reverse the branch by
1060 // inserting a 0 at the beginning of the Cond vector.
1062 bool HexagonInstrInfo::
1063 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1064 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
1065 Cond.erase(Cond.begin());
1067 Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
1073 bool HexagonInstrInfo::
1074 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
1075 const BranchProbability &Probability) const {
1076 return (NumInstrs <= 4);
1079 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
1080 switch (MI->getOpcode()) {
1081 default: return false;
1082 case Hexagon::DEALLOC_RET_V4 :
1083 case Hexagon::DEALLOC_RET_cPt_V4 :
1084 case Hexagon::DEALLOC_RET_cNotPt_V4 :
1085 case Hexagon::DEALLOC_RET_cdnPnt_V4 :
1086 case Hexagon::DEALLOC_RET_cNotdnPnt_V4 :
1087 case Hexagon::DEALLOC_RET_cdnPt_V4 :
1088 case Hexagon::DEALLOC_RET_cNotdnPt_V4 :
1094 bool HexagonInstrInfo::
1095 isValidOffset(const int Opcode, const int Offset) const {
1096 // This function is to check whether the "Offset" is in the correct range of
1097 // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
1098 // inserted to calculate the final address. Due to this reason, the function
1099 // assumes that the "Offset" has correct alignment.
1100 // We used to assert if the offset was not properly aligned, however,
1101 // there are cases where a misaligned pointer recast can cause this
1102 // problem, and we need to allow for it. The front end warns of such
1103 // misaligns with respect to load size.
1107 case Hexagon::LDriw:
1108 case Hexagon::LDriw_indexed:
1109 case Hexagon::LDriw_f:
1110 case Hexagon::STriw_indexed:
1111 case Hexagon::STriw:
1112 case Hexagon::STriw_f:
1113 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
1114 (Offset <= Hexagon_MEMW_OFFSET_MAX);
1116 case Hexagon::LDrid:
1117 case Hexagon::LDrid_indexed:
1118 case Hexagon::LDrid_f:
1119 case Hexagon::STrid:
1120 case Hexagon::STrid_indexed:
1121 case Hexagon::STrid_f:
1122 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
1123 (Offset <= Hexagon_MEMD_OFFSET_MAX);
1125 case Hexagon::LDrih:
1126 case Hexagon::LDriuh:
1127 case Hexagon::STrih:
1128 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
1129 (Offset <= Hexagon_MEMH_OFFSET_MAX);
1131 case Hexagon::LDrib:
1132 case Hexagon::STrib:
1133 case Hexagon::LDriub:
1134 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
1135 (Offset <= Hexagon_MEMB_OFFSET_MAX);
1137 case Hexagon::ADD_ri:
1138 case Hexagon::TFR_FI:
1139 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
1140 (Offset <= Hexagon_ADDI_OFFSET_MAX);
1142 case Hexagon::MemOPw_ADDi_V4 :
1143 case Hexagon::MemOPw_SUBi_V4 :
1144 case Hexagon::MemOPw_ADDr_V4 :
1145 case Hexagon::MemOPw_SUBr_V4 :
1146 case Hexagon::MemOPw_ANDr_V4 :
1147 case Hexagon::MemOPw_ORr_V4 :
1148 return (0 <= Offset && Offset <= 255);
1150 case Hexagon::MemOPh_ADDi_V4 :
1151 case Hexagon::MemOPh_SUBi_V4 :
1152 case Hexagon::MemOPh_ADDr_V4 :
1153 case Hexagon::MemOPh_SUBr_V4 :
1154 case Hexagon::MemOPh_ANDr_V4 :
1155 case Hexagon::MemOPh_ORr_V4 :
1156 return (0 <= Offset && Offset <= 127);
1158 case Hexagon::MemOPb_ADDi_V4 :
1159 case Hexagon::MemOPb_SUBi_V4 :
1160 case Hexagon::MemOPb_ADDr_V4 :
1161 case Hexagon::MemOPb_SUBr_V4 :
1162 case Hexagon::MemOPb_ANDr_V4 :
1163 case Hexagon::MemOPb_ORr_V4 :
1164 return (0 <= Offset && Offset <= 63);
1166 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
1167 // any size. Later pass knows how to handle it.
1168 case Hexagon::STriw_pred:
1169 case Hexagon::LDriw_pred:
1172 case Hexagon::LOOP0_i:
1173 return isUInt<10>(Offset);
1175 // INLINEASM is very special.
1176 case Hexagon::INLINEASM:
1180 llvm_unreachable("No offset range is defined for this opcode. "
1181 "Please define it in the above switch statement!");
1186 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
1188 bool HexagonInstrInfo::
1189 isValidAutoIncImm(const EVT VT, const int Offset) const {
1191 if (VT == MVT::i64) {
1192 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
1193 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
1194 (Offset & 0x7) == 0);
1196 if (VT == MVT::i32) {
1197 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
1198 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
1199 (Offset & 0x3) == 0);
1201 if (VT == MVT::i16) {
1202 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
1203 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
1204 (Offset & 0x1) == 0);
1206 if (VT == MVT::i8) {
1207 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
1208 Offset <= Hexagon_MEMB_AUTOINC_MAX);
1210 llvm_unreachable("Not an auto-inc opc!");
1214 bool HexagonInstrInfo::
1215 isMemOp(const MachineInstr *MI) const {
1216 // return MI->getDesc().mayLoad() && MI->getDesc().mayStore();
1218 switch (MI->getOpcode())
1220 default: return false;
1221 case Hexagon::MemOPw_ADDi_V4 :
1222 case Hexagon::MemOPw_SUBi_V4 :
1223 case Hexagon::MemOPw_ADDr_V4 :
1224 case Hexagon::MemOPw_SUBr_V4 :
1225 case Hexagon::MemOPw_ANDr_V4 :
1226 case Hexagon::MemOPw_ORr_V4 :
1227 case Hexagon::MemOPh_ADDi_V4 :
1228 case Hexagon::MemOPh_SUBi_V4 :
1229 case Hexagon::MemOPh_ADDr_V4 :
1230 case Hexagon::MemOPh_SUBr_V4 :
1231 case Hexagon::MemOPh_ANDr_V4 :
1232 case Hexagon::MemOPh_ORr_V4 :
1233 case Hexagon::MemOPb_ADDi_V4 :
1234 case Hexagon::MemOPb_SUBi_V4 :
1235 case Hexagon::MemOPb_ADDr_V4 :
1236 case Hexagon::MemOPb_SUBr_V4 :
1237 case Hexagon::MemOPb_ANDr_V4 :
1238 case Hexagon::MemOPb_ORr_V4 :
1239 case Hexagon::MemOPb_SETBITi_V4:
1240 case Hexagon::MemOPh_SETBITi_V4:
1241 case Hexagon::MemOPw_SETBITi_V4:
1242 case Hexagon::MemOPb_CLRBITi_V4:
1243 case Hexagon::MemOPh_CLRBITi_V4:
1244 case Hexagon::MemOPw_CLRBITi_V4:
1251 bool HexagonInstrInfo::
1252 isSpillPredRegOp(const MachineInstr *MI) const {
1253 switch (MI->getOpcode()) {
1254 default: return false;
1255 case Hexagon::STriw_pred :
1256 case Hexagon::LDriw_pred :
1261 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
1262 switch (MI->getOpcode()) {
1263 default: return false;
1264 case Hexagon::CMPEQrr:
1265 case Hexagon::CMPEQri:
1266 case Hexagon::CMPGTrr:
1267 case Hexagon::CMPGTri:
1268 case Hexagon::CMPGTUrr:
1269 case Hexagon::CMPGTUri:
1274 bool HexagonInstrInfo::
1275 isConditionalTransfer (const MachineInstr *MI) const {
1276 switch (MI->getOpcode()) {
1277 default: return false;
1278 case Hexagon::TFR_cPt:
1279 case Hexagon::TFR_cNotPt:
1280 case Hexagon::TFRI_cPt:
1281 case Hexagon::TFRI_cNotPt:
1282 case Hexagon::TFR_cdnPt:
1283 case Hexagon::TFR_cdnNotPt:
1284 case Hexagon::TFRI_cdnPt:
1285 case Hexagon::TFRI_cdnNotPt:
1290 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
1291 const HexagonRegisterInfo& QRI = getRegisterInfo();
1292 switch (MI->getOpcode())
1294 default: return false;
1295 case Hexagon::ADD_ri_cPt:
1296 case Hexagon::ADD_ri_cNotPt:
1297 case Hexagon::ADD_rr_cPt:
1298 case Hexagon::ADD_rr_cNotPt:
1299 case Hexagon::XOR_rr_cPt:
1300 case Hexagon::XOR_rr_cNotPt:
1301 case Hexagon::AND_rr_cPt:
1302 case Hexagon::AND_rr_cNotPt:
1303 case Hexagon::OR_rr_cPt:
1304 case Hexagon::OR_rr_cNotPt:
1305 case Hexagon::SUB_rr_cPt:
1306 case Hexagon::SUB_rr_cNotPt:
1307 case Hexagon::COMBINE_rr_cPt:
1308 case Hexagon::COMBINE_rr_cNotPt:
1310 case Hexagon::ASLH_cPt_V4:
1311 case Hexagon::ASLH_cNotPt_V4:
1312 case Hexagon::ASRH_cPt_V4:
1313 case Hexagon::ASRH_cNotPt_V4:
1314 case Hexagon::SXTB_cPt_V4:
1315 case Hexagon::SXTB_cNotPt_V4:
1316 case Hexagon::SXTH_cPt_V4:
1317 case Hexagon::SXTH_cNotPt_V4:
1318 case Hexagon::ZXTB_cPt_V4:
1319 case Hexagon::ZXTB_cNotPt_V4:
1320 case Hexagon::ZXTH_cPt_V4:
1321 case Hexagon::ZXTH_cNotPt_V4:
1322 return QRI.Subtarget.hasV4TOps();
1326 bool HexagonInstrInfo::
1327 isConditionalLoad (const MachineInstr* MI) const {
1328 const HexagonRegisterInfo& QRI = getRegisterInfo();
1329 switch (MI->getOpcode())
1331 default: return false;
1332 case Hexagon::LDrid_cPt :
1333 case Hexagon::LDrid_cNotPt :
1334 case Hexagon::LDrid_indexed_cPt :
1335 case Hexagon::LDrid_indexed_cNotPt :
1336 case Hexagon::LDriw_cPt :
1337 case Hexagon::LDriw_cNotPt :
1338 case Hexagon::LDriw_indexed_cPt :
1339 case Hexagon::LDriw_indexed_cNotPt :
1340 case Hexagon::LDrih_cPt :
1341 case Hexagon::LDrih_cNotPt :
1342 case Hexagon::LDrih_indexed_cPt :
1343 case Hexagon::LDrih_indexed_cNotPt :
1344 case Hexagon::LDrib_cPt :
1345 case Hexagon::LDrib_cNotPt :
1346 case Hexagon::LDrib_indexed_cPt :
1347 case Hexagon::LDrib_indexed_cNotPt :
1348 case Hexagon::LDriuh_cPt :
1349 case Hexagon::LDriuh_cNotPt :
1350 case Hexagon::LDriuh_indexed_cPt :
1351 case Hexagon::LDriuh_indexed_cNotPt :
1352 case Hexagon::LDriub_cPt :
1353 case Hexagon::LDriub_cNotPt :
1354 case Hexagon::LDriub_indexed_cPt :
1355 case Hexagon::LDriub_indexed_cNotPt :
1357 case Hexagon::POST_LDrid_cPt :
1358 case Hexagon::POST_LDrid_cNotPt :
1359 case Hexagon::POST_LDriw_cPt :
1360 case Hexagon::POST_LDriw_cNotPt :
1361 case Hexagon::POST_LDrih_cPt :
1362 case Hexagon::POST_LDrih_cNotPt :
1363 case Hexagon::POST_LDrib_cPt :
1364 case Hexagon::POST_LDrib_cNotPt :
1365 case Hexagon::POST_LDriuh_cPt :
1366 case Hexagon::POST_LDriuh_cNotPt :
1367 case Hexagon::POST_LDriub_cPt :
1368 case Hexagon::POST_LDriub_cNotPt :
1369 return QRI.Subtarget.hasV4TOps();
1370 case Hexagon::LDrid_indexed_shl_cPt_V4 :
1371 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
1372 case Hexagon::LDrib_indexed_shl_cPt_V4 :
1373 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
1374 case Hexagon::LDriub_indexed_shl_cPt_V4 :
1375 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
1376 case Hexagon::LDrih_indexed_shl_cPt_V4 :
1377 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
1378 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
1379 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
1380 case Hexagon::LDriw_indexed_shl_cPt_V4 :
1381 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
1382 return QRI.Subtarget.hasV4TOps();
1386 // Returns true if an instruction is a conditional store.
1388 // Note: It doesn't include conditional new-value stores as they can't be
1389 // converted to .new predicate.
1391 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
1393 // / \ (not OK. it will cause new-value store to be
1394 // / X conditional on p0.new while R2 producer is
1397 // p.new store p.old NV store
1398 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
1404 // [if (p0)memw(R0+#0)=R2]
1406 // The above diagram shows the steps involoved in the conversion of a predicated
1407 // store instruction to its .new predicated new-value form.
1409 // The following set of instructions further explains the scenario where
1410 // conditional new-value store becomes invalid when promoted to .new predicate
1413 // { 1) if (p0) r0 = add(r1, r2)
1414 // 2) p0 = cmp.eq(r3, #0) }
1416 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
1417 // the first two instructions because in instr 1, r0 is conditional on old value
1418 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
1419 // is not valid for new-value stores.
1420 bool HexagonInstrInfo::
1421 isConditionalStore (const MachineInstr* MI) const {
1422 const HexagonRegisterInfo& QRI = getRegisterInfo();
1423 switch (MI->getOpcode())
1425 default: return false;
1426 case Hexagon::STrib_imm_cPt_V4 :
1427 case Hexagon::STrib_imm_cNotPt_V4 :
1428 case Hexagon::STrib_indexed_shl_cPt_V4 :
1429 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
1430 case Hexagon::STrib_cPt :
1431 case Hexagon::STrib_cNotPt :
1432 case Hexagon::POST_STbri_cPt :
1433 case Hexagon::POST_STbri_cNotPt :
1434 case Hexagon::STrid_indexed_cPt :
1435 case Hexagon::STrid_indexed_cNotPt :
1436 case Hexagon::STrid_indexed_shl_cPt_V4 :
1437 case Hexagon::POST_STdri_cPt :
1438 case Hexagon::POST_STdri_cNotPt :
1439 case Hexagon::STrih_cPt :
1440 case Hexagon::STrih_cNotPt :
1441 case Hexagon::STrih_indexed_cPt :
1442 case Hexagon::STrih_indexed_cNotPt :
1443 case Hexagon::STrih_imm_cPt_V4 :
1444 case Hexagon::STrih_imm_cNotPt_V4 :
1445 case Hexagon::STrih_indexed_shl_cPt_V4 :
1446 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
1447 case Hexagon::POST_SThri_cPt :
1448 case Hexagon::POST_SThri_cNotPt :
1449 case Hexagon::STriw_cPt :
1450 case Hexagon::STriw_cNotPt :
1451 case Hexagon::STriw_indexed_cPt :
1452 case Hexagon::STriw_indexed_cNotPt :
1453 case Hexagon::STriw_imm_cPt_V4 :
1454 case Hexagon::STriw_imm_cNotPt_V4 :
1455 case Hexagon::STriw_indexed_shl_cPt_V4 :
1456 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
1457 case Hexagon::POST_STwri_cPt :
1458 case Hexagon::POST_STwri_cNotPt :
1459 return QRI.Subtarget.hasV4TOps();
1461 // V4 global address store before promoting to dot new.
1462 case Hexagon::STd_GP_cPt_V4 :
1463 case Hexagon::STd_GP_cNotPt_V4 :
1464 case Hexagon::STb_GP_cPt_V4 :
1465 case Hexagon::STb_GP_cNotPt_V4 :
1466 case Hexagon::STh_GP_cPt_V4 :
1467 case Hexagon::STh_GP_cNotPt_V4 :
1468 case Hexagon::STw_GP_cPt_V4 :
1469 case Hexagon::STw_GP_cNotPt_V4 :
1470 return QRI.Subtarget.hasV4TOps();
1472 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
1473 // from the "Conditional Store" list. Because a predicated new value store
1474 // would NOT be promoted to a double dot new store. See diagram below:
1475 // This function returns yes for those stores that are predicated but not
1476 // yet promoted to predicate dot new instructions.
1478 // +---------------------+
1479 // /-----| if (p0) memw(..)=r0 |---------\~
1480 // || +---------------------+ ||
1481 // promote || /\ /\ || promote
1483 // \||/ demote || \||/
1485 // +-------------------------+ || +-------------------------+
1486 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
1487 // +-------------------------+ || +-------------------------+
1490 // promote || \/ NOT possible
1494 // +-----------------------------+
1495 // | if (p0.new) memw(..)=r0.new |
1496 // +-----------------------------+
1497 // Double Dot New Store
1503 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
1504 if (isNewValue(MI) && isBranch(MI))
1509 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
1510 return (getAddrMode(MI) == HexagonII::PostInc);
1513 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
1514 const uint64_t F = MI->getDesc().TSFlags;
1515 return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
1518 // Returns true, if any one of the operands is a dot new
1519 // insn, whether it is predicated dot new or register dot new.
1520 bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
1521 return (isNewValueInst(MI) ||
1522 (isPredicated(MI) && isPredicatedNew(MI)));
1525 // Returns the most basic instruction for the .new predicated instructions and
1526 // new-value stores.
1527 // For example, all of the following instructions will be converted back to the
1528 // same instruction:
1529 // 1) if (p0.new) memw(R0+#0) = R1.new --->
1530 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
1531 // 3) if (p0.new) memw(R0+#0) = R1 --->
1534 int HexagonInstrInfo::GetDotOldOp(const int opc) const {
1536 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
1537 NewOp = Hexagon::getPredOldOpcode(NewOp);
1539 assert(0 && "Couldn't change predicate new instruction to its old form.");
1542 if (isNewValueStore(NewOp)) { // Convert into non-new-value format
1543 NewOp = Hexagon::getNonNVStore(NewOp);
1545 assert(0 && "Couldn't change new-value store to its old form.");
1550 // Return the new value instruction for a given store.
1551 int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
1552 int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
1553 if (NVOpcode >= 0) // Valid new-value store instruction.
1556 switch (MI->getOpcode()) {
1557 default: llvm_unreachable("Unknown .new type");
1558 // store new value byte
1559 case Hexagon::STrib_shl_V4:
1560 return Hexagon::STrib_shl_nv_V4;
1562 case Hexagon::STrih_shl_V4:
1563 return Hexagon::STrih_shl_nv_V4;
1565 case Hexagon::STriw_f:
1566 return Hexagon::STriw_nv_V4;
1568 case Hexagon::STriw_indexed_f:
1569 return Hexagon::STriw_indexed_nv_V4;
1571 case Hexagon::STriw_shl_V4:
1572 return Hexagon::STriw_shl_nv_V4;
1578 // Return .new predicate version for an instruction.
1579 int HexagonInstrInfo::GetDotNewPredOp(MachineInstr *MI,
1580 const MachineBranchProbabilityInfo
1583 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
1584 if (NewOpcode >= 0) // Valid predicate new instruction
1587 switch (MI->getOpcode()) {
1588 default: llvm_unreachable("Unknown .new type");
1590 case Hexagon::JMP_t:
1591 case Hexagon::JMP_f:
1592 return getDotNewPredJumpOp(MI, MBPI);
1594 case Hexagon::JMPR_t:
1595 return Hexagon::JMPR_tnew_tV3;
1597 case Hexagon::JMPR_f:
1598 return Hexagon::JMPR_fnew_tV3;
1600 case Hexagon::JMPret_t:
1601 return Hexagon::JMPret_tnew_tV3;
1603 case Hexagon::JMPret_f:
1604 return Hexagon::JMPret_fnew_tV3;
1607 // Conditional combine
1608 case Hexagon::COMBINE_rr_cPt :
1609 return Hexagon::COMBINE_rr_cdnPt;
1610 case Hexagon::COMBINE_rr_cNotPt :
1611 return Hexagon::COMBINE_rr_cdnNotPt;
1616 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
1617 const uint64_t F = MI->getDesc().TSFlags;
1619 return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
1622 /// immediateExtend - Changes the instruction in place to one using an immediate
1624 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
1625 assert((isExtendable(MI)||isConstExtended(MI)) &&
1626 "Instruction must be extendable");
1627 // Find which operand is extendable.
1628 short ExtOpNum = getCExtOpNum(MI);
1629 MachineOperand &MO = MI->getOperand(ExtOpNum);
1630 // This needs to be something we understand.
1631 assert((MO.isMBB() || MO.isImm()) &&
1632 "Branch with unknown extendable field type");
1633 // Mark given operand as extended.
1634 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
1637 DFAPacketizer *HexagonInstrInfo::
1638 CreateTargetScheduleState(const TargetMachine *TM,
1639 const ScheduleDAG *DAG) const {
1640 const InstrItineraryData *II = TM->getInstrItineraryData();
1641 return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II);
1644 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1645 const MachineBasicBlock *MBB,
1646 const MachineFunction &MF) const {
1647 // Debug info is never a scheduling boundary. It's necessary to be explicit
1648 // due to the special treatment of IT instructions below, otherwise a
1649 // dbg_value followed by an IT will result in the IT instruction being
1650 // considered a scheduling hazard, which is wrong. It should be the actual
1651 // instruction preceding the dbg_value instruction(s), just like it is
1652 // when debug info is not present.
1653 if (MI->isDebugValue())
1656 // Terminators and labels can't be scheduled around.
1657 if (MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm())
1663 bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const {
1665 // Constant extenders are allowed only for V4 and above.
1666 if (!Subtarget.hasV4TOps())
1669 const uint64_t F = MI->getDesc().TSFlags;
1670 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
1671 if (isExtended) // Instruction must be extended.
1674 unsigned isExtendable = (F >> HexagonII::ExtendablePos)
1675 & HexagonII::ExtendableMask;
1679 short ExtOpNum = getCExtOpNum(MI);
1680 const MachineOperand &MO = MI->getOperand(ExtOpNum);
1681 // Use MO operand flags to determine if MO
1682 // has the HMOTF_ConstExtended flag set.
1683 if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
1685 // If this is a Machine BB address we are talking about, and it is
1686 // not marked as extended, say so.
1690 // We could be using an instruction with an extendable immediate and shoehorn
1691 // a global address into it. If it is a global address it will be constant
1692 // extended. We do this for COMBINE.
1693 // We currently only handle isGlobal() because it is the only kind of
1694 // object we are going to end up with here for now.
1695 // In the future we probably should add isSymbol(), etc.
1696 if (MO.isGlobal() || MO.isSymbol())
1699 // If the extendable operand is not 'Immediate' type, the instruction should
1700 // have 'isExtended' flag set.
1701 assert(MO.isImm() && "Extendable operand must be Immediate type");
1703 int MinValue = getMinValue(MI);
1704 int MaxValue = getMaxValue(MI);
1705 int ImmValue = MO.getImm();
1707 return (ImmValue < MinValue || ImmValue > MaxValue);
1710 // Returns the opcode to use when converting MI, which is a conditional jump,
1711 // into a conditional instruction which uses the .new value of the predicate.
1712 // We also use branch probabilities to add a hint to the jump.
1714 HexagonInstrInfo::getDotNewPredJumpOp(MachineInstr *MI,
1716 MachineBranchProbabilityInfo *MBPI) const {
1718 // We assume that block can have at most two successors.
1720 MachineBasicBlock *Src = MI->getParent();
1721 MachineOperand *BrTarget = &MI->getOperand(1);
1722 MachineBasicBlock *Dst = BrTarget->getMBB();
1724 const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
1725 if (Prediction >= BranchProbability(1,2))
1728 switch (MI->getOpcode()) {
1729 case Hexagon::JMP_t:
1730 return taken ? Hexagon::JMP_tnew_t : Hexagon::JMP_tnew_nt;
1731 case Hexagon::JMP_f:
1732 return taken ? Hexagon::JMP_fnew_t : Hexagon::JMP_fnew_nt;
1735 llvm_unreachable("Unexpected jump instruction.");
1738 // Returns true if a particular operand is extendable for an instruction.
1739 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
1740 unsigned short OperandNum) const {
1741 // Constant extenders are allowed only for V4 and above.
1742 if (!Subtarget.hasV4TOps())
1745 const uint64_t F = MI->getDesc().TSFlags;
1747 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
1751 // Returns Operand Index for the constant extended instruction.
1752 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
1753 const uint64_t F = MI->getDesc().TSFlags;
1754 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
1757 // Returns the min value that doesn't need to be extended.
1758 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
1759 const uint64_t F = MI->getDesc().TSFlags;
1760 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1761 & HexagonII::ExtentSignedMask;
1762 unsigned bits = (F >> HexagonII::ExtentBitsPos)
1763 & HexagonII::ExtentBitsMask;
1765 if (isSigned) // if value is signed
1766 return -1 << (bits - 1);
1771 // Returns the max value that doesn't need to be extended.
1772 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
1773 const uint64_t F = MI->getDesc().TSFlags;
1774 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1775 & HexagonII::ExtentSignedMask;
1776 unsigned bits = (F >> HexagonII::ExtentBitsPos)
1777 & HexagonII::ExtentBitsMask;
1779 if (isSigned) // if value is signed
1780 return ~(-1 << (bits - 1));
1782 return ~(-1 << bits);
1785 // Returns true if an instruction can be converted into a non-extended
1786 // equivalent instruction.
1787 bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const {
1790 // Check if the instruction has a register form that uses register in place
1791 // of the extended operand, if so return that as the non-extended form.
1792 if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
1795 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1796 // Check addressing mode and retrieve non-ext equivalent instruction.
1798 switch (getAddrMode(MI)) {
1799 case HexagonII::Absolute :
1800 // Load/store with absolute addressing mode can be converted into
1801 // base+offset mode.
1802 NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
1804 case HexagonII::BaseImmOffset :
1805 // Load/store with base+offset addressing mode can be converted into
1806 // base+register offset addressing mode. However left shift operand should
1808 NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
1813 if (NonExtOpcode < 0)
1820 // Returns opcode of the non-extended equivalent instruction.
1821 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
1823 // Check if the instruction has a register form that uses register in place
1824 // of the extended operand, if so return that as the non-extended form.
1825 short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
1826 if (NonExtOpcode >= 0)
1827 return NonExtOpcode;
1829 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1830 // Check addressing mode and retrieve non-ext equivalent instruction.
1831 switch (getAddrMode(MI)) {
1832 case HexagonII::Absolute :
1833 return Hexagon::getBasedWithImmOffset(MI->getOpcode());
1834 case HexagonII::BaseImmOffset :
1835 return Hexagon::getBaseWithRegOffset(MI->getOpcode());
1843 bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const {
1844 return (Opcode == Hexagon::JMP_t) ||
1845 (Opcode == Hexagon::JMP_f) ||
1846 (Opcode == Hexagon::JMP_tnew_t) ||
1847 (Opcode == Hexagon::JMP_fnew_t) ||
1848 (Opcode == Hexagon::JMP_tnew_nt) ||
1849 (Opcode == Hexagon::JMP_fnew_nt);
1852 bool HexagonInstrInfo::PredOpcodeHasNot(Opcode_t Opcode) const {
1853 return (Opcode == Hexagon::JMP_f) ||
1854 (Opcode == Hexagon::JMP_fnew_t) ||
1855 (Opcode == Hexagon::JMP_fnew_nt);