1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonInstrInfo.h"
15 #include "HexagonRegisterInfo.h"
16 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Support/MathExtras.h"
27 #define GET_INSTRINFO_CTOR
28 #include "HexagonGenInstrInfo.inc"
29 #include "HexagonGenDFAPacketizer.inc"
30 #include "HexagonConstExtInfo.h"
35 /// Constants for Hexagon instructions.
37 const int Hexagon_MEMW_OFFSET_MAX = 4095;
38 const int Hexagon_MEMW_OFFSET_MIN = -4096;
39 const int Hexagon_MEMD_OFFSET_MAX = 8191;
40 const int Hexagon_MEMD_OFFSET_MIN = -8192;
41 const int Hexagon_MEMH_OFFSET_MAX = 2047;
42 const int Hexagon_MEMH_OFFSET_MIN = -2048;
43 const int Hexagon_MEMB_OFFSET_MAX = 1023;
44 const int Hexagon_MEMB_OFFSET_MIN = -1024;
45 const int Hexagon_ADDI_OFFSET_MAX = 32767;
46 const int Hexagon_ADDI_OFFSET_MIN = -32768;
47 const int Hexagon_MEMD_AUTOINC_MAX = 56;
48 const int Hexagon_MEMD_AUTOINC_MIN = -64;
49 const int Hexagon_MEMW_AUTOINC_MAX = 28;
50 const int Hexagon_MEMW_AUTOINC_MIN = -32;
51 const int Hexagon_MEMH_AUTOINC_MAX = 14;
52 const int Hexagon_MEMH_AUTOINC_MIN = -16;
53 const int Hexagon_MEMB_AUTOINC_MAX = 7;
54 const int Hexagon_MEMB_AUTOINC_MIN = -8;
57 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
58 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
59 RI(ST, *this), Subtarget(ST) {
63 /// isLoadFromStackSlot - If the specified machine instruction is a direct
64 /// load from a stack slot, return the virtual or physical register number of
65 /// the destination along with the FrameIndex of the loaded stack slot. If
66 /// not, return 0. This predicate must return 0 if the instruction has
67 /// any side effects other than loading from the stack slot.
68 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
69 int &FrameIndex) const {
72 switch (MI->getOpcode()) {
79 if (MI->getOperand(2).isFI() &&
80 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
81 FrameIndex = MI->getOperand(2).getIndex();
82 return MI->getOperand(0).getReg();
90 /// isStoreToStackSlot - If the specified machine instruction is a direct
91 /// store to a stack slot, return the virtual or physical register number of
92 /// the source reg along with the FrameIndex of the loaded stack slot. If
93 /// not, return 0. This predicate must return 0 if the instruction has
94 /// any side effects other than storing to the stack slot.
95 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
96 int &FrameIndex) const {
97 switch (MI->getOpcode()) {
99 case Hexagon::STriw_indexed:
104 if (MI->getOperand(2).isFI() &&
105 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
106 FrameIndex = MI->getOperand(2).getIndex();
107 return MI->getOperand(0).getReg();
116 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
117 MachineBasicBlock *FBB,
118 const SmallVectorImpl<MachineOperand> &Cond,
121 int BOpc = Hexagon::JMP;
122 int BccOpc = Hexagon::JMP_c;
124 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
127 // Check if ReverseBranchCondition has asked to reverse this branch
128 // If we want to reverse the branch an odd number of times, we want
130 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
131 BccOpc = Hexagon::JMP_cNot;
137 // Due to a bug in TailMerging/CFG Optimization, we need to add a
138 // special case handling of a predicated jump followed by an
139 // unconditional jump. If not, Tail Merging and CFG Optimization go
140 // into an infinite loop.
141 MachineBasicBlock *NewTBB, *NewFBB;
142 SmallVector<MachineOperand, 4> Cond;
143 MachineInstr *Term = MBB.getFirstTerminator();
144 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
146 MachineBasicBlock *NextBB =
147 llvm::next(MachineFunction::iterator(&MBB));
148 if (NewTBB == NextBB) {
149 ReverseBranchCondition(Cond);
151 return InsertBranch(MBB, TBB, 0, Cond, DL);
154 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
157 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
162 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
163 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
169 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
170 MachineBasicBlock *&TBB,
171 MachineBasicBlock *&FBB,
172 SmallVectorImpl<MachineOperand> &Cond,
173 bool AllowModify) const {
176 // If the block has no terminators, it just falls into the block after it.
177 MachineBasicBlock::iterator I = MBB.end();
178 if (I == MBB.begin())
181 // A basic block may looks like this:
191 // It has two succs but does not have a terminator
192 // Don't know how to handle it.
197 } while (I != MBB.begin());
202 while (I->isDebugValue()) {
203 if (I == MBB.begin())
207 if (!isUnpredicatedTerminator(I))
210 // Get the last instruction in the block.
211 MachineInstr *LastInst = I;
213 // If there is only one terminator instruction, process it.
214 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
215 if (LastInst->getOpcode() == Hexagon::JMP) {
216 TBB = LastInst->getOperand(0).getMBB();
219 if (LastInst->getOpcode() == Hexagon::JMP_c) {
220 // Block ends with fall-through true condbranch.
221 TBB = LastInst->getOperand(1).getMBB();
222 Cond.push_back(LastInst->getOperand(0));
225 if (LastInst->getOpcode() == Hexagon::JMP_cNot) {
226 // Block ends with fall-through false condbranch.
227 TBB = LastInst->getOperand(1).getMBB();
228 Cond.push_back(MachineOperand::CreateImm(0));
229 Cond.push_back(LastInst->getOperand(0));
232 // Otherwise, don't know what this is.
236 // Get the instruction before it if it's a terminator.
237 MachineInstr *SecondLastInst = I;
239 // If there are three terminators, we don't know what sort of block this is.
240 if (SecondLastInst && I != MBB.begin() &&
241 isUnpredicatedTerminator(--I))
244 // If the block ends with Hexagon::BRCOND and Hexagon:JMP, handle it.
245 if (((SecondLastInst->getOpcode() == Hexagon::BRCOND) ||
246 (SecondLastInst->getOpcode() == Hexagon::JMP_c)) &&
247 LastInst->getOpcode() == Hexagon::JMP) {
248 TBB = SecondLastInst->getOperand(1).getMBB();
249 Cond.push_back(SecondLastInst->getOperand(0));
250 FBB = LastInst->getOperand(0).getMBB();
254 // If the block ends with Hexagon::JMP_cNot and Hexagon:JMP, handle it.
255 if ((SecondLastInst->getOpcode() == Hexagon::JMP_cNot) &&
256 LastInst->getOpcode() == Hexagon::JMP) {
257 TBB = SecondLastInst->getOperand(1).getMBB();
258 Cond.push_back(MachineOperand::CreateImm(0));
259 Cond.push_back(SecondLastInst->getOperand(0));
260 FBB = LastInst->getOperand(0).getMBB();
264 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
265 // executed, so remove it.
266 if (SecondLastInst->getOpcode() == Hexagon::JMP &&
267 LastInst->getOpcode() == Hexagon::JMP) {
268 TBB = SecondLastInst->getOperand(0).getMBB();
271 I->eraseFromParent();
275 // Otherwise, can't handle this.
280 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
281 int BOpc = Hexagon::JMP;
282 int BccOpc = Hexagon::JMP_c;
283 int BccOpcNot = Hexagon::JMP_cNot;
285 MachineBasicBlock::iterator I = MBB.end();
286 if (I == MBB.begin()) return 0;
288 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
289 I->getOpcode() != BccOpcNot)
292 // Remove the branch.
293 I->eraseFromParent();
297 if (I == MBB.begin()) return 1;
299 if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
302 // Remove the branch.
303 I->eraseFromParent();
308 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
309 MachineBasicBlock::iterator I, DebugLoc DL,
310 unsigned DestReg, unsigned SrcReg,
311 bool KillSrc) const {
312 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
313 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
316 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
317 BuildMI(MBB, I, DL, get(Hexagon::TFR_64), DestReg).addReg(SrcReg);
320 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
321 // Map Pd = Ps to Pd = or(Ps, Ps).
322 BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
323 DestReg).addReg(SrcReg).addReg(SrcReg);
326 if (Hexagon::DoubleRegsRegClass.contains(DestReg, SrcReg)) {
327 // We can have an overlap between single and double reg: r1:0 = r0.
328 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
330 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
331 Hexagon::subreg_hireg))).addImm(0);
333 // r1:0 = r1 or no overlap.
334 BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
335 Hexagon::subreg_loreg))).addReg(SrcReg);
336 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
337 Hexagon::subreg_hireg))).addImm(0);
341 if (Hexagon::CRRegsRegClass.contains(DestReg, SrcReg)) {
342 BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
346 llvm_unreachable("Unimplemented");
350 void HexagonInstrInfo::
351 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
352 unsigned SrcReg, bool isKill, int FI,
353 const TargetRegisterClass *RC,
354 const TargetRegisterInfo *TRI) const {
356 DebugLoc DL = MBB.findDebugLoc(I);
357 MachineFunction &MF = *MBB.getParent();
358 MachineFrameInfo &MFI = *MF.getFrameInfo();
359 unsigned Align = MFI.getObjectAlignment(FI);
361 MachineMemOperand *MMO =
362 MF.getMachineMemOperand(
363 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
364 MachineMemOperand::MOStore,
365 MFI.getObjectSize(FI),
368 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
369 BuildMI(MBB, I, DL, get(Hexagon::STriw_indexed))
370 .addFrameIndex(FI).addImm(0)
371 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
372 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
373 BuildMI(MBB, I, DL, get(Hexagon::STrid))
374 .addFrameIndex(FI).addImm(0)
375 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
376 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
377 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
378 .addFrameIndex(FI).addImm(0)
379 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
381 llvm_unreachable("Unimplemented");
386 void HexagonInstrInfo::storeRegToAddr(
387 MachineFunction &MF, unsigned SrcReg,
389 SmallVectorImpl<MachineOperand> &Addr,
390 const TargetRegisterClass *RC,
391 SmallVectorImpl<MachineInstr*> &NewMIs) const
393 llvm_unreachable("Unimplemented");
397 void HexagonInstrInfo::
398 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
399 unsigned DestReg, int FI,
400 const TargetRegisterClass *RC,
401 const TargetRegisterInfo *TRI) const {
402 DebugLoc DL = MBB.findDebugLoc(I);
403 MachineFunction &MF = *MBB.getParent();
404 MachineFrameInfo &MFI = *MF.getFrameInfo();
405 unsigned Align = MFI.getObjectAlignment(FI);
407 MachineMemOperand *MMO =
408 MF.getMachineMemOperand(
409 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
410 MachineMemOperand::MOLoad,
411 MFI.getObjectSize(FI),
413 if (RC == &Hexagon::IntRegsRegClass) {
414 BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)
415 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
416 } else if (RC == &Hexagon::DoubleRegsRegClass) {
417 BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
418 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
419 } else if (RC == &Hexagon::PredRegsRegClass) {
420 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
421 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
423 llvm_unreachable("Can't store this register to stack slot");
428 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
429 SmallVectorImpl<MachineOperand> &Addr,
430 const TargetRegisterClass *RC,
431 SmallVectorImpl<MachineInstr*> &NewMIs) const {
432 llvm_unreachable("Unimplemented");
436 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
438 const SmallVectorImpl<unsigned> &Ops,
440 // Hexagon_TODO: Implement.
445 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
447 MachineRegisterInfo &RegInfo = MF->getRegInfo();
448 const TargetRegisterClass *TRC;
450 TRC = &Hexagon::PredRegsRegClass;
451 } else if (VT == MVT::i32 || VT == MVT::f32) {
452 TRC = &Hexagon::IntRegsRegClass;
453 } else if (VT == MVT::i64 || VT == MVT::f64) {
454 TRC = &Hexagon::DoubleRegsRegClass;
456 llvm_unreachable("Cannot handle this register class");
459 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
463 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
464 switch(MI->getOpcode()) {
465 default: return false;
467 case Hexagon::JMP_EQriPt_nv_V4:
468 case Hexagon::JMP_EQriPnt_nv_V4:
469 case Hexagon::JMP_EQriNotPt_nv_V4:
470 case Hexagon::JMP_EQriNotPnt_nv_V4:
472 // JMP_EQri - with -1
473 case Hexagon::JMP_EQriPtneg_nv_V4:
474 case Hexagon::JMP_EQriPntneg_nv_V4:
475 case Hexagon::JMP_EQriNotPtneg_nv_V4:
476 case Hexagon::JMP_EQriNotPntneg_nv_V4:
479 case Hexagon::JMP_EQrrPt_nv_V4:
480 case Hexagon::JMP_EQrrPnt_nv_V4:
481 case Hexagon::JMP_EQrrNotPt_nv_V4:
482 case Hexagon::JMP_EQrrNotPnt_nv_V4:
485 case Hexagon::JMP_GTriPt_nv_V4:
486 case Hexagon::JMP_GTriPnt_nv_V4:
487 case Hexagon::JMP_GTriNotPt_nv_V4:
488 case Hexagon::JMP_GTriNotPnt_nv_V4:
490 // JMP_GTri - with -1
491 case Hexagon::JMP_GTriPtneg_nv_V4:
492 case Hexagon::JMP_GTriPntneg_nv_V4:
493 case Hexagon::JMP_GTriNotPtneg_nv_V4:
494 case Hexagon::JMP_GTriNotPntneg_nv_V4:
497 case Hexagon::JMP_GTrrPt_nv_V4:
498 case Hexagon::JMP_GTrrPnt_nv_V4:
499 case Hexagon::JMP_GTrrNotPt_nv_V4:
500 case Hexagon::JMP_GTrrNotPnt_nv_V4:
503 case Hexagon::JMP_GTrrdnPt_nv_V4:
504 case Hexagon::JMP_GTrrdnPnt_nv_V4:
505 case Hexagon::JMP_GTrrdnNotPt_nv_V4:
506 case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
509 case Hexagon::JMP_GTUriPt_nv_V4:
510 case Hexagon::JMP_GTUriPnt_nv_V4:
511 case Hexagon::JMP_GTUriNotPt_nv_V4:
512 case Hexagon::JMP_GTUriNotPnt_nv_V4:
515 case Hexagon::JMP_GTUrrPt_nv_V4:
516 case Hexagon::JMP_GTUrrPnt_nv_V4:
517 case Hexagon::JMP_GTUrrNotPt_nv_V4:
518 case Hexagon::JMP_GTUrrNotPnt_nv_V4:
521 case Hexagon::JMP_GTUrrdnPt_nv_V4:
522 case Hexagon::JMP_GTUrrdnPnt_nv_V4:
523 case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
524 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
527 case Hexagon::TFR_FI:
532 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
533 switch(MI->getOpcode()) {
534 default: return false;
536 case Hexagon::JMP_EQriPt_ie_nv_V4:
537 case Hexagon::JMP_EQriPnt_ie_nv_V4:
538 case Hexagon::JMP_EQriNotPt_ie_nv_V4:
539 case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
541 // JMP_EQri - with -1
542 case Hexagon::JMP_EQriPtneg_ie_nv_V4:
543 case Hexagon::JMP_EQriPntneg_ie_nv_V4:
544 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
545 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
548 case Hexagon::JMP_EQrrPt_ie_nv_V4:
549 case Hexagon::JMP_EQrrPnt_ie_nv_V4:
550 case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
551 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
554 case Hexagon::JMP_GTriPt_ie_nv_V4:
555 case Hexagon::JMP_GTriPnt_ie_nv_V4:
556 case Hexagon::JMP_GTriNotPt_ie_nv_V4:
557 case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
559 // JMP_GTri - with -1
560 case Hexagon::JMP_GTriPtneg_ie_nv_V4:
561 case Hexagon::JMP_GTriPntneg_ie_nv_V4:
562 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
563 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
566 case Hexagon::JMP_GTrrPt_ie_nv_V4:
567 case Hexagon::JMP_GTrrPnt_ie_nv_V4:
568 case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
569 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
572 case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
573 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
574 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
575 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
578 case Hexagon::JMP_GTUriPt_ie_nv_V4:
579 case Hexagon::JMP_GTUriPnt_ie_nv_V4:
580 case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
581 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
584 case Hexagon::JMP_GTUrrPt_ie_nv_V4:
585 case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
586 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
587 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
590 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
591 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
592 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
593 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
595 // V4 absolute set addressing.
596 case Hexagon::LDrid_abs_setimm_V4:
597 case Hexagon::LDriw_abs_setimm_V4:
598 case Hexagon::LDrih_abs_setimm_V4:
599 case Hexagon::LDrib_abs_setimm_V4:
600 case Hexagon::LDriuh_abs_setimm_V4:
601 case Hexagon::LDriub_abs_setimm_V4:
603 case Hexagon::STrid_abs_setimm_V4:
604 case Hexagon::STrib_abs_setimm_V4:
605 case Hexagon::STrih_abs_setimm_V4:
606 case Hexagon::STriw_abs_setimm_V4:
608 // V4 global address load.
609 case Hexagon::LDrid_GP_cPt_V4 :
610 case Hexagon::LDrid_GP_cNotPt_V4 :
611 case Hexagon::LDrid_GP_cdnPt_V4 :
612 case Hexagon::LDrid_GP_cdnNotPt_V4 :
613 case Hexagon::LDrib_GP_cPt_V4 :
614 case Hexagon::LDrib_GP_cNotPt_V4 :
615 case Hexagon::LDrib_GP_cdnPt_V4 :
616 case Hexagon::LDrib_GP_cdnNotPt_V4 :
617 case Hexagon::LDriub_GP_cPt_V4 :
618 case Hexagon::LDriub_GP_cNotPt_V4 :
619 case Hexagon::LDriub_GP_cdnPt_V4 :
620 case Hexagon::LDriub_GP_cdnNotPt_V4 :
621 case Hexagon::LDrih_GP_cPt_V4 :
622 case Hexagon::LDrih_GP_cNotPt_V4 :
623 case Hexagon::LDrih_GP_cdnPt_V4 :
624 case Hexagon::LDrih_GP_cdnNotPt_V4 :
625 case Hexagon::LDriuh_GP_cPt_V4 :
626 case Hexagon::LDriuh_GP_cNotPt_V4 :
627 case Hexagon::LDriuh_GP_cdnPt_V4 :
628 case Hexagon::LDriuh_GP_cdnNotPt_V4 :
629 case Hexagon::LDriw_GP_cPt_V4 :
630 case Hexagon::LDriw_GP_cNotPt_V4 :
631 case Hexagon::LDriw_GP_cdnPt_V4 :
632 case Hexagon::LDriw_GP_cdnNotPt_V4 :
633 case Hexagon::LDd_GP_cPt_V4 :
634 case Hexagon::LDd_GP_cNotPt_V4 :
635 case Hexagon::LDd_GP_cdnPt_V4 :
636 case Hexagon::LDd_GP_cdnNotPt_V4 :
637 case Hexagon::LDb_GP_cPt_V4 :
638 case Hexagon::LDb_GP_cNotPt_V4 :
639 case Hexagon::LDb_GP_cdnPt_V4 :
640 case Hexagon::LDb_GP_cdnNotPt_V4 :
641 case Hexagon::LDub_GP_cPt_V4 :
642 case Hexagon::LDub_GP_cNotPt_V4 :
643 case Hexagon::LDub_GP_cdnPt_V4 :
644 case Hexagon::LDub_GP_cdnNotPt_V4 :
645 case Hexagon::LDh_GP_cPt_V4 :
646 case Hexagon::LDh_GP_cNotPt_V4 :
647 case Hexagon::LDh_GP_cdnPt_V4 :
648 case Hexagon::LDh_GP_cdnNotPt_V4 :
649 case Hexagon::LDuh_GP_cPt_V4 :
650 case Hexagon::LDuh_GP_cNotPt_V4 :
651 case Hexagon::LDuh_GP_cdnPt_V4 :
652 case Hexagon::LDuh_GP_cdnNotPt_V4 :
653 case Hexagon::LDw_GP_cPt_V4 :
654 case Hexagon::LDw_GP_cNotPt_V4 :
655 case Hexagon::LDw_GP_cdnPt_V4 :
656 case Hexagon::LDw_GP_cdnNotPt_V4 :
658 // V4 global address store.
659 case Hexagon::STrid_GP_cPt_V4 :
660 case Hexagon::STrid_GP_cNotPt_V4 :
661 case Hexagon::STrid_GP_cdnPt_V4 :
662 case Hexagon::STrid_GP_cdnNotPt_V4 :
663 case Hexagon::STrib_GP_cPt_V4 :
664 case Hexagon::STrib_GP_cNotPt_V4 :
665 case Hexagon::STrib_GP_cdnPt_V4 :
666 case Hexagon::STrib_GP_cdnNotPt_V4 :
667 case Hexagon::STrih_GP_cPt_V4 :
668 case Hexagon::STrih_GP_cNotPt_V4 :
669 case Hexagon::STrih_GP_cdnPt_V4 :
670 case Hexagon::STrih_GP_cdnNotPt_V4 :
671 case Hexagon::STriw_GP_cPt_V4 :
672 case Hexagon::STriw_GP_cNotPt_V4 :
673 case Hexagon::STriw_GP_cdnPt_V4 :
674 case Hexagon::STriw_GP_cdnNotPt_V4 :
675 case Hexagon::STd_GP_cPt_V4 :
676 case Hexagon::STd_GP_cNotPt_V4 :
677 case Hexagon::STd_GP_cdnPt_V4 :
678 case Hexagon::STd_GP_cdnNotPt_V4 :
679 case Hexagon::STb_GP_cPt_V4 :
680 case Hexagon::STb_GP_cNotPt_V4 :
681 case Hexagon::STb_GP_cdnPt_V4 :
682 case Hexagon::STb_GP_cdnNotPt_V4 :
683 case Hexagon::STh_GP_cPt_V4 :
684 case Hexagon::STh_GP_cNotPt_V4 :
685 case Hexagon::STh_GP_cdnPt_V4 :
686 case Hexagon::STh_GP_cdnNotPt_V4 :
687 case Hexagon::STw_GP_cPt_V4 :
688 case Hexagon::STw_GP_cNotPt_V4 :
689 case Hexagon::STw_GP_cdnPt_V4 :
690 case Hexagon::STw_GP_cdnNotPt_V4 :
692 // V4 predicated global address new value store.
693 case Hexagon::STrib_GP_cPt_nv_V4 :
694 case Hexagon::STrib_GP_cNotPt_nv_V4 :
695 case Hexagon::STrib_GP_cdnPt_nv_V4 :
696 case Hexagon::STrib_GP_cdnNotPt_nv_V4 :
697 case Hexagon::STrih_GP_cPt_nv_V4 :
698 case Hexagon::STrih_GP_cNotPt_nv_V4 :
699 case Hexagon::STrih_GP_cdnPt_nv_V4 :
700 case Hexagon::STrih_GP_cdnNotPt_nv_V4 :
701 case Hexagon::STriw_GP_cPt_nv_V4 :
702 case Hexagon::STriw_GP_cNotPt_nv_V4 :
703 case Hexagon::STriw_GP_cdnPt_nv_V4 :
704 case Hexagon::STriw_GP_cdnNotPt_nv_V4 :
705 case Hexagon::STb_GP_cPt_nv_V4 :
706 case Hexagon::STb_GP_cNotPt_nv_V4 :
707 case Hexagon::STb_GP_cdnPt_nv_V4 :
708 case Hexagon::STb_GP_cdnNotPt_nv_V4 :
709 case Hexagon::STh_GP_cPt_nv_V4 :
710 case Hexagon::STh_GP_cNotPt_nv_V4 :
711 case Hexagon::STh_GP_cdnPt_nv_V4 :
712 case Hexagon::STh_GP_cdnNotPt_nv_V4 :
713 case Hexagon::STw_GP_cPt_nv_V4 :
714 case Hexagon::STw_GP_cNotPt_nv_V4 :
715 case Hexagon::STw_GP_cdnPt_nv_V4 :
716 case Hexagon::STw_GP_cdnNotPt_nv_V4 :
719 case Hexagon::TFR_FI_immext_V4:
722 case Hexagon::TFRI_f:
723 case Hexagon::TFRI_cPt_f:
724 case Hexagon::TFRI_cNotPt_f:
725 case Hexagon::CONST64_Float_Real:
730 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
731 switch (MI->getOpcode()) {
732 default: return false;
734 case Hexagon::JMP_EQriPt_nv_V4:
735 case Hexagon::JMP_EQriPnt_nv_V4:
736 case Hexagon::JMP_EQriNotPt_nv_V4:
737 case Hexagon::JMP_EQriNotPnt_nv_V4:
738 case Hexagon::JMP_EQriPt_ie_nv_V4:
739 case Hexagon::JMP_EQriPnt_ie_nv_V4:
740 case Hexagon::JMP_EQriNotPt_ie_nv_V4:
741 case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
743 // JMP_EQri - with -1
744 case Hexagon::JMP_EQriPtneg_nv_V4:
745 case Hexagon::JMP_EQriPntneg_nv_V4:
746 case Hexagon::JMP_EQriNotPtneg_nv_V4:
747 case Hexagon::JMP_EQriNotPntneg_nv_V4:
748 case Hexagon::JMP_EQriPtneg_ie_nv_V4:
749 case Hexagon::JMP_EQriPntneg_ie_nv_V4:
750 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
751 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
754 case Hexagon::JMP_EQrrPt_nv_V4:
755 case Hexagon::JMP_EQrrPnt_nv_V4:
756 case Hexagon::JMP_EQrrNotPt_nv_V4:
757 case Hexagon::JMP_EQrrNotPnt_nv_V4:
758 case Hexagon::JMP_EQrrPt_ie_nv_V4:
759 case Hexagon::JMP_EQrrPnt_ie_nv_V4:
760 case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
761 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
764 case Hexagon::JMP_GTriPt_nv_V4:
765 case Hexagon::JMP_GTriPnt_nv_V4:
766 case Hexagon::JMP_GTriNotPt_nv_V4:
767 case Hexagon::JMP_GTriNotPnt_nv_V4:
768 case Hexagon::JMP_GTriPt_ie_nv_V4:
769 case Hexagon::JMP_GTriPnt_ie_nv_V4:
770 case Hexagon::JMP_GTriNotPt_ie_nv_V4:
771 case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
773 // JMP_GTri - with -1
774 case Hexagon::JMP_GTriPtneg_nv_V4:
775 case Hexagon::JMP_GTriPntneg_nv_V4:
776 case Hexagon::JMP_GTriNotPtneg_nv_V4:
777 case Hexagon::JMP_GTriNotPntneg_nv_V4:
778 case Hexagon::JMP_GTriPtneg_ie_nv_V4:
779 case Hexagon::JMP_GTriPntneg_ie_nv_V4:
780 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
781 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
784 case Hexagon::JMP_GTrrPt_nv_V4:
785 case Hexagon::JMP_GTrrPnt_nv_V4:
786 case Hexagon::JMP_GTrrNotPt_nv_V4:
787 case Hexagon::JMP_GTrrNotPnt_nv_V4:
788 case Hexagon::JMP_GTrrPt_ie_nv_V4:
789 case Hexagon::JMP_GTrrPnt_ie_nv_V4:
790 case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
791 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
794 case Hexagon::JMP_GTrrdnPt_nv_V4:
795 case Hexagon::JMP_GTrrdnPnt_nv_V4:
796 case Hexagon::JMP_GTrrdnNotPt_nv_V4:
797 case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
798 case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
799 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
800 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
801 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
804 case Hexagon::JMP_GTUriPt_nv_V4:
805 case Hexagon::JMP_GTUriPnt_nv_V4:
806 case Hexagon::JMP_GTUriNotPt_nv_V4:
807 case Hexagon::JMP_GTUriNotPnt_nv_V4:
808 case Hexagon::JMP_GTUriPt_ie_nv_V4:
809 case Hexagon::JMP_GTUriPnt_ie_nv_V4:
810 case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
811 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
814 case Hexagon::JMP_GTUrrPt_nv_V4:
815 case Hexagon::JMP_GTUrrPnt_nv_V4:
816 case Hexagon::JMP_GTUrrNotPt_nv_V4:
817 case Hexagon::JMP_GTUrrNotPnt_nv_V4:
818 case Hexagon::JMP_GTUrrPt_ie_nv_V4:
819 case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
820 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
821 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
824 case Hexagon::JMP_GTUrrdnPt_nv_V4:
825 case Hexagon::JMP_GTUrrdnPnt_nv_V4:
826 case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
827 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
828 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
829 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
830 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
831 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
836 unsigned HexagonInstrInfo::getImmExtForm(const MachineInstr* MI) const {
837 switch(MI->getOpcode()) {
838 default: llvm_unreachable("Unknown type of instruction.");
840 case Hexagon::JMP_EQriPt_nv_V4:
841 return Hexagon::JMP_EQriPt_ie_nv_V4;
842 case Hexagon::JMP_EQriNotPt_nv_V4:
843 return Hexagon::JMP_EQriNotPt_ie_nv_V4;
844 case Hexagon::JMP_EQriPnt_nv_V4:
845 return Hexagon::JMP_EQriPnt_ie_nv_V4;
846 case Hexagon::JMP_EQriNotPnt_nv_V4:
847 return Hexagon::JMP_EQriNotPnt_ie_nv_V4;
849 // JMP_EQri -- with -1
850 case Hexagon::JMP_EQriPtneg_nv_V4:
851 return Hexagon::JMP_EQriPtneg_ie_nv_V4;
852 case Hexagon::JMP_EQriNotPtneg_nv_V4:
853 return Hexagon::JMP_EQriNotPtneg_ie_nv_V4;
854 case Hexagon::JMP_EQriPntneg_nv_V4:
855 return Hexagon::JMP_EQriPntneg_ie_nv_V4;
856 case Hexagon::JMP_EQriNotPntneg_nv_V4:
857 return Hexagon::JMP_EQriNotPntneg_ie_nv_V4;
860 case Hexagon::JMP_EQrrPt_nv_V4:
861 return Hexagon::JMP_EQrrPt_ie_nv_V4;
862 case Hexagon::JMP_EQrrNotPt_nv_V4:
863 return Hexagon::JMP_EQrrNotPt_ie_nv_V4;
864 case Hexagon::JMP_EQrrPnt_nv_V4:
865 return Hexagon::JMP_EQrrPnt_ie_nv_V4;
866 case Hexagon::JMP_EQrrNotPnt_nv_V4:
867 return Hexagon::JMP_EQrrNotPnt_ie_nv_V4;
870 case Hexagon::JMP_GTriPt_nv_V4:
871 return Hexagon::JMP_GTriPt_ie_nv_V4;
872 case Hexagon::JMP_GTriNotPt_nv_V4:
873 return Hexagon::JMP_GTriNotPt_ie_nv_V4;
874 case Hexagon::JMP_GTriPnt_nv_V4:
875 return Hexagon::JMP_GTriPnt_ie_nv_V4;
876 case Hexagon::JMP_GTriNotPnt_nv_V4:
877 return Hexagon::JMP_GTriNotPnt_ie_nv_V4;
879 // JMP_GTri -- with -1
880 case Hexagon::JMP_GTriPtneg_nv_V4:
881 return Hexagon::JMP_GTriPtneg_ie_nv_V4;
882 case Hexagon::JMP_GTriNotPtneg_nv_V4:
883 return Hexagon::JMP_GTriNotPtneg_ie_nv_V4;
884 case Hexagon::JMP_GTriPntneg_nv_V4:
885 return Hexagon::JMP_GTriPntneg_ie_nv_V4;
886 case Hexagon::JMP_GTriNotPntneg_nv_V4:
887 return Hexagon::JMP_GTriNotPntneg_ie_nv_V4;
890 case Hexagon::JMP_GTrrPt_nv_V4:
891 return Hexagon::JMP_GTrrPt_ie_nv_V4;
892 case Hexagon::JMP_GTrrNotPt_nv_V4:
893 return Hexagon::JMP_GTrrNotPt_ie_nv_V4;
894 case Hexagon::JMP_GTrrPnt_nv_V4:
895 return Hexagon::JMP_GTrrPnt_ie_nv_V4;
896 case Hexagon::JMP_GTrrNotPnt_nv_V4:
897 return Hexagon::JMP_GTrrNotPnt_ie_nv_V4;
900 case Hexagon::JMP_GTrrdnPt_nv_V4:
901 return Hexagon::JMP_GTrrdnPt_ie_nv_V4;
902 case Hexagon::JMP_GTrrdnNotPt_nv_V4:
903 return Hexagon::JMP_GTrrdnNotPt_ie_nv_V4;
904 case Hexagon::JMP_GTrrdnPnt_nv_V4:
905 return Hexagon::JMP_GTrrdnPnt_ie_nv_V4;
906 case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
907 return Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4;
910 case Hexagon::JMP_GTUriPt_nv_V4:
911 return Hexagon::JMP_GTUriPt_ie_nv_V4;
912 case Hexagon::JMP_GTUriNotPt_nv_V4:
913 return Hexagon::JMP_GTUriNotPt_ie_nv_V4;
914 case Hexagon::JMP_GTUriPnt_nv_V4:
915 return Hexagon::JMP_GTUriPnt_ie_nv_V4;
916 case Hexagon::JMP_GTUriNotPnt_nv_V4:
917 return Hexagon::JMP_GTUriNotPnt_ie_nv_V4;
920 case Hexagon::JMP_GTUrrPt_nv_V4:
921 return Hexagon::JMP_GTUrrPt_ie_nv_V4;
922 case Hexagon::JMP_GTUrrNotPt_nv_V4:
923 return Hexagon::JMP_GTUrrNotPt_ie_nv_V4;
924 case Hexagon::JMP_GTUrrPnt_nv_V4:
925 return Hexagon::JMP_GTUrrPnt_ie_nv_V4;
926 case Hexagon::JMP_GTUrrNotPnt_nv_V4:
927 return Hexagon::JMP_GTUrrNotPnt_ie_nv_V4;
930 case Hexagon::JMP_GTUrrdnPt_nv_V4:
931 return Hexagon::JMP_GTUrrdnPt_ie_nv_V4;
932 case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
933 return Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4;
934 case Hexagon::JMP_GTUrrdnPnt_nv_V4:
935 return Hexagon::JMP_GTUrrdnPnt_ie_nv_V4;
936 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
937 return Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4;
939 case Hexagon::TFR_FI:
940 return Hexagon::TFR_FI_immext_V4;
942 case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
943 case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
944 case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
945 case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
946 case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
947 case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
948 case Hexagon::MEMw_ORr_indexed_MEM_V4 :
949 case Hexagon::MEMw_ADDSUBi_MEM_V4 :
950 case Hexagon::MEMw_ADDi_MEM_V4 :
951 case Hexagon::MEMw_SUBi_MEM_V4 :
952 case Hexagon::MEMw_ADDr_MEM_V4 :
953 case Hexagon::MEMw_SUBr_MEM_V4 :
954 case Hexagon::MEMw_ANDr_MEM_V4 :
955 case Hexagon::MEMw_ORr_MEM_V4 :
956 case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
957 case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
958 case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
959 case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
960 case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
961 case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
962 case Hexagon::MEMh_ORr_indexed_MEM_V4 :
963 case Hexagon::MEMh_ADDSUBi_MEM_V4 :
964 case Hexagon::MEMh_ADDi_MEM_V4 :
965 case Hexagon::MEMh_SUBi_MEM_V4 :
966 case Hexagon::MEMh_ADDr_MEM_V4 :
967 case Hexagon::MEMh_SUBr_MEM_V4 :
968 case Hexagon::MEMh_ANDr_MEM_V4 :
969 case Hexagon::MEMh_ORr_MEM_V4 :
970 case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
971 case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
972 case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
973 case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
974 case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
975 case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
976 case Hexagon::MEMb_ORr_indexed_MEM_V4 :
977 case Hexagon::MEMb_ADDSUBi_MEM_V4 :
978 case Hexagon::MEMb_ADDi_MEM_V4 :
979 case Hexagon::MEMb_SUBi_MEM_V4 :
980 case Hexagon::MEMb_ADDr_MEM_V4 :
981 case Hexagon::MEMb_SUBr_MEM_V4 :
982 case Hexagon::MEMb_ANDr_MEM_V4 :
983 case Hexagon::MEMb_ORr_MEM_V4 :
984 llvm_unreachable("Needs implementing.");
988 unsigned HexagonInstrInfo::getNormalBranchForm(const MachineInstr* MI) const {
989 switch(MI->getOpcode()) {
990 default: llvm_unreachable("Unknown type of jump instruction.");
992 case Hexagon::JMP_EQriPt_ie_nv_V4:
993 return Hexagon::JMP_EQriPt_nv_V4;
994 case Hexagon::JMP_EQriNotPt_ie_nv_V4:
995 return Hexagon::JMP_EQriNotPt_nv_V4;
996 case Hexagon::JMP_EQriPnt_ie_nv_V4:
997 return Hexagon::JMP_EQriPnt_nv_V4;
998 case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
999 return Hexagon::JMP_EQriNotPnt_nv_V4;
1001 // JMP_EQri -- with -1
1002 case Hexagon::JMP_EQriPtneg_ie_nv_V4:
1003 return Hexagon::JMP_EQriPtneg_nv_V4;
1004 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
1005 return Hexagon::JMP_EQriNotPtneg_nv_V4;
1006 case Hexagon::JMP_EQriPntneg_ie_nv_V4:
1007 return Hexagon::JMP_EQriPntneg_nv_V4;
1008 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
1009 return Hexagon::JMP_EQriNotPntneg_nv_V4;
1012 case Hexagon::JMP_EQrrPt_ie_nv_V4:
1013 return Hexagon::JMP_EQrrPt_nv_V4;
1014 case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
1015 return Hexagon::JMP_EQrrNotPt_nv_V4;
1016 case Hexagon::JMP_EQrrPnt_ie_nv_V4:
1017 return Hexagon::JMP_EQrrPnt_nv_V4;
1018 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
1019 return Hexagon::JMP_EQrrNotPnt_nv_V4;
1022 case Hexagon::JMP_GTriPt_ie_nv_V4:
1023 return Hexagon::JMP_GTriPt_nv_V4;
1024 case Hexagon::JMP_GTriNotPt_ie_nv_V4:
1025 return Hexagon::JMP_GTriNotPt_nv_V4;
1026 case Hexagon::JMP_GTriPnt_ie_nv_V4:
1027 return Hexagon::JMP_GTriPnt_nv_V4;
1028 case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
1029 return Hexagon::JMP_GTriNotPnt_nv_V4;
1031 // JMP_GTri -- with -1
1032 case Hexagon::JMP_GTriPtneg_ie_nv_V4:
1033 return Hexagon::JMP_GTriPtneg_nv_V4;
1034 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
1035 return Hexagon::JMP_GTriNotPtneg_nv_V4;
1036 case Hexagon::JMP_GTriPntneg_ie_nv_V4:
1037 return Hexagon::JMP_GTriPntneg_nv_V4;
1038 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
1039 return Hexagon::JMP_GTriNotPntneg_nv_V4;
1042 case Hexagon::JMP_GTrrPt_ie_nv_V4:
1043 return Hexagon::JMP_GTrrPt_nv_V4;
1044 case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
1045 return Hexagon::JMP_GTrrNotPt_nv_V4;
1046 case Hexagon::JMP_GTrrPnt_ie_nv_V4:
1047 return Hexagon::JMP_GTrrPnt_nv_V4;
1048 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
1049 return Hexagon::JMP_GTrrNotPnt_nv_V4;
1052 case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
1053 return Hexagon::JMP_GTrrdnPt_nv_V4;
1054 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
1055 return Hexagon::JMP_GTrrdnNotPt_nv_V4;
1056 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
1057 return Hexagon::JMP_GTrrdnPnt_nv_V4;
1058 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
1059 return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
1062 case Hexagon::JMP_GTUriPt_ie_nv_V4:
1063 return Hexagon::JMP_GTUriPt_nv_V4;
1064 case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
1065 return Hexagon::JMP_GTUriNotPt_nv_V4;
1066 case Hexagon::JMP_GTUriPnt_ie_nv_V4:
1067 return Hexagon::JMP_GTUriPnt_nv_V4;
1068 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
1069 return Hexagon::JMP_GTUriNotPnt_nv_V4;
1072 case Hexagon::JMP_GTUrrPt_ie_nv_V4:
1073 return Hexagon::JMP_GTUrrPt_nv_V4;
1074 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
1075 return Hexagon::JMP_GTUrrNotPt_nv_V4;
1076 case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
1077 return Hexagon::JMP_GTUrrPnt_nv_V4;
1078 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
1079 return Hexagon::JMP_GTUrrNotPnt_nv_V4;
1082 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
1083 return Hexagon::JMP_GTUrrdnPt_nv_V4;
1084 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
1085 return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
1086 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
1087 return Hexagon::JMP_GTUrrdnPnt_nv_V4;
1088 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
1089 return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
1094 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
1095 switch (MI->getOpcode()) {
1096 default: return false;
1098 case Hexagon::STrib_nv_V4:
1099 case Hexagon::STrib_indexed_nv_V4:
1100 case Hexagon::STrib_indexed_shl_nv_V4:
1101 case Hexagon::STrib_shl_nv_V4:
1102 case Hexagon::STrib_GP_nv_V4:
1103 case Hexagon::STb_GP_nv_V4:
1104 case Hexagon::POST_STbri_nv_V4:
1105 case Hexagon::STrib_cPt_nv_V4:
1106 case Hexagon::STrib_cdnPt_nv_V4:
1107 case Hexagon::STrib_cNotPt_nv_V4:
1108 case Hexagon::STrib_cdnNotPt_nv_V4:
1109 case Hexagon::STrib_indexed_cPt_nv_V4:
1110 case Hexagon::STrib_indexed_cdnPt_nv_V4:
1111 case Hexagon::STrib_indexed_cNotPt_nv_V4:
1112 case Hexagon::STrib_indexed_cdnNotPt_nv_V4:
1113 case Hexagon::STrib_indexed_shl_cPt_nv_V4:
1114 case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
1115 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4:
1116 case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
1117 case Hexagon::POST_STbri_cPt_nv_V4:
1118 case Hexagon::POST_STbri_cdnPt_nv_V4:
1119 case Hexagon::POST_STbri_cNotPt_nv_V4:
1120 case Hexagon::POST_STbri_cdnNotPt_nv_V4:
1121 case Hexagon::STb_GP_cPt_nv_V4:
1122 case Hexagon::STb_GP_cNotPt_nv_V4:
1123 case Hexagon::STb_GP_cdnPt_nv_V4:
1124 case Hexagon::STb_GP_cdnNotPt_nv_V4:
1125 case Hexagon::STrib_GP_cPt_nv_V4:
1126 case Hexagon::STrib_GP_cNotPt_nv_V4:
1127 case Hexagon::STrib_GP_cdnPt_nv_V4:
1128 case Hexagon::STrib_GP_cdnNotPt_nv_V4:
1129 case Hexagon::STrib_abs_nv_V4:
1130 case Hexagon::STrib_abs_cPt_nv_V4:
1131 case Hexagon::STrib_abs_cdnPt_nv_V4:
1132 case Hexagon::STrib_abs_cNotPt_nv_V4:
1133 case Hexagon::STrib_abs_cdnNotPt_nv_V4:
1134 case Hexagon::STrib_imm_abs_nv_V4:
1135 case Hexagon::STrib_imm_abs_cPt_nv_V4:
1136 case Hexagon::STrib_imm_abs_cdnPt_nv_V4:
1137 case Hexagon::STrib_imm_abs_cNotPt_nv_V4:
1138 case Hexagon::STrib_imm_abs_cdnNotPt_nv_V4:
1141 case Hexagon::STrih_nv_V4:
1142 case Hexagon::STrih_indexed_nv_V4:
1143 case Hexagon::STrih_indexed_shl_nv_V4:
1144 case Hexagon::STrih_shl_nv_V4:
1145 case Hexagon::STrih_GP_nv_V4:
1146 case Hexagon::STh_GP_nv_V4:
1147 case Hexagon::POST_SThri_nv_V4:
1148 case Hexagon::STrih_cPt_nv_V4:
1149 case Hexagon::STrih_cdnPt_nv_V4:
1150 case Hexagon::STrih_cNotPt_nv_V4:
1151 case Hexagon::STrih_cdnNotPt_nv_V4:
1152 case Hexagon::STrih_indexed_cPt_nv_V4:
1153 case Hexagon::STrih_indexed_cdnPt_nv_V4:
1154 case Hexagon::STrih_indexed_cNotPt_nv_V4:
1155 case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
1156 case Hexagon::STrih_indexed_shl_cPt_nv_V4:
1157 case Hexagon::STrih_indexed_shl_cdnPt_nv_V4:
1158 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4:
1159 case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4:
1160 case Hexagon::POST_SThri_cPt_nv_V4:
1161 case Hexagon::POST_SThri_cdnPt_nv_V4:
1162 case Hexagon::POST_SThri_cNotPt_nv_V4:
1163 case Hexagon::POST_SThri_cdnNotPt_nv_V4:
1164 case Hexagon::STh_GP_cPt_nv_V4:
1165 case Hexagon::STh_GP_cNotPt_nv_V4:
1166 case Hexagon::STh_GP_cdnPt_nv_V4:
1167 case Hexagon::STh_GP_cdnNotPt_nv_V4:
1168 case Hexagon::STrih_GP_cPt_nv_V4:
1169 case Hexagon::STrih_GP_cNotPt_nv_V4:
1170 case Hexagon::STrih_GP_cdnPt_nv_V4:
1171 case Hexagon::STrih_GP_cdnNotPt_nv_V4:
1172 case Hexagon::STrih_abs_nv_V4:
1173 case Hexagon::STrih_abs_cPt_nv_V4:
1174 case Hexagon::STrih_abs_cdnPt_nv_V4:
1175 case Hexagon::STrih_abs_cNotPt_nv_V4:
1176 case Hexagon::STrih_abs_cdnNotPt_nv_V4:
1177 case Hexagon::STrih_imm_abs_nv_V4:
1178 case Hexagon::STrih_imm_abs_cPt_nv_V4:
1179 case Hexagon::STrih_imm_abs_cdnPt_nv_V4:
1180 case Hexagon::STrih_imm_abs_cNotPt_nv_V4:
1181 case Hexagon::STrih_imm_abs_cdnNotPt_nv_V4:
1184 case Hexagon::STriw_nv_V4:
1185 case Hexagon::STriw_indexed_nv_V4:
1186 case Hexagon::STriw_indexed_shl_nv_V4:
1187 case Hexagon::STriw_shl_nv_V4:
1188 case Hexagon::STriw_GP_nv_V4:
1189 case Hexagon::STw_GP_nv_V4:
1190 case Hexagon::POST_STwri_nv_V4:
1191 case Hexagon::STriw_cPt_nv_V4:
1192 case Hexagon::STriw_cdnPt_nv_V4:
1193 case Hexagon::STriw_cNotPt_nv_V4:
1194 case Hexagon::STriw_cdnNotPt_nv_V4:
1195 case Hexagon::STriw_indexed_cPt_nv_V4:
1196 case Hexagon::STriw_indexed_cdnPt_nv_V4:
1197 case Hexagon::STriw_indexed_cNotPt_nv_V4:
1198 case Hexagon::STriw_indexed_cdnNotPt_nv_V4:
1199 case Hexagon::STriw_indexed_shl_cPt_nv_V4:
1200 case Hexagon::STriw_indexed_shl_cdnPt_nv_V4:
1201 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4:
1202 case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4:
1203 case Hexagon::POST_STwri_cPt_nv_V4:
1204 case Hexagon::POST_STwri_cdnPt_nv_V4:
1205 case Hexagon::POST_STwri_cNotPt_nv_V4:
1206 case Hexagon::POST_STwri_cdnNotPt_nv_V4:
1207 case Hexagon::STw_GP_cPt_nv_V4:
1208 case Hexagon::STw_GP_cNotPt_nv_V4:
1209 case Hexagon::STw_GP_cdnPt_nv_V4:
1210 case Hexagon::STw_GP_cdnNotPt_nv_V4:
1211 case Hexagon::STriw_GP_cPt_nv_V4:
1212 case Hexagon::STriw_GP_cNotPt_nv_V4:
1213 case Hexagon::STriw_GP_cdnPt_nv_V4:
1214 case Hexagon::STriw_GP_cdnNotPt_nv_V4:
1215 case Hexagon::STriw_abs_nv_V4:
1216 case Hexagon::STriw_abs_cPt_nv_V4:
1217 case Hexagon::STriw_abs_cdnPt_nv_V4:
1218 case Hexagon::STriw_abs_cNotPt_nv_V4:
1219 case Hexagon::STriw_abs_cdnNotPt_nv_V4:
1220 case Hexagon::STriw_imm_abs_nv_V4:
1221 case Hexagon::STriw_imm_abs_cPt_nv_V4:
1222 case Hexagon::STriw_imm_abs_cdnPt_nv_V4:
1223 case Hexagon::STriw_imm_abs_cNotPt_nv_V4:
1224 case Hexagon::STriw_imm_abs_cdnNotPt_nv_V4:
1229 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
1230 switch (MI->getOpcode())
1232 default: return false;
1234 case Hexagon::POST_LDrib:
1235 case Hexagon::POST_LDrib_cPt:
1236 case Hexagon::POST_LDrib_cNotPt:
1237 case Hexagon::POST_LDrib_cdnPt_V4:
1238 case Hexagon::POST_LDrib_cdnNotPt_V4:
1240 // Load unsigned byte
1241 case Hexagon::POST_LDriub:
1242 case Hexagon::POST_LDriub_cPt:
1243 case Hexagon::POST_LDriub_cNotPt:
1244 case Hexagon::POST_LDriub_cdnPt_V4:
1245 case Hexagon::POST_LDriub_cdnNotPt_V4:
1248 case Hexagon::POST_LDrih:
1249 case Hexagon::POST_LDrih_cPt:
1250 case Hexagon::POST_LDrih_cNotPt:
1251 case Hexagon::POST_LDrih_cdnPt_V4:
1252 case Hexagon::POST_LDrih_cdnNotPt_V4:
1254 // Load unsigned halfword
1255 case Hexagon::POST_LDriuh:
1256 case Hexagon::POST_LDriuh_cPt:
1257 case Hexagon::POST_LDriuh_cNotPt:
1258 case Hexagon::POST_LDriuh_cdnPt_V4:
1259 case Hexagon::POST_LDriuh_cdnNotPt_V4:
1262 case Hexagon::POST_LDriw:
1263 case Hexagon::POST_LDriw_cPt:
1264 case Hexagon::POST_LDriw_cNotPt:
1265 case Hexagon::POST_LDriw_cdnPt_V4:
1266 case Hexagon::POST_LDriw_cdnNotPt_V4:
1269 case Hexagon::POST_LDrid:
1270 case Hexagon::POST_LDrid_cPt:
1271 case Hexagon::POST_LDrid_cNotPt:
1272 case Hexagon::POST_LDrid_cdnPt_V4:
1273 case Hexagon::POST_LDrid_cdnNotPt_V4:
1276 case Hexagon::POST_STbri:
1277 case Hexagon::POST_STbri_cPt:
1278 case Hexagon::POST_STbri_cNotPt:
1279 case Hexagon::POST_STbri_cdnPt_V4:
1280 case Hexagon::POST_STbri_cdnNotPt_V4:
1283 case Hexagon::POST_SThri:
1284 case Hexagon::POST_SThri_cPt:
1285 case Hexagon::POST_SThri_cNotPt:
1286 case Hexagon::POST_SThri_cdnPt_V4:
1287 case Hexagon::POST_SThri_cdnNotPt_V4:
1290 case Hexagon::POST_STwri:
1291 case Hexagon::POST_STwri_cPt:
1292 case Hexagon::POST_STwri_cNotPt:
1293 case Hexagon::POST_STwri_cdnPt_V4:
1294 case Hexagon::POST_STwri_cdnNotPt_V4:
1296 // Store double word
1297 case Hexagon::POST_STdri:
1298 case Hexagon::POST_STdri_cPt:
1299 case Hexagon::POST_STdri_cNotPt:
1300 case Hexagon::POST_STdri_cdnPt_V4:
1301 case Hexagon::POST_STdri_cdnNotPt_V4:
1306 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
1307 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
1310 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
1311 bool isPred = MI->getDesc().isPredicable();
1316 const int Opc = MI->getOpcode();
1317 int NumOperands = MI->getNumOperands();
1319 // Keep a flag for upto 4 operands in the instructions, to indicate if
1320 // that operand has been constant extended.
1321 bool OpCExtended[4];
1322 if (NumOperands > 4)
1325 for (int i=0; i<NumOperands; i++)
1326 OpCExtended[i] = (HexagonConstExt::isOperandExtended(Opc, 1) &&
1327 isConstExtended(MI));
1331 // Return true if MI is constant extended as predicated form will also be
1332 // extended so immediate value doesn't have to fit within range.
1333 return OpCExtended[1] || isInt<12>(MI->getOperand(1).getImm());
1335 case Hexagon::STrid:
1336 case Hexagon::STrid_indexed:
1337 return OpCExtended[1] || isShiftedUInt<6,3>(MI->getOperand(1).getImm());
1339 case Hexagon::STriw:
1340 case Hexagon::STriw_indexed:
1341 case Hexagon::STriw_nv_V4:
1342 return OpCExtended[1] || isShiftedUInt<6,2>(MI->getOperand(1).getImm());
1344 case Hexagon::STrih:
1345 case Hexagon::STrih_indexed:
1346 case Hexagon::STrih_nv_V4:
1347 return OpCExtended[1] || isShiftedUInt<6,1>(MI->getOperand(1).getImm());
1349 case Hexagon::STrib:
1350 case Hexagon::STrib_indexed:
1351 case Hexagon::STrib_nv_V4:
1352 return OpCExtended[1] || isUInt<6>(MI->getOperand(1).getImm());
1354 case Hexagon::LDrid:
1355 case Hexagon::LDrid_indexed:
1356 return OpCExtended[2] || isShiftedUInt<6,3>(MI->getOperand(2).getImm());
1358 case Hexagon::LDriw:
1359 case Hexagon::LDriw_indexed:
1360 return OpCExtended[2] || isShiftedUInt<6,2>(MI->getOperand(2).getImm());
1362 case Hexagon::LDrih:
1363 case Hexagon::LDriuh:
1364 case Hexagon::LDrih_indexed:
1365 case Hexagon::LDriuh_indexed:
1366 return OpCExtended[2] || isShiftedUInt<6,1>(MI->getOperand(2).getImm());
1368 case Hexagon::LDrib:
1369 case Hexagon::LDriub:
1370 case Hexagon::LDrib_indexed:
1371 case Hexagon::LDriub_indexed:
1372 return OpCExtended[2] || isUInt<6>(MI->getOperand(2).getImm());
1374 case Hexagon::POST_LDrid:
1375 return OpCExtended[3] || isShiftedInt<4,3>(MI->getOperand(3).getImm());
1377 case Hexagon::POST_LDriw:
1378 return OpCExtended[3] || isShiftedInt<4,2>(MI->getOperand(3).getImm());
1380 case Hexagon::POST_LDrih:
1381 case Hexagon::POST_LDriuh:
1382 return OpCExtended[3] || isShiftedInt<4,1>(MI->getOperand(3).getImm());
1384 case Hexagon::POST_LDrib:
1385 case Hexagon::POST_LDriub:
1386 return OpCExtended[3] || isInt<4>(MI->getOperand(3).getImm());
1388 case Hexagon::STrib_imm_V4:
1389 case Hexagon::STrih_imm_V4:
1390 case Hexagon::STriw_imm_V4:
1391 return ((OpCExtended[1] || isUInt<6>(MI->getOperand(1).getImm())) &&
1392 (OpCExtended[2] || isInt<6>(MI->getOperand(2).getImm())));
1394 case Hexagon::ADD_ri:
1395 return OpCExtended[2] || isInt<8>(MI->getOperand(2).getImm());
1403 return Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
1412 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
1414 default: llvm_unreachable("Unexpected predicated instruction");
1415 case Hexagon::TFR_cPt:
1416 return Hexagon::TFR_cNotPt;
1417 case Hexagon::TFR_cNotPt:
1418 return Hexagon::TFR_cPt;
1420 case Hexagon::TFRI_cPt:
1421 return Hexagon::TFRI_cNotPt;
1422 case Hexagon::TFRI_cNotPt:
1423 return Hexagon::TFRI_cPt;
1425 case Hexagon::JMP_c:
1426 return Hexagon::JMP_cNot;
1427 case Hexagon::JMP_cNot:
1428 return Hexagon::JMP_c;
1430 case Hexagon::ADD_ri_cPt:
1431 return Hexagon::ADD_ri_cNotPt;
1432 case Hexagon::ADD_ri_cNotPt:
1433 return Hexagon::ADD_ri_cPt;
1435 case Hexagon::ADD_rr_cPt:
1436 return Hexagon::ADD_rr_cNotPt;
1437 case Hexagon::ADD_rr_cNotPt:
1438 return Hexagon::ADD_rr_cPt;
1440 case Hexagon::XOR_rr_cPt:
1441 return Hexagon::XOR_rr_cNotPt;
1442 case Hexagon::XOR_rr_cNotPt:
1443 return Hexagon::XOR_rr_cPt;
1445 case Hexagon::AND_rr_cPt:
1446 return Hexagon::AND_rr_cNotPt;
1447 case Hexagon::AND_rr_cNotPt:
1448 return Hexagon::AND_rr_cPt;
1450 case Hexagon::OR_rr_cPt:
1451 return Hexagon::OR_rr_cNotPt;
1452 case Hexagon::OR_rr_cNotPt:
1453 return Hexagon::OR_rr_cPt;
1455 case Hexagon::SUB_rr_cPt:
1456 return Hexagon::SUB_rr_cNotPt;
1457 case Hexagon::SUB_rr_cNotPt:
1458 return Hexagon::SUB_rr_cPt;
1460 case Hexagon::COMBINE_rr_cPt:
1461 return Hexagon::COMBINE_rr_cNotPt;
1462 case Hexagon::COMBINE_rr_cNotPt:
1463 return Hexagon::COMBINE_rr_cPt;
1465 case Hexagon::ASLH_cPt_V4:
1466 return Hexagon::ASLH_cNotPt_V4;
1467 case Hexagon::ASLH_cNotPt_V4:
1468 return Hexagon::ASLH_cPt_V4;
1470 case Hexagon::ASRH_cPt_V4:
1471 return Hexagon::ASRH_cNotPt_V4;
1472 case Hexagon::ASRH_cNotPt_V4:
1473 return Hexagon::ASRH_cPt_V4;
1475 case Hexagon::SXTB_cPt_V4:
1476 return Hexagon::SXTB_cNotPt_V4;
1477 case Hexagon::SXTB_cNotPt_V4:
1478 return Hexagon::SXTB_cPt_V4;
1480 case Hexagon::SXTH_cPt_V4:
1481 return Hexagon::SXTH_cNotPt_V4;
1482 case Hexagon::SXTH_cNotPt_V4:
1483 return Hexagon::SXTH_cPt_V4;
1485 case Hexagon::ZXTB_cPt_V4:
1486 return Hexagon::ZXTB_cNotPt_V4;
1487 case Hexagon::ZXTB_cNotPt_V4:
1488 return Hexagon::ZXTB_cPt_V4;
1490 case Hexagon::ZXTH_cPt_V4:
1491 return Hexagon::ZXTH_cNotPt_V4;
1492 case Hexagon::ZXTH_cNotPt_V4:
1493 return Hexagon::ZXTH_cPt_V4;
1496 case Hexagon::JMPR_cPt:
1497 return Hexagon::JMPR_cNotPt;
1498 case Hexagon::JMPR_cNotPt:
1499 return Hexagon::JMPR_cPt;
1501 // V4 indexed+scaled load.
1502 case Hexagon::LDrid_indexed_cPt_V4:
1503 return Hexagon::LDrid_indexed_cNotPt_V4;
1504 case Hexagon::LDrid_indexed_cNotPt_V4:
1505 return Hexagon::LDrid_indexed_cPt_V4;
1507 case Hexagon::LDrid_indexed_shl_cPt_V4:
1508 return Hexagon::LDrid_indexed_shl_cNotPt_V4;
1509 case Hexagon::LDrid_indexed_shl_cNotPt_V4:
1510 return Hexagon::LDrid_indexed_shl_cPt_V4;
1512 case Hexagon::LDrib_indexed_cPt_V4:
1513 return Hexagon::LDrib_indexed_cNotPt_V4;
1514 case Hexagon::LDrib_indexed_cNotPt_V4:
1515 return Hexagon::LDrib_indexed_cPt_V4;
1517 case Hexagon::LDriub_indexed_cPt_V4:
1518 return Hexagon::LDriub_indexed_cNotPt_V4;
1519 case Hexagon::LDriub_indexed_cNotPt_V4:
1520 return Hexagon::LDriub_indexed_cPt_V4;
1522 case Hexagon::LDrib_indexed_shl_cPt_V4:
1523 return Hexagon::LDrib_indexed_shl_cNotPt_V4;
1524 case Hexagon::LDrib_indexed_shl_cNotPt_V4:
1525 return Hexagon::LDrib_indexed_shl_cPt_V4;
1527 case Hexagon::LDriub_indexed_shl_cPt_V4:
1528 return Hexagon::LDriub_indexed_shl_cNotPt_V4;
1529 case Hexagon::LDriub_indexed_shl_cNotPt_V4:
1530 return Hexagon::LDriub_indexed_shl_cPt_V4;
1532 case Hexagon::LDrih_indexed_cPt_V4:
1533 return Hexagon::LDrih_indexed_cNotPt_V4;
1534 case Hexagon::LDrih_indexed_cNotPt_V4:
1535 return Hexagon::LDrih_indexed_cPt_V4;
1537 case Hexagon::LDriuh_indexed_cPt_V4:
1538 return Hexagon::LDriuh_indexed_cNotPt_V4;
1539 case Hexagon::LDriuh_indexed_cNotPt_V4:
1540 return Hexagon::LDriuh_indexed_cPt_V4;
1542 case Hexagon::LDrih_indexed_shl_cPt_V4:
1543 return Hexagon::LDrih_indexed_shl_cNotPt_V4;
1544 case Hexagon::LDrih_indexed_shl_cNotPt_V4:
1545 return Hexagon::LDrih_indexed_shl_cPt_V4;
1547 case Hexagon::LDriuh_indexed_shl_cPt_V4:
1548 return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1549 case Hexagon::LDriuh_indexed_shl_cNotPt_V4:
1550 return Hexagon::LDriuh_indexed_shl_cPt_V4;
1552 case Hexagon::LDriw_indexed_cPt_V4:
1553 return Hexagon::LDriw_indexed_cNotPt_V4;
1554 case Hexagon::LDriw_indexed_cNotPt_V4:
1555 return Hexagon::LDriw_indexed_cPt_V4;
1557 case Hexagon::LDriw_indexed_shl_cPt_V4:
1558 return Hexagon::LDriw_indexed_shl_cNotPt_V4;
1559 case Hexagon::LDriw_indexed_shl_cNotPt_V4:
1560 return Hexagon::LDriw_indexed_shl_cPt_V4;
1563 case Hexagon::POST_STbri_cPt:
1564 return Hexagon::POST_STbri_cNotPt;
1565 case Hexagon::POST_STbri_cNotPt:
1566 return Hexagon::POST_STbri_cPt;
1568 case Hexagon::STrib_cPt:
1569 return Hexagon::STrib_cNotPt;
1570 case Hexagon::STrib_cNotPt:
1571 return Hexagon::STrib_cPt;
1573 case Hexagon::STrib_indexed_cPt:
1574 return Hexagon::STrib_indexed_cNotPt;
1575 case Hexagon::STrib_indexed_cNotPt:
1576 return Hexagon::STrib_indexed_cPt;
1578 case Hexagon::STrib_imm_cPt_V4:
1579 return Hexagon::STrib_imm_cNotPt_V4;
1580 case Hexagon::STrib_imm_cNotPt_V4:
1581 return Hexagon::STrib_imm_cPt_V4;
1583 case Hexagon::STrib_indexed_shl_cPt_V4:
1584 return Hexagon::STrib_indexed_shl_cNotPt_V4;
1585 case Hexagon::STrib_indexed_shl_cNotPt_V4:
1586 return Hexagon::STrib_indexed_shl_cPt_V4;
1589 case Hexagon::POST_SThri_cPt:
1590 return Hexagon::POST_SThri_cNotPt;
1591 case Hexagon::POST_SThri_cNotPt:
1592 return Hexagon::POST_SThri_cPt;
1594 case Hexagon::STrih_cPt:
1595 return Hexagon::STrih_cNotPt;
1596 case Hexagon::STrih_cNotPt:
1597 return Hexagon::STrih_cPt;
1599 case Hexagon::STrih_indexed_cPt:
1600 return Hexagon::STrih_indexed_cNotPt;
1601 case Hexagon::STrih_indexed_cNotPt:
1602 return Hexagon::STrih_indexed_cPt;
1604 case Hexagon::STrih_imm_cPt_V4:
1605 return Hexagon::STrih_imm_cNotPt_V4;
1606 case Hexagon::STrih_imm_cNotPt_V4:
1607 return Hexagon::STrih_imm_cPt_V4;
1609 case Hexagon::STrih_indexed_shl_cPt_V4:
1610 return Hexagon::STrih_indexed_shl_cNotPt_V4;
1611 case Hexagon::STrih_indexed_shl_cNotPt_V4:
1612 return Hexagon::STrih_indexed_shl_cPt_V4;
1615 case Hexagon::POST_STwri_cPt:
1616 return Hexagon::POST_STwri_cNotPt;
1617 case Hexagon::POST_STwri_cNotPt:
1618 return Hexagon::POST_STwri_cPt;
1620 case Hexagon::STriw_cPt:
1621 return Hexagon::STriw_cNotPt;
1622 case Hexagon::STriw_cNotPt:
1623 return Hexagon::STriw_cPt;
1625 case Hexagon::STriw_indexed_cPt:
1626 return Hexagon::STriw_indexed_cNotPt;
1627 case Hexagon::STriw_indexed_cNotPt:
1628 return Hexagon::STriw_indexed_cPt;
1630 case Hexagon::STriw_indexed_shl_cPt_V4:
1631 return Hexagon::STriw_indexed_shl_cNotPt_V4;
1632 case Hexagon::STriw_indexed_shl_cNotPt_V4:
1633 return Hexagon::STriw_indexed_shl_cPt_V4;
1635 case Hexagon::STriw_imm_cPt_V4:
1636 return Hexagon::STriw_imm_cNotPt_V4;
1637 case Hexagon::STriw_imm_cNotPt_V4:
1638 return Hexagon::STriw_imm_cPt_V4;
1641 case Hexagon::POST_STdri_cPt:
1642 return Hexagon::POST_STdri_cNotPt;
1643 case Hexagon::POST_STdri_cNotPt:
1644 return Hexagon::POST_STdri_cPt;
1646 case Hexagon::STrid_cPt:
1647 return Hexagon::STrid_cNotPt;
1648 case Hexagon::STrid_cNotPt:
1649 return Hexagon::STrid_cPt;
1651 case Hexagon::STrid_indexed_cPt:
1652 return Hexagon::STrid_indexed_cNotPt;
1653 case Hexagon::STrid_indexed_cNotPt:
1654 return Hexagon::STrid_indexed_cPt;
1656 case Hexagon::STrid_indexed_shl_cPt_V4:
1657 return Hexagon::STrid_indexed_shl_cNotPt_V4;
1658 case Hexagon::STrid_indexed_shl_cNotPt_V4:
1659 return Hexagon::STrid_indexed_shl_cPt_V4;
1661 // V4 Store to global address.
1662 case Hexagon::STd_GP_cPt_V4:
1663 return Hexagon::STd_GP_cNotPt_V4;
1664 case Hexagon::STd_GP_cNotPt_V4:
1665 return Hexagon::STd_GP_cPt_V4;
1667 case Hexagon::STb_GP_cPt_V4:
1668 return Hexagon::STb_GP_cNotPt_V4;
1669 case Hexagon::STb_GP_cNotPt_V4:
1670 return Hexagon::STb_GP_cPt_V4;
1672 case Hexagon::STh_GP_cPt_V4:
1673 return Hexagon::STh_GP_cNotPt_V4;
1674 case Hexagon::STh_GP_cNotPt_V4:
1675 return Hexagon::STh_GP_cPt_V4;
1677 case Hexagon::STw_GP_cPt_V4:
1678 return Hexagon::STw_GP_cNotPt_V4;
1679 case Hexagon::STw_GP_cNotPt_V4:
1680 return Hexagon::STw_GP_cPt_V4;
1682 case Hexagon::STrid_GP_cPt_V4:
1683 return Hexagon::STrid_GP_cNotPt_V4;
1684 case Hexagon::STrid_GP_cNotPt_V4:
1685 return Hexagon::STrid_GP_cPt_V4;
1687 case Hexagon::STrib_GP_cPt_V4:
1688 return Hexagon::STrib_GP_cNotPt_V4;
1689 case Hexagon::STrib_GP_cNotPt_V4:
1690 return Hexagon::STrib_GP_cPt_V4;
1692 case Hexagon::STrih_GP_cPt_V4:
1693 return Hexagon::STrih_GP_cNotPt_V4;
1694 case Hexagon::STrih_GP_cNotPt_V4:
1695 return Hexagon::STrih_GP_cPt_V4;
1697 case Hexagon::STriw_GP_cPt_V4:
1698 return Hexagon::STriw_GP_cNotPt_V4;
1699 case Hexagon::STriw_GP_cNotPt_V4:
1700 return Hexagon::STriw_GP_cPt_V4;
1703 case Hexagon::LDrid_cPt:
1704 return Hexagon::LDrid_cNotPt;
1705 case Hexagon::LDrid_cNotPt:
1706 return Hexagon::LDrid_cPt;
1708 case Hexagon::LDriw_cPt:
1709 return Hexagon::LDriw_cNotPt;
1710 case Hexagon::LDriw_cNotPt:
1711 return Hexagon::LDriw_cPt;
1713 case Hexagon::LDrih_cPt:
1714 return Hexagon::LDrih_cNotPt;
1715 case Hexagon::LDrih_cNotPt:
1716 return Hexagon::LDrih_cPt;
1718 case Hexagon::LDriuh_cPt:
1719 return Hexagon::LDriuh_cNotPt;
1720 case Hexagon::LDriuh_cNotPt:
1721 return Hexagon::LDriuh_cPt;
1723 case Hexagon::LDrib_cPt:
1724 return Hexagon::LDrib_cNotPt;
1725 case Hexagon::LDrib_cNotPt:
1726 return Hexagon::LDrib_cPt;
1728 case Hexagon::LDriub_cPt:
1729 return Hexagon::LDriub_cNotPt;
1730 case Hexagon::LDriub_cNotPt:
1731 return Hexagon::LDriub_cPt;
1734 case Hexagon::LDrid_indexed_cPt:
1735 return Hexagon::LDrid_indexed_cNotPt;
1736 case Hexagon::LDrid_indexed_cNotPt:
1737 return Hexagon::LDrid_indexed_cPt;
1739 case Hexagon::LDriw_indexed_cPt:
1740 return Hexagon::LDriw_indexed_cNotPt;
1741 case Hexagon::LDriw_indexed_cNotPt:
1742 return Hexagon::LDriw_indexed_cPt;
1744 case Hexagon::LDrih_indexed_cPt:
1745 return Hexagon::LDrih_indexed_cNotPt;
1746 case Hexagon::LDrih_indexed_cNotPt:
1747 return Hexagon::LDrih_indexed_cPt;
1749 case Hexagon::LDriuh_indexed_cPt:
1750 return Hexagon::LDriuh_indexed_cNotPt;
1751 case Hexagon::LDriuh_indexed_cNotPt:
1752 return Hexagon::LDriuh_indexed_cPt;
1754 case Hexagon::LDrib_indexed_cPt:
1755 return Hexagon::LDrib_indexed_cNotPt;
1756 case Hexagon::LDrib_indexed_cNotPt:
1757 return Hexagon::LDrib_indexed_cPt;
1759 case Hexagon::LDriub_indexed_cPt:
1760 return Hexagon::LDriub_indexed_cNotPt;
1761 case Hexagon::LDriub_indexed_cNotPt:
1762 return Hexagon::LDriub_indexed_cPt;
1765 case Hexagon::POST_LDrid_cPt:
1766 return Hexagon::POST_LDrid_cNotPt;
1767 case Hexagon::POST_LDriw_cNotPt:
1768 return Hexagon::POST_LDriw_cPt;
1770 case Hexagon::POST_LDrih_cPt:
1771 return Hexagon::POST_LDrih_cNotPt;
1772 case Hexagon::POST_LDrih_cNotPt:
1773 return Hexagon::POST_LDrih_cPt;
1775 case Hexagon::POST_LDriuh_cPt:
1776 return Hexagon::POST_LDriuh_cNotPt;
1777 case Hexagon::POST_LDriuh_cNotPt:
1778 return Hexagon::POST_LDriuh_cPt;
1780 case Hexagon::POST_LDrib_cPt:
1781 return Hexagon::POST_LDrib_cNotPt;
1782 case Hexagon::POST_LDrib_cNotPt:
1783 return Hexagon::POST_LDrib_cPt;
1785 case Hexagon::POST_LDriub_cPt:
1786 return Hexagon::POST_LDriub_cNotPt;
1787 case Hexagon::POST_LDriub_cNotPt:
1788 return Hexagon::POST_LDriub_cPt;
1791 case Hexagon::DEALLOC_RET_cPt_V4:
1792 return Hexagon::DEALLOC_RET_cNotPt_V4;
1793 case Hexagon::DEALLOC_RET_cNotPt_V4:
1794 return Hexagon::DEALLOC_RET_cPt_V4;
1797 // JMPEQ_ri - with -1.
1798 case Hexagon::JMP_EQriPtneg_nv_V4:
1799 return Hexagon::JMP_EQriNotPtneg_nv_V4;
1800 case Hexagon::JMP_EQriNotPtneg_nv_V4:
1801 return Hexagon::JMP_EQriPtneg_nv_V4;
1803 case Hexagon::JMP_EQriPntneg_nv_V4:
1804 return Hexagon::JMP_EQriNotPntneg_nv_V4;
1805 case Hexagon::JMP_EQriNotPntneg_nv_V4:
1806 return Hexagon::JMP_EQriPntneg_nv_V4;
1809 case Hexagon::JMP_EQriPt_nv_V4:
1810 return Hexagon::JMP_EQriNotPt_nv_V4;
1811 case Hexagon::JMP_EQriNotPt_nv_V4:
1812 return Hexagon::JMP_EQriPt_nv_V4;
1814 case Hexagon::JMP_EQriPnt_nv_V4:
1815 return Hexagon::JMP_EQriNotPnt_nv_V4;
1816 case Hexagon::JMP_EQriNotPnt_nv_V4:
1817 return Hexagon::JMP_EQriPnt_nv_V4;
1820 case Hexagon::JMP_EQrrPt_nv_V4:
1821 return Hexagon::JMP_EQrrNotPt_nv_V4;
1822 case Hexagon::JMP_EQrrNotPt_nv_V4:
1823 return Hexagon::JMP_EQrrPt_nv_V4;
1825 case Hexagon::JMP_EQrrPnt_nv_V4:
1826 return Hexagon::JMP_EQrrNotPnt_nv_V4;
1827 case Hexagon::JMP_EQrrNotPnt_nv_V4:
1828 return Hexagon::JMP_EQrrPnt_nv_V4;
1830 // JMPGT_ri - with -1.
1831 case Hexagon::JMP_GTriPtneg_nv_V4:
1832 return Hexagon::JMP_GTriNotPtneg_nv_V4;
1833 case Hexagon::JMP_GTriNotPtneg_nv_V4:
1834 return Hexagon::JMP_GTriPtneg_nv_V4;
1836 case Hexagon::JMP_GTriPntneg_nv_V4:
1837 return Hexagon::JMP_GTriNotPntneg_nv_V4;
1838 case Hexagon::JMP_GTriNotPntneg_nv_V4:
1839 return Hexagon::JMP_GTriPntneg_nv_V4;
1842 case Hexagon::JMP_GTriPt_nv_V4:
1843 return Hexagon::JMP_GTriNotPt_nv_V4;
1844 case Hexagon::JMP_GTriNotPt_nv_V4:
1845 return Hexagon::JMP_GTriPt_nv_V4;
1847 case Hexagon::JMP_GTriPnt_nv_V4:
1848 return Hexagon::JMP_GTriNotPnt_nv_V4;
1849 case Hexagon::JMP_GTriNotPnt_nv_V4:
1850 return Hexagon::JMP_GTriPnt_nv_V4;
1853 case Hexagon::JMP_GTrrPt_nv_V4:
1854 return Hexagon::JMP_GTrrNotPt_nv_V4;
1855 case Hexagon::JMP_GTrrNotPt_nv_V4:
1856 return Hexagon::JMP_GTrrPt_nv_V4;
1858 case Hexagon::JMP_GTrrPnt_nv_V4:
1859 return Hexagon::JMP_GTrrNotPnt_nv_V4;
1860 case Hexagon::JMP_GTrrNotPnt_nv_V4:
1861 return Hexagon::JMP_GTrrPnt_nv_V4;
1864 case Hexagon::JMP_GTrrdnPt_nv_V4:
1865 return Hexagon::JMP_GTrrdnNotPt_nv_V4;
1866 case Hexagon::JMP_GTrrdnNotPt_nv_V4:
1867 return Hexagon::JMP_GTrrdnPt_nv_V4;
1869 case Hexagon::JMP_GTrrdnPnt_nv_V4:
1870 return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
1871 case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
1872 return Hexagon::JMP_GTrrdnPnt_nv_V4;
1875 case Hexagon::JMP_GTUriPt_nv_V4:
1876 return Hexagon::JMP_GTUriNotPt_nv_V4;
1877 case Hexagon::JMP_GTUriNotPt_nv_V4:
1878 return Hexagon::JMP_GTUriPt_nv_V4;
1880 case Hexagon::JMP_GTUriPnt_nv_V4:
1881 return Hexagon::JMP_GTUriNotPnt_nv_V4;
1882 case Hexagon::JMP_GTUriNotPnt_nv_V4:
1883 return Hexagon::JMP_GTUriPnt_nv_V4;
1886 case Hexagon::JMP_GTUrrPt_nv_V4:
1887 return Hexagon::JMP_GTUrrNotPt_nv_V4;
1888 case Hexagon::JMP_GTUrrNotPt_nv_V4:
1889 return Hexagon::JMP_GTUrrPt_nv_V4;
1891 case Hexagon::JMP_GTUrrPnt_nv_V4:
1892 return Hexagon::JMP_GTUrrNotPnt_nv_V4;
1893 case Hexagon::JMP_GTUrrNotPnt_nv_V4:
1894 return Hexagon::JMP_GTUrrPnt_nv_V4;
1897 case Hexagon::JMP_GTUrrdnPt_nv_V4:
1898 return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
1899 case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
1900 return Hexagon::JMP_GTUrrdnPt_nv_V4;
1902 case Hexagon::JMP_GTUrrdnPnt_nv_V4:
1903 return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
1904 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
1905 return Hexagon::JMP_GTUrrdnPnt_nv_V4;
1910 int HexagonInstrInfo::
1911 getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
1914 return !invertPredicate ? Hexagon::TFR_cPt :
1915 Hexagon::TFR_cNotPt;
1916 case Hexagon::TFRI_f:
1917 return !invertPredicate ? Hexagon::TFRI_cPt_f :
1918 Hexagon::TFRI_cNotPt_f;
1920 return !invertPredicate ? Hexagon::TFRI_cPt :
1921 Hexagon::TFRI_cNotPt;
1923 return !invertPredicate ? Hexagon::JMP_c :
1925 case Hexagon::ADD_ri:
1926 return !invertPredicate ? Hexagon::ADD_ri_cPt :
1927 Hexagon::ADD_ri_cNotPt;
1928 case Hexagon::ADD_rr:
1929 return !invertPredicate ? Hexagon::ADD_rr_cPt :
1930 Hexagon::ADD_rr_cNotPt;
1931 case Hexagon::XOR_rr:
1932 return !invertPredicate ? Hexagon::XOR_rr_cPt :
1933 Hexagon::XOR_rr_cNotPt;
1934 case Hexagon::AND_rr:
1935 return !invertPredicate ? Hexagon::AND_rr_cPt :
1936 Hexagon::AND_rr_cNotPt;
1937 case Hexagon::OR_rr:
1938 return !invertPredicate ? Hexagon::OR_rr_cPt :
1939 Hexagon::OR_rr_cNotPt;
1940 case Hexagon::SUB_rr:
1941 return !invertPredicate ? Hexagon::SUB_rr_cPt :
1942 Hexagon::SUB_rr_cNotPt;
1943 case Hexagon::COMBINE_rr:
1944 return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
1945 Hexagon::COMBINE_rr_cNotPt;
1947 return !invertPredicate ? Hexagon::ASLH_cPt_V4 :
1948 Hexagon::ASLH_cNotPt_V4;
1950 return !invertPredicate ? Hexagon::ASRH_cPt_V4 :
1951 Hexagon::ASRH_cNotPt_V4;
1953 return !invertPredicate ? Hexagon::SXTB_cPt_V4 :
1954 Hexagon::SXTB_cNotPt_V4;
1956 return !invertPredicate ? Hexagon::SXTH_cPt_V4 :
1957 Hexagon::SXTH_cNotPt_V4;
1959 return !invertPredicate ? Hexagon::ZXTB_cPt_V4 :
1960 Hexagon::ZXTB_cNotPt_V4;
1962 return !invertPredicate ? Hexagon::ZXTH_cPt_V4 :
1963 Hexagon::ZXTH_cNotPt_V4;
1966 return !invertPredicate ? Hexagon::JMPR_cPt :
1967 Hexagon::JMPR_cNotPt;
1969 // V4 indexed+scaled load.
1970 case Hexagon::LDrid_indexed_V4:
1971 return !invertPredicate ? Hexagon::LDrid_indexed_cPt_V4 :
1972 Hexagon::LDrid_indexed_cNotPt_V4;
1973 case Hexagon::LDrid_indexed_shl_V4:
1974 return !invertPredicate ? Hexagon::LDrid_indexed_shl_cPt_V4 :
1975 Hexagon::LDrid_indexed_shl_cNotPt_V4;
1976 case Hexagon::LDrib_indexed_V4:
1977 return !invertPredicate ? Hexagon::LDrib_indexed_cPt_V4 :
1978 Hexagon::LDrib_indexed_cNotPt_V4;
1979 case Hexagon::LDriub_indexed_V4:
1980 return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 :
1981 Hexagon::LDriub_indexed_cNotPt_V4;
1982 case Hexagon::LDriub_ae_indexed_V4:
1983 return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 :
1984 Hexagon::LDriub_indexed_cNotPt_V4;
1985 case Hexagon::LDrib_indexed_shl_V4:
1986 return !invertPredicate ? Hexagon::LDrib_indexed_shl_cPt_V4 :
1987 Hexagon::LDrib_indexed_shl_cNotPt_V4;
1988 case Hexagon::LDriub_indexed_shl_V4:
1989 return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
1990 Hexagon::LDriub_indexed_shl_cNotPt_V4;
1991 case Hexagon::LDriub_ae_indexed_shl_V4:
1992 return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
1993 Hexagon::LDriub_indexed_shl_cNotPt_V4;
1994 case Hexagon::LDrih_indexed_V4:
1995 return !invertPredicate ? Hexagon::LDrih_indexed_cPt_V4 :
1996 Hexagon::LDrih_indexed_cNotPt_V4;
1997 case Hexagon::LDriuh_indexed_V4:
1998 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 :
1999 Hexagon::LDriuh_indexed_cNotPt_V4;
2000 case Hexagon::LDriuh_ae_indexed_V4:
2001 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 :
2002 Hexagon::LDriuh_indexed_cNotPt_V4;
2003 case Hexagon::LDrih_indexed_shl_V4:
2004 return !invertPredicate ? Hexagon::LDrih_indexed_shl_cPt_V4 :
2005 Hexagon::LDrih_indexed_shl_cNotPt_V4;
2006 case Hexagon::LDriuh_indexed_shl_V4:
2007 return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
2008 Hexagon::LDriuh_indexed_shl_cNotPt_V4;
2009 case Hexagon::LDriuh_ae_indexed_shl_V4:
2010 return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
2011 Hexagon::LDriuh_indexed_shl_cNotPt_V4;
2012 case Hexagon::LDriw_indexed_V4:
2013 return !invertPredicate ? Hexagon::LDriw_indexed_cPt_V4 :
2014 Hexagon::LDriw_indexed_cNotPt_V4;
2015 case Hexagon::LDriw_indexed_shl_V4:
2016 return !invertPredicate ? Hexagon::LDriw_indexed_shl_cPt_V4 :
2017 Hexagon::LDriw_indexed_shl_cNotPt_V4;
2019 // V4 Load from global address
2020 case Hexagon::LDrid_GP_V4:
2021 return !invertPredicate ? Hexagon::LDrid_GP_cPt_V4 :
2022 Hexagon::LDrid_GP_cNotPt_V4;
2023 case Hexagon::LDrib_GP_V4:
2024 return !invertPredicate ? Hexagon::LDrib_GP_cPt_V4 :
2025 Hexagon::LDrib_GP_cNotPt_V4;
2026 case Hexagon::LDriub_GP_V4:
2027 return !invertPredicate ? Hexagon::LDriub_GP_cPt_V4 :
2028 Hexagon::LDriub_GP_cNotPt_V4;
2029 case Hexagon::LDrih_GP_V4:
2030 return !invertPredicate ? Hexagon::LDrih_GP_cPt_V4 :
2031 Hexagon::LDrih_GP_cNotPt_V4;
2032 case Hexagon::LDriuh_GP_V4:
2033 return !invertPredicate ? Hexagon::LDriuh_GP_cPt_V4 :
2034 Hexagon::LDriuh_GP_cNotPt_V4;
2035 case Hexagon::LDriw_GP_V4:
2036 return !invertPredicate ? Hexagon::LDriw_GP_cPt_V4 :
2037 Hexagon::LDriw_GP_cNotPt_V4;
2039 case Hexagon::LDd_GP_V4:
2040 return !invertPredicate ? Hexagon::LDd_GP_cPt_V4 :
2041 Hexagon::LDd_GP_cNotPt_V4;
2042 case Hexagon::LDb_GP_V4:
2043 return !invertPredicate ? Hexagon::LDb_GP_cPt_V4 :
2044 Hexagon::LDb_GP_cNotPt_V4;
2045 case Hexagon::LDub_GP_V4:
2046 return !invertPredicate ? Hexagon::LDub_GP_cPt_V4 :
2047 Hexagon::LDub_GP_cNotPt_V4;
2048 case Hexagon::LDh_GP_V4:
2049 return !invertPredicate ? Hexagon::LDh_GP_cPt_V4 :
2050 Hexagon::LDh_GP_cNotPt_V4;
2051 case Hexagon::LDuh_GP_V4:
2052 return !invertPredicate ? Hexagon::LDuh_GP_cPt_V4 :
2053 Hexagon::LDuh_GP_cNotPt_V4;
2054 case Hexagon::LDw_GP_V4:
2055 return !invertPredicate ? Hexagon::LDw_GP_cPt_V4 :
2056 Hexagon::LDw_GP_cNotPt_V4;
2059 case Hexagon::POST_STbri:
2060 return !invertPredicate ? Hexagon::POST_STbri_cPt :
2061 Hexagon::POST_STbri_cNotPt;
2062 case Hexagon::STrib:
2063 return !invertPredicate ? Hexagon::STrib_cPt :
2064 Hexagon::STrib_cNotPt;
2065 case Hexagon::STrib_indexed:
2066 return !invertPredicate ? Hexagon::STrib_indexed_cPt :
2067 Hexagon::STrib_indexed_cNotPt;
2068 case Hexagon::STrib_imm_V4:
2069 return !invertPredicate ? Hexagon::STrib_imm_cPt_V4 :
2070 Hexagon::STrib_imm_cNotPt_V4;
2071 case Hexagon::STrib_indexed_shl_V4:
2072 return !invertPredicate ? Hexagon::STrib_indexed_shl_cPt_V4 :
2073 Hexagon::STrib_indexed_shl_cNotPt_V4;
2075 case Hexagon::POST_SThri:
2076 return !invertPredicate ? Hexagon::POST_SThri_cPt :
2077 Hexagon::POST_SThri_cNotPt;
2078 case Hexagon::STrih:
2079 return !invertPredicate ? Hexagon::STrih_cPt :
2080 Hexagon::STrih_cNotPt;
2081 case Hexagon::STrih_indexed:
2082 return !invertPredicate ? Hexagon::STrih_indexed_cPt :
2083 Hexagon::STrih_indexed_cNotPt;
2084 case Hexagon::STrih_imm_V4:
2085 return !invertPredicate ? Hexagon::STrih_imm_cPt_V4 :
2086 Hexagon::STrih_imm_cNotPt_V4;
2087 case Hexagon::STrih_indexed_shl_V4:
2088 return !invertPredicate ? Hexagon::STrih_indexed_shl_cPt_V4 :
2089 Hexagon::STrih_indexed_shl_cNotPt_V4;
2091 case Hexagon::POST_STwri:
2092 return !invertPredicate ? Hexagon::POST_STwri_cPt :
2093 Hexagon::POST_STwri_cNotPt;
2094 case Hexagon::STriw:
2095 return !invertPredicate ? Hexagon::STriw_cPt :
2096 Hexagon::STriw_cNotPt;
2097 case Hexagon::STriw_indexed:
2098 return !invertPredicate ? Hexagon::STriw_indexed_cPt :
2099 Hexagon::STriw_indexed_cNotPt;
2100 case Hexagon::STriw_indexed_shl_V4:
2101 return !invertPredicate ? Hexagon::STriw_indexed_shl_cPt_V4 :
2102 Hexagon::STriw_indexed_shl_cNotPt_V4;
2103 case Hexagon::STriw_imm_V4:
2104 return !invertPredicate ? Hexagon::STriw_imm_cPt_V4 :
2105 Hexagon::STriw_imm_cNotPt_V4;
2107 case Hexagon::POST_STdri:
2108 return !invertPredicate ? Hexagon::POST_STdri_cPt :
2109 Hexagon::POST_STdri_cNotPt;
2110 case Hexagon::STrid:
2111 return !invertPredicate ? Hexagon::STrid_cPt :
2112 Hexagon::STrid_cNotPt;
2113 case Hexagon::STrid_indexed:
2114 return !invertPredicate ? Hexagon::STrid_indexed_cPt :
2115 Hexagon::STrid_indexed_cNotPt;
2116 case Hexagon::STrid_indexed_shl_V4:
2117 return !invertPredicate ? Hexagon::STrid_indexed_shl_cPt_V4 :
2118 Hexagon::STrid_indexed_shl_cNotPt_V4;
2120 // V4 Store to global address
2121 case Hexagon::STrid_GP_V4:
2122 return !invertPredicate ? Hexagon::STrid_GP_cPt_V4 :
2123 Hexagon::STrid_GP_cNotPt_V4;
2124 case Hexagon::STrib_GP_V4:
2125 return !invertPredicate ? Hexagon::STrib_GP_cPt_V4 :
2126 Hexagon::STrib_GP_cNotPt_V4;
2127 case Hexagon::STrih_GP_V4:
2128 return !invertPredicate ? Hexagon::STrih_GP_cPt_V4 :
2129 Hexagon::STrih_GP_cNotPt_V4;
2130 case Hexagon::STriw_GP_V4:
2131 return !invertPredicate ? Hexagon::STriw_GP_cPt_V4 :
2132 Hexagon::STriw_GP_cNotPt_V4;
2134 case Hexagon::STd_GP_V4:
2135 return !invertPredicate ? Hexagon::STd_GP_cPt_V4 :
2136 Hexagon::STd_GP_cNotPt_V4;
2137 case Hexagon::STb_GP_V4:
2138 return !invertPredicate ? Hexagon::STb_GP_cPt_V4 :
2139 Hexagon::STb_GP_cNotPt_V4;
2140 case Hexagon::STh_GP_V4:
2141 return !invertPredicate ? Hexagon::STh_GP_cPt_V4 :
2142 Hexagon::STh_GP_cNotPt_V4;
2143 case Hexagon::STw_GP_V4:
2144 return !invertPredicate ? Hexagon::STw_GP_cPt_V4 :
2145 Hexagon::STw_GP_cNotPt_V4;
2148 case Hexagon::LDrid:
2149 return !invertPredicate ? Hexagon::LDrid_cPt :
2150 Hexagon::LDrid_cNotPt;
2151 case Hexagon::LDriw:
2152 return !invertPredicate ? Hexagon::LDriw_cPt :
2153 Hexagon::LDriw_cNotPt;
2154 case Hexagon::LDrih:
2155 return !invertPredicate ? Hexagon::LDrih_cPt :
2156 Hexagon::LDrih_cNotPt;
2157 case Hexagon::LDriuh:
2158 return !invertPredicate ? Hexagon::LDriuh_cPt :
2159 Hexagon::LDriuh_cNotPt;
2160 case Hexagon::LDrib:
2161 return !invertPredicate ? Hexagon::LDrib_cPt :
2162 Hexagon::LDrib_cNotPt;
2163 case Hexagon::LDriub:
2164 return !invertPredicate ? Hexagon::LDriub_cPt :
2165 Hexagon::LDriub_cNotPt;
2167 case Hexagon::LDrid_indexed:
2168 return !invertPredicate ? Hexagon::LDrid_indexed_cPt :
2169 Hexagon::LDrid_indexed_cNotPt;
2170 case Hexagon::LDriw_indexed:
2171 return !invertPredicate ? Hexagon::LDriw_indexed_cPt :
2172 Hexagon::LDriw_indexed_cNotPt;
2173 case Hexagon::LDrih_indexed:
2174 return !invertPredicate ? Hexagon::LDrih_indexed_cPt :
2175 Hexagon::LDrih_indexed_cNotPt;
2176 case Hexagon::LDriuh_indexed:
2177 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt :
2178 Hexagon::LDriuh_indexed_cNotPt;
2179 case Hexagon::LDrib_indexed:
2180 return !invertPredicate ? Hexagon::LDrib_indexed_cPt :
2181 Hexagon::LDrib_indexed_cNotPt;
2182 case Hexagon::LDriub_indexed:
2183 return !invertPredicate ? Hexagon::LDriub_indexed_cPt :
2184 Hexagon::LDriub_indexed_cNotPt;
2185 // Post Increment Load.
2186 case Hexagon::POST_LDrid:
2187 return !invertPredicate ? Hexagon::POST_LDrid_cPt :
2188 Hexagon::POST_LDrid_cNotPt;
2189 case Hexagon::POST_LDriw:
2190 return !invertPredicate ? Hexagon::POST_LDriw_cPt :
2191 Hexagon::POST_LDriw_cNotPt;
2192 case Hexagon::POST_LDrih:
2193 return !invertPredicate ? Hexagon::POST_LDrih_cPt :
2194 Hexagon::POST_LDrih_cNotPt;
2195 case Hexagon::POST_LDriuh:
2196 return !invertPredicate ? Hexagon::POST_LDriuh_cPt :
2197 Hexagon::POST_LDriuh_cNotPt;
2198 case Hexagon::POST_LDrib:
2199 return !invertPredicate ? Hexagon::POST_LDrib_cPt :
2200 Hexagon::POST_LDrib_cNotPt;
2201 case Hexagon::POST_LDriub:
2202 return !invertPredicate ? Hexagon::POST_LDriub_cPt :
2203 Hexagon::POST_LDriub_cNotPt;
2205 case Hexagon::DEALLOC_RET_V4:
2206 return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
2207 Hexagon::DEALLOC_RET_cNotPt_V4;
2209 // Load Absolute Addressing -- global address.
2210 case Hexagon::LDrib_abs_V4:
2211 return !invertPredicate ? Hexagon::LDrib_abs_cPt_V4 :
2212 Hexagon::LDrib_abs_cNotPt_V4;
2213 case Hexagon::LDriub_abs_V4:
2214 return !invertPredicate ? Hexagon::LDriub_abs_cPt_V4 :
2215 Hexagon::LDriub_abs_cNotPt_V4;
2216 case Hexagon::LDrih_abs_V4:
2217 return !invertPredicate ? Hexagon::LDrih_abs_cPt_V4 :
2218 Hexagon::LDrih_abs_cNotPt_V4;
2219 case Hexagon::LDriuh_abs_V4:
2220 return !invertPredicate ? Hexagon::LDriuh_abs_cPt_V4 :
2221 Hexagon::LDriuh_abs_cNotPt_V4;
2222 case Hexagon::LDriw_abs_V4:
2223 return !invertPredicate ? Hexagon::LDriw_abs_cPt_V4 :
2224 Hexagon::LDriw_abs_cNotPt_V4;
2225 case Hexagon::LDrid_abs_V4:
2226 return !invertPredicate ? Hexagon::LDrid_abs_cPt_V4 :
2227 Hexagon::LDrid_abs_cNotPt_V4;
2229 // Load Absolute Addressing -- immediate value.
2230 case Hexagon::LDrib_imm_abs_V4:
2231 return !invertPredicate ? Hexagon::LDrib_imm_abs_cPt_V4 :
2232 Hexagon::LDrib_imm_abs_cNotPt_V4;
2233 case Hexagon::LDriub_imm_abs_V4:
2234 return !invertPredicate ? Hexagon::LDriub_imm_abs_cPt_V4 :
2235 Hexagon::LDriub_imm_abs_cNotPt_V4;
2236 case Hexagon::LDrih_imm_abs_V4:
2237 return !invertPredicate ? Hexagon::LDrih_imm_abs_cPt_V4 :
2238 Hexagon::LDrih_imm_abs_cNotPt_V4;
2239 case Hexagon::LDriuh_imm_abs_V4:
2240 return !invertPredicate ? Hexagon::LDriuh_imm_abs_cPt_V4 :
2241 Hexagon::LDriuh_imm_abs_cNotPt_V4;
2242 case Hexagon::LDriw_imm_abs_V4:
2243 return !invertPredicate ? Hexagon::LDriw_imm_abs_cPt_V4 :
2244 Hexagon::LDriw_imm_abs_cNotPt_V4;
2246 // Store Absolute Addressing.
2247 case Hexagon::STrib_abs_V4:
2248 return !invertPredicate ? Hexagon::STrib_abs_cPt_V4 :
2249 Hexagon::STrib_abs_cNotPt_V4;
2250 case Hexagon::STrih_abs_V4:
2251 return !invertPredicate ? Hexagon::STrih_abs_cPt_V4 :
2252 Hexagon::STrih_abs_cNotPt_V4;
2253 case Hexagon::STriw_abs_V4:
2254 return !invertPredicate ? Hexagon::STriw_abs_cPt_V4 :
2255 Hexagon::STriw_abs_cNotPt_V4;
2256 case Hexagon::STrid_abs_V4:
2257 return !invertPredicate ? Hexagon::STrid_abs_cPt_V4 :
2258 Hexagon::STrid_abs_cNotPt_V4;
2260 // Store Absolute Addressing - global address.
2261 case Hexagon::STrib_imm_abs_V4:
2262 return !invertPredicate ? Hexagon::STrib_imm_abs_cPt_V4 :
2263 Hexagon::STrib_imm_abs_cNotPt_V4;
2264 case Hexagon::STrih_imm_abs_V4:
2265 return !invertPredicate ? Hexagon::STrih_imm_abs_cPt_V4 :
2266 Hexagon::STrih_imm_abs_cNotPt_V4;
2267 case Hexagon::STriw_imm_abs_V4:
2268 return !invertPredicate ? Hexagon::STriw_imm_abs_cPt_V4 :
2269 Hexagon::STriw_imm_abs_cNotPt_V4;
2272 case Hexagon::TFRI_V4:
2273 return !invertPredicate ? Hexagon::TFRI_cPt_V4 :
2274 Hexagon::TFRI_cNotPt_V4;
2276 llvm_unreachable("Unexpected predicable instruction");
2280 bool HexagonInstrInfo::
2281 PredicateInstruction(MachineInstr *MI,
2282 const SmallVectorImpl<MachineOperand> &Cond) const {
2283 int Opc = MI->getOpcode();
2284 assert (isPredicable(MI) && "Expected predicable instruction");
2285 bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
2286 (Cond[0].getImm() == 0));
2287 MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
2289 // This assumes that the predicate is always the first operand
2290 // in the set of inputs.
2292 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
2294 for (oper = MI->getNumOperands() - 3; oper >= 0; --oper) {
2295 MachineOperand MO = MI->getOperand(oper);
2296 if ((MO.isReg() && !MO.isUse() && !MO.isImplicit())) {
2301 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
2302 MO.isImplicit(), MO.isKill(),
2303 MO.isDead(), MO.isUndef(),
2305 } else if (MO.isImm()) {
2306 MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
2308 llvm_unreachable("Unexpected operand type");
2312 int regPos = invertJump ? 1 : 0;
2313 MachineOperand PredMO = Cond[regPos];
2314 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
2315 PredMO.isImplicit(), PredMO.isKill(),
2316 PredMO.isDead(), PredMO.isUndef(),
2325 isProfitableToIfCvt(MachineBasicBlock &MBB,
2327 unsigned ExtraPredCycles,
2328 const BranchProbability &Probability) const {
2335 isProfitableToIfCvt(MachineBasicBlock &TMBB,
2336 unsigned NumTCycles,
2337 unsigned ExtraTCycles,
2338 MachineBasicBlock &FMBB,
2339 unsigned NumFCycles,
2340 unsigned ExtraFCycles,
2341 const BranchProbability &Probability) const {
2346 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
2347 const uint64_t F = MI->getDesc().TSFlags;
2349 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
2353 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
2354 std::vector<MachineOperand> &Pred) const {
2355 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
2356 MachineOperand MO = MI->getOperand(oper);
2357 if (MO.isReg() && MO.isDef()) {
2358 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
2359 if (RC == &Hexagon::PredRegsRegClass) {
2371 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
2372 const SmallVectorImpl<MachineOperand> &Pred2) const {
2379 // We indicate that we want to reverse the branch by
2380 // inserting a 0 at the beginning of the Cond vector.
2382 bool HexagonInstrInfo::
2383 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2384 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
2385 Cond.erase(Cond.begin());
2387 Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
2393 bool HexagonInstrInfo::
2394 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
2395 const BranchProbability &Probability) const {
2396 return (NumInstrs <= 4);
2399 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
2400 switch (MI->getOpcode()) {
2401 default: return false;
2402 case Hexagon::DEALLOC_RET_V4 :
2403 case Hexagon::DEALLOC_RET_cPt_V4 :
2404 case Hexagon::DEALLOC_RET_cNotPt_V4 :
2405 case Hexagon::DEALLOC_RET_cdnPnt_V4 :
2406 case Hexagon::DEALLOC_RET_cNotdnPnt_V4 :
2407 case Hexagon::DEALLOC_RET_cdnPt_V4 :
2408 case Hexagon::DEALLOC_RET_cNotdnPt_V4 :
2414 bool HexagonInstrInfo::
2415 isValidOffset(const int Opcode, const int Offset) const {
2416 // This function is to check whether the "Offset" is in the correct range of
2417 // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
2418 // inserted to calculate the final address. Due to this reason, the function
2419 // assumes that the "Offset" has correct alignment.
2423 case Hexagon::LDriw:
2424 case Hexagon::LDriw_f:
2425 case Hexagon::STriw_indexed:
2426 case Hexagon::STriw:
2427 case Hexagon::STriw_f:
2428 assert((Offset % 4 == 0) && "Offset has incorrect alignment");
2429 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2430 (Offset <= Hexagon_MEMW_OFFSET_MAX);
2432 case Hexagon::LDrid:
2433 case Hexagon::LDrid_f:
2434 case Hexagon::STrid:
2435 case Hexagon::STrid_f:
2436 assert((Offset % 8 == 0) && "Offset has incorrect alignment");
2437 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2438 (Offset <= Hexagon_MEMD_OFFSET_MAX);
2440 case Hexagon::LDrih:
2441 case Hexagon::LDriuh:
2442 case Hexagon::STrih:
2443 assert((Offset % 2 == 0) && "Offset has incorrect alignment");
2444 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2445 (Offset <= Hexagon_MEMH_OFFSET_MAX);
2447 case Hexagon::LDrib:
2448 case Hexagon::STrib:
2449 case Hexagon::LDriub:
2450 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2451 (Offset <= Hexagon_MEMB_OFFSET_MAX);
2453 case Hexagon::ADD_ri:
2454 case Hexagon::TFR_FI:
2455 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2456 (Offset <= Hexagon_ADDI_OFFSET_MAX);
2458 case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
2459 case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
2460 case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
2461 case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
2462 case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
2463 case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
2464 case Hexagon::MEMw_ORr_indexed_MEM_V4 :
2465 case Hexagon::MEMw_ADDSUBi_MEM_V4 :
2466 case Hexagon::MEMw_ADDi_MEM_V4 :
2467 case Hexagon::MEMw_SUBi_MEM_V4 :
2468 case Hexagon::MEMw_ADDr_MEM_V4 :
2469 case Hexagon::MEMw_SUBr_MEM_V4 :
2470 case Hexagon::MEMw_ANDr_MEM_V4 :
2471 case Hexagon::MEMw_ORr_MEM_V4 :
2472 assert ((Offset % 4) == 0 && "MEMOPw offset is not aligned correctly." );
2473 return (0 <= Offset && Offset <= 255);
2475 case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
2476 case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
2477 case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
2478 case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
2479 case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
2480 case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
2481 case Hexagon::MEMh_ORr_indexed_MEM_V4 :
2482 case Hexagon::MEMh_ADDSUBi_MEM_V4 :
2483 case Hexagon::MEMh_ADDi_MEM_V4 :
2484 case Hexagon::MEMh_SUBi_MEM_V4 :
2485 case Hexagon::MEMh_ADDr_MEM_V4 :
2486 case Hexagon::MEMh_SUBr_MEM_V4 :
2487 case Hexagon::MEMh_ANDr_MEM_V4 :
2488 case Hexagon::MEMh_ORr_MEM_V4 :
2489 assert ((Offset % 2) == 0 && "MEMOPh offset is not aligned correctly." );
2490 return (0 <= Offset && Offset <= 127);
2492 case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
2493 case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
2494 case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
2495 case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
2496 case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
2497 case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
2498 case Hexagon::MEMb_ORr_indexed_MEM_V4 :
2499 case Hexagon::MEMb_ADDSUBi_MEM_V4 :
2500 case Hexagon::MEMb_ADDi_MEM_V4 :
2501 case Hexagon::MEMb_SUBi_MEM_V4 :
2502 case Hexagon::MEMb_ADDr_MEM_V4 :
2503 case Hexagon::MEMb_SUBr_MEM_V4 :
2504 case Hexagon::MEMb_ANDr_MEM_V4 :
2505 case Hexagon::MEMb_ORr_MEM_V4 :
2506 return (0 <= Offset && Offset <= 63);
2508 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
2509 // any size. Later pass knows how to handle it.
2510 case Hexagon::STriw_pred:
2511 case Hexagon::LDriw_pred:
2514 // INLINEASM is very special.
2515 case Hexagon::INLINEASM:
2519 llvm_unreachable("No offset range is defined for this opcode. "
2520 "Please define it in the above switch statement!");
2525 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2527 bool HexagonInstrInfo::
2528 isValidAutoIncImm(const EVT VT, const int Offset) const {
2530 if (VT == MVT::i64) {
2531 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
2532 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
2533 (Offset & 0x7) == 0);
2535 if (VT == MVT::i32) {
2536 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
2537 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
2538 (Offset & 0x3) == 0);
2540 if (VT == MVT::i16) {
2541 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
2542 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
2543 (Offset & 0x1) == 0);
2545 if (VT == MVT::i8) {
2546 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
2547 Offset <= Hexagon_MEMB_AUTOINC_MAX);
2549 llvm_unreachable("Not an auto-inc opc!");
2553 bool HexagonInstrInfo::
2554 isMemOp(const MachineInstr *MI) const {
2555 switch (MI->getOpcode())
2557 default: return false;
2558 case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
2559 case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
2560 case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
2561 case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
2562 case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
2563 case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
2564 case Hexagon::MEMw_ORr_indexed_MEM_V4 :
2565 case Hexagon::MEMw_ADDSUBi_MEM_V4 :
2566 case Hexagon::MEMw_ADDi_MEM_V4 :
2567 case Hexagon::MEMw_SUBi_MEM_V4 :
2568 case Hexagon::MEMw_ADDr_MEM_V4 :
2569 case Hexagon::MEMw_SUBr_MEM_V4 :
2570 case Hexagon::MEMw_ANDr_MEM_V4 :
2571 case Hexagon::MEMw_ORr_MEM_V4 :
2572 case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
2573 case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
2574 case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
2575 case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
2576 case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
2577 case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
2578 case Hexagon::MEMh_ORr_indexed_MEM_V4 :
2579 case Hexagon::MEMh_ADDSUBi_MEM_V4 :
2580 case Hexagon::MEMh_ADDi_MEM_V4 :
2581 case Hexagon::MEMh_SUBi_MEM_V4 :
2582 case Hexagon::MEMh_ADDr_MEM_V4 :
2583 case Hexagon::MEMh_SUBr_MEM_V4 :
2584 case Hexagon::MEMh_ANDr_MEM_V4 :
2585 case Hexagon::MEMh_ORr_MEM_V4 :
2586 case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
2587 case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
2588 case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
2589 case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
2590 case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
2591 case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
2592 case Hexagon::MEMb_ORr_indexed_MEM_V4 :
2593 case Hexagon::MEMb_ADDSUBi_MEM_V4 :
2594 case Hexagon::MEMb_ADDi_MEM_V4 :
2595 case Hexagon::MEMb_SUBi_MEM_V4 :
2596 case Hexagon::MEMb_ADDr_MEM_V4 :
2597 case Hexagon::MEMb_SUBr_MEM_V4 :
2598 case Hexagon::MEMb_ANDr_MEM_V4 :
2599 case Hexagon::MEMb_ORr_MEM_V4 :
2605 bool HexagonInstrInfo::
2606 isSpillPredRegOp(const MachineInstr *MI) const {
2607 switch (MI->getOpcode()) {
2608 default: return false;
2609 case Hexagon::STriw_pred :
2610 case Hexagon::LDriw_pred :
2616 bool HexagonInstrInfo::
2617 isConditionalTransfer (const MachineInstr *MI) const {
2618 switch (MI->getOpcode()) {
2619 default: return false;
2620 case Hexagon::TFR_cPt:
2621 case Hexagon::TFR_cNotPt:
2622 case Hexagon::TFRI_cPt:
2623 case Hexagon::TFRI_cNotPt:
2624 case Hexagon::TFR_cdnPt:
2625 case Hexagon::TFR_cdnNotPt:
2626 case Hexagon::TFRI_cdnPt:
2627 case Hexagon::TFRI_cdnNotPt:
2632 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
2633 const HexagonRegisterInfo& QRI = getRegisterInfo();
2634 switch (MI->getOpcode())
2636 default: return false;
2637 case Hexagon::ADD_ri_cPt:
2638 case Hexagon::ADD_ri_cNotPt:
2639 case Hexagon::ADD_rr_cPt:
2640 case Hexagon::ADD_rr_cNotPt:
2641 case Hexagon::XOR_rr_cPt:
2642 case Hexagon::XOR_rr_cNotPt:
2643 case Hexagon::AND_rr_cPt:
2644 case Hexagon::AND_rr_cNotPt:
2645 case Hexagon::OR_rr_cPt:
2646 case Hexagon::OR_rr_cNotPt:
2647 case Hexagon::SUB_rr_cPt:
2648 case Hexagon::SUB_rr_cNotPt:
2649 case Hexagon::COMBINE_rr_cPt:
2650 case Hexagon::COMBINE_rr_cNotPt:
2652 case Hexagon::ASLH_cPt_V4:
2653 case Hexagon::ASLH_cNotPt_V4:
2654 case Hexagon::ASRH_cPt_V4:
2655 case Hexagon::ASRH_cNotPt_V4:
2656 case Hexagon::SXTB_cPt_V4:
2657 case Hexagon::SXTB_cNotPt_V4:
2658 case Hexagon::SXTH_cPt_V4:
2659 case Hexagon::SXTH_cNotPt_V4:
2660 case Hexagon::ZXTB_cPt_V4:
2661 case Hexagon::ZXTB_cNotPt_V4:
2662 case Hexagon::ZXTH_cPt_V4:
2663 case Hexagon::ZXTH_cNotPt_V4:
2664 return QRI.Subtarget.hasV4TOps();
2668 bool HexagonInstrInfo::
2669 isConditionalLoad (const MachineInstr* MI) const {
2670 const HexagonRegisterInfo& QRI = getRegisterInfo();
2671 switch (MI->getOpcode())
2673 default: return false;
2674 case Hexagon::LDrid_cPt :
2675 case Hexagon::LDrid_cNotPt :
2676 case Hexagon::LDrid_indexed_cPt :
2677 case Hexagon::LDrid_indexed_cNotPt :
2678 case Hexagon::LDriw_cPt :
2679 case Hexagon::LDriw_cNotPt :
2680 case Hexagon::LDriw_indexed_cPt :
2681 case Hexagon::LDriw_indexed_cNotPt :
2682 case Hexagon::LDrih_cPt :
2683 case Hexagon::LDrih_cNotPt :
2684 case Hexagon::LDrih_indexed_cPt :
2685 case Hexagon::LDrih_indexed_cNotPt :
2686 case Hexagon::LDrib_cPt :
2687 case Hexagon::LDrib_cNotPt :
2688 case Hexagon::LDrib_indexed_cPt :
2689 case Hexagon::LDrib_indexed_cNotPt :
2690 case Hexagon::LDriuh_cPt :
2691 case Hexagon::LDriuh_cNotPt :
2692 case Hexagon::LDriuh_indexed_cPt :
2693 case Hexagon::LDriuh_indexed_cNotPt :
2694 case Hexagon::LDriub_cPt :
2695 case Hexagon::LDriub_cNotPt :
2696 case Hexagon::LDriub_indexed_cPt :
2697 case Hexagon::LDriub_indexed_cNotPt :
2699 case Hexagon::POST_LDrid_cPt :
2700 case Hexagon::POST_LDrid_cNotPt :
2701 case Hexagon::POST_LDriw_cPt :
2702 case Hexagon::POST_LDriw_cNotPt :
2703 case Hexagon::POST_LDrih_cPt :
2704 case Hexagon::POST_LDrih_cNotPt :
2705 case Hexagon::POST_LDrib_cPt :
2706 case Hexagon::POST_LDrib_cNotPt :
2707 case Hexagon::POST_LDriuh_cPt :
2708 case Hexagon::POST_LDriuh_cNotPt :
2709 case Hexagon::POST_LDriub_cPt :
2710 case Hexagon::POST_LDriub_cNotPt :
2711 return QRI.Subtarget.hasV4TOps();
2712 case Hexagon::LDrid_indexed_cPt_V4 :
2713 case Hexagon::LDrid_indexed_cNotPt_V4 :
2714 case Hexagon::LDrid_indexed_shl_cPt_V4 :
2715 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
2716 case Hexagon::LDrib_indexed_cPt_V4 :
2717 case Hexagon::LDrib_indexed_cNotPt_V4 :
2718 case Hexagon::LDrib_indexed_shl_cPt_V4 :
2719 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
2720 case Hexagon::LDriub_indexed_cPt_V4 :
2721 case Hexagon::LDriub_indexed_cNotPt_V4 :
2722 case Hexagon::LDriub_indexed_shl_cPt_V4 :
2723 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
2724 case Hexagon::LDrih_indexed_cPt_V4 :
2725 case Hexagon::LDrih_indexed_cNotPt_V4 :
2726 case Hexagon::LDrih_indexed_shl_cPt_V4 :
2727 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
2728 case Hexagon::LDriuh_indexed_cPt_V4 :
2729 case Hexagon::LDriuh_indexed_cNotPt_V4 :
2730 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
2731 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
2732 case Hexagon::LDriw_indexed_cPt_V4 :
2733 case Hexagon::LDriw_indexed_cNotPt_V4 :
2734 case Hexagon::LDriw_indexed_shl_cPt_V4 :
2735 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
2736 return QRI.Subtarget.hasV4TOps();
2740 // Returns true if an instruction is a conditional store.
2742 // Note: It doesn't include conditional new-value stores as they can't be
2743 // converted to .new predicate.
2745 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
2747 // / \ (not OK. it will cause new-value store to be
2748 // / X conditional on p0.new while R2 producer is
2751 // p.new store p.old NV store
2752 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
2758 // [if (p0)memw(R0+#0)=R2]
2760 // The above diagram shows the steps involoved in the conversion of a predicated
2761 // store instruction to its .new predicated new-value form.
2763 // The following set of instructions further explains the scenario where
2764 // conditional new-value store becomes invalid when promoted to .new predicate
2767 // { 1) if (p0) r0 = add(r1, r2)
2768 // 2) p0 = cmp.eq(r3, #0) }
2770 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
2771 // the first two instructions because in instr 1, r0 is conditional on old value
2772 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
2773 // is not valid for new-value stores.
2774 bool HexagonInstrInfo::
2775 isConditionalStore (const MachineInstr* MI) const {
2776 const HexagonRegisterInfo& QRI = getRegisterInfo();
2777 switch (MI->getOpcode())
2779 default: return false;
2780 case Hexagon::STrib_imm_cPt_V4 :
2781 case Hexagon::STrib_imm_cNotPt_V4 :
2782 case Hexagon::STrib_indexed_shl_cPt_V4 :
2783 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
2784 case Hexagon::STrib_cPt :
2785 case Hexagon::STrib_cNotPt :
2786 case Hexagon::POST_STbri_cPt :
2787 case Hexagon::POST_STbri_cNotPt :
2788 case Hexagon::STrid_indexed_cPt :
2789 case Hexagon::STrid_indexed_cNotPt :
2790 case Hexagon::STrid_indexed_shl_cPt_V4 :
2791 case Hexagon::POST_STdri_cPt :
2792 case Hexagon::POST_STdri_cNotPt :
2793 case Hexagon::STrih_cPt :
2794 case Hexagon::STrih_cNotPt :
2795 case Hexagon::STrih_indexed_cPt :
2796 case Hexagon::STrih_indexed_cNotPt :
2797 case Hexagon::STrih_imm_cPt_V4 :
2798 case Hexagon::STrih_imm_cNotPt_V4 :
2799 case Hexagon::STrih_indexed_shl_cPt_V4 :
2800 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
2801 case Hexagon::POST_SThri_cPt :
2802 case Hexagon::POST_SThri_cNotPt :
2803 case Hexagon::STriw_cPt :
2804 case Hexagon::STriw_cNotPt :
2805 case Hexagon::STriw_indexed_cPt :
2806 case Hexagon::STriw_indexed_cNotPt :
2807 case Hexagon::STriw_imm_cPt_V4 :
2808 case Hexagon::STriw_imm_cNotPt_V4 :
2809 case Hexagon::STriw_indexed_shl_cPt_V4 :
2810 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
2811 case Hexagon::POST_STwri_cPt :
2812 case Hexagon::POST_STwri_cNotPt :
2813 return QRI.Subtarget.hasV4TOps();
2815 // V4 global address store before promoting to dot new.
2816 case Hexagon::STrid_GP_cPt_V4 :
2817 case Hexagon::STrid_GP_cNotPt_V4 :
2818 case Hexagon::STrib_GP_cPt_V4 :
2819 case Hexagon::STrib_GP_cNotPt_V4 :
2820 case Hexagon::STrih_GP_cPt_V4 :
2821 case Hexagon::STrih_GP_cNotPt_V4 :
2822 case Hexagon::STriw_GP_cPt_V4 :
2823 case Hexagon::STriw_GP_cNotPt_V4 :
2824 case Hexagon::STd_GP_cPt_V4 :
2825 case Hexagon::STd_GP_cNotPt_V4 :
2826 case Hexagon::STb_GP_cPt_V4 :
2827 case Hexagon::STb_GP_cNotPt_V4 :
2828 case Hexagon::STh_GP_cPt_V4 :
2829 case Hexagon::STh_GP_cNotPt_V4 :
2830 case Hexagon::STw_GP_cPt_V4 :
2831 case Hexagon::STw_GP_cNotPt_V4 :
2832 return QRI.Subtarget.hasV4TOps();
2834 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
2835 // from the "Conditional Store" list. Because a predicated new value store
2836 // would NOT be promoted to a double dot new store. See diagram below:
2837 // This function returns yes for those stores that are predicated but not
2838 // yet promoted to predicate dot new instructions.
2840 // +---------------------+
2841 // /-----| if (p0) memw(..)=r0 |---------\~
2842 // || +---------------------+ ||
2843 // promote || /\ /\ || promote
2845 // \||/ demote || \||/
2847 // +-------------------------+ || +-------------------------+
2848 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
2849 // +-------------------------+ || +-------------------------+
2852 // promote || \/ NOT possible
2856 // +-----------------------------+
2857 // | if (p0.new) memw(..)=r0.new |
2858 // +-----------------------------+
2859 // Double Dot New Store
2866 DFAPacketizer *HexagonInstrInfo::
2867 CreateTargetScheduleState(const TargetMachine *TM,
2868 const ScheduleDAG *DAG) const {
2869 const InstrItineraryData *II = TM->getInstrItineraryData();
2870 return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II);
2873 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
2874 const MachineBasicBlock *MBB,
2875 const MachineFunction &MF) const {
2876 // Debug info is never a scheduling boundary. It's necessary to be explicit
2877 // due to the special treatment of IT instructions below, otherwise a
2878 // dbg_value followed by an IT will result in the IT instruction being
2879 // considered a scheduling hazard, which is wrong. It should be the actual
2880 // instruction preceding the dbg_value instruction(s), just like it is
2881 // when debug info is not present.
2882 if (MI->isDebugValue())
2885 // Terminators and labels can't be scheduled around.
2886 if (MI->getDesc().isTerminator() || MI->isLabel() || MI->isInlineAsm())
2892 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2894 case MachineOperand::MO_MachineBasicBlock:
2895 case MachineOperand::MO_GlobalAddress:
2896 case MachineOperand::MO_ExternalSymbol:
2897 case MachineOperand::MO_JumpTableIndex:
2898 case MachineOperand::MO_ConstantPoolIndex:
2899 case MachineOperand::MO_BlockAddress:
2906 bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const {
2907 unsigned short Opcode = MI->getOpcode();
2908 short ExtOpNum = HexagonConstExt::getCExtOpNum(Opcode);
2910 // Instruction has no constant extended operand.
2915 int MinValue = HexagonConstExt::getMinValue(Opcode);
2916 int MaxValue = HexagonConstExt::getMaxValue(Opcode);
2917 const MachineOperand &MO = MI->getOperand(ExtOpNum);
2918 if (!MO.isImm()) // no range check if the operand is non-immediate.
2921 int ImmValue =MO.getImm();
2922 return (ImmValue < MinValue || ImmValue > MaxValue);
2926 // Returns true if a particular operand is extended for an instruction.
2927 bool HexagonConstExt::isOperandExtended(unsigned short Opcode,
2928 unsigned short OperandNum) {
2929 return HexagonCExt[Opcode].CExtOpNum == OperandNum;
2932 // Returns Operand Index for the constant extended instruction.
2933 unsigned short HexagonConstExt::getCExtOpNum(unsigned short Opcode) {
2934 return HexagonCExt[Opcode].CExtOpNum;
2937 // Returns the min value that doesn't need to be extended.
2938 int HexagonConstExt::getMinValue(unsigned short Opcode) {
2939 return HexagonCExt[Opcode].MinValue;
2942 // Returns the max value that doesn't need to be extended.
2943 int HexagonConstExt::getMaxValue(unsigned short Opcode) {
2944 return HexagonCExt[Opcode].MaxValue;
2947 // Returns true if an instruction can be converted into a non-extended
2948 // equivalent instruction.
2949 bool HexagonConstExt::NonExtEquivalentExists (unsigned short Opcode) {
2950 if (HexagonCExt[Opcode].NonExtOpcode < 0 )
2955 // Returns opcode of the non-extended equivalent instruction.
2956 int HexagonConstExt::getNonExtOpcode (unsigned short Opcode) {
2957 return HexagonCExt[Opcode].NonExtOpcode;