1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/raw_ostream.h"
32 #define DEBUG_TYPE "hexagon-instrinfo"
34 #define GET_INSTRINFO_CTOR_DTOR
35 #define GET_INSTRMAP_INFO
36 #include "HexagonGenInstrInfo.inc"
37 #include "HexagonGenDFAPacketizer.inc"
40 /// Constants for Hexagon instructions.
42 const int Hexagon_MEMW_OFFSET_MAX = 4095;
43 const int Hexagon_MEMW_OFFSET_MIN = -4096;
44 const int Hexagon_MEMD_OFFSET_MAX = 8191;
45 const int Hexagon_MEMD_OFFSET_MIN = -8192;
46 const int Hexagon_MEMH_OFFSET_MAX = 2047;
47 const int Hexagon_MEMH_OFFSET_MIN = -2048;
48 const int Hexagon_MEMB_OFFSET_MAX = 1023;
49 const int Hexagon_MEMB_OFFSET_MIN = -1024;
50 const int Hexagon_ADDI_OFFSET_MAX = 32767;
51 const int Hexagon_ADDI_OFFSET_MIN = -32768;
52 const int Hexagon_MEMD_AUTOINC_MAX = 56;
53 const int Hexagon_MEMD_AUTOINC_MIN = -64;
54 const int Hexagon_MEMW_AUTOINC_MAX = 28;
55 const int Hexagon_MEMW_AUTOINC_MIN = -32;
56 const int Hexagon_MEMH_AUTOINC_MAX = 14;
57 const int Hexagon_MEMH_AUTOINC_MIN = -16;
58 const int Hexagon_MEMB_AUTOINC_MAX = 7;
59 const int Hexagon_MEMB_AUTOINC_MIN = -8;
61 // Pin the vtable to this file.
62 void HexagonInstrInfo::anchor() {}
64 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
65 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
66 RI(ST), Subtarget(ST) {
70 /// isLoadFromStackSlot - If the specified machine instruction is a direct
71 /// load from a stack slot, return the virtual or physical register number of
72 /// the destination along with the FrameIndex of the loaded stack slot. If
73 /// not, return 0. This predicate must return 0 if the instruction has
74 /// any side effects other than loading from the stack slot.
75 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
76 int &FrameIndex) const {
79 switch (MI->getOpcode()) {
86 if (MI->getOperand(2).isFI() &&
87 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
88 FrameIndex = MI->getOperand(2).getIndex();
89 return MI->getOperand(0).getReg();
97 /// isStoreToStackSlot - If the specified machine instruction is a direct
98 /// store to a stack slot, return the virtual or physical register number of
99 /// the source reg along with the FrameIndex of the loaded stack slot. If
100 /// not, return 0. This predicate must return 0 if the instruction has
101 /// any side effects other than storing to the stack slot.
102 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
103 int &FrameIndex) const {
104 switch (MI->getOpcode()) {
110 if (MI->getOperand(2).isFI() &&
111 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
112 FrameIndex = MI->getOperand(0).getIndex();
113 return MI->getOperand(2).getReg();
122 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
123 MachineBasicBlock *FBB,
124 const SmallVectorImpl<MachineOperand> &Cond,
127 int BOpc = Hexagon::JMP;
128 int BccOpc = Hexagon::JMP_t;
130 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
133 // Check if ReverseBranchCondition has asked to reverse this branch
134 // If we want to reverse the branch an odd number of times, we want
136 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
137 BccOpc = Hexagon::JMP_f;
143 // Due to a bug in TailMerging/CFG Optimization, we need to add a
144 // special case handling of a predicated jump followed by an
145 // unconditional jump. If not, Tail Merging and CFG Optimization go
146 // into an infinite loop.
147 MachineBasicBlock *NewTBB, *NewFBB;
148 SmallVector<MachineOperand, 4> Cond;
149 MachineInstr *Term = MBB.getFirstTerminator();
150 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
152 MachineBasicBlock *NextBB =
153 std::next(MachineFunction::iterator(&MBB));
154 if (NewTBB == NextBB) {
155 ReverseBranchCondition(Cond);
157 return InsertBranch(MBB, TBB, nullptr, Cond, DL);
160 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
163 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
168 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
169 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
175 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
176 MachineBasicBlock *&TBB,
177 MachineBasicBlock *&FBB,
178 SmallVectorImpl<MachineOperand> &Cond,
179 bool AllowModify) const {
183 // If the block has no terminators, it just falls into the block after it.
184 MachineBasicBlock::instr_iterator I = MBB.instr_end();
185 if (I == MBB.instr_begin())
188 // A basic block may looks like this:
198 // It has two succs but does not have a terminator
199 // Don't know how to handle it.
204 } while (I != MBB.instr_begin());
209 while (I->isDebugValue()) {
210 if (I == MBB.instr_begin())
215 // Delete the JMP if it's equivalent to a fall-through.
216 if (AllowModify && I->getOpcode() == Hexagon::JMP &&
217 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
218 DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
219 I->eraseFromParent();
221 if (I == MBB.instr_begin())
225 if (!isUnpredicatedTerminator(I))
228 // Get the last instruction in the block.
229 MachineInstr *LastInst = I;
230 MachineInstr *SecondLastInst = nullptr;
231 // Find one more terminator if present.
233 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(I)) {
237 // This is a third branch.
240 if (I == MBB.instr_begin())
245 int LastOpcode = LastInst->getOpcode();
247 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
248 bool LastOpcodeHasNot = PredOpcodeHasNot(LastOpcode);
250 // If there is only one terminator instruction, process it.
251 if (LastInst && !SecondLastInst) {
252 if (LastOpcode == Hexagon::JMP) {
253 TBB = LastInst->getOperand(0).getMBB();
256 if (LastOpcode == Hexagon::ENDLOOP0) {
257 TBB = LastInst->getOperand(0).getMBB();
258 Cond.push_back(LastInst->getOperand(0));
261 if (LastOpcodeHasJMP_c) {
262 TBB = LastInst->getOperand(1).getMBB();
263 if (LastOpcodeHasNot) {
264 Cond.push_back(MachineOperand::CreateImm(0));
266 Cond.push_back(LastInst->getOperand(0));
269 // Otherwise, don't know what this is.
273 int SecLastOpcode = SecondLastInst->getOpcode();
275 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
276 bool SecLastOpcodeHasNot = PredOpcodeHasNot(SecLastOpcode);
277 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::JMP)) {
278 TBB = SecondLastInst->getOperand(1).getMBB();
279 if (SecLastOpcodeHasNot)
280 Cond.push_back(MachineOperand::CreateImm(0));
281 Cond.push_back(SecondLastInst->getOperand(0));
282 FBB = LastInst->getOperand(0).getMBB();
286 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
287 // executed, so remove it.
288 if (SecLastOpcode == Hexagon::JMP && LastOpcode == Hexagon::JMP) {
289 TBB = SecondLastInst->getOperand(0).getMBB();
292 I->eraseFromParent();
296 // If the block ends with an ENDLOOP, and JMP, handle it.
297 if (SecLastOpcode == Hexagon::ENDLOOP0 &&
298 LastOpcode == Hexagon::JMP) {
299 TBB = SecondLastInst->getOperand(0).getMBB();
300 Cond.push_back(SecondLastInst->getOperand(0));
301 FBB = LastInst->getOperand(0).getMBB();
305 // Otherwise, can't handle this.
310 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
311 int BOpc = Hexagon::JMP;
312 int BccOpc = Hexagon::JMP_t;
313 int BccOpcNot = Hexagon::JMP_f;
315 MachineBasicBlock::iterator I = MBB.end();
316 if (I == MBB.begin()) return 0;
318 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
319 I->getOpcode() != BccOpcNot)
322 // Remove the branch.
323 I->eraseFromParent();
327 if (I == MBB.begin()) return 1;
329 if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
332 // Remove the branch.
333 I->eraseFromParent();
338 /// \brief For a comparison instruction, return the source registers in
339 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
340 /// compares against in CmpValue. Return true if the comparison instruction
342 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
343 unsigned &SrcReg, unsigned &SrcReg2,
344 int &Mask, int &Value) const {
345 unsigned Opc = MI->getOpcode();
347 // Set mask and the first source register.
349 case Hexagon::CMPEHexagon4rr:
350 case Hexagon::CMPEQri:
351 case Hexagon::CMPEQrr:
352 case Hexagon::CMPGT64rr:
353 case Hexagon::CMPGTU64rr:
354 case Hexagon::CMPGTUri:
355 case Hexagon::CMPGTUrr:
356 case Hexagon::CMPGTri:
357 case Hexagon::CMPGTrr:
358 SrcReg = MI->getOperand(1).getReg();
361 case Hexagon::CMPbEQri_V4:
362 case Hexagon::CMPbEQrr_sbsb_V4:
363 case Hexagon::CMPbEQrr_ubub_V4:
364 case Hexagon::CMPbGTUri_V4:
365 case Hexagon::CMPbGTUrr_V4:
366 case Hexagon::CMPbGTrr_V4:
367 SrcReg = MI->getOperand(1).getReg();
370 case Hexagon::CMPhEQri_V4:
371 case Hexagon::CMPhEQrr_shl_V4:
372 case Hexagon::CMPhEQrr_xor_V4:
373 case Hexagon::CMPhGTUri_V4:
374 case Hexagon::CMPhGTUrr_V4:
375 case Hexagon::CMPhGTrr_shl_V4:
376 SrcReg = MI->getOperand(1).getReg();
381 // Set the value/second source register.
383 case Hexagon::CMPEHexagon4rr:
384 case Hexagon::CMPEQrr:
385 case Hexagon::CMPGT64rr:
386 case Hexagon::CMPGTU64rr:
387 case Hexagon::CMPGTUrr:
388 case Hexagon::CMPGTrr:
389 case Hexagon::CMPbEQrr_sbsb_V4:
390 case Hexagon::CMPbEQrr_ubub_V4:
391 case Hexagon::CMPbGTUrr_V4:
392 case Hexagon::CMPbGTrr_V4:
393 case Hexagon::CMPhEQrr_shl_V4:
394 case Hexagon::CMPhEQrr_xor_V4:
395 case Hexagon::CMPhGTUrr_V4:
396 case Hexagon::CMPhGTrr_shl_V4:
397 SrcReg2 = MI->getOperand(2).getReg();
400 case Hexagon::CMPEQri:
401 case Hexagon::CMPGTUri:
402 case Hexagon::CMPGTri:
403 case Hexagon::CMPbEQri_V4:
404 case Hexagon::CMPbGTUri_V4:
405 case Hexagon::CMPhEQri_V4:
406 case Hexagon::CMPhGTUri_V4:
408 Value = MI->getOperand(2).getImm();
416 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
417 MachineBasicBlock::iterator I, DebugLoc DL,
418 unsigned DestReg, unsigned SrcReg,
419 bool KillSrc) const {
420 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
421 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
424 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
425 BuildMI(MBB, I, DL, get(Hexagon::TFR64), DestReg).addReg(SrcReg);
428 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
429 // Map Pd = Ps to Pd = or(Ps, Ps).
430 BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
431 DestReg).addReg(SrcReg).addReg(SrcReg);
434 if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
435 Hexagon::IntRegsRegClass.contains(SrcReg)) {
436 // We can have an overlap between single and double reg: r1:0 = r0.
437 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
439 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
440 Hexagon::subreg_hireg))).addImm(0);
442 // r1:0 = r1 or no overlap.
443 BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
444 Hexagon::subreg_loreg))).addReg(SrcReg);
445 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
446 Hexagon::subreg_hireg))).addImm(0);
450 if (Hexagon::CRRegsRegClass.contains(DestReg) &&
451 Hexagon::IntRegsRegClass.contains(SrcReg)) {
452 BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
455 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
456 Hexagon::IntRegsRegClass.contains(DestReg)) {
457 BuildMI(MBB, I, DL, get(Hexagon::TFR_RsPd), DestReg).
458 addReg(SrcReg, getKillRegState(KillSrc));
461 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
462 Hexagon::PredRegsRegClass.contains(DestReg)) {
463 BuildMI(MBB, I, DL, get(Hexagon::TFR_PdRs), DestReg).
464 addReg(SrcReg, getKillRegState(KillSrc));
468 llvm_unreachable("Unimplemented");
472 void HexagonInstrInfo::
473 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
474 unsigned SrcReg, bool isKill, int FI,
475 const TargetRegisterClass *RC,
476 const TargetRegisterInfo *TRI) const {
478 DebugLoc DL = MBB.findDebugLoc(I);
479 MachineFunction &MF = *MBB.getParent();
480 MachineFrameInfo &MFI = *MF.getFrameInfo();
481 unsigned Align = MFI.getObjectAlignment(FI);
483 MachineMemOperand *MMO =
484 MF.getMachineMemOperand(
485 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
486 MachineMemOperand::MOStore,
487 MFI.getObjectSize(FI),
490 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
491 BuildMI(MBB, I, DL, get(Hexagon::STriw))
492 .addFrameIndex(FI).addImm(0)
493 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
494 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
495 BuildMI(MBB, I, DL, get(Hexagon::STrid))
496 .addFrameIndex(FI).addImm(0)
497 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
498 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
499 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
500 .addFrameIndex(FI).addImm(0)
501 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
503 llvm_unreachable("Unimplemented");
508 void HexagonInstrInfo::storeRegToAddr(
509 MachineFunction &MF, unsigned SrcReg,
511 SmallVectorImpl<MachineOperand> &Addr,
512 const TargetRegisterClass *RC,
513 SmallVectorImpl<MachineInstr*> &NewMIs) const
515 llvm_unreachable("Unimplemented");
519 void HexagonInstrInfo::
520 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
521 unsigned DestReg, int FI,
522 const TargetRegisterClass *RC,
523 const TargetRegisterInfo *TRI) const {
524 DebugLoc DL = MBB.findDebugLoc(I);
525 MachineFunction &MF = *MBB.getParent();
526 MachineFrameInfo &MFI = *MF.getFrameInfo();
527 unsigned Align = MFI.getObjectAlignment(FI);
529 MachineMemOperand *MMO =
530 MF.getMachineMemOperand(
531 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
532 MachineMemOperand::MOLoad,
533 MFI.getObjectSize(FI),
535 if (RC == &Hexagon::IntRegsRegClass) {
536 BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)
537 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
538 } else if (RC == &Hexagon::DoubleRegsRegClass) {
539 BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
540 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
541 } else if (RC == &Hexagon::PredRegsRegClass) {
542 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
543 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
545 llvm_unreachable("Can't store this register to stack slot");
550 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
551 SmallVectorImpl<MachineOperand> &Addr,
552 const TargetRegisterClass *RC,
553 SmallVectorImpl<MachineInstr*> &NewMIs) const {
554 llvm_unreachable("Unimplemented");
558 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
560 const SmallVectorImpl<unsigned> &Ops,
562 // Hexagon_TODO: Implement.
566 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
568 MachineRegisterInfo &RegInfo = MF->getRegInfo();
569 const TargetRegisterClass *TRC;
571 TRC = &Hexagon::PredRegsRegClass;
572 } else if (VT == MVT::i32 || VT == MVT::f32) {
573 TRC = &Hexagon::IntRegsRegClass;
574 } else if (VT == MVT::i64 || VT == MVT::f64) {
575 TRC = &Hexagon::DoubleRegsRegClass;
577 llvm_unreachable("Cannot handle this register class");
580 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
584 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
585 // Constant extenders are allowed only for V4 and above.
586 if (!Subtarget.hasV4TOps())
589 const MCInstrDesc &MID = MI->getDesc();
590 const uint64_t F = MID.TSFlags;
591 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
594 // TODO: This is largely obsolete now. Will need to be removed
595 // in consecutive patches.
596 switch(MI->getOpcode()) {
597 // TFR_FI Remains a special case.
598 case Hexagon::TFR_FI:
606 // This returns true in two cases:
607 // - The OP code itself indicates that this is an extended instruction.
608 // - One of MOs has been marked with HMOTF_ConstExtended flag.
609 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
610 // First check if this is permanently extended op code.
611 const uint64_t F = MI->getDesc().TSFlags;
612 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
614 // Use MO operand flags to determine if one of MI's operands
615 // has HMOTF_ConstExtended flag set.
616 for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
617 E = MI->operands_end(); I != E; ++I) {
618 if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
624 bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
625 return MI->getDesc().isBranch();
628 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
629 if (isNewValueJump(MI))
632 if (isNewValueStore(MI))
638 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
639 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
642 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
643 bool isPred = MI->getDesc().isPredicable();
648 const int Opc = MI->getOpcode();
652 return isInt<12>(MI->getOperand(1).getImm());
655 case Hexagon::STrid_indexed:
656 return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
659 case Hexagon::STriw_indexed:
660 case Hexagon::STriw_nv_V4:
661 return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
664 case Hexagon::STrih_indexed:
665 case Hexagon::STrih_nv_V4:
666 return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
669 case Hexagon::STrib_indexed:
670 case Hexagon::STrib_nv_V4:
671 return isUInt<6>(MI->getOperand(1).getImm());
674 case Hexagon::LDrid_indexed:
675 return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
678 case Hexagon::LDriw_indexed:
679 return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
682 case Hexagon::LDriuh:
683 case Hexagon::LDrih_indexed:
684 case Hexagon::LDriuh_indexed:
685 return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
688 case Hexagon::LDriub:
689 case Hexagon::LDrib_indexed:
690 case Hexagon::LDriub_indexed:
691 return isUInt<6>(MI->getOperand(2).getImm());
693 case Hexagon::POST_LDrid:
694 return isShiftedInt<4,3>(MI->getOperand(3).getImm());
696 case Hexagon::POST_LDriw:
697 return isShiftedInt<4,2>(MI->getOperand(3).getImm());
699 case Hexagon::POST_LDrih:
700 case Hexagon::POST_LDriuh:
701 return isShiftedInt<4,1>(MI->getOperand(3).getImm());
703 case Hexagon::POST_LDrib:
704 case Hexagon::POST_LDriub:
705 return isInt<4>(MI->getOperand(3).getImm());
707 case Hexagon::STrib_imm_V4:
708 case Hexagon::STrih_imm_V4:
709 case Hexagon::STriw_imm_V4:
710 return (isUInt<6>(MI->getOperand(1).getImm()) &&
711 isInt<6>(MI->getOperand(2).getImm()));
713 case Hexagon::ADD_ri:
714 return isInt<8>(MI->getOperand(2).getImm());
722 return Subtarget.hasV4TOps();
728 // This function performs the following inversiones:
733 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
735 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
736 : Hexagon::getTruePredOpcode(Opc);
737 if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
738 return InvPredOpcode;
741 default: llvm_unreachable("Unexpected predicated instruction");
742 case Hexagon::COMBINE_rr_cPt:
743 return Hexagon::COMBINE_rr_cNotPt;
744 case Hexagon::COMBINE_rr_cNotPt:
745 return Hexagon::COMBINE_rr_cPt;
748 case Hexagon::DEALLOC_RET_cPt_V4:
749 return Hexagon::DEALLOC_RET_cNotPt_V4;
750 case Hexagon::DEALLOC_RET_cNotPt_V4:
751 return Hexagon::DEALLOC_RET_cPt_V4;
755 // New Value Store instructions.
756 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
757 const uint64_t F = MI->getDesc().TSFlags;
759 return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
762 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
763 const uint64_t F = get(Opcode).TSFlags;
765 return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
768 int HexagonInstrInfo::
769 getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
770 enum Hexagon::PredSense inPredSense;
771 inPredSense = invertPredicate ? Hexagon::PredSense_false :
772 Hexagon::PredSense_true;
773 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
774 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
777 // This switch case will be removed once all the instructions have been
778 // modified to use relation maps.
780 case Hexagon::TFRI_f:
781 return !invertPredicate ? Hexagon::TFRI_cPt_f :
782 Hexagon::TFRI_cNotPt_f;
783 case Hexagon::COMBINE_rr:
784 return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
785 Hexagon::COMBINE_rr_cNotPt;
788 case Hexagon::STriw_f:
789 return !invertPredicate ? Hexagon::STriw_cPt :
790 Hexagon::STriw_cNotPt;
791 case Hexagon::STriw_indexed_f:
792 return !invertPredicate ? Hexagon::STriw_indexed_cPt :
793 Hexagon::STriw_indexed_cNotPt;
796 case Hexagon::DEALLOC_RET_V4:
797 return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
798 Hexagon::DEALLOC_RET_cNotPt_V4;
800 llvm_unreachable("Unexpected predicable instruction");
804 bool HexagonInstrInfo::
805 PredicateInstruction(MachineInstr *MI,
806 const SmallVectorImpl<MachineOperand> &Cond) const {
807 int Opc = MI->getOpcode();
808 assert (isPredicable(MI) && "Expected predicable instruction");
809 bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
810 (Cond[0].getImm() == 0));
812 // This will change MI's opcode to its predicate version.
813 // However, its operand list is still the old one, i.e. the
814 // non-predicate one.
815 MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
818 unsigned int GAIdx = 0;
820 // Indicates whether the current MI has a GlobalAddress operand
821 bool hasGAOpnd = false;
822 std::vector<MachineOperand> tmpOpnds;
824 // Indicates whether we need to shift operands to right.
825 bool needShift = true;
827 // The predicate is ALWAYS the FIRST input operand !!!
828 if (MI->getNumOperands() == 0) {
829 // The non-predicate version of MI does not take any operands,
830 // i.e. no outs and no ins. In this condition, the predicate
831 // operand will be directly placed at Operands[0]. No operand
837 else if ( MI->getOperand(MI->getNumOperands()-1).isReg()
838 && MI->getOperand(MI->getNumOperands()-1).isDef()
839 && !MI->getOperand(MI->getNumOperands()-1).isImplicit()) {
840 // The non-predicate version of MI does not have any input operands.
841 // In this condition, we extend the length of Operands[] by one and
842 // copy the original last operand to the newly allocated slot.
843 // At this moment, it is just a place holder. Later, we will put
844 // predicate operand directly into it. No operand shift is needed.
845 // Example: r0=BARRIER (this is a faked insn used here for illustration)
846 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
848 oper = MI->getNumOperands() - 2;
851 // We need to right shift all input operands by one. Duplicate the
852 // last operand into the newly allocated slot.
853 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
858 // Operands[ MI->getNumOperands() - 2 ] has been copied into
859 // Operands[ MI->getNumOperands() - 1 ], so we start from
860 // Operands[ MI->getNumOperands() - 3 ].
861 // oper is a signed int.
862 // It is ok if "MI->getNumOperands()-3" is -3, -2, or -1.
863 for (oper = MI->getNumOperands() - 3; oper >= 0; --oper)
865 MachineOperand &MO = MI->getOperand(oper);
867 // Opnd[0] Opnd[1] Opnd[2] Opnd[3] Opnd[4] Opnd[5] Opnd[6] Opnd[7]
868 // <Def0> <Def1> <Use0> <Use1> <ImpDef0> <ImpDef1> <ImpUse0> <ImpUse1>
872 // Predicate Operand here
873 if (MO.isReg() && !MO.isUse() && !MO.isImplicit()) {
877 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
878 MO.isImplicit(), MO.isKill(),
879 MO.isDead(), MO.isUndef(),
882 else if (MO.isImm()) {
883 MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
885 else if (MO.isGlobal()) {
886 // MI can not have more than one GlobalAddress operand.
887 assert(hasGAOpnd == false && "MI can only have one GlobalAddress opnd");
889 // There is no member function called "ChangeToGlobalAddress" in the
890 // MachineOperand class (not like "ChangeToRegister" and
891 // "ChangeToImmediate"). So we have to remove them from Operands[] list
892 // first, and then add them back after we have inserted the predicate
893 // operand. tmpOpnds[] is to remember these operands before we remove
895 tmpOpnds.push_back(MO);
897 // Operands[oper] is a GlobalAddress operand;
898 // Operands[oper+1] has been copied into Operands[oper+2];
904 assert(false && "Unexpected operand type");
909 int regPos = invertJump ? 1 : 0;
910 MachineOperand PredMO = Cond[regPos];
912 // [oper] now points to the last explicit Def. Predicate operand must be
913 // located at [oper+1]. See diagram above.
914 // This assumes that the predicate is always the first operand,
915 // i.e. Operands[0+numResults], in the set of inputs
916 // It is better to have an assert here to check this. But I don't know how
917 // to write this assert because findFirstPredOperandIdx() would return -1
918 if (oper < -1) oper = -1;
920 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
921 PredMO.isImplicit(), false,
922 PredMO.isDead(), PredMO.isUndef(),
925 MachineRegisterInfo &RegInfo = MI->getParent()->getParent()->getRegInfo();
926 RegInfo.clearKillFlags(PredMO.getReg());
932 // Operands[GAIdx] is the original GlobalAddress operand, which is
933 // already copied into tmpOpnds[0].
934 // Operands[GAIdx] now stores a copy of Operands[GAIdx-1]
935 // Operands[GAIdx+1] has already been copied into Operands[GAIdx+2],
936 // so we start from [GAIdx+2]
937 for (i = GAIdx + 2; i < MI->getNumOperands(); ++i)
938 tmpOpnds.push_back(MI->getOperand(i));
940 // Remove all operands in range [ (GAIdx+1) ... (MI->getNumOperands()-1) ]
941 // It is very important that we always remove from the end of Operands[]
942 // MI->getNumOperands() is at least 2 if program goes to here.
943 for (i = MI->getNumOperands() - 1; i > GAIdx; --i)
944 MI->RemoveOperand(i);
946 for (i = 0; i < tmpOpnds.size(); ++i)
947 MI->addOperand(tmpOpnds[i]);
956 isProfitableToIfCvt(MachineBasicBlock &MBB,
958 unsigned ExtraPredCycles,
959 const BranchProbability &Probability) const {
966 isProfitableToIfCvt(MachineBasicBlock &TMBB,
968 unsigned ExtraTCycles,
969 MachineBasicBlock &FMBB,
971 unsigned ExtraFCycles,
972 const BranchProbability &Probability) const {
976 // Returns true if an instruction is predicated irrespective of the predicate
977 // sense. For example, all of the following will return true.
978 // if (p0) R1 = add(R2, R3)
979 // if (!p0) R1 = add(R2, R3)
980 // if (p0.new) R1 = add(R2, R3)
981 // if (!p0.new) R1 = add(R2, R3)
982 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
983 const uint64_t F = MI->getDesc().TSFlags;
985 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
988 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
989 const uint64_t F = get(Opcode).TSFlags;
991 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
994 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
995 const uint64_t F = MI->getDesc().TSFlags;
997 assert(isPredicated(MI));
998 return (!((F >> HexagonII::PredicatedFalsePos) &
999 HexagonII::PredicatedFalseMask));
1002 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
1003 const uint64_t F = get(Opcode).TSFlags;
1005 // Make sure that the instruction is predicated.
1006 assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1007 return (!((F >> HexagonII::PredicatedFalsePos) &
1008 HexagonII::PredicatedFalseMask));
1011 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
1012 const uint64_t F = MI->getDesc().TSFlags;
1014 assert(isPredicated(MI));
1015 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1018 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
1019 const uint64_t F = get(Opcode).TSFlags;
1021 assert(isPredicated(Opcode));
1022 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1025 // Returns true, if a ST insn can be promoted to a new-value store.
1026 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
1027 const HexagonRegisterInfo& QRI = getRegisterInfo();
1028 const uint64_t F = MI->getDesc().TSFlags;
1030 return ((F >> HexagonII::mayNVStorePos) &
1031 HexagonII::mayNVStoreMask &
1032 QRI.Subtarget.hasV4TOps());
1036 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
1037 std::vector<MachineOperand> &Pred) const {
1038 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
1039 MachineOperand MO = MI->getOperand(oper);
1040 if (MO.isReg() && MO.isDef()) {
1041 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
1042 if (RC == &Hexagon::PredRegsRegClass) {
1054 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
1055 const SmallVectorImpl<MachineOperand> &Pred2) const {
1062 // We indicate that we want to reverse the branch by
1063 // inserting a 0 at the beginning of the Cond vector.
1065 bool HexagonInstrInfo::
1066 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1067 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
1068 Cond.erase(Cond.begin());
1070 Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
1076 bool HexagonInstrInfo::
1077 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
1078 const BranchProbability &Probability) const {
1079 return (NumInstrs <= 4);
1082 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
1083 switch (MI->getOpcode()) {
1084 default: return false;
1085 case Hexagon::DEALLOC_RET_V4 :
1086 case Hexagon::DEALLOC_RET_cPt_V4 :
1087 case Hexagon::DEALLOC_RET_cNotPt_V4 :
1088 case Hexagon::DEALLOC_RET_cdnPnt_V4 :
1089 case Hexagon::DEALLOC_RET_cNotdnPnt_V4 :
1090 case Hexagon::DEALLOC_RET_cdnPt_V4 :
1091 case Hexagon::DEALLOC_RET_cNotdnPt_V4 :
1097 bool HexagonInstrInfo::
1098 isValidOffset(const int Opcode, const int Offset) const {
1099 // This function is to check whether the "Offset" is in the correct range of
1100 // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
1101 // inserted to calculate the final address. Due to this reason, the function
1102 // assumes that the "Offset" has correct alignment.
1103 // We used to assert if the offset was not properly aligned, however,
1104 // there are cases where a misaligned pointer recast can cause this
1105 // problem, and we need to allow for it. The front end warns of such
1106 // misaligns with respect to load size.
1110 case Hexagon::LDriw:
1111 case Hexagon::LDriw_indexed:
1112 case Hexagon::LDriw_f:
1113 case Hexagon::STriw_indexed:
1114 case Hexagon::STriw:
1115 case Hexagon::STriw_f:
1116 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
1117 (Offset <= Hexagon_MEMW_OFFSET_MAX);
1119 case Hexagon::LDrid:
1120 case Hexagon::LDrid_indexed:
1121 case Hexagon::LDrid_f:
1122 case Hexagon::STrid:
1123 case Hexagon::STrid_indexed:
1124 case Hexagon::STrid_f:
1125 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
1126 (Offset <= Hexagon_MEMD_OFFSET_MAX);
1128 case Hexagon::LDrih:
1129 case Hexagon::LDriuh:
1130 case Hexagon::STrih:
1131 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
1132 (Offset <= Hexagon_MEMH_OFFSET_MAX);
1134 case Hexagon::LDrib:
1135 case Hexagon::STrib:
1136 case Hexagon::LDriub:
1137 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
1138 (Offset <= Hexagon_MEMB_OFFSET_MAX);
1140 case Hexagon::ADD_ri:
1141 case Hexagon::TFR_FI:
1142 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
1143 (Offset <= Hexagon_ADDI_OFFSET_MAX);
1145 case Hexagon::MemOPw_ADDi_V4 :
1146 case Hexagon::MemOPw_SUBi_V4 :
1147 case Hexagon::MemOPw_ADDr_V4 :
1148 case Hexagon::MemOPw_SUBr_V4 :
1149 case Hexagon::MemOPw_ANDr_V4 :
1150 case Hexagon::MemOPw_ORr_V4 :
1151 return (0 <= Offset && Offset <= 255);
1153 case Hexagon::MemOPh_ADDi_V4 :
1154 case Hexagon::MemOPh_SUBi_V4 :
1155 case Hexagon::MemOPh_ADDr_V4 :
1156 case Hexagon::MemOPh_SUBr_V4 :
1157 case Hexagon::MemOPh_ANDr_V4 :
1158 case Hexagon::MemOPh_ORr_V4 :
1159 return (0 <= Offset && Offset <= 127);
1161 case Hexagon::MemOPb_ADDi_V4 :
1162 case Hexagon::MemOPb_SUBi_V4 :
1163 case Hexagon::MemOPb_ADDr_V4 :
1164 case Hexagon::MemOPb_SUBr_V4 :
1165 case Hexagon::MemOPb_ANDr_V4 :
1166 case Hexagon::MemOPb_ORr_V4 :
1167 return (0 <= Offset && Offset <= 63);
1169 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
1170 // any size. Later pass knows how to handle it.
1171 case Hexagon::STriw_pred:
1172 case Hexagon::LDriw_pred:
1175 case Hexagon::LOOP0_i:
1176 return isUInt<10>(Offset);
1178 // INLINEASM is very special.
1179 case Hexagon::INLINEASM:
1183 llvm_unreachable("No offset range is defined for this opcode. "
1184 "Please define it in the above switch statement!");
1189 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
1191 bool HexagonInstrInfo::
1192 isValidAutoIncImm(const EVT VT, const int Offset) const {
1194 if (VT == MVT::i64) {
1195 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
1196 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
1197 (Offset & 0x7) == 0);
1199 if (VT == MVT::i32) {
1200 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
1201 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
1202 (Offset & 0x3) == 0);
1204 if (VT == MVT::i16) {
1205 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
1206 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
1207 (Offset & 0x1) == 0);
1209 if (VT == MVT::i8) {
1210 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
1211 Offset <= Hexagon_MEMB_AUTOINC_MAX);
1213 llvm_unreachable("Not an auto-inc opc!");
1217 bool HexagonInstrInfo::
1218 isMemOp(const MachineInstr *MI) const {
1219 // return MI->getDesc().mayLoad() && MI->getDesc().mayStore();
1221 switch (MI->getOpcode())
1223 default: return false;
1224 case Hexagon::MemOPw_ADDi_V4 :
1225 case Hexagon::MemOPw_SUBi_V4 :
1226 case Hexagon::MemOPw_ADDr_V4 :
1227 case Hexagon::MemOPw_SUBr_V4 :
1228 case Hexagon::MemOPw_ANDr_V4 :
1229 case Hexagon::MemOPw_ORr_V4 :
1230 case Hexagon::MemOPh_ADDi_V4 :
1231 case Hexagon::MemOPh_SUBi_V4 :
1232 case Hexagon::MemOPh_ADDr_V4 :
1233 case Hexagon::MemOPh_SUBr_V4 :
1234 case Hexagon::MemOPh_ANDr_V4 :
1235 case Hexagon::MemOPh_ORr_V4 :
1236 case Hexagon::MemOPb_ADDi_V4 :
1237 case Hexagon::MemOPb_SUBi_V4 :
1238 case Hexagon::MemOPb_ADDr_V4 :
1239 case Hexagon::MemOPb_SUBr_V4 :
1240 case Hexagon::MemOPb_ANDr_V4 :
1241 case Hexagon::MemOPb_ORr_V4 :
1242 case Hexagon::MemOPb_SETBITi_V4:
1243 case Hexagon::MemOPh_SETBITi_V4:
1244 case Hexagon::MemOPw_SETBITi_V4:
1245 case Hexagon::MemOPb_CLRBITi_V4:
1246 case Hexagon::MemOPh_CLRBITi_V4:
1247 case Hexagon::MemOPw_CLRBITi_V4:
1254 bool HexagonInstrInfo::
1255 isSpillPredRegOp(const MachineInstr *MI) const {
1256 switch (MI->getOpcode()) {
1257 default: return false;
1258 case Hexagon::STriw_pred :
1259 case Hexagon::LDriw_pred :
1264 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
1265 switch (MI->getOpcode()) {
1266 default: return false;
1267 case Hexagon::CMPEQrr:
1268 case Hexagon::CMPEQri:
1269 case Hexagon::CMPGTrr:
1270 case Hexagon::CMPGTri:
1271 case Hexagon::CMPGTUrr:
1272 case Hexagon::CMPGTUri:
1277 bool HexagonInstrInfo::
1278 isConditionalTransfer (const MachineInstr *MI) const {
1279 switch (MI->getOpcode()) {
1280 default: return false;
1281 case Hexagon::TFR_cPt:
1282 case Hexagon::TFR_cNotPt:
1283 case Hexagon::TFRI_cPt:
1284 case Hexagon::TFRI_cNotPt:
1285 case Hexagon::TFR_cdnPt:
1286 case Hexagon::TFR_cdnNotPt:
1287 case Hexagon::TFRI_cdnPt:
1288 case Hexagon::TFRI_cdnNotPt:
1293 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
1294 const HexagonRegisterInfo& QRI = getRegisterInfo();
1295 switch (MI->getOpcode())
1297 default: return false;
1298 case Hexagon::ADD_ri_cPt:
1299 case Hexagon::ADD_ri_cNotPt:
1300 case Hexagon::ADD_rr_cPt:
1301 case Hexagon::ADD_rr_cNotPt:
1302 case Hexagon::XOR_rr_cPt:
1303 case Hexagon::XOR_rr_cNotPt:
1304 case Hexagon::AND_rr_cPt:
1305 case Hexagon::AND_rr_cNotPt:
1306 case Hexagon::OR_rr_cPt:
1307 case Hexagon::OR_rr_cNotPt:
1308 case Hexagon::SUB_rr_cPt:
1309 case Hexagon::SUB_rr_cNotPt:
1310 case Hexagon::COMBINE_rr_cPt:
1311 case Hexagon::COMBINE_rr_cNotPt:
1313 case Hexagon::ASLH_cPt_V4:
1314 case Hexagon::ASLH_cNotPt_V4:
1315 case Hexagon::ASRH_cPt_V4:
1316 case Hexagon::ASRH_cNotPt_V4:
1317 case Hexagon::SXTB_cPt_V4:
1318 case Hexagon::SXTB_cNotPt_V4:
1319 case Hexagon::SXTH_cPt_V4:
1320 case Hexagon::SXTH_cNotPt_V4:
1321 case Hexagon::ZXTB_cPt_V4:
1322 case Hexagon::ZXTB_cNotPt_V4:
1323 case Hexagon::ZXTH_cPt_V4:
1324 case Hexagon::ZXTH_cNotPt_V4:
1325 return QRI.Subtarget.hasV4TOps();
1329 bool HexagonInstrInfo::
1330 isConditionalLoad (const MachineInstr* MI) const {
1331 const HexagonRegisterInfo& QRI = getRegisterInfo();
1332 switch (MI->getOpcode())
1334 default: return false;
1335 case Hexagon::LDrid_cPt :
1336 case Hexagon::LDrid_cNotPt :
1337 case Hexagon::LDrid_indexed_cPt :
1338 case Hexagon::LDrid_indexed_cNotPt :
1339 case Hexagon::LDriw_cPt :
1340 case Hexagon::LDriw_cNotPt :
1341 case Hexagon::LDriw_indexed_cPt :
1342 case Hexagon::LDriw_indexed_cNotPt :
1343 case Hexagon::LDrih_cPt :
1344 case Hexagon::LDrih_cNotPt :
1345 case Hexagon::LDrih_indexed_cPt :
1346 case Hexagon::LDrih_indexed_cNotPt :
1347 case Hexagon::LDrib_cPt :
1348 case Hexagon::LDrib_cNotPt :
1349 case Hexagon::LDrib_indexed_cPt :
1350 case Hexagon::LDrib_indexed_cNotPt :
1351 case Hexagon::LDriuh_cPt :
1352 case Hexagon::LDriuh_cNotPt :
1353 case Hexagon::LDriuh_indexed_cPt :
1354 case Hexagon::LDriuh_indexed_cNotPt :
1355 case Hexagon::LDriub_cPt :
1356 case Hexagon::LDriub_cNotPt :
1357 case Hexagon::LDriub_indexed_cPt :
1358 case Hexagon::LDriub_indexed_cNotPt :
1360 case Hexagon::POST_LDrid_cPt :
1361 case Hexagon::POST_LDrid_cNotPt :
1362 case Hexagon::POST_LDriw_cPt :
1363 case Hexagon::POST_LDriw_cNotPt :
1364 case Hexagon::POST_LDrih_cPt :
1365 case Hexagon::POST_LDrih_cNotPt :
1366 case Hexagon::POST_LDrib_cPt :
1367 case Hexagon::POST_LDrib_cNotPt :
1368 case Hexagon::POST_LDriuh_cPt :
1369 case Hexagon::POST_LDriuh_cNotPt :
1370 case Hexagon::POST_LDriub_cPt :
1371 case Hexagon::POST_LDriub_cNotPt :
1372 return QRI.Subtarget.hasV4TOps();
1373 case Hexagon::LDrid_indexed_shl_cPt_V4 :
1374 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
1375 case Hexagon::LDrib_indexed_shl_cPt_V4 :
1376 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
1377 case Hexagon::LDriub_indexed_shl_cPt_V4 :
1378 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
1379 case Hexagon::LDrih_indexed_shl_cPt_V4 :
1380 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
1381 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
1382 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
1383 case Hexagon::LDriw_indexed_shl_cPt_V4 :
1384 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
1385 return QRI.Subtarget.hasV4TOps();
1389 // Returns true if an instruction is a conditional store.
1391 // Note: It doesn't include conditional new-value stores as they can't be
1392 // converted to .new predicate.
1394 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
1396 // / \ (not OK. it will cause new-value store to be
1397 // / X conditional on p0.new while R2 producer is
1400 // p.new store p.old NV store
1401 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
1407 // [if (p0)memw(R0+#0)=R2]
1409 // The above diagram shows the steps involoved in the conversion of a predicated
1410 // store instruction to its .new predicated new-value form.
1412 // The following set of instructions further explains the scenario where
1413 // conditional new-value store becomes invalid when promoted to .new predicate
1416 // { 1) if (p0) r0 = add(r1, r2)
1417 // 2) p0 = cmp.eq(r3, #0) }
1419 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
1420 // the first two instructions because in instr 1, r0 is conditional on old value
1421 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
1422 // is not valid for new-value stores.
1423 bool HexagonInstrInfo::
1424 isConditionalStore (const MachineInstr* MI) const {
1425 const HexagonRegisterInfo& QRI = getRegisterInfo();
1426 switch (MI->getOpcode())
1428 default: return false;
1429 case Hexagon::STrib_imm_cPt_V4 :
1430 case Hexagon::STrib_imm_cNotPt_V4 :
1431 case Hexagon::STrib_indexed_shl_cPt_V4 :
1432 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
1433 case Hexagon::STrib_cPt :
1434 case Hexagon::STrib_cNotPt :
1435 case Hexagon::POST_STbri_cPt :
1436 case Hexagon::POST_STbri_cNotPt :
1437 case Hexagon::STrid_indexed_cPt :
1438 case Hexagon::STrid_indexed_cNotPt :
1439 case Hexagon::STrid_indexed_shl_cPt_V4 :
1440 case Hexagon::POST_STdri_cPt :
1441 case Hexagon::POST_STdri_cNotPt :
1442 case Hexagon::STrih_cPt :
1443 case Hexagon::STrih_cNotPt :
1444 case Hexagon::STrih_indexed_cPt :
1445 case Hexagon::STrih_indexed_cNotPt :
1446 case Hexagon::STrih_imm_cPt_V4 :
1447 case Hexagon::STrih_imm_cNotPt_V4 :
1448 case Hexagon::STrih_indexed_shl_cPt_V4 :
1449 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
1450 case Hexagon::POST_SThri_cPt :
1451 case Hexagon::POST_SThri_cNotPt :
1452 case Hexagon::STriw_cPt :
1453 case Hexagon::STriw_cNotPt :
1454 case Hexagon::STriw_indexed_cPt :
1455 case Hexagon::STriw_indexed_cNotPt :
1456 case Hexagon::STriw_imm_cPt_V4 :
1457 case Hexagon::STriw_imm_cNotPt_V4 :
1458 case Hexagon::STriw_indexed_shl_cPt_V4 :
1459 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
1460 case Hexagon::POST_STwri_cPt :
1461 case Hexagon::POST_STwri_cNotPt :
1462 return QRI.Subtarget.hasV4TOps();
1464 // V4 global address store before promoting to dot new.
1465 case Hexagon::STd_GP_cPt_V4 :
1466 case Hexagon::STd_GP_cNotPt_V4 :
1467 case Hexagon::STb_GP_cPt_V4 :
1468 case Hexagon::STb_GP_cNotPt_V4 :
1469 case Hexagon::STh_GP_cPt_V4 :
1470 case Hexagon::STh_GP_cNotPt_V4 :
1471 case Hexagon::STw_GP_cPt_V4 :
1472 case Hexagon::STw_GP_cNotPt_V4 :
1473 return QRI.Subtarget.hasV4TOps();
1475 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
1476 // from the "Conditional Store" list. Because a predicated new value store
1477 // would NOT be promoted to a double dot new store. See diagram below:
1478 // This function returns yes for those stores that are predicated but not
1479 // yet promoted to predicate dot new instructions.
1481 // +---------------------+
1482 // /-----| if (p0) memw(..)=r0 |---------\~
1483 // || +---------------------+ ||
1484 // promote || /\ /\ || promote
1486 // \||/ demote || \||/
1488 // +-------------------------+ || +-------------------------+
1489 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
1490 // +-------------------------+ || +-------------------------+
1493 // promote || \/ NOT possible
1497 // +-----------------------------+
1498 // | if (p0.new) memw(..)=r0.new |
1499 // +-----------------------------+
1500 // Double Dot New Store
1506 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
1507 if (isNewValue(MI) && isBranch(MI))
1512 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
1513 return (getAddrMode(MI) == HexagonII::PostInc);
1516 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
1517 const uint64_t F = MI->getDesc().TSFlags;
1518 return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
1521 // Returns true, if any one of the operands is a dot new
1522 // insn, whether it is predicated dot new or register dot new.
1523 bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
1524 return (isNewValueInst(MI) ||
1525 (isPredicated(MI) && isPredicatedNew(MI)));
1528 // Returns the most basic instruction for the .new predicated instructions and
1529 // new-value stores.
1530 // For example, all of the following instructions will be converted back to the
1531 // same instruction:
1532 // 1) if (p0.new) memw(R0+#0) = R1.new --->
1533 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
1534 // 3) if (p0.new) memw(R0+#0) = R1 --->
1537 int HexagonInstrInfo::GetDotOldOp(const int opc) const {
1539 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
1540 NewOp = Hexagon::getPredOldOpcode(NewOp);
1541 assert(NewOp >= 0 &&
1542 "Couldn't change predicate new instruction to its old form.");
1545 if (isNewValueStore(NewOp)) { // Convert into non-new-value format
1546 NewOp = Hexagon::getNonNVStore(NewOp);
1547 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
1552 // Return the new value instruction for a given store.
1553 int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
1554 int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
1555 if (NVOpcode >= 0) // Valid new-value store instruction.
1558 switch (MI->getOpcode()) {
1559 default: llvm_unreachable("Unknown .new type");
1560 // store new value byte
1561 case Hexagon::STrib_shl_V4:
1562 return Hexagon::STrib_shl_nv_V4;
1564 case Hexagon::STrih_shl_V4:
1565 return Hexagon::STrih_shl_nv_V4;
1567 case Hexagon::STriw_f:
1568 return Hexagon::STriw_nv_V4;
1570 case Hexagon::STriw_indexed_f:
1571 return Hexagon::STriw_indexed_nv_V4;
1573 case Hexagon::STriw_shl_V4:
1574 return Hexagon::STriw_shl_nv_V4;
1580 // Return .new predicate version for an instruction.
1581 int HexagonInstrInfo::GetDotNewPredOp(MachineInstr *MI,
1582 const MachineBranchProbabilityInfo
1585 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
1586 if (NewOpcode >= 0) // Valid predicate new instruction
1589 switch (MI->getOpcode()) {
1590 default: llvm_unreachable("Unknown .new type");
1592 case Hexagon::JMP_t:
1593 case Hexagon::JMP_f:
1594 return getDotNewPredJumpOp(MI, MBPI);
1596 case Hexagon::JMPR_t:
1597 return Hexagon::JMPR_tnew_tV3;
1599 case Hexagon::JMPR_f:
1600 return Hexagon::JMPR_fnew_tV3;
1602 case Hexagon::JMPret_t:
1603 return Hexagon::JMPret_tnew_tV3;
1605 case Hexagon::JMPret_f:
1606 return Hexagon::JMPret_fnew_tV3;
1609 // Conditional combine
1610 case Hexagon::COMBINE_rr_cPt :
1611 return Hexagon::COMBINE_rr_cdnPt;
1612 case Hexagon::COMBINE_rr_cNotPt :
1613 return Hexagon::COMBINE_rr_cdnNotPt;
1618 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
1619 const uint64_t F = MI->getDesc().TSFlags;
1621 return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
1624 /// immediateExtend - Changes the instruction in place to one using an immediate
1626 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
1627 assert((isExtendable(MI)||isConstExtended(MI)) &&
1628 "Instruction must be extendable");
1629 // Find which operand is extendable.
1630 short ExtOpNum = getCExtOpNum(MI);
1631 MachineOperand &MO = MI->getOperand(ExtOpNum);
1632 // This needs to be something we understand.
1633 assert((MO.isMBB() || MO.isImm()) &&
1634 "Branch with unknown extendable field type");
1635 // Mark given operand as extended.
1636 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
1639 DFAPacketizer *HexagonInstrInfo::
1640 CreateTargetScheduleState(const TargetMachine *TM,
1641 const ScheduleDAG *DAG) const {
1642 const InstrItineraryData *II =
1643 TM->getSubtargetImpl()->getInstrItineraryData();
1644 return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II);
1647 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1648 const MachineBasicBlock *MBB,
1649 const MachineFunction &MF) const {
1650 // Debug info is never a scheduling boundary. It's necessary to be explicit
1651 // due to the special treatment of IT instructions below, otherwise a
1652 // dbg_value followed by an IT will result in the IT instruction being
1653 // considered a scheduling hazard, which is wrong. It should be the actual
1654 // instruction preceding the dbg_value instruction(s), just like it is
1655 // when debug info is not present.
1656 if (MI->isDebugValue())
1659 // Terminators and labels can't be scheduled around.
1660 if (MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm())
1666 bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const {
1668 // Constant extenders are allowed only for V4 and above.
1669 if (!Subtarget.hasV4TOps())
1672 const uint64_t F = MI->getDesc().TSFlags;
1673 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
1674 if (isExtended) // Instruction must be extended.
1677 unsigned isExtendable = (F >> HexagonII::ExtendablePos)
1678 & HexagonII::ExtendableMask;
1682 short ExtOpNum = getCExtOpNum(MI);
1683 const MachineOperand &MO = MI->getOperand(ExtOpNum);
1684 // Use MO operand flags to determine if MO
1685 // has the HMOTF_ConstExtended flag set.
1686 if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
1688 // If this is a Machine BB address we are talking about, and it is
1689 // not marked as extended, say so.
1693 // We could be using an instruction with an extendable immediate and shoehorn
1694 // a global address into it. If it is a global address it will be constant
1695 // extended. We do this for COMBINE.
1696 // We currently only handle isGlobal() because it is the only kind of
1697 // object we are going to end up with here for now.
1698 // In the future we probably should add isSymbol(), etc.
1699 if (MO.isGlobal() || MO.isSymbol())
1702 // If the extendable operand is not 'Immediate' type, the instruction should
1703 // have 'isExtended' flag set.
1704 assert(MO.isImm() && "Extendable operand must be Immediate type");
1706 int MinValue = getMinValue(MI);
1707 int MaxValue = getMaxValue(MI);
1708 int ImmValue = MO.getImm();
1710 return (ImmValue < MinValue || ImmValue > MaxValue);
1713 // Returns the opcode to use when converting MI, which is a conditional jump,
1714 // into a conditional instruction which uses the .new value of the predicate.
1715 // We also use branch probabilities to add a hint to the jump.
1717 HexagonInstrInfo::getDotNewPredJumpOp(MachineInstr *MI,
1719 MachineBranchProbabilityInfo *MBPI) const {
1721 // We assume that block can have at most two successors.
1723 MachineBasicBlock *Src = MI->getParent();
1724 MachineOperand *BrTarget = &MI->getOperand(1);
1725 MachineBasicBlock *Dst = BrTarget->getMBB();
1727 const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
1728 if (Prediction >= BranchProbability(1,2))
1731 switch (MI->getOpcode()) {
1732 case Hexagon::JMP_t:
1733 return taken ? Hexagon::JMP_tnew_t : Hexagon::JMP_tnew_nt;
1734 case Hexagon::JMP_f:
1735 return taken ? Hexagon::JMP_fnew_t : Hexagon::JMP_fnew_nt;
1738 llvm_unreachable("Unexpected jump instruction.");
1741 // Returns true if a particular operand is extendable for an instruction.
1742 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
1743 unsigned short OperandNum) const {
1744 // Constant extenders are allowed only for V4 and above.
1745 if (!Subtarget.hasV4TOps())
1748 const uint64_t F = MI->getDesc().TSFlags;
1750 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
1754 // Returns Operand Index for the constant extended instruction.
1755 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
1756 const uint64_t F = MI->getDesc().TSFlags;
1757 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
1760 // Returns the min value that doesn't need to be extended.
1761 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
1762 const uint64_t F = MI->getDesc().TSFlags;
1763 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1764 & HexagonII::ExtentSignedMask;
1765 unsigned bits = (F >> HexagonII::ExtentBitsPos)
1766 & HexagonII::ExtentBitsMask;
1768 if (isSigned) // if value is signed
1769 return -1U << (bits - 1);
1774 // Returns the max value that doesn't need to be extended.
1775 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
1776 const uint64_t F = MI->getDesc().TSFlags;
1777 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1778 & HexagonII::ExtentSignedMask;
1779 unsigned bits = (F >> HexagonII::ExtentBitsPos)
1780 & HexagonII::ExtentBitsMask;
1782 if (isSigned) // if value is signed
1783 return ~(-1U << (bits - 1));
1785 return ~(-1U << bits);
1788 // Returns true if an instruction can be converted into a non-extended
1789 // equivalent instruction.
1790 bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const {
1793 // Check if the instruction has a register form that uses register in place
1794 // of the extended operand, if so return that as the non-extended form.
1795 if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
1798 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1799 // Check addressing mode and retrieve non-ext equivalent instruction.
1801 switch (getAddrMode(MI)) {
1802 case HexagonII::Absolute :
1803 // Load/store with absolute addressing mode can be converted into
1804 // base+offset mode.
1805 NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
1807 case HexagonII::BaseImmOffset :
1808 // Load/store with base+offset addressing mode can be converted into
1809 // base+register offset addressing mode. However left shift operand should
1811 NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
1816 if (NonExtOpcode < 0)
1823 // Returns opcode of the non-extended equivalent instruction.
1824 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
1826 // Check if the instruction has a register form that uses register in place
1827 // of the extended operand, if so return that as the non-extended form.
1828 short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
1829 if (NonExtOpcode >= 0)
1830 return NonExtOpcode;
1832 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1833 // Check addressing mode and retrieve non-ext equivalent instruction.
1834 switch (getAddrMode(MI)) {
1835 case HexagonII::Absolute :
1836 return Hexagon::getBasedWithImmOffset(MI->getOpcode());
1837 case HexagonII::BaseImmOffset :
1838 return Hexagon::getBaseWithRegOffset(MI->getOpcode());
1846 bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const {
1847 return (Opcode == Hexagon::JMP_t) ||
1848 (Opcode == Hexagon::JMP_f) ||
1849 (Opcode == Hexagon::JMP_tnew_t) ||
1850 (Opcode == Hexagon::JMP_fnew_t) ||
1851 (Opcode == Hexagon::JMP_tnew_nt) ||
1852 (Opcode == Hexagon::JMP_fnew_nt);
1855 bool HexagonInstrInfo::PredOpcodeHasNot(Opcode_t Opcode) const {
1856 return (Opcode == Hexagon::JMP_f) ||
1857 (Opcode == Hexagon::JMP_fnew_t) ||
1858 (Opcode == Hexagon::JMP_fnew_nt);