1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/raw_ostream.h"
29 #define GET_INSTRINFO_CTOR_DTOR
30 #define GET_INSTRMAP_INFO
31 #include "HexagonGenInstrInfo.inc"
32 #include "HexagonGenDFAPacketizer.inc"
36 #define DEBUG_TYPE "hexagon-instrinfo"
39 /// Constants for Hexagon instructions.
41 const int Hexagon_MEMW_OFFSET_MAX = 4095;
42 const int Hexagon_MEMW_OFFSET_MIN = -4096;
43 const int Hexagon_MEMD_OFFSET_MAX = 8191;
44 const int Hexagon_MEMD_OFFSET_MIN = -8192;
45 const int Hexagon_MEMH_OFFSET_MAX = 2047;
46 const int Hexagon_MEMH_OFFSET_MIN = -2048;
47 const int Hexagon_MEMB_OFFSET_MAX = 1023;
48 const int Hexagon_MEMB_OFFSET_MIN = -1024;
49 const int Hexagon_ADDI_OFFSET_MAX = 32767;
50 const int Hexagon_ADDI_OFFSET_MIN = -32768;
51 const int Hexagon_MEMD_AUTOINC_MAX = 56;
52 const int Hexagon_MEMD_AUTOINC_MIN = -64;
53 const int Hexagon_MEMW_AUTOINC_MAX = 28;
54 const int Hexagon_MEMW_AUTOINC_MIN = -32;
55 const int Hexagon_MEMH_AUTOINC_MAX = 14;
56 const int Hexagon_MEMH_AUTOINC_MIN = -16;
57 const int Hexagon_MEMB_AUTOINC_MAX = 7;
58 const int Hexagon_MEMB_AUTOINC_MIN = -8;
60 // Pin the vtable to this file.
61 void HexagonInstrInfo::anchor() {}
63 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
64 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
65 RI(ST), Subtarget(ST) {
69 /// isLoadFromStackSlot - If the specified machine instruction is a direct
70 /// load from a stack slot, return the virtual or physical register number of
71 /// the destination along with the FrameIndex of the loaded stack slot. If
72 /// not, return 0. This predicate must return 0 if the instruction has
73 /// any side effects other than loading from the stack slot.
74 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
75 int &FrameIndex) const {
78 switch (MI->getOpcode()) {
85 if (MI->getOperand(2).isFI() &&
86 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
87 FrameIndex = MI->getOperand(2).getIndex();
88 return MI->getOperand(0).getReg();
96 /// isStoreToStackSlot - If the specified machine instruction is a direct
97 /// store to a stack slot, return the virtual or physical register number of
98 /// the source reg along with the FrameIndex of the loaded stack slot. If
99 /// not, return 0. This predicate must return 0 if the instruction has
100 /// any side effects other than storing to the stack slot.
101 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
102 int &FrameIndex) const {
103 switch (MI->getOpcode()) {
109 if (MI->getOperand(2).isFI() &&
110 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
111 FrameIndex = MI->getOperand(0).getIndex();
112 return MI->getOperand(2).getReg();
121 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
122 MachineBasicBlock *FBB,
123 const SmallVectorImpl<MachineOperand> &Cond,
126 int BOpc = Hexagon::JMP;
127 int BccOpc = Hexagon::JMP_t;
129 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
132 // Check if ReverseBranchCondition has asked to reverse this branch
133 // If we want to reverse the branch an odd number of times, we want
135 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
136 BccOpc = Hexagon::JMP_f;
142 // Due to a bug in TailMerging/CFG Optimization, we need to add a
143 // special case handling of a predicated jump followed by an
144 // unconditional jump. If not, Tail Merging and CFG Optimization go
145 // into an infinite loop.
146 MachineBasicBlock *NewTBB, *NewFBB;
147 SmallVector<MachineOperand, 4> Cond;
148 MachineInstr *Term = MBB.getFirstTerminator();
149 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
151 MachineBasicBlock *NextBB =
152 std::next(MachineFunction::iterator(&MBB));
153 if (NewTBB == NextBB) {
154 ReverseBranchCondition(Cond);
156 return InsertBranch(MBB, TBB, 0, Cond, DL);
159 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
162 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
167 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
168 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
174 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
175 MachineBasicBlock *&TBB,
176 MachineBasicBlock *&FBB,
177 SmallVectorImpl<MachineOperand> &Cond,
178 bool AllowModify) const {
182 // If the block has no terminators, it just falls into the block after it.
183 MachineBasicBlock::instr_iterator I = MBB.instr_end();
184 if (I == MBB.instr_begin())
187 // A basic block may looks like this:
197 // It has two succs but does not have a terminator
198 // Don't know how to handle it.
203 } while (I != MBB.instr_begin());
208 while (I->isDebugValue()) {
209 if (I == MBB.instr_begin())
214 // Delete the JMP if it's equivalent to a fall-through.
215 if (AllowModify && I->getOpcode() == Hexagon::JMP &&
216 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
217 DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
218 I->eraseFromParent();
220 if (I == MBB.instr_begin())
224 if (!isUnpredicatedTerminator(I))
227 // Get the last instruction in the block.
228 MachineInstr *LastInst = I;
229 MachineInstr *SecondLastInst = NULL;
230 // Find one more terminator if present.
232 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(I)) {
236 // This is a third branch.
239 if (I == MBB.instr_begin())
244 int LastOpcode = LastInst->getOpcode();
246 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
247 bool LastOpcodeHasNot = PredOpcodeHasNot(LastOpcode);
249 // If there is only one terminator instruction, process it.
250 if (LastInst && !SecondLastInst) {
251 if (LastOpcode == Hexagon::JMP) {
252 TBB = LastInst->getOperand(0).getMBB();
255 if (LastOpcode == Hexagon::ENDLOOP0) {
256 TBB = LastInst->getOperand(0).getMBB();
257 Cond.push_back(LastInst->getOperand(0));
260 if (LastOpcodeHasJMP_c) {
261 TBB = LastInst->getOperand(1).getMBB();
262 if (LastOpcodeHasNot) {
263 Cond.push_back(MachineOperand::CreateImm(0));
265 Cond.push_back(LastInst->getOperand(0));
268 // Otherwise, don't know what this is.
272 int SecLastOpcode = SecondLastInst->getOpcode();
274 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
275 bool SecLastOpcodeHasNot = PredOpcodeHasNot(SecLastOpcode);
276 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::JMP)) {
277 TBB = SecondLastInst->getOperand(1).getMBB();
278 if (SecLastOpcodeHasNot)
279 Cond.push_back(MachineOperand::CreateImm(0));
280 Cond.push_back(SecondLastInst->getOperand(0));
281 FBB = LastInst->getOperand(0).getMBB();
285 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
286 // executed, so remove it.
287 if (SecLastOpcode == Hexagon::JMP && LastOpcode == Hexagon::JMP) {
288 TBB = SecondLastInst->getOperand(0).getMBB();
291 I->eraseFromParent();
295 // If the block ends with an ENDLOOP, and JMP, handle it.
296 if (SecLastOpcode == Hexagon::ENDLOOP0 &&
297 LastOpcode == Hexagon::JMP) {
298 TBB = SecondLastInst->getOperand(0).getMBB();
299 Cond.push_back(SecondLastInst->getOperand(0));
300 FBB = LastInst->getOperand(0).getMBB();
304 // Otherwise, can't handle this.
309 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
310 int BOpc = Hexagon::JMP;
311 int BccOpc = Hexagon::JMP_t;
312 int BccOpcNot = Hexagon::JMP_f;
314 MachineBasicBlock::iterator I = MBB.end();
315 if (I == MBB.begin()) return 0;
317 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
318 I->getOpcode() != BccOpcNot)
321 // Remove the branch.
322 I->eraseFromParent();
326 if (I == MBB.begin()) return 1;
328 if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
331 // Remove the branch.
332 I->eraseFromParent();
337 /// \brief For a comparison instruction, return the source registers in
338 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
339 /// compares against in CmpValue. Return true if the comparison instruction
341 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
342 unsigned &SrcReg, unsigned &SrcReg2,
343 int &Mask, int &Value) const {
344 unsigned Opc = MI->getOpcode();
346 // Set mask and the first source register.
348 case Hexagon::CMPEHexagon4rr:
349 case Hexagon::CMPEQri:
350 case Hexagon::CMPEQrr:
351 case Hexagon::CMPGT64rr:
352 case Hexagon::CMPGTU64rr:
353 case Hexagon::CMPGTUri:
354 case Hexagon::CMPGTUrr:
355 case Hexagon::CMPGTri:
356 case Hexagon::CMPGTrr:
357 SrcReg = MI->getOperand(1).getReg();
360 case Hexagon::CMPbEQri_V4:
361 case Hexagon::CMPbEQrr_sbsb_V4:
362 case Hexagon::CMPbEQrr_ubub_V4:
363 case Hexagon::CMPbGTUri_V4:
364 case Hexagon::CMPbGTUrr_V4:
365 case Hexagon::CMPbGTrr_V4:
366 SrcReg = MI->getOperand(1).getReg();
369 case Hexagon::CMPhEQri_V4:
370 case Hexagon::CMPhEQrr_shl_V4:
371 case Hexagon::CMPhEQrr_xor_V4:
372 case Hexagon::CMPhGTUri_V4:
373 case Hexagon::CMPhGTUrr_V4:
374 case Hexagon::CMPhGTrr_shl_V4:
375 SrcReg = MI->getOperand(1).getReg();
380 // Set the value/second source register.
382 case Hexagon::CMPEHexagon4rr:
383 case Hexagon::CMPEQrr:
384 case Hexagon::CMPGT64rr:
385 case Hexagon::CMPGTU64rr:
386 case Hexagon::CMPGTUrr:
387 case Hexagon::CMPGTrr:
388 case Hexagon::CMPbEQrr_sbsb_V4:
389 case Hexagon::CMPbEQrr_ubub_V4:
390 case Hexagon::CMPbGTUrr_V4:
391 case Hexagon::CMPbGTrr_V4:
392 case Hexagon::CMPhEQrr_shl_V4:
393 case Hexagon::CMPhEQrr_xor_V4:
394 case Hexagon::CMPhGTUrr_V4:
395 case Hexagon::CMPhGTrr_shl_V4:
396 SrcReg2 = MI->getOperand(2).getReg();
399 case Hexagon::CMPEQri:
400 case Hexagon::CMPGTUri:
401 case Hexagon::CMPGTri:
402 case Hexagon::CMPbEQri_V4:
403 case Hexagon::CMPbGTUri_V4:
404 case Hexagon::CMPhEQri_V4:
405 case Hexagon::CMPhGTUri_V4:
407 Value = MI->getOperand(2).getImm();
415 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
416 MachineBasicBlock::iterator I, DebugLoc DL,
417 unsigned DestReg, unsigned SrcReg,
418 bool KillSrc) const {
419 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
420 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
423 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
424 BuildMI(MBB, I, DL, get(Hexagon::TFR64), DestReg).addReg(SrcReg);
427 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
428 // Map Pd = Ps to Pd = or(Ps, Ps).
429 BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
430 DestReg).addReg(SrcReg).addReg(SrcReg);
433 if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
434 Hexagon::IntRegsRegClass.contains(SrcReg)) {
435 // We can have an overlap between single and double reg: r1:0 = r0.
436 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
438 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
439 Hexagon::subreg_hireg))).addImm(0);
441 // r1:0 = r1 or no overlap.
442 BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
443 Hexagon::subreg_loreg))).addReg(SrcReg);
444 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
445 Hexagon::subreg_hireg))).addImm(0);
449 if (Hexagon::CRRegsRegClass.contains(DestReg) &&
450 Hexagon::IntRegsRegClass.contains(SrcReg)) {
451 BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
454 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
455 Hexagon::IntRegsRegClass.contains(DestReg)) {
456 BuildMI(MBB, I, DL, get(Hexagon::TFR_RsPd), DestReg).
457 addReg(SrcReg, getKillRegState(KillSrc));
460 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
461 Hexagon::PredRegsRegClass.contains(DestReg)) {
462 BuildMI(MBB, I, DL, get(Hexagon::TFR_PdRs), DestReg).
463 addReg(SrcReg, getKillRegState(KillSrc));
467 llvm_unreachable("Unimplemented");
471 void HexagonInstrInfo::
472 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
473 unsigned SrcReg, bool isKill, int FI,
474 const TargetRegisterClass *RC,
475 const TargetRegisterInfo *TRI) const {
477 DebugLoc DL = MBB.findDebugLoc(I);
478 MachineFunction &MF = *MBB.getParent();
479 MachineFrameInfo &MFI = *MF.getFrameInfo();
480 unsigned Align = MFI.getObjectAlignment(FI);
482 MachineMemOperand *MMO =
483 MF.getMachineMemOperand(
484 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
485 MachineMemOperand::MOStore,
486 MFI.getObjectSize(FI),
489 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
490 BuildMI(MBB, I, DL, get(Hexagon::STriw))
491 .addFrameIndex(FI).addImm(0)
492 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
493 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
494 BuildMI(MBB, I, DL, get(Hexagon::STrid))
495 .addFrameIndex(FI).addImm(0)
496 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
497 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
498 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
499 .addFrameIndex(FI).addImm(0)
500 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
502 llvm_unreachable("Unimplemented");
507 void HexagonInstrInfo::storeRegToAddr(
508 MachineFunction &MF, unsigned SrcReg,
510 SmallVectorImpl<MachineOperand> &Addr,
511 const TargetRegisterClass *RC,
512 SmallVectorImpl<MachineInstr*> &NewMIs) const
514 llvm_unreachable("Unimplemented");
518 void HexagonInstrInfo::
519 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
520 unsigned DestReg, int FI,
521 const TargetRegisterClass *RC,
522 const TargetRegisterInfo *TRI) const {
523 DebugLoc DL = MBB.findDebugLoc(I);
524 MachineFunction &MF = *MBB.getParent();
525 MachineFrameInfo &MFI = *MF.getFrameInfo();
526 unsigned Align = MFI.getObjectAlignment(FI);
528 MachineMemOperand *MMO =
529 MF.getMachineMemOperand(
530 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
531 MachineMemOperand::MOLoad,
532 MFI.getObjectSize(FI),
534 if (RC == &Hexagon::IntRegsRegClass) {
535 BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)
536 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
537 } else if (RC == &Hexagon::DoubleRegsRegClass) {
538 BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
539 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
540 } else if (RC == &Hexagon::PredRegsRegClass) {
541 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
542 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
544 llvm_unreachable("Can't store this register to stack slot");
549 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
550 SmallVectorImpl<MachineOperand> &Addr,
551 const TargetRegisterClass *RC,
552 SmallVectorImpl<MachineInstr*> &NewMIs) const {
553 llvm_unreachable("Unimplemented");
557 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
559 const SmallVectorImpl<unsigned> &Ops,
561 // Hexagon_TODO: Implement.
565 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
567 MachineRegisterInfo &RegInfo = MF->getRegInfo();
568 const TargetRegisterClass *TRC;
570 TRC = &Hexagon::PredRegsRegClass;
571 } else if (VT == MVT::i32 || VT == MVT::f32) {
572 TRC = &Hexagon::IntRegsRegClass;
573 } else if (VT == MVT::i64 || VT == MVT::f64) {
574 TRC = &Hexagon::DoubleRegsRegClass;
576 llvm_unreachable("Cannot handle this register class");
579 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
583 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
584 // Constant extenders are allowed only for V4 and above.
585 if (!Subtarget.hasV4TOps())
588 const MCInstrDesc &MID = MI->getDesc();
589 const uint64_t F = MID.TSFlags;
590 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
593 // TODO: This is largely obsolete now. Will need to be removed
594 // in consecutive patches.
595 switch(MI->getOpcode()) {
596 // TFR_FI Remains a special case.
597 case Hexagon::TFR_FI:
605 // This returns true in two cases:
606 // - The OP code itself indicates that this is an extended instruction.
607 // - One of MOs has been marked with HMOTF_ConstExtended flag.
608 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
609 // First check if this is permanently extended op code.
610 const uint64_t F = MI->getDesc().TSFlags;
611 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
613 // Use MO operand flags to determine if one of MI's operands
614 // has HMOTF_ConstExtended flag set.
615 for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
616 E = MI->operands_end(); I != E; ++I) {
617 if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
623 bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
624 return MI->getDesc().isBranch();
627 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
628 if (isNewValueJump(MI))
631 if (isNewValueStore(MI))
637 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
638 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
641 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
642 bool isPred = MI->getDesc().isPredicable();
647 const int Opc = MI->getOpcode();
651 return isInt<12>(MI->getOperand(1).getImm());
654 case Hexagon::STrid_indexed:
655 return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
658 case Hexagon::STriw_indexed:
659 case Hexagon::STriw_nv_V4:
660 return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
663 case Hexagon::STrih_indexed:
664 case Hexagon::STrih_nv_V4:
665 return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
668 case Hexagon::STrib_indexed:
669 case Hexagon::STrib_nv_V4:
670 return isUInt<6>(MI->getOperand(1).getImm());
673 case Hexagon::LDrid_indexed:
674 return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
677 case Hexagon::LDriw_indexed:
678 return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
681 case Hexagon::LDriuh:
682 case Hexagon::LDrih_indexed:
683 case Hexagon::LDriuh_indexed:
684 return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
687 case Hexagon::LDriub:
688 case Hexagon::LDrib_indexed:
689 case Hexagon::LDriub_indexed:
690 return isUInt<6>(MI->getOperand(2).getImm());
692 case Hexagon::POST_LDrid:
693 return isShiftedInt<4,3>(MI->getOperand(3).getImm());
695 case Hexagon::POST_LDriw:
696 return isShiftedInt<4,2>(MI->getOperand(3).getImm());
698 case Hexagon::POST_LDrih:
699 case Hexagon::POST_LDriuh:
700 return isShiftedInt<4,1>(MI->getOperand(3).getImm());
702 case Hexagon::POST_LDrib:
703 case Hexagon::POST_LDriub:
704 return isInt<4>(MI->getOperand(3).getImm());
706 case Hexagon::STrib_imm_V4:
707 case Hexagon::STrih_imm_V4:
708 case Hexagon::STriw_imm_V4:
709 return (isUInt<6>(MI->getOperand(1).getImm()) &&
710 isInt<6>(MI->getOperand(2).getImm()));
712 case Hexagon::ADD_ri:
713 return isInt<8>(MI->getOperand(2).getImm());
721 return Subtarget.hasV4TOps();
727 // This function performs the following inversiones:
732 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
734 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
735 : Hexagon::getTruePredOpcode(Opc);
736 if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
737 return InvPredOpcode;
740 default: llvm_unreachable("Unexpected predicated instruction");
741 case Hexagon::COMBINE_rr_cPt:
742 return Hexagon::COMBINE_rr_cNotPt;
743 case Hexagon::COMBINE_rr_cNotPt:
744 return Hexagon::COMBINE_rr_cPt;
747 case Hexagon::DEALLOC_RET_cPt_V4:
748 return Hexagon::DEALLOC_RET_cNotPt_V4;
749 case Hexagon::DEALLOC_RET_cNotPt_V4:
750 return Hexagon::DEALLOC_RET_cPt_V4;
754 // New Value Store instructions.
755 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
756 const uint64_t F = MI->getDesc().TSFlags;
758 return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
761 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
762 const uint64_t F = get(Opcode).TSFlags;
764 return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
767 int HexagonInstrInfo::
768 getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
769 enum Hexagon::PredSense inPredSense;
770 inPredSense = invertPredicate ? Hexagon::PredSense_false :
771 Hexagon::PredSense_true;
772 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
773 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
776 // This switch case will be removed once all the instructions have been
777 // modified to use relation maps.
779 case Hexagon::TFRI_f:
780 return !invertPredicate ? Hexagon::TFRI_cPt_f :
781 Hexagon::TFRI_cNotPt_f;
782 case Hexagon::COMBINE_rr:
783 return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
784 Hexagon::COMBINE_rr_cNotPt;
787 case Hexagon::STriw_f:
788 return !invertPredicate ? Hexagon::STriw_cPt :
789 Hexagon::STriw_cNotPt;
790 case Hexagon::STriw_indexed_f:
791 return !invertPredicate ? Hexagon::STriw_indexed_cPt :
792 Hexagon::STriw_indexed_cNotPt;
795 case Hexagon::DEALLOC_RET_V4:
796 return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
797 Hexagon::DEALLOC_RET_cNotPt_V4;
799 llvm_unreachable("Unexpected predicable instruction");
803 bool HexagonInstrInfo::
804 PredicateInstruction(MachineInstr *MI,
805 const SmallVectorImpl<MachineOperand> &Cond) const {
806 int Opc = MI->getOpcode();
807 assert (isPredicable(MI) && "Expected predicable instruction");
808 bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
809 (Cond[0].getImm() == 0));
811 // This will change MI's opcode to its predicate version.
812 // However, its operand list is still the old one, i.e. the
813 // non-predicate one.
814 MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
817 unsigned int GAIdx = 0;
819 // Indicates whether the current MI has a GlobalAddress operand
820 bool hasGAOpnd = false;
821 std::vector<MachineOperand> tmpOpnds;
823 // Indicates whether we need to shift operands to right.
824 bool needShift = true;
826 // The predicate is ALWAYS the FIRST input operand !!!
827 if (MI->getNumOperands() == 0) {
828 // The non-predicate version of MI does not take any operands,
829 // i.e. no outs and no ins. In this condition, the predicate
830 // operand will be directly placed at Operands[0]. No operand
836 else if ( MI->getOperand(MI->getNumOperands()-1).isReg()
837 && MI->getOperand(MI->getNumOperands()-1).isDef()
838 && !MI->getOperand(MI->getNumOperands()-1).isImplicit()) {
839 // The non-predicate version of MI does not have any input operands.
840 // In this condition, we extend the length of Operands[] by one and
841 // copy the original last operand to the newly allocated slot.
842 // At this moment, it is just a place holder. Later, we will put
843 // predicate operand directly into it. No operand shift is needed.
844 // Example: r0=BARRIER (this is a faked insn used here for illustration)
845 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
847 oper = MI->getNumOperands() - 2;
850 // We need to right shift all input operands by one. Duplicate the
851 // last operand into the newly allocated slot.
852 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
857 // Operands[ MI->getNumOperands() - 2 ] has been copied into
858 // Operands[ MI->getNumOperands() - 1 ], so we start from
859 // Operands[ MI->getNumOperands() - 3 ].
860 // oper is a signed int.
861 // It is ok if "MI->getNumOperands()-3" is -3, -2, or -1.
862 for (oper = MI->getNumOperands() - 3; oper >= 0; --oper)
864 MachineOperand &MO = MI->getOperand(oper);
866 // Opnd[0] Opnd[1] Opnd[2] Opnd[3] Opnd[4] Opnd[5] Opnd[6] Opnd[7]
867 // <Def0> <Def1> <Use0> <Use1> <ImpDef0> <ImpDef1> <ImpUse0> <ImpUse1>
871 // Predicate Operand here
872 if (MO.isReg() && !MO.isUse() && !MO.isImplicit()) {
876 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
877 MO.isImplicit(), MO.isKill(),
878 MO.isDead(), MO.isUndef(),
881 else if (MO.isImm()) {
882 MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
884 else if (MO.isGlobal()) {
885 // MI can not have more than one GlobalAddress operand.
886 assert(hasGAOpnd == false && "MI can only have one GlobalAddress opnd");
888 // There is no member function called "ChangeToGlobalAddress" in the
889 // MachineOperand class (not like "ChangeToRegister" and
890 // "ChangeToImmediate"). So we have to remove them from Operands[] list
891 // first, and then add them back after we have inserted the predicate
892 // operand. tmpOpnds[] is to remember these operands before we remove
894 tmpOpnds.push_back(MO);
896 // Operands[oper] is a GlobalAddress operand;
897 // Operands[oper+1] has been copied into Operands[oper+2];
903 assert(false && "Unexpected operand type");
908 int regPos = invertJump ? 1 : 0;
909 MachineOperand PredMO = Cond[regPos];
911 // [oper] now points to the last explicit Def. Predicate operand must be
912 // located at [oper+1]. See diagram above.
913 // This assumes that the predicate is always the first operand,
914 // i.e. Operands[0+numResults], in the set of inputs
915 // It is better to have an assert here to check this. But I don't know how
916 // to write this assert because findFirstPredOperandIdx() would return -1
917 if (oper < -1) oper = -1;
919 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
920 PredMO.isImplicit(), false,
921 PredMO.isDead(), PredMO.isUndef(),
924 MachineRegisterInfo &RegInfo = MI->getParent()->getParent()->getRegInfo();
925 RegInfo.clearKillFlags(PredMO.getReg());
931 // Operands[GAIdx] is the original GlobalAddress operand, which is
932 // already copied into tmpOpnds[0].
933 // Operands[GAIdx] now stores a copy of Operands[GAIdx-1]
934 // Operands[GAIdx+1] has already been copied into Operands[GAIdx+2],
935 // so we start from [GAIdx+2]
936 for (i = GAIdx + 2; i < MI->getNumOperands(); ++i)
937 tmpOpnds.push_back(MI->getOperand(i));
939 // Remove all operands in range [ (GAIdx+1) ... (MI->getNumOperands()-1) ]
940 // It is very important that we always remove from the end of Operands[]
941 // MI->getNumOperands() is at least 2 if program goes to here.
942 for (i = MI->getNumOperands() - 1; i > GAIdx; --i)
943 MI->RemoveOperand(i);
945 for (i = 0; i < tmpOpnds.size(); ++i)
946 MI->addOperand(tmpOpnds[i]);
955 isProfitableToIfCvt(MachineBasicBlock &MBB,
957 unsigned ExtraPredCycles,
958 const BranchProbability &Probability) const {
965 isProfitableToIfCvt(MachineBasicBlock &TMBB,
967 unsigned ExtraTCycles,
968 MachineBasicBlock &FMBB,
970 unsigned ExtraFCycles,
971 const BranchProbability &Probability) const {
975 // Returns true if an instruction is predicated irrespective of the predicate
976 // sense. For example, all of the following will return true.
977 // if (p0) R1 = add(R2, R3)
978 // if (!p0) R1 = add(R2, R3)
979 // if (p0.new) R1 = add(R2, R3)
980 // if (!p0.new) R1 = add(R2, R3)
981 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
982 const uint64_t F = MI->getDesc().TSFlags;
984 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
987 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
988 const uint64_t F = get(Opcode).TSFlags;
990 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
993 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
994 const uint64_t F = MI->getDesc().TSFlags;
996 assert(isPredicated(MI));
997 return (!((F >> HexagonII::PredicatedFalsePos) &
998 HexagonII::PredicatedFalseMask));
1001 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
1002 const uint64_t F = get(Opcode).TSFlags;
1004 // Make sure that the instruction is predicated.
1005 assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1006 return (!((F >> HexagonII::PredicatedFalsePos) &
1007 HexagonII::PredicatedFalseMask));
1010 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
1011 const uint64_t F = MI->getDesc().TSFlags;
1013 assert(isPredicated(MI));
1014 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1017 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
1018 const uint64_t F = get(Opcode).TSFlags;
1020 assert(isPredicated(Opcode));
1021 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1024 // Returns true, if a ST insn can be promoted to a new-value store.
1025 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
1026 const HexagonRegisterInfo& QRI = getRegisterInfo();
1027 const uint64_t F = MI->getDesc().TSFlags;
1029 return ((F >> HexagonII::mayNVStorePos) &
1030 HexagonII::mayNVStoreMask &
1031 QRI.Subtarget.hasV4TOps());
1035 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
1036 std::vector<MachineOperand> &Pred) const {
1037 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
1038 MachineOperand MO = MI->getOperand(oper);
1039 if (MO.isReg() && MO.isDef()) {
1040 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
1041 if (RC == &Hexagon::PredRegsRegClass) {
1053 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
1054 const SmallVectorImpl<MachineOperand> &Pred2) const {
1061 // We indicate that we want to reverse the branch by
1062 // inserting a 0 at the beginning of the Cond vector.
1064 bool HexagonInstrInfo::
1065 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1066 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
1067 Cond.erase(Cond.begin());
1069 Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
1075 bool HexagonInstrInfo::
1076 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
1077 const BranchProbability &Probability) const {
1078 return (NumInstrs <= 4);
1081 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
1082 switch (MI->getOpcode()) {
1083 default: return false;
1084 case Hexagon::DEALLOC_RET_V4 :
1085 case Hexagon::DEALLOC_RET_cPt_V4 :
1086 case Hexagon::DEALLOC_RET_cNotPt_V4 :
1087 case Hexagon::DEALLOC_RET_cdnPnt_V4 :
1088 case Hexagon::DEALLOC_RET_cNotdnPnt_V4 :
1089 case Hexagon::DEALLOC_RET_cdnPt_V4 :
1090 case Hexagon::DEALLOC_RET_cNotdnPt_V4 :
1096 bool HexagonInstrInfo::
1097 isValidOffset(const int Opcode, const int Offset) const {
1098 // This function is to check whether the "Offset" is in the correct range of
1099 // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
1100 // inserted to calculate the final address. Due to this reason, the function
1101 // assumes that the "Offset" has correct alignment.
1102 // We used to assert if the offset was not properly aligned, however,
1103 // there are cases where a misaligned pointer recast can cause this
1104 // problem, and we need to allow for it. The front end warns of such
1105 // misaligns with respect to load size.
1109 case Hexagon::LDriw:
1110 case Hexagon::LDriw_indexed:
1111 case Hexagon::LDriw_f:
1112 case Hexagon::STriw_indexed:
1113 case Hexagon::STriw:
1114 case Hexagon::STriw_f:
1115 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
1116 (Offset <= Hexagon_MEMW_OFFSET_MAX);
1118 case Hexagon::LDrid:
1119 case Hexagon::LDrid_indexed:
1120 case Hexagon::LDrid_f:
1121 case Hexagon::STrid:
1122 case Hexagon::STrid_indexed:
1123 case Hexagon::STrid_f:
1124 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
1125 (Offset <= Hexagon_MEMD_OFFSET_MAX);
1127 case Hexagon::LDrih:
1128 case Hexagon::LDriuh:
1129 case Hexagon::STrih:
1130 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
1131 (Offset <= Hexagon_MEMH_OFFSET_MAX);
1133 case Hexagon::LDrib:
1134 case Hexagon::STrib:
1135 case Hexagon::LDriub:
1136 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
1137 (Offset <= Hexagon_MEMB_OFFSET_MAX);
1139 case Hexagon::ADD_ri:
1140 case Hexagon::TFR_FI:
1141 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
1142 (Offset <= Hexagon_ADDI_OFFSET_MAX);
1144 case Hexagon::MemOPw_ADDi_V4 :
1145 case Hexagon::MemOPw_SUBi_V4 :
1146 case Hexagon::MemOPw_ADDr_V4 :
1147 case Hexagon::MemOPw_SUBr_V4 :
1148 case Hexagon::MemOPw_ANDr_V4 :
1149 case Hexagon::MemOPw_ORr_V4 :
1150 return (0 <= Offset && Offset <= 255);
1152 case Hexagon::MemOPh_ADDi_V4 :
1153 case Hexagon::MemOPh_SUBi_V4 :
1154 case Hexagon::MemOPh_ADDr_V4 :
1155 case Hexagon::MemOPh_SUBr_V4 :
1156 case Hexagon::MemOPh_ANDr_V4 :
1157 case Hexagon::MemOPh_ORr_V4 :
1158 return (0 <= Offset && Offset <= 127);
1160 case Hexagon::MemOPb_ADDi_V4 :
1161 case Hexagon::MemOPb_SUBi_V4 :
1162 case Hexagon::MemOPb_ADDr_V4 :
1163 case Hexagon::MemOPb_SUBr_V4 :
1164 case Hexagon::MemOPb_ANDr_V4 :
1165 case Hexagon::MemOPb_ORr_V4 :
1166 return (0 <= Offset && Offset <= 63);
1168 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
1169 // any size. Later pass knows how to handle it.
1170 case Hexagon::STriw_pred:
1171 case Hexagon::LDriw_pred:
1174 case Hexagon::LOOP0_i:
1175 return isUInt<10>(Offset);
1177 // INLINEASM is very special.
1178 case Hexagon::INLINEASM:
1182 llvm_unreachable("No offset range is defined for this opcode. "
1183 "Please define it in the above switch statement!");
1188 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
1190 bool HexagonInstrInfo::
1191 isValidAutoIncImm(const EVT VT, const int Offset) const {
1193 if (VT == MVT::i64) {
1194 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
1195 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
1196 (Offset & 0x7) == 0);
1198 if (VT == MVT::i32) {
1199 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
1200 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
1201 (Offset & 0x3) == 0);
1203 if (VT == MVT::i16) {
1204 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
1205 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
1206 (Offset & 0x1) == 0);
1208 if (VT == MVT::i8) {
1209 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
1210 Offset <= Hexagon_MEMB_AUTOINC_MAX);
1212 llvm_unreachable("Not an auto-inc opc!");
1216 bool HexagonInstrInfo::
1217 isMemOp(const MachineInstr *MI) const {
1218 // return MI->getDesc().mayLoad() && MI->getDesc().mayStore();
1220 switch (MI->getOpcode())
1222 default: return false;
1223 case Hexagon::MemOPw_ADDi_V4 :
1224 case Hexagon::MemOPw_SUBi_V4 :
1225 case Hexagon::MemOPw_ADDr_V4 :
1226 case Hexagon::MemOPw_SUBr_V4 :
1227 case Hexagon::MemOPw_ANDr_V4 :
1228 case Hexagon::MemOPw_ORr_V4 :
1229 case Hexagon::MemOPh_ADDi_V4 :
1230 case Hexagon::MemOPh_SUBi_V4 :
1231 case Hexagon::MemOPh_ADDr_V4 :
1232 case Hexagon::MemOPh_SUBr_V4 :
1233 case Hexagon::MemOPh_ANDr_V4 :
1234 case Hexagon::MemOPh_ORr_V4 :
1235 case Hexagon::MemOPb_ADDi_V4 :
1236 case Hexagon::MemOPb_SUBi_V4 :
1237 case Hexagon::MemOPb_ADDr_V4 :
1238 case Hexagon::MemOPb_SUBr_V4 :
1239 case Hexagon::MemOPb_ANDr_V4 :
1240 case Hexagon::MemOPb_ORr_V4 :
1241 case Hexagon::MemOPb_SETBITi_V4:
1242 case Hexagon::MemOPh_SETBITi_V4:
1243 case Hexagon::MemOPw_SETBITi_V4:
1244 case Hexagon::MemOPb_CLRBITi_V4:
1245 case Hexagon::MemOPh_CLRBITi_V4:
1246 case Hexagon::MemOPw_CLRBITi_V4:
1253 bool HexagonInstrInfo::
1254 isSpillPredRegOp(const MachineInstr *MI) const {
1255 switch (MI->getOpcode()) {
1256 default: return false;
1257 case Hexagon::STriw_pred :
1258 case Hexagon::LDriw_pred :
1263 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
1264 switch (MI->getOpcode()) {
1265 default: return false;
1266 case Hexagon::CMPEQrr:
1267 case Hexagon::CMPEQri:
1268 case Hexagon::CMPGTrr:
1269 case Hexagon::CMPGTri:
1270 case Hexagon::CMPGTUrr:
1271 case Hexagon::CMPGTUri:
1276 bool HexagonInstrInfo::
1277 isConditionalTransfer (const MachineInstr *MI) const {
1278 switch (MI->getOpcode()) {
1279 default: return false;
1280 case Hexagon::TFR_cPt:
1281 case Hexagon::TFR_cNotPt:
1282 case Hexagon::TFRI_cPt:
1283 case Hexagon::TFRI_cNotPt:
1284 case Hexagon::TFR_cdnPt:
1285 case Hexagon::TFR_cdnNotPt:
1286 case Hexagon::TFRI_cdnPt:
1287 case Hexagon::TFRI_cdnNotPt:
1292 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
1293 const HexagonRegisterInfo& QRI = getRegisterInfo();
1294 switch (MI->getOpcode())
1296 default: return false;
1297 case Hexagon::ADD_ri_cPt:
1298 case Hexagon::ADD_ri_cNotPt:
1299 case Hexagon::ADD_rr_cPt:
1300 case Hexagon::ADD_rr_cNotPt:
1301 case Hexagon::XOR_rr_cPt:
1302 case Hexagon::XOR_rr_cNotPt:
1303 case Hexagon::AND_rr_cPt:
1304 case Hexagon::AND_rr_cNotPt:
1305 case Hexagon::OR_rr_cPt:
1306 case Hexagon::OR_rr_cNotPt:
1307 case Hexagon::SUB_rr_cPt:
1308 case Hexagon::SUB_rr_cNotPt:
1309 case Hexagon::COMBINE_rr_cPt:
1310 case Hexagon::COMBINE_rr_cNotPt:
1312 case Hexagon::ASLH_cPt_V4:
1313 case Hexagon::ASLH_cNotPt_V4:
1314 case Hexagon::ASRH_cPt_V4:
1315 case Hexagon::ASRH_cNotPt_V4:
1316 case Hexagon::SXTB_cPt_V4:
1317 case Hexagon::SXTB_cNotPt_V4:
1318 case Hexagon::SXTH_cPt_V4:
1319 case Hexagon::SXTH_cNotPt_V4:
1320 case Hexagon::ZXTB_cPt_V4:
1321 case Hexagon::ZXTB_cNotPt_V4:
1322 case Hexagon::ZXTH_cPt_V4:
1323 case Hexagon::ZXTH_cNotPt_V4:
1324 return QRI.Subtarget.hasV4TOps();
1328 bool HexagonInstrInfo::
1329 isConditionalLoad (const MachineInstr* MI) const {
1330 const HexagonRegisterInfo& QRI = getRegisterInfo();
1331 switch (MI->getOpcode())
1333 default: return false;
1334 case Hexagon::LDrid_cPt :
1335 case Hexagon::LDrid_cNotPt :
1336 case Hexagon::LDrid_indexed_cPt :
1337 case Hexagon::LDrid_indexed_cNotPt :
1338 case Hexagon::LDriw_cPt :
1339 case Hexagon::LDriw_cNotPt :
1340 case Hexagon::LDriw_indexed_cPt :
1341 case Hexagon::LDriw_indexed_cNotPt :
1342 case Hexagon::LDrih_cPt :
1343 case Hexagon::LDrih_cNotPt :
1344 case Hexagon::LDrih_indexed_cPt :
1345 case Hexagon::LDrih_indexed_cNotPt :
1346 case Hexagon::LDrib_cPt :
1347 case Hexagon::LDrib_cNotPt :
1348 case Hexagon::LDrib_indexed_cPt :
1349 case Hexagon::LDrib_indexed_cNotPt :
1350 case Hexagon::LDriuh_cPt :
1351 case Hexagon::LDriuh_cNotPt :
1352 case Hexagon::LDriuh_indexed_cPt :
1353 case Hexagon::LDriuh_indexed_cNotPt :
1354 case Hexagon::LDriub_cPt :
1355 case Hexagon::LDriub_cNotPt :
1356 case Hexagon::LDriub_indexed_cPt :
1357 case Hexagon::LDriub_indexed_cNotPt :
1359 case Hexagon::POST_LDrid_cPt :
1360 case Hexagon::POST_LDrid_cNotPt :
1361 case Hexagon::POST_LDriw_cPt :
1362 case Hexagon::POST_LDriw_cNotPt :
1363 case Hexagon::POST_LDrih_cPt :
1364 case Hexagon::POST_LDrih_cNotPt :
1365 case Hexagon::POST_LDrib_cPt :
1366 case Hexagon::POST_LDrib_cNotPt :
1367 case Hexagon::POST_LDriuh_cPt :
1368 case Hexagon::POST_LDriuh_cNotPt :
1369 case Hexagon::POST_LDriub_cPt :
1370 case Hexagon::POST_LDriub_cNotPt :
1371 return QRI.Subtarget.hasV4TOps();
1372 case Hexagon::LDrid_indexed_shl_cPt_V4 :
1373 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
1374 case Hexagon::LDrib_indexed_shl_cPt_V4 :
1375 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
1376 case Hexagon::LDriub_indexed_shl_cPt_V4 :
1377 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
1378 case Hexagon::LDrih_indexed_shl_cPt_V4 :
1379 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
1380 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
1381 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
1382 case Hexagon::LDriw_indexed_shl_cPt_V4 :
1383 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
1384 return QRI.Subtarget.hasV4TOps();
1388 // Returns true if an instruction is a conditional store.
1390 // Note: It doesn't include conditional new-value stores as they can't be
1391 // converted to .new predicate.
1393 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
1395 // / \ (not OK. it will cause new-value store to be
1396 // / X conditional on p0.new while R2 producer is
1399 // p.new store p.old NV store
1400 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
1406 // [if (p0)memw(R0+#0)=R2]
1408 // The above diagram shows the steps involoved in the conversion of a predicated
1409 // store instruction to its .new predicated new-value form.
1411 // The following set of instructions further explains the scenario where
1412 // conditional new-value store becomes invalid when promoted to .new predicate
1415 // { 1) if (p0) r0 = add(r1, r2)
1416 // 2) p0 = cmp.eq(r3, #0) }
1418 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
1419 // the first two instructions because in instr 1, r0 is conditional on old value
1420 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
1421 // is not valid for new-value stores.
1422 bool HexagonInstrInfo::
1423 isConditionalStore (const MachineInstr* MI) const {
1424 const HexagonRegisterInfo& QRI = getRegisterInfo();
1425 switch (MI->getOpcode())
1427 default: return false;
1428 case Hexagon::STrib_imm_cPt_V4 :
1429 case Hexagon::STrib_imm_cNotPt_V4 :
1430 case Hexagon::STrib_indexed_shl_cPt_V4 :
1431 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
1432 case Hexagon::STrib_cPt :
1433 case Hexagon::STrib_cNotPt :
1434 case Hexagon::POST_STbri_cPt :
1435 case Hexagon::POST_STbri_cNotPt :
1436 case Hexagon::STrid_indexed_cPt :
1437 case Hexagon::STrid_indexed_cNotPt :
1438 case Hexagon::STrid_indexed_shl_cPt_V4 :
1439 case Hexagon::POST_STdri_cPt :
1440 case Hexagon::POST_STdri_cNotPt :
1441 case Hexagon::STrih_cPt :
1442 case Hexagon::STrih_cNotPt :
1443 case Hexagon::STrih_indexed_cPt :
1444 case Hexagon::STrih_indexed_cNotPt :
1445 case Hexagon::STrih_imm_cPt_V4 :
1446 case Hexagon::STrih_imm_cNotPt_V4 :
1447 case Hexagon::STrih_indexed_shl_cPt_V4 :
1448 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
1449 case Hexagon::POST_SThri_cPt :
1450 case Hexagon::POST_SThri_cNotPt :
1451 case Hexagon::STriw_cPt :
1452 case Hexagon::STriw_cNotPt :
1453 case Hexagon::STriw_indexed_cPt :
1454 case Hexagon::STriw_indexed_cNotPt :
1455 case Hexagon::STriw_imm_cPt_V4 :
1456 case Hexagon::STriw_imm_cNotPt_V4 :
1457 case Hexagon::STriw_indexed_shl_cPt_V4 :
1458 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
1459 case Hexagon::POST_STwri_cPt :
1460 case Hexagon::POST_STwri_cNotPt :
1461 return QRI.Subtarget.hasV4TOps();
1463 // V4 global address store before promoting to dot new.
1464 case Hexagon::STd_GP_cPt_V4 :
1465 case Hexagon::STd_GP_cNotPt_V4 :
1466 case Hexagon::STb_GP_cPt_V4 :
1467 case Hexagon::STb_GP_cNotPt_V4 :
1468 case Hexagon::STh_GP_cPt_V4 :
1469 case Hexagon::STh_GP_cNotPt_V4 :
1470 case Hexagon::STw_GP_cPt_V4 :
1471 case Hexagon::STw_GP_cNotPt_V4 :
1472 return QRI.Subtarget.hasV4TOps();
1474 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
1475 // from the "Conditional Store" list. Because a predicated new value store
1476 // would NOT be promoted to a double dot new store. See diagram below:
1477 // This function returns yes for those stores that are predicated but not
1478 // yet promoted to predicate dot new instructions.
1480 // +---------------------+
1481 // /-----| if (p0) memw(..)=r0 |---------\~
1482 // || +---------------------+ ||
1483 // promote || /\ /\ || promote
1485 // \||/ demote || \||/
1487 // +-------------------------+ || +-------------------------+
1488 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
1489 // +-------------------------+ || +-------------------------+
1492 // promote || \/ NOT possible
1496 // +-----------------------------+
1497 // | if (p0.new) memw(..)=r0.new |
1498 // +-----------------------------+
1499 // Double Dot New Store
1505 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
1506 if (isNewValue(MI) && isBranch(MI))
1511 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
1512 return (getAddrMode(MI) == HexagonII::PostInc);
1515 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
1516 const uint64_t F = MI->getDesc().TSFlags;
1517 return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
1520 // Returns true, if any one of the operands is a dot new
1521 // insn, whether it is predicated dot new or register dot new.
1522 bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
1523 return (isNewValueInst(MI) ||
1524 (isPredicated(MI) && isPredicatedNew(MI)));
1527 // Returns the most basic instruction for the .new predicated instructions and
1528 // new-value stores.
1529 // For example, all of the following instructions will be converted back to the
1530 // same instruction:
1531 // 1) if (p0.new) memw(R0+#0) = R1.new --->
1532 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
1533 // 3) if (p0.new) memw(R0+#0) = R1 --->
1536 int HexagonInstrInfo::GetDotOldOp(const int opc) const {
1538 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
1539 NewOp = Hexagon::getPredOldOpcode(NewOp);
1541 assert(0 && "Couldn't change predicate new instruction to its old form.");
1544 if (isNewValueStore(NewOp)) { // Convert into non-new-value format
1545 NewOp = Hexagon::getNonNVStore(NewOp);
1547 assert(0 && "Couldn't change new-value store to its old form.");
1552 // Return the new value instruction for a given store.
1553 int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
1554 int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
1555 if (NVOpcode >= 0) // Valid new-value store instruction.
1558 switch (MI->getOpcode()) {
1559 default: llvm_unreachable("Unknown .new type");
1560 // store new value byte
1561 case Hexagon::STrib_shl_V4:
1562 return Hexagon::STrib_shl_nv_V4;
1564 case Hexagon::STrih_shl_V4:
1565 return Hexagon::STrih_shl_nv_V4;
1567 case Hexagon::STriw_f:
1568 return Hexagon::STriw_nv_V4;
1570 case Hexagon::STriw_indexed_f:
1571 return Hexagon::STriw_indexed_nv_V4;
1573 case Hexagon::STriw_shl_V4:
1574 return Hexagon::STriw_shl_nv_V4;
1580 // Return .new predicate version for an instruction.
1581 int HexagonInstrInfo::GetDotNewPredOp(MachineInstr *MI,
1582 const MachineBranchProbabilityInfo
1585 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
1586 if (NewOpcode >= 0) // Valid predicate new instruction
1589 switch (MI->getOpcode()) {
1590 default: llvm_unreachable("Unknown .new type");
1592 case Hexagon::JMP_t:
1593 case Hexagon::JMP_f:
1594 return getDotNewPredJumpOp(MI, MBPI);
1596 case Hexagon::JMPR_t:
1597 return Hexagon::JMPR_tnew_tV3;
1599 case Hexagon::JMPR_f:
1600 return Hexagon::JMPR_fnew_tV3;
1602 case Hexagon::JMPret_t:
1603 return Hexagon::JMPret_tnew_tV3;
1605 case Hexagon::JMPret_f:
1606 return Hexagon::JMPret_fnew_tV3;
1609 // Conditional combine
1610 case Hexagon::COMBINE_rr_cPt :
1611 return Hexagon::COMBINE_rr_cdnPt;
1612 case Hexagon::COMBINE_rr_cNotPt :
1613 return Hexagon::COMBINE_rr_cdnNotPt;
1618 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
1619 const uint64_t F = MI->getDesc().TSFlags;
1621 return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
1624 /// immediateExtend - Changes the instruction in place to one using an immediate
1626 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
1627 assert((isExtendable(MI)||isConstExtended(MI)) &&
1628 "Instruction must be extendable");
1629 // Find which operand is extendable.
1630 short ExtOpNum = getCExtOpNum(MI);
1631 MachineOperand &MO = MI->getOperand(ExtOpNum);
1632 // This needs to be something we understand.
1633 assert((MO.isMBB() || MO.isImm()) &&
1634 "Branch with unknown extendable field type");
1635 // Mark given operand as extended.
1636 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
1639 DFAPacketizer *HexagonInstrInfo::
1640 CreateTargetScheduleState(const TargetMachine *TM,
1641 const ScheduleDAG *DAG) const {
1642 const InstrItineraryData *II = TM->getInstrItineraryData();
1643 return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II);
1646 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1647 const MachineBasicBlock *MBB,
1648 const MachineFunction &MF) const {
1649 // Debug info is never a scheduling boundary. It's necessary to be explicit
1650 // due to the special treatment of IT instructions below, otherwise a
1651 // dbg_value followed by an IT will result in the IT instruction being
1652 // considered a scheduling hazard, which is wrong. It should be the actual
1653 // instruction preceding the dbg_value instruction(s), just like it is
1654 // when debug info is not present.
1655 if (MI->isDebugValue())
1658 // Terminators and labels can't be scheduled around.
1659 if (MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm())
1665 bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const {
1667 // Constant extenders are allowed only for V4 and above.
1668 if (!Subtarget.hasV4TOps())
1671 const uint64_t F = MI->getDesc().TSFlags;
1672 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
1673 if (isExtended) // Instruction must be extended.
1676 unsigned isExtendable = (F >> HexagonII::ExtendablePos)
1677 & HexagonII::ExtendableMask;
1681 short ExtOpNum = getCExtOpNum(MI);
1682 const MachineOperand &MO = MI->getOperand(ExtOpNum);
1683 // Use MO operand flags to determine if MO
1684 // has the HMOTF_ConstExtended flag set.
1685 if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
1687 // If this is a Machine BB address we are talking about, and it is
1688 // not marked as extended, say so.
1692 // We could be using an instruction with an extendable immediate and shoehorn
1693 // a global address into it. If it is a global address it will be constant
1694 // extended. We do this for COMBINE.
1695 // We currently only handle isGlobal() because it is the only kind of
1696 // object we are going to end up with here for now.
1697 // In the future we probably should add isSymbol(), etc.
1698 if (MO.isGlobal() || MO.isSymbol())
1701 // If the extendable operand is not 'Immediate' type, the instruction should
1702 // have 'isExtended' flag set.
1703 assert(MO.isImm() && "Extendable operand must be Immediate type");
1705 int MinValue = getMinValue(MI);
1706 int MaxValue = getMaxValue(MI);
1707 int ImmValue = MO.getImm();
1709 return (ImmValue < MinValue || ImmValue > MaxValue);
1712 // Returns the opcode to use when converting MI, which is a conditional jump,
1713 // into a conditional instruction which uses the .new value of the predicate.
1714 // We also use branch probabilities to add a hint to the jump.
1716 HexagonInstrInfo::getDotNewPredJumpOp(MachineInstr *MI,
1718 MachineBranchProbabilityInfo *MBPI) const {
1720 // We assume that block can have at most two successors.
1722 MachineBasicBlock *Src = MI->getParent();
1723 MachineOperand *BrTarget = &MI->getOperand(1);
1724 MachineBasicBlock *Dst = BrTarget->getMBB();
1726 const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
1727 if (Prediction >= BranchProbability(1,2))
1730 switch (MI->getOpcode()) {
1731 case Hexagon::JMP_t:
1732 return taken ? Hexagon::JMP_tnew_t : Hexagon::JMP_tnew_nt;
1733 case Hexagon::JMP_f:
1734 return taken ? Hexagon::JMP_fnew_t : Hexagon::JMP_fnew_nt;
1737 llvm_unreachable("Unexpected jump instruction.");
1740 // Returns true if a particular operand is extendable for an instruction.
1741 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
1742 unsigned short OperandNum) const {
1743 // Constant extenders are allowed only for V4 and above.
1744 if (!Subtarget.hasV4TOps())
1747 const uint64_t F = MI->getDesc().TSFlags;
1749 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
1753 // Returns Operand Index for the constant extended instruction.
1754 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
1755 const uint64_t F = MI->getDesc().TSFlags;
1756 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
1759 // Returns the min value that doesn't need to be extended.
1760 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
1761 const uint64_t F = MI->getDesc().TSFlags;
1762 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1763 & HexagonII::ExtentSignedMask;
1764 unsigned bits = (F >> HexagonII::ExtentBitsPos)
1765 & HexagonII::ExtentBitsMask;
1767 if (isSigned) // if value is signed
1768 return -1 << (bits - 1);
1773 // Returns the max value that doesn't need to be extended.
1774 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
1775 const uint64_t F = MI->getDesc().TSFlags;
1776 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1777 & HexagonII::ExtentSignedMask;
1778 unsigned bits = (F >> HexagonII::ExtentBitsPos)
1779 & HexagonII::ExtentBitsMask;
1781 if (isSigned) // if value is signed
1782 return ~(-1 << (bits - 1));
1784 return ~(-1 << bits);
1787 // Returns true if an instruction can be converted into a non-extended
1788 // equivalent instruction.
1789 bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const {
1792 // Check if the instruction has a register form that uses register in place
1793 // of the extended operand, if so return that as the non-extended form.
1794 if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
1797 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1798 // Check addressing mode and retrieve non-ext equivalent instruction.
1800 switch (getAddrMode(MI)) {
1801 case HexagonII::Absolute :
1802 // Load/store with absolute addressing mode can be converted into
1803 // base+offset mode.
1804 NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
1806 case HexagonII::BaseImmOffset :
1807 // Load/store with base+offset addressing mode can be converted into
1808 // base+register offset addressing mode. However left shift operand should
1810 NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
1815 if (NonExtOpcode < 0)
1822 // Returns opcode of the non-extended equivalent instruction.
1823 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
1825 // Check if the instruction has a register form that uses register in place
1826 // of the extended operand, if so return that as the non-extended form.
1827 short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
1828 if (NonExtOpcode >= 0)
1829 return NonExtOpcode;
1831 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1832 // Check addressing mode and retrieve non-ext equivalent instruction.
1833 switch (getAddrMode(MI)) {
1834 case HexagonII::Absolute :
1835 return Hexagon::getBasedWithImmOffset(MI->getOpcode());
1836 case HexagonII::BaseImmOffset :
1837 return Hexagon::getBaseWithRegOffset(MI->getOpcode());
1845 bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const {
1846 return (Opcode == Hexagon::JMP_t) ||
1847 (Opcode == Hexagon::JMP_f) ||
1848 (Opcode == Hexagon::JMP_tnew_t) ||
1849 (Opcode == Hexagon::JMP_fnew_t) ||
1850 (Opcode == Hexagon::JMP_tnew_nt) ||
1851 (Opcode == Hexagon::JMP_fnew_nt);
1854 bool HexagonInstrInfo::PredOpcodeHasNot(Opcode_t Opcode) const {
1855 return (Opcode == Hexagon::JMP_f) ||
1856 (Opcode == Hexagon::JMP_fnew_t) ||
1857 (Opcode == Hexagon::JMP_fnew_nt);