1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Support/MathExtras.h"
27 #define GET_INSTRINFO_CTOR
28 #define GET_INSTRMAP_INFO
29 #include "HexagonGenInstrInfo.inc"
30 #include "HexagonGenDFAPacketizer.inc"
35 /// Constants for Hexagon instructions.
37 const int Hexagon_MEMW_OFFSET_MAX = 4095;
38 const int Hexagon_MEMW_OFFSET_MIN = -4096;
39 const int Hexagon_MEMD_OFFSET_MAX = 8191;
40 const int Hexagon_MEMD_OFFSET_MIN = -8192;
41 const int Hexagon_MEMH_OFFSET_MAX = 2047;
42 const int Hexagon_MEMH_OFFSET_MIN = -2048;
43 const int Hexagon_MEMB_OFFSET_MAX = 1023;
44 const int Hexagon_MEMB_OFFSET_MIN = -1024;
45 const int Hexagon_ADDI_OFFSET_MAX = 32767;
46 const int Hexagon_ADDI_OFFSET_MIN = -32768;
47 const int Hexagon_MEMD_AUTOINC_MAX = 56;
48 const int Hexagon_MEMD_AUTOINC_MIN = -64;
49 const int Hexagon_MEMW_AUTOINC_MAX = 28;
50 const int Hexagon_MEMW_AUTOINC_MIN = -32;
51 const int Hexagon_MEMH_AUTOINC_MAX = 14;
52 const int Hexagon_MEMH_AUTOINC_MIN = -16;
53 const int Hexagon_MEMB_AUTOINC_MAX = 7;
54 const int Hexagon_MEMB_AUTOINC_MIN = -8;
57 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
58 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
59 RI(ST, *this), Subtarget(ST) {
63 /// isLoadFromStackSlot - If the specified machine instruction is a direct
64 /// load from a stack slot, return the virtual or physical register number of
65 /// the destination along with the FrameIndex of the loaded stack slot. If
66 /// not, return 0. This predicate must return 0 if the instruction has
67 /// any side effects other than loading from the stack slot.
68 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
69 int &FrameIndex) const {
72 switch (MI->getOpcode()) {
79 if (MI->getOperand(2).isFI() &&
80 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
81 FrameIndex = MI->getOperand(2).getIndex();
82 return MI->getOperand(0).getReg();
90 /// isStoreToStackSlot - If the specified machine instruction is a direct
91 /// store to a stack slot, return the virtual or physical register number of
92 /// the source reg along with the FrameIndex of the loaded stack slot. If
93 /// not, return 0. This predicate must return 0 if the instruction has
94 /// any side effects other than storing to the stack slot.
95 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
96 int &FrameIndex) const {
97 switch (MI->getOpcode()) {
103 if (MI->getOperand(2).isFI() &&
104 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
105 FrameIndex = MI->getOperand(0).getIndex();
106 return MI->getOperand(2).getReg();
115 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
116 MachineBasicBlock *FBB,
117 const SmallVectorImpl<MachineOperand> &Cond,
120 int BOpc = Hexagon::JMP;
121 int BccOpc = Hexagon::JMP_c;
123 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
126 // Check if ReverseBranchCondition has asked to reverse this branch
127 // If we want to reverse the branch an odd number of times, we want
129 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
130 BccOpc = Hexagon::JMP_cNot;
136 // Due to a bug in TailMerging/CFG Optimization, we need to add a
137 // special case handling of a predicated jump followed by an
138 // unconditional jump. If not, Tail Merging and CFG Optimization go
139 // into an infinite loop.
140 MachineBasicBlock *NewTBB, *NewFBB;
141 SmallVector<MachineOperand, 4> Cond;
142 MachineInstr *Term = MBB.getFirstTerminator();
143 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
145 MachineBasicBlock *NextBB =
146 llvm::next(MachineFunction::iterator(&MBB));
147 if (NewTBB == NextBB) {
148 ReverseBranchCondition(Cond);
150 return InsertBranch(MBB, TBB, 0, Cond, DL);
153 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
156 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
161 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
162 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
168 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
169 MachineBasicBlock *&TBB,
170 MachineBasicBlock *&FBB,
171 SmallVectorImpl<MachineOperand> &Cond,
172 bool AllowModify) const {
176 // If the block has no terminators, it just falls into the block after it.
177 MachineBasicBlock::iterator I = MBB.end();
178 if (I == MBB.begin())
181 // A basic block may looks like this:
191 // It has two succs but does not have a terminator
192 // Don't know how to handle it.
197 } while (I != MBB.begin());
202 while (I->isDebugValue()) {
203 if (I == MBB.begin())
207 if (!isUnpredicatedTerminator(I))
210 // Get the last instruction in the block.
211 MachineInstr *LastInst = I;
213 // If there is only one terminator instruction, process it.
214 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
215 if (LastInst->getOpcode() == Hexagon::JMP) {
216 TBB = LastInst->getOperand(0).getMBB();
219 if (LastInst->getOpcode() == Hexagon::JMP_c) {
220 // Block ends with fall-through true condbranch.
221 TBB = LastInst->getOperand(1).getMBB();
222 Cond.push_back(LastInst->getOperand(0));
225 if (LastInst->getOpcode() == Hexagon::JMP_cNot) {
226 // Block ends with fall-through false condbranch.
227 TBB = LastInst->getOperand(1).getMBB();
228 Cond.push_back(MachineOperand::CreateImm(0));
229 Cond.push_back(LastInst->getOperand(0));
232 // Otherwise, don't know what this is.
236 // Get the instruction before it if it's a terminator.
237 MachineInstr *SecondLastInst = I;
239 // If there are three terminators, we don't know what sort of block this is.
240 if (SecondLastInst && I != MBB.begin() &&
241 isUnpredicatedTerminator(--I))
244 // If the block ends with Hexagon::BRCOND and Hexagon:JMP, handle it.
245 if (((SecondLastInst->getOpcode() == Hexagon::BRCOND) ||
246 (SecondLastInst->getOpcode() == Hexagon::JMP_c)) &&
247 LastInst->getOpcode() == Hexagon::JMP) {
248 TBB = SecondLastInst->getOperand(1).getMBB();
249 Cond.push_back(SecondLastInst->getOperand(0));
250 FBB = LastInst->getOperand(0).getMBB();
254 // If the block ends with Hexagon::JMP_cNot and Hexagon:JMP, handle it.
255 if ((SecondLastInst->getOpcode() == Hexagon::JMP_cNot) &&
256 LastInst->getOpcode() == Hexagon::JMP) {
257 TBB = SecondLastInst->getOperand(1).getMBB();
258 Cond.push_back(MachineOperand::CreateImm(0));
259 Cond.push_back(SecondLastInst->getOperand(0));
260 FBB = LastInst->getOperand(0).getMBB();
264 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
265 // executed, so remove it.
266 if (SecondLastInst->getOpcode() == Hexagon::JMP &&
267 LastInst->getOpcode() == Hexagon::JMP) {
268 TBB = SecondLastInst->getOperand(0).getMBB();
271 I->eraseFromParent();
275 // Otherwise, can't handle this.
280 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
281 int BOpc = Hexagon::JMP;
282 int BccOpc = Hexagon::JMP_c;
283 int BccOpcNot = Hexagon::JMP_cNot;
285 MachineBasicBlock::iterator I = MBB.end();
286 if (I == MBB.begin()) return 0;
288 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
289 I->getOpcode() != BccOpcNot)
292 // Remove the branch.
293 I->eraseFromParent();
297 if (I == MBB.begin()) return 1;
299 if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
302 // Remove the branch.
303 I->eraseFromParent();
308 /// \brief For a comparison instruction, return the source registers in
309 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
310 /// compares against in CmpValue. Return true if the comparison instruction
312 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
313 unsigned &SrcReg, unsigned &SrcReg2,
314 int &Mask, int &Value) const {
315 unsigned Opc = MI->getOpcode();
317 // Set mask and the first source register.
319 case Hexagon::CMPEHexagon4rr:
320 case Hexagon::CMPEQri:
321 case Hexagon::CMPEQrr:
322 case Hexagon::CMPGT64rr:
323 case Hexagon::CMPGTU64rr:
324 case Hexagon::CMPGTUri:
325 case Hexagon::CMPGTUrr:
326 case Hexagon::CMPGTri:
327 case Hexagon::CMPGTrr:
328 case Hexagon::CMPLTUrr:
329 case Hexagon::CMPLTrr:
330 SrcReg = MI->getOperand(1).getReg();
333 case Hexagon::CMPbEQri_V4:
334 case Hexagon::CMPbEQrr_sbsb_V4:
335 case Hexagon::CMPbEQrr_ubub_V4:
336 case Hexagon::CMPbGTUri_V4:
337 case Hexagon::CMPbGTUrr_V4:
338 case Hexagon::CMPbGTrr_V4:
339 SrcReg = MI->getOperand(1).getReg();
342 case Hexagon::CMPhEQri_V4:
343 case Hexagon::CMPhEQrr_shl_V4:
344 case Hexagon::CMPhEQrr_xor_V4:
345 case Hexagon::CMPhGTUri_V4:
346 case Hexagon::CMPhGTUrr_V4:
347 case Hexagon::CMPhGTrr_shl_V4:
348 SrcReg = MI->getOperand(1).getReg();
353 // Set the value/second source register.
355 case Hexagon::CMPEHexagon4rr:
356 case Hexagon::CMPEQrr:
357 case Hexagon::CMPGT64rr:
358 case Hexagon::CMPGTU64rr:
359 case Hexagon::CMPGTUrr:
360 case Hexagon::CMPGTrr:
361 case Hexagon::CMPbEQrr_sbsb_V4:
362 case Hexagon::CMPbEQrr_ubub_V4:
363 case Hexagon::CMPbGTUrr_V4:
364 case Hexagon::CMPbGTrr_V4:
365 case Hexagon::CMPhEQrr_shl_V4:
366 case Hexagon::CMPhEQrr_xor_V4:
367 case Hexagon::CMPhGTUrr_V4:
368 case Hexagon::CMPhGTrr_shl_V4:
369 case Hexagon::CMPLTUrr:
370 case Hexagon::CMPLTrr:
371 SrcReg2 = MI->getOperand(2).getReg();
374 case Hexagon::CMPEQri:
375 case Hexagon::CMPGTUri:
376 case Hexagon::CMPGTri:
377 case Hexagon::CMPbEQri_V4:
378 case Hexagon::CMPbGTUri_V4:
379 case Hexagon::CMPhEQri_V4:
380 case Hexagon::CMPhGTUri_V4:
382 Value = MI->getOperand(2).getImm();
390 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
391 MachineBasicBlock::iterator I, DebugLoc DL,
392 unsigned DestReg, unsigned SrcReg,
393 bool KillSrc) const {
394 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
395 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
398 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
399 BuildMI(MBB, I, DL, get(Hexagon::TFR64), DestReg).addReg(SrcReg);
402 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
403 // Map Pd = Ps to Pd = or(Ps, Ps).
404 BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
405 DestReg).addReg(SrcReg).addReg(SrcReg);
408 if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
409 Hexagon::IntRegsRegClass.contains(SrcReg)) {
410 // We can have an overlap between single and double reg: r1:0 = r0.
411 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
413 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
414 Hexagon::subreg_hireg))).addImm(0);
416 // r1:0 = r1 or no overlap.
417 BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
418 Hexagon::subreg_loreg))).addReg(SrcReg);
419 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
420 Hexagon::subreg_hireg))).addImm(0);
424 if (Hexagon::CRRegsRegClass.contains(DestReg) &&
425 Hexagon::IntRegsRegClass.contains(SrcReg)) {
426 BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
429 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
430 Hexagon::IntRegsRegClass.contains(DestReg)) {
431 BuildMI(MBB, I, DL, get(Hexagon::TFR_RsPd), DestReg).
432 addReg(SrcReg, getKillRegState(KillSrc));
435 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
436 Hexagon::PredRegsRegClass.contains(DestReg)) {
437 BuildMI(MBB, I, DL, get(Hexagon::TFR_PdRs), DestReg).
438 addReg(SrcReg, getKillRegState(KillSrc));
442 llvm_unreachable("Unimplemented");
446 void HexagonInstrInfo::
447 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
448 unsigned SrcReg, bool isKill, int FI,
449 const TargetRegisterClass *RC,
450 const TargetRegisterInfo *TRI) const {
452 DebugLoc DL = MBB.findDebugLoc(I);
453 MachineFunction &MF = *MBB.getParent();
454 MachineFrameInfo &MFI = *MF.getFrameInfo();
455 unsigned Align = MFI.getObjectAlignment(FI);
457 MachineMemOperand *MMO =
458 MF.getMachineMemOperand(
459 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
460 MachineMemOperand::MOStore,
461 MFI.getObjectSize(FI),
464 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
465 BuildMI(MBB, I, DL, get(Hexagon::STriw))
466 .addFrameIndex(FI).addImm(0)
467 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
468 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
469 BuildMI(MBB, I, DL, get(Hexagon::STrid))
470 .addFrameIndex(FI).addImm(0)
471 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
472 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
473 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
474 .addFrameIndex(FI).addImm(0)
475 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
477 llvm_unreachable("Unimplemented");
482 void HexagonInstrInfo::storeRegToAddr(
483 MachineFunction &MF, unsigned SrcReg,
485 SmallVectorImpl<MachineOperand> &Addr,
486 const TargetRegisterClass *RC,
487 SmallVectorImpl<MachineInstr*> &NewMIs) const
489 llvm_unreachable("Unimplemented");
493 void HexagonInstrInfo::
494 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
495 unsigned DestReg, int FI,
496 const TargetRegisterClass *RC,
497 const TargetRegisterInfo *TRI) const {
498 DebugLoc DL = MBB.findDebugLoc(I);
499 MachineFunction &MF = *MBB.getParent();
500 MachineFrameInfo &MFI = *MF.getFrameInfo();
501 unsigned Align = MFI.getObjectAlignment(FI);
503 MachineMemOperand *MMO =
504 MF.getMachineMemOperand(
505 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
506 MachineMemOperand::MOLoad,
507 MFI.getObjectSize(FI),
509 if (RC == &Hexagon::IntRegsRegClass) {
510 BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)
511 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
512 } else if (RC == &Hexagon::DoubleRegsRegClass) {
513 BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
514 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
515 } else if (RC == &Hexagon::PredRegsRegClass) {
516 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
517 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
519 llvm_unreachable("Can't store this register to stack slot");
524 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
525 SmallVectorImpl<MachineOperand> &Addr,
526 const TargetRegisterClass *RC,
527 SmallVectorImpl<MachineInstr*> &NewMIs) const {
528 llvm_unreachable("Unimplemented");
532 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
534 const SmallVectorImpl<unsigned> &Ops,
536 // Hexagon_TODO: Implement.
541 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
543 MachineRegisterInfo &RegInfo = MF->getRegInfo();
544 const TargetRegisterClass *TRC;
546 TRC = &Hexagon::PredRegsRegClass;
547 } else if (VT == MVT::i32 || VT == MVT::f32) {
548 TRC = &Hexagon::IntRegsRegClass;
549 } else if (VT == MVT::i64 || VT == MVT::f64) {
550 TRC = &Hexagon::DoubleRegsRegClass;
552 llvm_unreachable("Cannot handle this register class");
555 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
559 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
560 // Constant extenders are allowed only for V4 and above.
561 if (!Subtarget.hasV4TOps())
564 const MCInstrDesc &MID = MI->getDesc();
565 const uint64_t F = MID.TSFlags;
566 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
569 // TODO: This is largely obsolete now. Will need to be removed
570 // in consecutive patches.
571 switch(MI->getOpcode()) {
572 // TFR_FI Remains a special case.
573 case Hexagon::TFR_FI:
581 // This returns true in two cases:
582 // - The OP code itself indicates that this is an extended instruction.
583 // - One of MOs has been marked with HMOTF_ConstExtended flag.
584 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
585 // First check if this is permanently extended op code.
586 const uint64_t F = MI->getDesc().TSFlags;
587 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
589 // Use MO operand flags to determine if one of MI's operands
590 // has HMOTF_ConstExtended flag set.
591 for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
592 E = MI->operands_end(); I != E; ++I) {
593 if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
599 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
600 switch (MI->getOpcode()) {
601 default: return false;
603 case Hexagon::JMP_EQriPt_nv_V4:
604 case Hexagon::JMP_EQriPnt_nv_V4:
605 case Hexagon::JMP_EQriNotPt_nv_V4:
606 case Hexagon::JMP_EQriNotPnt_nv_V4:
607 case Hexagon::JMP_EQriPt_ie_nv_V4:
608 case Hexagon::JMP_EQriPnt_ie_nv_V4:
609 case Hexagon::JMP_EQriNotPt_ie_nv_V4:
610 case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
612 // JMP_EQri - with -1
613 case Hexagon::JMP_EQriPtneg_nv_V4:
614 case Hexagon::JMP_EQriPntneg_nv_V4:
615 case Hexagon::JMP_EQriNotPtneg_nv_V4:
616 case Hexagon::JMP_EQriNotPntneg_nv_V4:
617 case Hexagon::JMP_EQriPtneg_ie_nv_V4:
618 case Hexagon::JMP_EQriPntneg_ie_nv_V4:
619 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
620 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
623 case Hexagon::JMP_EQrrPt_nv_V4:
624 case Hexagon::JMP_EQrrPnt_nv_V4:
625 case Hexagon::JMP_EQrrNotPt_nv_V4:
626 case Hexagon::JMP_EQrrNotPnt_nv_V4:
627 case Hexagon::JMP_EQrrPt_ie_nv_V4:
628 case Hexagon::JMP_EQrrPnt_ie_nv_V4:
629 case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
630 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
633 case Hexagon::JMP_GTriPt_nv_V4:
634 case Hexagon::JMP_GTriPnt_nv_V4:
635 case Hexagon::JMP_GTriNotPt_nv_V4:
636 case Hexagon::JMP_GTriNotPnt_nv_V4:
637 case Hexagon::JMP_GTriPt_ie_nv_V4:
638 case Hexagon::JMP_GTriPnt_ie_nv_V4:
639 case Hexagon::JMP_GTriNotPt_ie_nv_V4:
640 case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
642 // JMP_GTri - with -1
643 case Hexagon::JMP_GTriPtneg_nv_V4:
644 case Hexagon::JMP_GTriPntneg_nv_V4:
645 case Hexagon::JMP_GTriNotPtneg_nv_V4:
646 case Hexagon::JMP_GTriNotPntneg_nv_V4:
647 case Hexagon::JMP_GTriPtneg_ie_nv_V4:
648 case Hexagon::JMP_GTriPntneg_ie_nv_V4:
649 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
650 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
653 case Hexagon::JMP_GTrrPt_nv_V4:
654 case Hexagon::JMP_GTrrPnt_nv_V4:
655 case Hexagon::JMP_GTrrNotPt_nv_V4:
656 case Hexagon::JMP_GTrrNotPnt_nv_V4:
657 case Hexagon::JMP_GTrrPt_ie_nv_V4:
658 case Hexagon::JMP_GTrrPnt_ie_nv_V4:
659 case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
660 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
663 case Hexagon::JMP_GTrrdnPt_nv_V4:
664 case Hexagon::JMP_GTrrdnPnt_nv_V4:
665 case Hexagon::JMP_GTrrdnNotPt_nv_V4:
666 case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
667 case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
668 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
669 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
670 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
673 case Hexagon::JMP_GTUriPt_nv_V4:
674 case Hexagon::JMP_GTUriPnt_nv_V4:
675 case Hexagon::JMP_GTUriNotPt_nv_V4:
676 case Hexagon::JMP_GTUriNotPnt_nv_V4:
677 case Hexagon::JMP_GTUriPt_ie_nv_V4:
678 case Hexagon::JMP_GTUriPnt_ie_nv_V4:
679 case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
680 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
683 case Hexagon::JMP_GTUrrPt_nv_V4:
684 case Hexagon::JMP_GTUrrPnt_nv_V4:
685 case Hexagon::JMP_GTUrrNotPt_nv_V4:
686 case Hexagon::JMP_GTUrrNotPnt_nv_V4:
687 case Hexagon::JMP_GTUrrPt_ie_nv_V4:
688 case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
689 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
690 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
693 case Hexagon::JMP_GTUrrdnPt_nv_V4:
694 case Hexagon::JMP_GTUrrdnPnt_nv_V4:
695 case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
696 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
697 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
698 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
699 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
700 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
705 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
706 switch (MI->getOpcode()) {
707 default: return false;
709 case Hexagon::STrib_nv_V4:
710 case Hexagon::STrib_indexed_nv_V4:
711 case Hexagon::STrib_indexed_shl_nv_V4:
712 case Hexagon::STrib_shl_nv_V4:
713 case Hexagon::STb_GP_nv_V4:
714 case Hexagon::POST_STbri_nv_V4:
715 case Hexagon::STrib_cPt_nv_V4:
716 case Hexagon::STrib_cdnPt_nv_V4:
717 case Hexagon::STrib_cNotPt_nv_V4:
718 case Hexagon::STrib_cdnNotPt_nv_V4:
719 case Hexagon::STrib_indexed_cPt_nv_V4:
720 case Hexagon::STrib_indexed_cdnPt_nv_V4:
721 case Hexagon::STrib_indexed_cNotPt_nv_V4:
722 case Hexagon::STrib_indexed_cdnNotPt_nv_V4:
723 case Hexagon::STrib_indexed_shl_cPt_nv_V4:
724 case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
725 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4:
726 case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
727 case Hexagon::POST_STbri_cPt_nv_V4:
728 case Hexagon::POST_STbri_cdnPt_nv_V4:
729 case Hexagon::POST_STbri_cNotPt_nv_V4:
730 case Hexagon::POST_STbri_cdnNotPt_nv_V4:
731 case Hexagon::STb_GP_cPt_nv_V4:
732 case Hexagon::STb_GP_cNotPt_nv_V4:
733 case Hexagon::STb_GP_cdnPt_nv_V4:
734 case Hexagon::STb_GP_cdnNotPt_nv_V4:
735 case Hexagon::STrib_abs_nv_V4:
736 case Hexagon::STrib_abs_cPt_nv_V4:
737 case Hexagon::STrib_abs_cdnPt_nv_V4:
738 case Hexagon::STrib_abs_cNotPt_nv_V4:
739 case Hexagon::STrib_abs_cdnNotPt_nv_V4:
740 case Hexagon::STrib_imm_abs_nv_V4:
741 case Hexagon::STrib_imm_abs_cPt_nv_V4:
742 case Hexagon::STrib_imm_abs_cdnPt_nv_V4:
743 case Hexagon::STrib_imm_abs_cNotPt_nv_V4:
744 case Hexagon::STrib_imm_abs_cdnNotPt_nv_V4:
747 case Hexagon::STrih_nv_V4:
748 case Hexagon::STrih_indexed_nv_V4:
749 case Hexagon::STrih_indexed_shl_nv_V4:
750 case Hexagon::STrih_shl_nv_V4:
751 case Hexagon::STh_GP_nv_V4:
752 case Hexagon::POST_SThri_nv_V4:
753 case Hexagon::STrih_cPt_nv_V4:
754 case Hexagon::STrih_cdnPt_nv_V4:
755 case Hexagon::STrih_cNotPt_nv_V4:
756 case Hexagon::STrih_cdnNotPt_nv_V4:
757 case Hexagon::STrih_indexed_cPt_nv_V4:
758 case Hexagon::STrih_indexed_cdnPt_nv_V4:
759 case Hexagon::STrih_indexed_cNotPt_nv_V4:
760 case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
761 case Hexagon::STrih_indexed_shl_cPt_nv_V4:
762 case Hexagon::STrih_indexed_shl_cdnPt_nv_V4:
763 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4:
764 case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4:
765 case Hexagon::POST_SThri_cPt_nv_V4:
766 case Hexagon::POST_SThri_cdnPt_nv_V4:
767 case Hexagon::POST_SThri_cNotPt_nv_V4:
768 case Hexagon::POST_SThri_cdnNotPt_nv_V4:
769 case Hexagon::STh_GP_cPt_nv_V4:
770 case Hexagon::STh_GP_cNotPt_nv_V4:
771 case Hexagon::STh_GP_cdnPt_nv_V4:
772 case Hexagon::STh_GP_cdnNotPt_nv_V4:
773 case Hexagon::STrih_abs_nv_V4:
774 case Hexagon::STrih_abs_cPt_nv_V4:
775 case Hexagon::STrih_abs_cdnPt_nv_V4:
776 case Hexagon::STrih_abs_cNotPt_nv_V4:
777 case Hexagon::STrih_abs_cdnNotPt_nv_V4:
778 case Hexagon::STrih_imm_abs_nv_V4:
779 case Hexagon::STrih_imm_abs_cPt_nv_V4:
780 case Hexagon::STrih_imm_abs_cdnPt_nv_V4:
781 case Hexagon::STrih_imm_abs_cNotPt_nv_V4:
782 case Hexagon::STrih_imm_abs_cdnNotPt_nv_V4:
785 case Hexagon::STriw_nv_V4:
786 case Hexagon::STriw_indexed_nv_V4:
787 case Hexagon::STriw_indexed_shl_nv_V4:
788 case Hexagon::STriw_shl_nv_V4:
789 case Hexagon::STw_GP_nv_V4:
790 case Hexagon::POST_STwri_nv_V4:
791 case Hexagon::STriw_cPt_nv_V4:
792 case Hexagon::STriw_cdnPt_nv_V4:
793 case Hexagon::STriw_cNotPt_nv_V4:
794 case Hexagon::STriw_cdnNotPt_nv_V4:
795 case Hexagon::STriw_indexed_cPt_nv_V4:
796 case Hexagon::STriw_indexed_cdnPt_nv_V4:
797 case Hexagon::STriw_indexed_cNotPt_nv_V4:
798 case Hexagon::STriw_indexed_cdnNotPt_nv_V4:
799 case Hexagon::STriw_indexed_shl_cPt_nv_V4:
800 case Hexagon::STriw_indexed_shl_cdnPt_nv_V4:
801 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4:
802 case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4:
803 case Hexagon::POST_STwri_cPt_nv_V4:
804 case Hexagon::POST_STwri_cdnPt_nv_V4:
805 case Hexagon::POST_STwri_cNotPt_nv_V4:
806 case Hexagon::POST_STwri_cdnNotPt_nv_V4:
807 case Hexagon::STw_GP_cPt_nv_V4:
808 case Hexagon::STw_GP_cNotPt_nv_V4:
809 case Hexagon::STw_GP_cdnPt_nv_V4:
810 case Hexagon::STw_GP_cdnNotPt_nv_V4:
811 case Hexagon::STriw_abs_nv_V4:
812 case Hexagon::STriw_abs_cPt_nv_V4:
813 case Hexagon::STriw_abs_cdnPt_nv_V4:
814 case Hexagon::STriw_abs_cNotPt_nv_V4:
815 case Hexagon::STriw_abs_cdnNotPt_nv_V4:
816 case Hexagon::STriw_imm_abs_nv_V4:
817 case Hexagon::STriw_imm_abs_cPt_nv_V4:
818 case Hexagon::STriw_imm_abs_cdnPt_nv_V4:
819 case Hexagon::STriw_imm_abs_cNotPt_nv_V4:
820 case Hexagon::STriw_imm_abs_cdnNotPt_nv_V4:
825 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
826 switch (MI->getOpcode())
828 default: return false;
830 case Hexagon::POST_LDrib:
831 case Hexagon::POST_LDrib_cPt:
832 case Hexagon::POST_LDrib_cNotPt:
833 case Hexagon::POST_LDrib_cdnPt_V4:
834 case Hexagon::POST_LDrib_cdnNotPt_V4:
836 // Load unsigned byte
837 case Hexagon::POST_LDriub:
838 case Hexagon::POST_LDriub_cPt:
839 case Hexagon::POST_LDriub_cNotPt:
840 case Hexagon::POST_LDriub_cdnPt_V4:
841 case Hexagon::POST_LDriub_cdnNotPt_V4:
844 case Hexagon::POST_LDrih:
845 case Hexagon::POST_LDrih_cPt:
846 case Hexagon::POST_LDrih_cNotPt:
847 case Hexagon::POST_LDrih_cdnPt_V4:
848 case Hexagon::POST_LDrih_cdnNotPt_V4:
850 // Load unsigned halfword
851 case Hexagon::POST_LDriuh:
852 case Hexagon::POST_LDriuh_cPt:
853 case Hexagon::POST_LDriuh_cNotPt:
854 case Hexagon::POST_LDriuh_cdnPt_V4:
855 case Hexagon::POST_LDriuh_cdnNotPt_V4:
858 case Hexagon::POST_LDriw:
859 case Hexagon::POST_LDriw_cPt:
860 case Hexagon::POST_LDriw_cNotPt:
861 case Hexagon::POST_LDriw_cdnPt_V4:
862 case Hexagon::POST_LDriw_cdnNotPt_V4:
865 case Hexagon::POST_LDrid:
866 case Hexagon::POST_LDrid_cPt:
867 case Hexagon::POST_LDrid_cNotPt:
868 case Hexagon::POST_LDrid_cdnPt_V4:
869 case Hexagon::POST_LDrid_cdnNotPt_V4:
872 case Hexagon::POST_STbri:
873 case Hexagon::POST_STbri_cPt:
874 case Hexagon::POST_STbri_cNotPt:
875 case Hexagon::POST_STbri_cdnPt_V4:
876 case Hexagon::POST_STbri_cdnNotPt_V4:
879 case Hexagon::POST_SThri:
880 case Hexagon::POST_SThri_cPt:
881 case Hexagon::POST_SThri_cNotPt:
882 case Hexagon::POST_SThri_cdnPt_V4:
883 case Hexagon::POST_SThri_cdnNotPt_V4:
886 case Hexagon::POST_STwri:
887 case Hexagon::POST_STwri_cPt:
888 case Hexagon::POST_STwri_cNotPt:
889 case Hexagon::POST_STwri_cdnPt_V4:
890 case Hexagon::POST_STwri_cdnNotPt_V4:
893 case Hexagon::POST_STdri:
894 case Hexagon::POST_STdri_cPt:
895 case Hexagon::POST_STdri_cNotPt:
896 case Hexagon::POST_STdri_cdnPt_V4:
897 case Hexagon::POST_STdri_cdnNotPt_V4:
902 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
903 if (isNewValueJump(MI))
906 if (isNewValueStore(MI))
912 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
913 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
916 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
917 bool isPred = MI->getDesc().isPredicable();
922 const int Opc = MI->getOpcode();
926 return isInt<12>(MI->getOperand(1).getImm());
929 case Hexagon::STrid_indexed:
930 return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
933 case Hexagon::STriw_indexed:
934 case Hexagon::STriw_nv_V4:
935 return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
938 case Hexagon::STrih_indexed:
939 case Hexagon::STrih_nv_V4:
940 return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
943 case Hexagon::STrib_indexed:
944 case Hexagon::STrib_nv_V4:
945 return isUInt<6>(MI->getOperand(1).getImm());
948 case Hexagon::LDrid_indexed:
949 return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
952 case Hexagon::LDriw_indexed:
953 return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
956 case Hexagon::LDriuh:
957 case Hexagon::LDrih_indexed:
958 case Hexagon::LDriuh_indexed:
959 return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
962 case Hexagon::LDriub:
963 case Hexagon::LDrib_indexed:
964 case Hexagon::LDriub_indexed:
965 return isUInt<6>(MI->getOperand(2).getImm());
967 case Hexagon::POST_LDrid:
968 return isShiftedInt<4,3>(MI->getOperand(3).getImm());
970 case Hexagon::POST_LDriw:
971 return isShiftedInt<4,2>(MI->getOperand(3).getImm());
973 case Hexagon::POST_LDrih:
974 case Hexagon::POST_LDriuh:
975 return isShiftedInt<4,1>(MI->getOperand(3).getImm());
977 case Hexagon::POST_LDrib:
978 case Hexagon::POST_LDriub:
979 return isInt<4>(MI->getOperand(3).getImm());
981 case Hexagon::STrib_imm_V4:
982 case Hexagon::STrih_imm_V4:
983 case Hexagon::STriw_imm_V4:
984 return (isUInt<6>(MI->getOperand(1).getImm()) &&
985 isInt<6>(MI->getOperand(2).getImm()));
987 case Hexagon::ADD_ri:
988 return isInt<8>(MI->getOperand(2).getImm());
996 return Subtarget.hasV4TOps();
1005 // This function performs the following inversiones:
1010 // however, these inversiones are NOT included:
1012 // cdnPt -X-> cdnNotPt
1013 // cdnNotPt -X-> cdnPt
1014 // cPt_nv -X-> cNotPt_nv (new value stores)
1015 // cNotPt_nv -X-> cPt_nv (new value stores)
1017 // because only the following transformations are allowed:
1019 // cNotPt ---> cdnNotPt
1021 // cNotPt ---> cNotPt_nv
1023 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
1025 default: llvm_unreachable("Unexpected predicated instruction");
1026 case Hexagon::TFR_cPt:
1027 return Hexagon::TFR_cNotPt;
1028 case Hexagon::TFR_cNotPt:
1029 return Hexagon::TFR_cPt;
1031 case Hexagon::TFRI_cPt:
1032 return Hexagon::TFRI_cNotPt;
1033 case Hexagon::TFRI_cNotPt:
1034 return Hexagon::TFRI_cPt;
1036 case Hexagon::JMP_c:
1037 return Hexagon::JMP_cNot;
1038 case Hexagon::JMP_cNot:
1039 return Hexagon::JMP_c;
1041 case Hexagon::ADD_ri_cPt:
1042 return Hexagon::ADD_ri_cNotPt;
1043 case Hexagon::ADD_ri_cNotPt:
1044 return Hexagon::ADD_ri_cPt;
1046 case Hexagon::ADD_rr_cPt:
1047 return Hexagon::ADD_rr_cNotPt;
1048 case Hexagon::ADD_rr_cNotPt:
1049 return Hexagon::ADD_rr_cPt;
1051 case Hexagon::XOR_rr_cPt:
1052 return Hexagon::XOR_rr_cNotPt;
1053 case Hexagon::XOR_rr_cNotPt:
1054 return Hexagon::XOR_rr_cPt;
1056 case Hexagon::AND_rr_cPt:
1057 return Hexagon::AND_rr_cNotPt;
1058 case Hexagon::AND_rr_cNotPt:
1059 return Hexagon::AND_rr_cPt;
1061 case Hexagon::OR_rr_cPt:
1062 return Hexagon::OR_rr_cNotPt;
1063 case Hexagon::OR_rr_cNotPt:
1064 return Hexagon::OR_rr_cPt;
1066 case Hexagon::SUB_rr_cPt:
1067 return Hexagon::SUB_rr_cNotPt;
1068 case Hexagon::SUB_rr_cNotPt:
1069 return Hexagon::SUB_rr_cPt;
1071 case Hexagon::COMBINE_rr_cPt:
1072 return Hexagon::COMBINE_rr_cNotPt;
1073 case Hexagon::COMBINE_rr_cNotPt:
1074 return Hexagon::COMBINE_rr_cPt;
1076 case Hexagon::ASLH_cPt_V4:
1077 return Hexagon::ASLH_cNotPt_V4;
1078 case Hexagon::ASLH_cNotPt_V4:
1079 return Hexagon::ASLH_cPt_V4;
1081 case Hexagon::ASRH_cPt_V4:
1082 return Hexagon::ASRH_cNotPt_V4;
1083 case Hexagon::ASRH_cNotPt_V4:
1084 return Hexagon::ASRH_cPt_V4;
1086 case Hexagon::SXTB_cPt_V4:
1087 return Hexagon::SXTB_cNotPt_V4;
1088 case Hexagon::SXTB_cNotPt_V4:
1089 return Hexagon::SXTB_cPt_V4;
1091 case Hexagon::SXTH_cPt_V4:
1092 return Hexagon::SXTH_cNotPt_V4;
1093 case Hexagon::SXTH_cNotPt_V4:
1094 return Hexagon::SXTH_cPt_V4;
1096 case Hexagon::ZXTB_cPt_V4:
1097 return Hexagon::ZXTB_cNotPt_V4;
1098 case Hexagon::ZXTB_cNotPt_V4:
1099 return Hexagon::ZXTB_cPt_V4;
1101 case Hexagon::ZXTH_cPt_V4:
1102 return Hexagon::ZXTH_cNotPt_V4;
1103 case Hexagon::ZXTH_cNotPt_V4:
1104 return Hexagon::ZXTH_cPt_V4;
1107 case Hexagon::JMPR_cPt:
1108 return Hexagon::JMPR_cNotPt;
1109 case Hexagon::JMPR_cNotPt:
1110 return Hexagon::JMPR_cPt;
1112 // V4 indexed+scaled load.
1113 case Hexagon::LDrid_indexed_shl_cPt_V4:
1114 return Hexagon::LDrid_indexed_shl_cNotPt_V4;
1115 case Hexagon::LDrid_indexed_shl_cNotPt_V4:
1116 return Hexagon::LDrid_indexed_shl_cPt_V4;
1118 case Hexagon::LDrib_indexed_shl_cPt_V4:
1119 return Hexagon::LDrib_indexed_shl_cNotPt_V4;
1120 case Hexagon::LDrib_indexed_shl_cNotPt_V4:
1121 return Hexagon::LDrib_indexed_shl_cPt_V4;
1123 case Hexagon::LDriub_indexed_shl_cPt_V4:
1124 return Hexagon::LDriub_indexed_shl_cNotPt_V4;
1125 case Hexagon::LDriub_indexed_shl_cNotPt_V4:
1126 return Hexagon::LDriub_indexed_shl_cPt_V4;
1128 case Hexagon::LDrih_indexed_shl_cPt_V4:
1129 return Hexagon::LDrih_indexed_shl_cNotPt_V4;
1130 case Hexagon::LDrih_indexed_shl_cNotPt_V4:
1131 return Hexagon::LDrih_indexed_shl_cPt_V4;
1133 case Hexagon::LDriuh_indexed_shl_cPt_V4:
1134 return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1135 case Hexagon::LDriuh_indexed_shl_cNotPt_V4:
1136 return Hexagon::LDriuh_indexed_shl_cPt_V4;
1138 case Hexagon::LDriw_indexed_shl_cPt_V4:
1139 return Hexagon::LDriw_indexed_shl_cNotPt_V4;
1140 case Hexagon::LDriw_indexed_shl_cNotPt_V4:
1141 return Hexagon::LDriw_indexed_shl_cPt_V4;
1144 case Hexagon::POST_STbri_cPt:
1145 return Hexagon::POST_STbri_cNotPt;
1146 case Hexagon::POST_STbri_cNotPt:
1147 return Hexagon::POST_STbri_cPt;
1149 case Hexagon::STrib_cPt:
1150 return Hexagon::STrib_cNotPt;
1151 case Hexagon::STrib_cNotPt:
1152 return Hexagon::STrib_cPt;
1154 case Hexagon::STrib_indexed_cPt:
1155 return Hexagon::STrib_indexed_cNotPt;
1156 case Hexagon::STrib_indexed_cNotPt:
1157 return Hexagon::STrib_indexed_cPt;
1159 case Hexagon::STrib_imm_cPt_V4:
1160 return Hexagon::STrib_imm_cNotPt_V4;
1161 case Hexagon::STrib_imm_cNotPt_V4:
1162 return Hexagon::STrib_imm_cPt_V4;
1164 case Hexagon::STrib_indexed_shl_cPt_V4:
1165 return Hexagon::STrib_indexed_shl_cNotPt_V4;
1166 case Hexagon::STrib_indexed_shl_cNotPt_V4:
1167 return Hexagon::STrib_indexed_shl_cPt_V4;
1170 case Hexagon::POST_SThri_cPt:
1171 return Hexagon::POST_SThri_cNotPt;
1172 case Hexagon::POST_SThri_cNotPt:
1173 return Hexagon::POST_SThri_cPt;
1175 case Hexagon::STrih_cPt:
1176 return Hexagon::STrih_cNotPt;
1177 case Hexagon::STrih_cNotPt:
1178 return Hexagon::STrih_cPt;
1180 case Hexagon::STrih_indexed_cPt:
1181 return Hexagon::STrih_indexed_cNotPt;
1182 case Hexagon::STrih_indexed_cNotPt:
1183 return Hexagon::STrih_indexed_cPt;
1185 case Hexagon::STrih_imm_cPt_V4:
1186 return Hexagon::STrih_imm_cNotPt_V4;
1187 case Hexagon::STrih_imm_cNotPt_V4:
1188 return Hexagon::STrih_imm_cPt_V4;
1190 case Hexagon::STrih_indexed_shl_cPt_V4:
1191 return Hexagon::STrih_indexed_shl_cNotPt_V4;
1192 case Hexagon::STrih_indexed_shl_cNotPt_V4:
1193 return Hexagon::STrih_indexed_shl_cPt_V4;
1196 case Hexagon::POST_STwri_cPt:
1197 return Hexagon::POST_STwri_cNotPt;
1198 case Hexagon::POST_STwri_cNotPt:
1199 return Hexagon::POST_STwri_cPt;
1201 case Hexagon::STriw_cPt:
1202 return Hexagon::STriw_cNotPt;
1203 case Hexagon::STriw_cNotPt:
1204 return Hexagon::STriw_cPt;
1206 case Hexagon::STriw_indexed_cPt:
1207 return Hexagon::STriw_indexed_cNotPt;
1208 case Hexagon::STriw_indexed_cNotPt:
1209 return Hexagon::STriw_indexed_cPt;
1211 case Hexagon::STriw_indexed_shl_cPt_V4:
1212 return Hexagon::STriw_indexed_shl_cNotPt_V4;
1213 case Hexagon::STriw_indexed_shl_cNotPt_V4:
1214 return Hexagon::STriw_indexed_shl_cPt_V4;
1216 case Hexagon::STriw_imm_cPt_V4:
1217 return Hexagon::STriw_imm_cNotPt_V4;
1218 case Hexagon::STriw_imm_cNotPt_V4:
1219 return Hexagon::STriw_imm_cPt_V4;
1222 case Hexagon::POST_STdri_cPt:
1223 return Hexagon::POST_STdri_cNotPt;
1224 case Hexagon::POST_STdri_cNotPt:
1225 return Hexagon::POST_STdri_cPt;
1227 case Hexagon::STrid_cPt:
1228 return Hexagon::STrid_cNotPt;
1229 case Hexagon::STrid_cNotPt:
1230 return Hexagon::STrid_cPt;
1232 case Hexagon::STrid_indexed_cPt:
1233 return Hexagon::STrid_indexed_cNotPt;
1234 case Hexagon::STrid_indexed_cNotPt:
1235 return Hexagon::STrid_indexed_cPt;
1237 case Hexagon::STrid_indexed_shl_cPt_V4:
1238 return Hexagon::STrid_indexed_shl_cNotPt_V4;
1239 case Hexagon::STrid_indexed_shl_cNotPt_V4:
1240 return Hexagon::STrid_indexed_shl_cPt_V4;
1242 // V4 Store to global address.
1243 case Hexagon::STd_GP_cPt_V4:
1244 return Hexagon::STd_GP_cNotPt_V4;
1245 case Hexagon::STd_GP_cNotPt_V4:
1246 return Hexagon::STd_GP_cPt_V4;
1248 case Hexagon::STb_GP_cPt_V4:
1249 return Hexagon::STb_GP_cNotPt_V4;
1250 case Hexagon::STb_GP_cNotPt_V4:
1251 return Hexagon::STb_GP_cPt_V4;
1253 case Hexagon::STh_GP_cPt_V4:
1254 return Hexagon::STh_GP_cNotPt_V4;
1255 case Hexagon::STh_GP_cNotPt_V4:
1256 return Hexagon::STh_GP_cPt_V4;
1258 case Hexagon::STw_GP_cPt_V4:
1259 return Hexagon::STw_GP_cNotPt_V4;
1260 case Hexagon::STw_GP_cNotPt_V4:
1261 return Hexagon::STw_GP_cPt_V4;
1264 case Hexagon::LDrid_cPt:
1265 return Hexagon::LDrid_cNotPt;
1266 case Hexagon::LDrid_cNotPt:
1267 return Hexagon::LDrid_cPt;
1269 case Hexagon::LDriw_cPt:
1270 return Hexagon::LDriw_cNotPt;
1271 case Hexagon::LDriw_cNotPt:
1272 return Hexagon::LDriw_cPt;
1274 case Hexagon::LDrih_cPt:
1275 return Hexagon::LDrih_cNotPt;
1276 case Hexagon::LDrih_cNotPt:
1277 return Hexagon::LDrih_cPt;
1279 case Hexagon::LDriuh_cPt:
1280 return Hexagon::LDriuh_cNotPt;
1281 case Hexagon::LDriuh_cNotPt:
1282 return Hexagon::LDriuh_cPt;
1284 case Hexagon::LDrib_cPt:
1285 return Hexagon::LDrib_cNotPt;
1286 case Hexagon::LDrib_cNotPt:
1287 return Hexagon::LDrib_cPt;
1289 case Hexagon::LDriub_cPt:
1290 return Hexagon::LDriub_cNotPt;
1291 case Hexagon::LDriub_cNotPt:
1292 return Hexagon::LDriub_cPt;
1295 case Hexagon::LDrid_indexed_cPt:
1296 return Hexagon::LDrid_indexed_cNotPt;
1297 case Hexagon::LDrid_indexed_cNotPt:
1298 return Hexagon::LDrid_indexed_cPt;
1300 case Hexagon::LDriw_indexed_cPt:
1301 return Hexagon::LDriw_indexed_cNotPt;
1302 case Hexagon::LDriw_indexed_cNotPt:
1303 return Hexagon::LDriw_indexed_cPt;
1305 case Hexagon::LDrih_indexed_cPt:
1306 return Hexagon::LDrih_indexed_cNotPt;
1307 case Hexagon::LDrih_indexed_cNotPt:
1308 return Hexagon::LDrih_indexed_cPt;
1310 case Hexagon::LDriuh_indexed_cPt:
1311 return Hexagon::LDriuh_indexed_cNotPt;
1312 case Hexagon::LDriuh_indexed_cNotPt:
1313 return Hexagon::LDriuh_indexed_cPt;
1315 case Hexagon::LDrib_indexed_cPt:
1316 return Hexagon::LDrib_indexed_cNotPt;
1317 case Hexagon::LDrib_indexed_cNotPt:
1318 return Hexagon::LDrib_indexed_cPt;
1320 case Hexagon::LDriub_indexed_cPt:
1321 return Hexagon::LDriub_indexed_cNotPt;
1322 case Hexagon::LDriub_indexed_cNotPt:
1323 return Hexagon::LDriub_indexed_cPt;
1326 case Hexagon::POST_LDrid_cPt:
1327 return Hexagon::POST_LDrid_cNotPt;
1328 case Hexagon::POST_LDriw_cNotPt:
1329 return Hexagon::POST_LDriw_cPt;
1331 case Hexagon::POST_LDrih_cPt:
1332 return Hexagon::POST_LDrih_cNotPt;
1333 case Hexagon::POST_LDrih_cNotPt:
1334 return Hexagon::POST_LDrih_cPt;
1336 case Hexagon::POST_LDriuh_cPt:
1337 return Hexagon::POST_LDriuh_cNotPt;
1338 case Hexagon::POST_LDriuh_cNotPt:
1339 return Hexagon::POST_LDriuh_cPt;
1341 case Hexagon::POST_LDrib_cPt:
1342 return Hexagon::POST_LDrib_cNotPt;
1343 case Hexagon::POST_LDrib_cNotPt:
1344 return Hexagon::POST_LDrib_cPt;
1346 case Hexagon::POST_LDriub_cPt:
1347 return Hexagon::POST_LDriub_cNotPt;
1348 case Hexagon::POST_LDriub_cNotPt:
1349 return Hexagon::POST_LDriub_cPt;
1352 case Hexagon::DEALLOC_RET_cPt_V4:
1353 return Hexagon::DEALLOC_RET_cNotPt_V4;
1354 case Hexagon::DEALLOC_RET_cNotPt_V4:
1355 return Hexagon::DEALLOC_RET_cPt_V4;
1358 // JMPEQ_ri - with -1.
1359 case Hexagon::JMP_EQriPtneg_nv_V4:
1360 return Hexagon::JMP_EQriNotPtneg_nv_V4;
1361 case Hexagon::JMP_EQriNotPtneg_nv_V4:
1362 return Hexagon::JMP_EQriPtneg_nv_V4;
1364 case Hexagon::JMP_EQriPntneg_nv_V4:
1365 return Hexagon::JMP_EQriNotPntneg_nv_V4;
1366 case Hexagon::JMP_EQriNotPntneg_nv_V4:
1367 return Hexagon::JMP_EQriPntneg_nv_V4;
1370 case Hexagon::JMP_EQriPt_nv_V4:
1371 return Hexagon::JMP_EQriNotPt_nv_V4;
1372 case Hexagon::JMP_EQriNotPt_nv_V4:
1373 return Hexagon::JMP_EQriPt_nv_V4;
1375 case Hexagon::JMP_EQriPnt_nv_V4:
1376 return Hexagon::JMP_EQriNotPnt_nv_V4;
1377 case Hexagon::JMP_EQriNotPnt_nv_V4:
1378 return Hexagon::JMP_EQriPnt_nv_V4;
1381 case Hexagon::JMP_EQrrPt_nv_V4:
1382 return Hexagon::JMP_EQrrNotPt_nv_V4;
1383 case Hexagon::JMP_EQrrNotPt_nv_V4:
1384 return Hexagon::JMP_EQrrPt_nv_V4;
1386 case Hexagon::JMP_EQrrPnt_nv_V4:
1387 return Hexagon::JMP_EQrrNotPnt_nv_V4;
1388 case Hexagon::JMP_EQrrNotPnt_nv_V4:
1389 return Hexagon::JMP_EQrrPnt_nv_V4;
1391 // JMPGT_ri - with -1.
1392 case Hexagon::JMP_GTriPtneg_nv_V4:
1393 return Hexagon::JMP_GTriNotPtneg_nv_V4;
1394 case Hexagon::JMP_GTriNotPtneg_nv_V4:
1395 return Hexagon::JMP_GTriPtneg_nv_V4;
1397 case Hexagon::JMP_GTriPntneg_nv_V4:
1398 return Hexagon::JMP_GTriNotPntneg_nv_V4;
1399 case Hexagon::JMP_GTriNotPntneg_nv_V4:
1400 return Hexagon::JMP_GTriPntneg_nv_V4;
1403 case Hexagon::JMP_GTriPt_nv_V4:
1404 return Hexagon::JMP_GTriNotPt_nv_V4;
1405 case Hexagon::JMP_GTriNotPt_nv_V4:
1406 return Hexagon::JMP_GTriPt_nv_V4;
1408 case Hexagon::JMP_GTriPnt_nv_V4:
1409 return Hexagon::JMP_GTriNotPnt_nv_V4;
1410 case Hexagon::JMP_GTriNotPnt_nv_V4:
1411 return Hexagon::JMP_GTriPnt_nv_V4;
1414 case Hexagon::JMP_GTrrPt_nv_V4:
1415 return Hexagon::JMP_GTrrNotPt_nv_V4;
1416 case Hexagon::JMP_GTrrNotPt_nv_V4:
1417 return Hexagon::JMP_GTrrPt_nv_V4;
1419 case Hexagon::JMP_GTrrPnt_nv_V4:
1420 return Hexagon::JMP_GTrrNotPnt_nv_V4;
1421 case Hexagon::JMP_GTrrNotPnt_nv_V4:
1422 return Hexagon::JMP_GTrrPnt_nv_V4;
1425 case Hexagon::JMP_GTrrdnPt_nv_V4:
1426 return Hexagon::JMP_GTrrdnNotPt_nv_V4;
1427 case Hexagon::JMP_GTrrdnNotPt_nv_V4:
1428 return Hexagon::JMP_GTrrdnPt_nv_V4;
1430 case Hexagon::JMP_GTrrdnPnt_nv_V4:
1431 return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
1432 case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
1433 return Hexagon::JMP_GTrrdnPnt_nv_V4;
1436 case Hexagon::JMP_GTUriPt_nv_V4:
1437 return Hexagon::JMP_GTUriNotPt_nv_V4;
1438 case Hexagon::JMP_GTUriNotPt_nv_V4:
1439 return Hexagon::JMP_GTUriPt_nv_V4;
1441 case Hexagon::JMP_GTUriPnt_nv_V4:
1442 return Hexagon::JMP_GTUriNotPnt_nv_V4;
1443 case Hexagon::JMP_GTUriNotPnt_nv_V4:
1444 return Hexagon::JMP_GTUriPnt_nv_V4;
1447 case Hexagon::JMP_GTUrrPt_nv_V4:
1448 return Hexagon::JMP_GTUrrNotPt_nv_V4;
1449 case Hexagon::JMP_GTUrrNotPt_nv_V4:
1450 return Hexagon::JMP_GTUrrPt_nv_V4;
1452 case Hexagon::JMP_GTUrrPnt_nv_V4:
1453 return Hexagon::JMP_GTUrrNotPnt_nv_V4;
1454 case Hexagon::JMP_GTUrrNotPnt_nv_V4:
1455 return Hexagon::JMP_GTUrrPnt_nv_V4;
1458 case Hexagon::JMP_GTUrrdnPt_nv_V4:
1459 return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
1460 case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
1461 return Hexagon::JMP_GTUrrdnPt_nv_V4;
1463 case Hexagon::JMP_GTUrrdnPnt_nv_V4:
1464 return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
1465 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
1466 return Hexagon::JMP_GTUrrdnPnt_nv_V4;
1471 int HexagonInstrInfo::
1472 getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
1473 enum Hexagon::PredSense inPredSense;
1474 inPredSense = invertPredicate ? Hexagon::PredSense_false :
1475 Hexagon::PredSense_true;
1476 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
1477 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
1480 // This switch case will be removed once all the instructions have been
1481 // modified to use relation maps.
1484 return !invertPredicate ? Hexagon::TFR_cPt :
1485 Hexagon::TFR_cNotPt;
1486 case Hexagon::TFRI_f:
1487 return !invertPredicate ? Hexagon::TFRI_cPt_f :
1488 Hexagon::TFRI_cNotPt_f;
1490 return !invertPredicate ? Hexagon::TFRI_cPt :
1491 Hexagon::TFRI_cNotPt;
1493 return !invertPredicate ? Hexagon::JMP_c :
1495 case Hexagon::JMP_EQrrPt_nv_V4:
1496 return !invertPredicate ? Hexagon::JMP_EQrrPt_nv_V4 :
1497 Hexagon::JMP_EQrrNotPt_nv_V4;
1498 case Hexagon::JMP_EQriPt_nv_V4:
1499 return !invertPredicate ? Hexagon::JMP_EQriPt_nv_V4 :
1500 Hexagon::JMP_EQriNotPt_nv_V4;
1501 case Hexagon::COMBINE_rr:
1502 return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
1503 Hexagon::COMBINE_rr_cNotPt;
1505 return !invertPredicate ? Hexagon::ASLH_cPt_V4 :
1506 Hexagon::ASLH_cNotPt_V4;
1508 return !invertPredicate ? Hexagon::ASRH_cPt_V4 :
1509 Hexagon::ASRH_cNotPt_V4;
1511 return !invertPredicate ? Hexagon::SXTB_cPt_V4 :
1512 Hexagon::SXTB_cNotPt_V4;
1514 return !invertPredicate ? Hexagon::SXTH_cPt_V4 :
1515 Hexagon::SXTH_cNotPt_V4;
1517 return !invertPredicate ? Hexagon::ZXTB_cPt_V4 :
1518 Hexagon::ZXTB_cNotPt_V4;
1520 return !invertPredicate ? Hexagon::ZXTH_cPt_V4 :
1521 Hexagon::ZXTH_cNotPt_V4;
1524 return !invertPredicate ? Hexagon::JMPR_cPt :
1525 Hexagon::JMPR_cNotPt;
1527 // V4 indexed+scaled load.
1528 case Hexagon::LDrid_indexed_shl_V4:
1529 return !invertPredicate ? Hexagon::LDrid_indexed_shl_cPt_V4 :
1530 Hexagon::LDrid_indexed_shl_cNotPt_V4;
1531 case Hexagon::LDrib_indexed_shl_V4:
1532 return !invertPredicate ? Hexagon::LDrib_indexed_shl_cPt_V4 :
1533 Hexagon::LDrib_indexed_shl_cNotPt_V4;
1534 case Hexagon::LDriub_indexed_shl_V4:
1535 return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
1536 Hexagon::LDriub_indexed_shl_cNotPt_V4;
1537 case Hexagon::LDrih_indexed_shl_V4:
1538 return !invertPredicate ? Hexagon::LDrih_indexed_shl_cPt_V4 :
1539 Hexagon::LDrih_indexed_shl_cNotPt_V4;
1540 case Hexagon::LDriuh_indexed_shl_V4:
1541 return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
1542 Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1543 case Hexagon::LDriw_indexed_shl_V4:
1544 return !invertPredicate ? Hexagon::LDriw_indexed_shl_cPt_V4 :
1545 Hexagon::LDriw_indexed_shl_cNotPt_V4;
1547 // V4 Load from global address
1548 case Hexagon::LDd_GP_V4:
1549 return !invertPredicate ? Hexagon::LDd_GP_cPt_V4 :
1550 Hexagon::LDd_GP_cNotPt_V4;
1551 case Hexagon::LDb_GP_V4:
1552 return !invertPredicate ? Hexagon::LDb_GP_cPt_V4 :
1553 Hexagon::LDb_GP_cNotPt_V4;
1554 case Hexagon::LDub_GP_V4:
1555 return !invertPredicate ? Hexagon::LDub_GP_cPt_V4 :
1556 Hexagon::LDub_GP_cNotPt_V4;
1557 case Hexagon::LDh_GP_V4:
1558 return !invertPredicate ? Hexagon::LDh_GP_cPt_V4 :
1559 Hexagon::LDh_GP_cNotPt_V4;
1560 case Hexagon::LDuh_GP_V4:
1561 return !invertPredicate ? Hexagon::LDuh_GP_cPt_V4 :
1562 Hexagon::LDuh_GP_cNotPt_V4;
1563 case Hexagon::LDw_GP_V4:
1564 return !invertPredicate ? Hexagon::LDw_GP_cPt_V4 :
1565 Hexagon::LDw_GP_cNotPt_V4;
1568 case Hexagon::POST_STbri:
1569 return !invertPredicate ? Hexagon::POST_STbri_cPt :
1570 Hexagon::POST_STbri_cNotPt;
1571 case Hexagon::STrib:
1572 return !invertPredicate ? Hexagon::STrib_cPt :
1573 Hexagon::STrib_cNotPt;
1574 case Hexagon::STrib_indexed:
1575 return !invertPredicate ? Hexagon::STrib_indexed_cPt :
1576 Hexagon::STrib_indexed_cNotPt;
1577 case Hexagon::STrib_imm_V4:
1578 return !invertPredicate ? Hexagon::STrib_imm_cPt_V4 :
1579 Hexagon::STrib_imm_cNotPt_V4;
1580 case Hexagon::STrib_indexed_shl_V4:
1581 return !invertPredicate ? Hexagon::STrib_indexed_shl_cPt_V4 :
1582 Hexagon::STrib_indexed_shl_cNotPt_V4;
1584 case Hexagon::POST_SThri:
1585 return !invertPredicate ? Hexagon::POST_SThri_cPt :
1586 Hexagon::POST_SThri_cNotPt;
1587 case Hexagon::STrih:
1588 return !invertPredicate ? Hexagon::STrih_cPt :
1589 Hexagon::STrih_cNotPt;
1590 case Hexagon::STrih_indexed:
1591 return !invertPredicate ? Hexagon::STrih_indexed_cPt :
1592 Hexagon::STrih_indexed_cNotPt;
1593 case Hexagon::STrih_imm_V4:
1594 return !invertPredicate ? Hexagon::STrih_imm_cPt_V4 :
1595 Hexagon::STrih_imm_cNotPt_V4;
1596 case Hexagon::STrih_indexed_shl_V4:
1597 return !invertPredicate ? Hexagon::STrih_indexed_shl_cPt_V4 :
1598 Hexagon::STrih_indexed_shl_cNotPt_V4;
1600 case Hexagon::POST_STwri:
1601 return !invertPredicate ? Hexagon::POST_STwri_cPt :
1602 Hexagon::POST_STwri_cNotPt;
1603 case Hexagon::STriw:
1604 return !invertPredicate ? Hexagon::STriw_cPt :
1605 Hexagon::STriw_cNotPt;
1606 case Hexagon::STriw_indexed:
1607 return !invertPredicate ? Hexagon::STriw_indexed_cPt :
1608 Hexagon::STriw_indexed_cNotPt;
1609 case Hexagon::STriw_indexed_shl_V4:
1610 return !invertPredicate ? Hexagon::STriw_indexed_shl_cPt_V4 :
1611 Hexagon::STriw_indexed_shl_cNotPt_V4;
1612 case Hexagon::STriw_imm_V4:
1613 return !invertPredicate ? Hexagon::STriw_imm_cPt_V4 :
1614 Hexagon::STriw_imm_cNotPt_V4;
1616 case Hexagon::POST_STdri:
1617 return !invertPredicate ? Hexagon::POST_STdri_cPt :
1618 Hexagon::POST_STdri_cNotPt;
1619 case Hexagon::STrid:
1620 return !invertPredicate ? Hexagon::STrid_cPt :
1621 Hexagon::STrid_cNotPt;
1622 case Hexagon::STrid_indexed:
1623 return !invertPredicate ? Hexagon::STrid_indexed_cPt :
1624 Hexagon::STrid_indexed_cNotPt;
1625 case Hexagon::STrid_indexed_shl_V4:
1626 return !invertPredicate ? Hexagon::STrid_indexed_shl_cPt_V4 :
1627 Hexagon::STrid_indexed_shl_cNotPt_V4;
1629 // V4 Store to global address
1630 case Hexagon::STd_GP_V4:
1631 return !invertPredicate ? Hexagon::STd_GP_cPt_V4 :
1632 Hexagon::STd_GP_cNotPt_V4;
1633 case Hexagon::STb_GP_V4:
1634 return !invertPredicate ? Hexagon::STb_GP_cPt_V4 :
1635 Hexagon::STb_GP_cNotPt_V4;
1636 case Hexagon::STh_GP_V4:
1637 return !invertPredicate ? Hexagon::STh_GP_cPt_V4 :
1638 Hexagon::STh_GP_cNotPt_V4;
1639 case Hexagon::STw_GP_V4:
1640 return !invertPredicate ? Hexagon::STw_GP_cPt_V4 :
1641 Hexagon::STw_GP_cNotPt_V4;
1644 case Hexagon::LDrid:
1645 return !invertPredicate ? Hexagon::LDrid_cPt :
1646 Hexagon::LDrid_cNotPt;
1647 case Hexagon::LDriw:
1648 return !invertPredicate ? Hexagon::LDriw_cPt :
1649 Hexagon::LDriw_cNotPt;
1650 case Hexagon::LDrih:
1651 return !invertPredicate ? Hexagon::LDrih_cPt :
1652 Hexagon::LDrih_cNotPt;
1653 case Hexagon::LDriuh:
1654 return !invertPredicate ? Hexagon::LDriuh_cPt :
1655 Hexagon::LDriuh_cNotPt;
1656 case Hexagon::LDrib:
1657 return !invertPredicate ? Hexagon::LDrib_cPt :
1658 Hexagon::LDrib_cNotPt;
1659 case Hexagon::LDriub:
1660 return !invertPredicate ? Hexagon::LDriub_cPt :
1661 Hexagon::LDriub_cNotPt;
1663 case Hexagon::LDrid_indexed:
1664 return !invertPredicate ? Hexagon::LDrid_indexed_cPt :
1665 Hexagon::LDrid_indexed_cNotPt;
1666 case Hexagon::LDriw_indexed:
1667 return !invertPredicate ? Hexagon::LDriw_indexed_cPt :
1668 Hexagon::LDriw_indexed_cNotPt;
1669 case Hexagon::LDrih_indexed:
1670 return !invertPredicate ? Hexagon::LDrih_indexed_cPt :
1671 Hexagon::LDrih_indexed_cNotPt;
1672 case Hexagon::LDriuh_indexed:
1673 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt :
1674 Hexagon::LDriuh_indexed_cNotPt;
1675 case Hexagon::LDrib_indexed:
1676 return !invertPredicate ? Hexagon::LDrib_indexed_cPt :
1677 Hexagon::LDrib_indexed_cNotPt;
1678 case Hexagon::LDriub_indexed:
1679 return !invertPredicate ? Hexagon::LDriub_indexed_cPt :
1680 Hexagon::LDriub_indexed_cNotPt;
1681 // Post Increment Load.
1682 case Hexagon::POST_LDrid:
1683 return !invertPredicate ? Hexagon::POST_LDrid_cPt :
1684 Hexagon::POST_LDrid_cNotPt;
1685 case Hexagon::POST_LDriw:
1686 return !invertPredicate ? Hexagon::POST_LDriw_cPt :
1687 Hexagon::POST_LDriw_cNotPt;
1688 case Hexagon::POST_LDrih:
1689 return !invertPredicate ? Hexagon::POST_LDrih_cPt :
1690 Hexagon::POST_LDrih_cNotPt;
1691 case Hexagon::POST_LDriuh:
1692 return !invertPredicate ? Hexagon::POST_LDriuh_cPt :
1693 Hexagon::POST_LDriuh_cNotPt;
1694 case Hexagon::POST_LDrib:
1695 return !invertPredicate ? Hexagon::POST_LDrib_cPt :
1696 Hexagon::POST_LDrib_cNotPt;
1697 case Hexagon::POST_LDriub:
1698 return !invertPredicate ? Hexagon::POST_LDriub_cPt :
1699 Hexagon::POST_LDriub_cNotPt;
1701 case Hexagon::DEALLOC_RET_V4:
1702 return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
1703 Hexagon::DEALLOC_RET_cNotPt_V4;
1705 llvm_unreachable("Unexpected predicable instruction");
1709 bool HexagonInstrInfo::
1710 PredicateInstruction(MachineInstr *MI,
1711 const SmallVectorImpl<MachineOperand> &Cond) const {
1712 int Opc = MI->getOpcode();
1713 assert (isPredicable(MI) && "Expected predicable instruction");
1714 bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
1715 (Cond[0].getImm() == 0));
1717 // This will change MI's opcode to its predicate version.
1718 // However, its operand list is still the old one, i.e. the
1719 // non-predicate one.
1720 MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
1723 unsigned int GAIdx = 0;
1725 // Indicates whether the current MI has a GlobalAddress operand
1726 bool hasGAOpnd = false;
1727 std::vector<MachineOperand> tmpOpnds;
1729 // Indicates whether we need to shift operands to right.
1730 bool needShift = true;
1732 // The predicate is ALWAYS the FIRST input operand !!!
1733 if (MI->getNumOperands() == 0) {
1734 // The non-predicate version of MI does not take any operands,
1735 // i.e. no outs and no ins. In this condition, the predicate
1736 // operand will be directly placed at Operands[0]. No operand
1742 else if ( MI->getOperand(MI->getNumOperands()-1).isReg()
1743 && MI->getOperand(MI->getNumOperands()-1).isDef()
1744 && !MI->getOperand(MI->getNumOperands()-1).isImplicit()) {
1745 // The non-predicate version of MI does not have any input operands.
1746 // In this condition, we extend the length of Operands[] by one and
1747 // copy the original last operand to the newly allocated slot.
1748 // At this moment, it is just a place holder. Later, we will put
1749 // predicate operand directly into it. No operand shift is needed.
1750 // Example: r0=BARRIER (this is a faked insn used here for illustration)
1751 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
1753 oper = MI->getNumOperands() - 2;
1756 // We need to right shift all input operands by one. Duplicate the
1757 // last operand into the newly allocated slot.
1758 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
1763 // Operands[ MI->getNumOperands() - 2 ] has been copied into
1764 // Operands[ MI->getNumOperands() - 1 ], so we start from
1765 // Operands[ MI->getNumOperands() - 3 ].
1766 // oper is a signed int.
1767 // It is ok if "MI->getNumOperands()-3" is -3, -2, or -1.
1768 for (oper = MI->getNumOperands() - 3; oper >= 0; --oper)
1770 MachineOperand &MO = MI->getOperand(oper);
1772 // Opnd[0] Opnd[1] Opnd[2] Opnd[3] Opnd[4] Opnd[5] Opnd[6] Opnd[7]
1773 // <Def0> <Def1> <Use0> <Use1> <ImpDef0> <ImpDef1> <ImpUse0> <ImpUse1>
1777 // Predicate Operand here
1778 if (MO.isReg() && !MO.isUse() && !MO.isImplicit()) {
1782 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
1783 MO.isImplicit(), MO.isKill(),
1784 MO.isDead(), MO.isUndef(),
1787 else if (MO.isImm()) {
1788 MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
1790 else if (MO.isGlobal()) {
1791 // MI can not have more than one GlobalAddress operand.
1792 assert(hasGAOpnd == false && "MI can only have one GlobalAddress opnd");
1794 // There is no member function called "ChangeToGlobalAddress" in the
1795 // MachineOperand class (not like "ChangeToRegister" and
1796 // "ChangeToImmediate"). So we have to remove them from Operands[] list
1797 // first, and then add them back after we have inserted the predicate
1798 // operand. tmpOpnds[] is to remember these operands before we remove
1800 tmpOpnds.push_back(MO);
1802 // Operands[oper] is a GlobalAddress operand;
1803 // Operands[oper+1] has been copied into Operands[oper+2];
1809 assert(false && "Unexpected operand type");
1814 int regPos = invertJump ? 1 : 0;
1815 MachineOperand PredMO = Cond[regPos];
1817 // [oper] now points to the last explicit Def. Predicate operand must be
1818 // located at [oper+1]. See diagram above.
1819 // This assumes that the predicate is always the first operand,
1820 // i.e. Operands[0+numResults], in the set of inputs
1821 // It is better to have an assert here to check this. But I don't know how
1822 // to write this assert because findFirstPredOperandIdx() would return -1
1823 if (oper < -1) oper = -1;
1824 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
1825 PredMO.isImplicit(), PredMO.isKill(),
1826 PredMO.isDead(), PredMO.isUndef(),
1833 // Operands[GAIdx] is the original GlobalAddress operand, which is
1834 // already copied into tmpOpnds[0].
1835 // Operands[GAIdx] now stores a copy of Operands[GAIdx-1]
1836 // Operands[GAIdx+1] has already been copied into Operands[GAIdx+2],
1837 // so we start from [GAIdx+2]
1838 for (i = GAIdx + 2; i < MI->getNumOperands(); ++i)
1839 tmpOpnds.push_back(MI->getOperand(i));
1841 // Remove all operands in range [ (GAIdx+1) ... (MI->getNumOperands()-1) ]
1842 // It is very important that we always remove from the end of Operands[]
1843 // MI->getNumOperands() is at least 2 if program goes to here.
1844 for (i = MI->getNumOperands() - 1; i > GAIdx; --i)
1845 MI->RemoveOperand(i);
1847 for (i = 0; i < tmpOpnds.size(); ++i)
1848 MI->addOperand(tmpOpnds[i]);
1857 isProfitableToIfCvt(MachineBasicBlock &MBB,
1859 unsigned ExtraPredCycles,
1860 const BranchProbability &Probability) const {
1867 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1868 unsigned NumTCycles,
1869 unsigned ExtraTCycles,
1870 MachineBasicBlock &FMBB,
1871 unsigned NumFCycles,
1872 unsigned ExtraFCycles,
1873 const BranchProbability &Probability) const {
1878 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
1879 const uint64_t F = MI->getDesc().TSFlags;
1881 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1885 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
1886 std::vector<MachineOperand> &Pred) const {
1887 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
1888 MachineOperand MO = MI->getOperand(oper);
1889 if (MO.isReg() && MO.isDef()) {
1890 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
1891 if (RC == &Hexagon::PredRegsRegClass) {
1903 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
1904 const SmallVectorImpl<MachineOperand> &Pred2) const {
1911 // We indicate that we want to reverse the branch by
1912 // inserting a 0 at the beginning of the Cond vector.
1914 bool HexagonInstrInfo::
1915 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1916 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
1917 Cond.erase(Cond.begin());
1919 Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
1925 bool HexagonInstrInfo::
1926 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
1927 const BranchProbability &Probability) const {
1928 return (NumInstrs <= 4);
1931 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
1932 switch (MI->getOpcode()) {
1933 default: return false;
1934 case Hexagon::DEALLOC_RET_V4 :
1935 case Hexagon::DEALLOC_RET_cPt_V4 :
1936 case Hexagon::DEALLOC_RET_cNotPt_V4 :
1937 case Hexagon::DEALLOC_RET_cdnPnt_V4 :
1938 case Hexagon::DEALLOC_RET_cNotdnPnt_V4 :
1939 case Hexagon::DEALLOC_RET_cdnPt_V4 :
1940 case Hexagon::DEALLOC_RET_cNotdnPt_V4 :
1946 bool HexagonInstrInfo::
1947 isValidOffset(const int Opcode, const int Offset) const {
1948 // This function is to check whether the "Offset" is in the correct range of
1949 // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
1950 // inserted to calculate the final address. Due to this reason, the function
1951 // assumes that the "Offset" has correct alignment.
1955 case Hexagon::LDriw:
1956 case Hexagon::LDriw_indexed:
1957 case Hexagon::LDriw_f:
1958 case Hexagon::STriw_indexed:
1959 case Hexagon::STriw:
1960 case Hexagon::STriw_f:
1961 assert((Offset % 4 == 0) && "Offset has incorrect alignment");
1962 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
1963 (Offset <= Hexagon_MEMW_OFFSET_MAX);
1965 case Hexagon::LDrid:
1966 case Hexagon::LDrid_indexed:
1967 case Hexagon::LDrid_f:
1968 case Hexagon::STrid:
1969 case Hexagon::STrid_indexed:
1970 case Hexagon::STrid_f:
1971 assert((Offset % 8 == 0) && "Offset has incorrect alignment");
1972 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
1973 (Offset <= Hexagon_MEMD_OFFSET_MAX);
1975 case Hexagon::LDrih:
1976 case Hexagon::LDriuh:
1977 case Hexagon::STrih:
1978 assert((Offset % 2 == 0) && "Offset has incorrect alignment");
1979 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
1980 (Offset <= Hexagon_MEMH_OFFSET_MAX);
1982 case Hexagon::LDrib:
1983 case Hexagon::STrib:
1984 case Hexagon::LDriub:
1985 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
1986 (Offset <= Hexagon_MEMB_OFFSET_MAX);
1988 case Hexagon::ADD_ri:
1989 case Hexagon::TFR_FI:
1990 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
1991 (Offset <= Hexagon_ADDI_OFFSET_MAX);
1993 case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
1994 case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
1995 case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
1996 case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
1997 case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
1998 case Hexagon::MEMw_ORr_indexed_MEM_V4 :
1999 case Hexagon::MEMw_ADDi_MEM_V4 :
2000 case Hexagon::MEMw_SUBi_MEM_V4 :
2001 case Hexagon::MEMw_ADDr_MEM_V4 :
2002 case Hexagon::MEMw_SUBr_MEM_V4 :
2003 case Hexagon::MEMw_ANDr_MEM_V4 :
2004 case Hexagon::MEMw_ORr_MEM_V4 :
2005 assert ((Offset % 4) == 0 && "MEMOPw offset is not aligned correctly." );
2006 return (0 <= Offset && Offset <= 255);
2008 case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
2009 case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
2010 case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
2011 case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
2012 case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
2013 case Hexagon::MEMh_ORr_indexed_MEM_V4 :
2014 case Hexagon::MEMh_ADDi_MEM_V4 :
2015 case Hexagon::MEMh_SUBi_MEM_V4 :
2016 case Hexagon::MEMh_ADDr_MEM_V4 :
2017 case Hexagon::MEMh_SUBr_MEM_V4 :
2018 case Hexagon::MEMh_ANDr_MEM_V4 :
2019 case Hexagon::MEMh_ORr_MEM_V4 :
2020 assert ((Offset % 2) == 0 && "MEMOPh offset is not aligned correctly." );
2021 return (0 <= Offset && Offset <= 127);
2023 case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
2024 case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
2025 case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
2026 case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
2027 case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
2028 case Hexagon::MEMb_ORr_indexed_MEM_V4 :
2029 case Hexagon::MEMb_ADDi_MEM_V4 :
2030 case Hexagon::MEMb_SUBi_MEM_V4 :
2031 case Hexagon::MEMb_ADDr_MEM_V4 :
2032 case Hexagon::MEMb_SUBr_MEM_V4 :
2033 case Hexagon::MEMb_ANDr_MEM_V4 :
2034 case Hexagon::MEMb_ORr_MEM_V4 :
2035 return (0 <= Offset && Offset <= 63);
2037 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
2038 // any size. Later pass knows how to handle it.
2039 case Hexagon::STriw_pred:
2040 case Hexagon::LDriw_pred:
2043 case Hexagon::LOOP0_i:
2044 return isUInt<10>(Offset);
2046 // INLINEASM is very special.
2047 case Hexagon::INLINEASM:
2051 llvm_unreachable("No offset range is defined for this opcode. "
2052 "Please define it in the above switch statement!");
2057 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2059 bool HexagonInstrInfo::
2060 isValidAutoIncImm(const EVT VT, const int Offset) const {
2062 if (VT == MVT::i64) {
2063 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
2064 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
2065 (Offset & 0x7) == 0);
2067 if (VT == MVT::i32) {
2068 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
2069 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
2070 (Offset & 0x3) == 0);
2072 if (VT == MVT::i16) {
2073 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
2074 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
2075 (Offset & 0x1) == 0);
2077 if (VT == MVT::i8) {
2078 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
2079 Offset <= Hexagon_MEMB_AUTOINC_MAX);
2081 llvm_unreachable("Not an auto-inc opc!");
2085 bool HexagonInstrInfo::
2086 isMemOp(const MachineInstr *MI) const {
2087 switch (MI->getOpcode())
2089 default: return false;
2090 case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
2091 case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
2092 case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
2093 case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
2094 case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
2095 case Hexagon::MEMw_ORr_indexed_MEM_V4 :
2096 case Hexagon::MEMw_ADDi_MEM_V4 :
2097 case Hexagon::MEMw_SUBi_MEM_V4 :
2098 case Hexagon::MEMw_ADDr_MEM_V4 :
2099 case Hexagon::MEMw_SUBr_MEM_V4 :
2100 case Hexagon::MEMw_ANDr_MEM_V4 :
2101 case Hexagon::MEMw_ORr_MEM_V4 :
2102 case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
2103 case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
2104 case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
2105 case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
2106 case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
2107 case Hexagon::MEMh_ORr_indexed_MEM_V4 :
2108 case Hexagon::MEMh_ADDi_MEM_V4 :
2109 case Hexagon::MEMh_SUBi_MEM_V4 :
2110 case Hexagon::MEMh_ADDr_MEM_V4 :
2111 case Hexagon::MEMh_SUBr_MEM_V4 :
2112 case Hexagon::MEMh_ANDr_MEM_V4 :
2113 case Hexagon::MEMh_ORr_MEM_V4 :
2114 case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
2115 case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
2116 case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
2117 case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
2118 case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
2119 case Hexagon::MEMb_ORr_indexed_MEM_V4 :
2120 case Hexagon::MEMb_ADDi_MEM_V4 :
2121 case Hexagon::MEMb_SUBi_MEM_V4 :
2122 case Hexagon::MEMb_ADDr_MEM_V4 :
2123 case Hexagon::MEMb_SUBr_MEM_V4 :
2124 case Hexagon::MEMb_ANDr_MEM_V4 :
2125 case Hexagon::MEMb_ORr_MEM_V4 :
2131 bool HexagonInstrInfo::
2132 isSpillPredRegOp(const MachineInstr *MI) const {
2133 switch (MI->getOpcode()) {
2134 default: return false;
2135 case Hexagon::STriw_pred :
2136 case Hexagon::LDriw_pred :
2141 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
2142 switch (MI->getOpcode()) {
2143 default: return false;
2144 case Hexagon::CMPEQrr:
2145 case Hexagon::CMPEQri:
2146 case Hexagon::CMPLTrr:
2147 case Hexagon::CMPGTrr:
2148 case Hexagon::CMPGTri:
2149 case Hexagon::CMPLTUrr:
2150 case Hexagon::CMPGTUrr:
2151 case Hexagon::CMPGTUri:
2152 case Hexagon::CMPGEri:
2153 case Hexagon::CMPGEUri:
2158 bool HexagonInstrInfo::
2159 isConditionalTransfer (const MachineInstr *MI) const {
2160 switch (MI->getOpcode()) {
2161 default: return false;
2162 case Hexagon::TFR_cPt:
2163 case Hexagon::TFR_cNotPt:
2164 case Hexagon::TFRI_cPt:
2165 case Hexagon::TFRI_cNotPt:
2166 case Hexagon::TFR_cdnPt:
2167 case Hexagon::TFR_cdnNotPt:
2168 case Hexagon::TFRI_cdnPt:
2169 case Hexagon::TFRI_cdnNotPt:
2174 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
2175 const HexagonRegisterInfo& QRI = getRegisterInfo();
2176 switch (MI->getOpcode())
2178 default: return false;
2179 case Hexagon::ADD_ri_cPt:
2180 case Hexagon::ADD_ri_cNotPt:
2181 case Hexagon::ADD_rr_cPt:
2182 case Hexagon::ADD_rr_cNotPt:
2183 case Hexagon::XOR_rr_cPt:
2184 case Hexagon::XOR_rr_cNotPt:
2185 case Hexagon::AND_rr_cPt:
2186 case Hexagon::AND_rr_cNotPt:
2187 case Hexagon::OR_rr_cPt:
2188 case Hexagon::OR_rr_cNotPt:
2189 case Hexagon::SUB_rr_cPt:
2190 case Hexagon::SUB_rr_cNotPt:
2191 case Hexagon::COMBINE_rr_cPt:
2192 case Hexagon::COMBINE_rr_cNotPt:
2194 case Hexagon::ASLH_cPt_V4:
2195 case Hexagon::ASLH_cNotPt_V4:
2196 case Hexagon::ASRH_cPt_V4:
2197 case Hexagon::ASRH_cNotPt_V4:
2198 case Hexagon::SXTB_cPt_V4:
2199 case Hexagon::SXTB_cNotPt_V4:
2200 case Hexagon::SXTH_cPt_V4:
2201 case Hexagon::SXTH_cNotPt_V4:
2202 case Hexagon::ZXTB_cPt_V4:
2203 case Hexagon::ZXTB_cNotPt_V4:
2204 case Hexagon::ZXTH_cPt_V4:
2205 case Hexagon::ZXTH_cNotPt_V4:
2206 return QRI.Subtarget.hasV4TOps();
2210 bool HexagonInstrInfo::
2211 isConditionalLoad (const MachineInstr* MI) const {
2212 const HexagonRegisterInfo& QRI = getRegisterInfo();
2213 switch (MI->getOpcode())
2215 default: return false;
2216 case Hexagon::LDrid_cPt :
2217 case Hexagon::LDrid_cNotPt :
2218 case Hexagon::LDrid_indexed_cPt :
2219 case Hexagon::LDrid_indexed_cNotPt :
2220 case Hexagon::LDriw_cPt :
2221 case Hexagon::LDriw_cNotPt :
2222 case Hexagon::LDriw_indexed_cPt :
2223 case Hexagon::LDriw_indexed_cNotPt :
2224 case Hexagon::LDrih_cPt :
2225 case Hexagon::LDrih_cNotPt :
2226 case Hexagon::LDrih_indexed_cPt :
2227 case Hexagon::LDrih_indexed_cNotPt :
2228 case Hexagon::LDrib_cPt :
2229 case Hexagon::LDrib_cNotPt :
2230 case Hexagon::LDrib_indexed_cPt :
2231 case Hexagon::LDrib_indexed_cNotPt :
2232 case Hexagon::LDriuh_cPt :
2233 case Hexagon::LDriuh_cNotPt :
2234 case Hexagon::LDriuh_indexed_cPt :
2235 case Hexagon::LDriuh_indexed_cNotPt :
2236 case Hexagon::LDriub_cPt :
2237 case Hexagon::LDriub_cNotPt :
2238 case Hexagon::LDriub_indexed_cPt :
2239 case Hexagon::LDriub_indexed_cNotPt :
2241 case Hexagon::POST_LDrid_cPt :
2242 case Hexagon::POST_LDrid_cNotPt :
2243 case Hexagon::POST_LDriw_cPt :
2244 case Hexagon::POST_LDriw_cNotPt :
2245 case Hexagon::POST_LDrih_cPt :
2246 case Hexagon::POST_LDrih_cNotPt :
2247 case Hexagon::POST_LDrib_cPt :
2248 case Hexagon::POST_LDrib_cNotPt :
2249 case Hexagon::POST_LDriuh_cPt :
2250 case Hexagon::POST_LDriuh_cNotPt :
2251 case Hexagon::POST_LDriub_cPt :
2252 case Hexagon::POST_LDriub_cNotPt :
2253 return QRI.Subtarget.hasV4TOps();
2254 case Hexagon::LDrid_indexed_shl_cPt_V4 :
2255 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
2256 case Hexagon::LDrib_indexed_shl_cPt_V4 :
2257 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
2258 case Hexagon::LDriub_indexed_shl_cPt_V4 :
2259 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
2260 case Hexagon::LDrih_indexed_shl_cPt_V4 :
2261 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
2262 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
2263 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
2264 case Hexagon::LDriw_indexed_shl_cPt_V4 :
2265 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
2266 return QRI.Subtarget.hasV4TOps();
2270 // Returns true if an instruction is a conditional store.
2272 // Note: It doesn't include conditional new-value stores as they can't be
2273 // converted to .new predicate.
2275 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
2277 // / \ (not OK. it will cause new-value store to be
2278 // / X conditional on p0.new while R2 producer is
2281 // p.new store p.old NV store
2282 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
2288 // [if (p0)memw(R0+#0)=R2]
2290 // The above diagram shows the steps involoved in the conversion of a predicated
2291 // store instruction to its .new predicated new-value form.
2293 // The following set of instructions further explains the scenario where
2294 // conditional new-value store becomes invalid when promoted to .new predicate
2297 // { 1) if (p0) r0 = add(r1, r2)
2298 // 2) p0 = cmp.eq(r3, #0) }
2300 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
2301 // the first two instructions because in instr 1, r0 is conditional on old value
2302 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
2303 // is not valid for new-value stores.
2304 bool HexagonInstrInfo::
2305 isConditionalStore (const MachineInstr* MI) const {
2306 const HexagonRegisterInfo& QRI = getRegisterInfo();
2307 switch (MI->getOpcode())
2309 default: return false;
2310 case Hexagon::STrib_imm_cPt_V4 :
2311 case Hexagon::STrib_imm_cNotPt_V4 :
2312 case Hexagon::STrib_indexed_shl_cPt_V4 :
2313 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
2314 case Hexagon::STrib_cPt :
2315 case Hexagon::STrib_cNotPt :
2316 case Hexagon::POST_STbri_cPt :
2317 case Hexagon::POST_STbri_cNotPt :
2318 case Hexagon::STrid_indexed_cPt :
2319 case Hexagon::STrid_indexed_cNotPt :
2320 case Hexagon::STrid_indexed_shl_cPt_V4 :
2321 case Hexagon::POST_STdri_cPt :
2322 case Hexagon::POST_STdri_cNotPt :
2323 case Hexagon::STrih_cPt :
2324 case Hexagon::STrih_cNotPt :
2325 case Hexagon::STrih_indexed_cPt :
2326 case Hexagon::STrih_indexed_cNotPt :
2327 case Hexagon::STrih_imm_cPt_V4 :
2328 case Hexagon::STrih_imm_cNotPt_V4 :
2329 case Hexagon::STrih_indexed_shl_cPt_V4 :
2330 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
2331 case Hexagon::POST_SThri_cPt :
2332 case Hexagon::POST_SThri_cNotPt :
2333 case Hexagon::STriw_cPt :
2334 case Hexagon::STriw_cNotPt :
2335 case Hexagon::STriw_indexed_cPt :
2336 case Hexagon::STriw_indexed_cNotPt :
2337 case Hexagon::STriw_imm_cPt_V4 :
2338 case Hexagon::STriw_imm_cNotPt_V4 :
2339 case Hexagon::STriw_indexed_shl_cPt_V4 :
2340 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
2341 case Hexagon::POST_STwri_cPt :
2342 case Hexagon::POST_STwri_cNotPt :
2343 return QRI.Subtarget.hasV4TOps();
2345 // V4 global address store before promoting to dot new.
2346 case Hexagon::STd_GP_cPt_V4 :
2347 case Hexagon::STd_GP_cNotPt_V4 :
2348 case Hexagon::STb_GP_cPt_V4 :
2349 case Hexagon::STb_GP_cNotPt_V4 :
2350 case Hexagon::STh_GP_cPt_V4 :
2351 case Hexagon::STh_GP_cNotPt_V4 :
2352 case Hexagon::STw_GP_cPt_V4 :
2353 case Hexagon::STw_GP_cNotPt_V4 :
2354 return QRI.Subtarget.hasV4TOps();
2356 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
2357 // from the "Conditional Store" list. Because a predicated new value store
2358 // would NOT be promoted to a double dot new store. See diagram below:
2359 // This function returns yes for those stores that are predicated but not
2360 // yet promoted to predicate dot new instructions.
2362 // +---------------------+
2363 // /-----| if (p0) memw(..)=r0 |---------\~
2364 // || +---------------------+ ||
2365 // promote || /\ /\ || promote
2367 // \||/ demote || \||/
2369 // +-------------------------+ || +-------------------------+
2370 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
2371 // +-------------------------+ || +-------------------------+
2374 // promote || \/ NOT possible
2378 // +-----------------------------+
2379 // | if (p0.new) memw(..)=r0.new |
2380 // +-----------------------------+
2381 // Double Dot New Store
2386 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
2387 const uint64_t F = MI->getDesc().TSFlags;
2389 return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
2392 /// immediateExtend - Changes the instruction in place to one using an immediate
2394 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
2395 assert((isExtendable(MI)||isConstExtended(MI)) &&
2396 "Instruction must be extendable");
2397 // Find which operand is extendable.
2398 short ExtOpNum = getCExtOpNum(MI);
2399 MachineOperand &MO = MI->getOperand(ExtOpNum);
2400 // This needs to be something we understand.
2401 assert((MO.isMBB() || MO.isImm()) &&
2402 "Branch with unknown extendable field type");
2403 // Mark given operand as extended.
2404 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
2407 DFAPacketizer *HexagonInstrInfo::
2408 CreateTargetScheduleState(const TargetMachine *TM,
2409 const ScheduleDAG *DAG) const {
2410 const InstrItineraryData *II = TM->getInstrItineraryData();
2411 return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II);
2414 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
2415 const MachineBasicBlock *MBB,
2416 const MachineFunction &MF) const {
2417 // Debug info is never a scheduling boundary. It's necessary to be explicit
2418 // due to the special treatment of IT instructions below, otherwise a
2419 // dbg_value followed by an IT will result in the IT instruction being
2420 // considered a scheduling hazard, which is wrong. It should be the actual
2421 // instruction preceding the dbg_value instruction(s), just like it is
2422 // when debug info is not present.
2423 if (MI->isDebugValue())
2426 // Terminators and labels can't be scheduled around.
2427 if (MI->getDesc().isTerminator() || MI->isLabel() || MI->isInlineAsm())
2433 bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const {
2435 // Constant extenders are allowed only for V4 and above.
2436 if (!Subtarget.hasV4TOps())
2439 const uint64_t F = MI->getDesc().TSFlags;
2440 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
2441 if (isExtended) // Instruction must be extended.
2444 unsigned isExtendable = (F >> HexagonII::ExtendablePos)
2445 & HexagonII::ExtendableMask;
2449 short ExtOpNum = getCExtOpNum(MI);
2450 const MachineOperand &MO = MI->getOperand(ExtOpNum);
2451 // Use MO operand flags to determine if MO
2452 // has the HMOTF_ConstExtended flag set.
2453 if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
2455 // If this is a Machine BB address we are talking about, and it is
2456 // not marked as extended, say so.
2460 // We could be using an instruction with an extendable immediate and shoehorn
2461 // a global address into it. If it is a global address it will be constant
2462 // extended. We do this for COMBINE.
2463 // We currently only handle isGlobal() because it is the only kind of
2464 // object we are going to end up with here for now.
2465 // In the future we probably should add isSymbol(), etc.
2466 if (MO.isGlobal() || MO.isSymbol())
2469 // If the extendable operand is not 'Immediate' type, the instruction should
2470 // have 'isExtended' flag set.
2471 assert(MO.isImm() && "Extendable operand must be Immediate type");
2473 int MinValue = getMinValue(MI);
2474 int MaxValue = getMaxValue(MI);
2475 int ImmValue = MO.getImm();
2477 return (ImmValue < MinValue || ImmValue > MaxValue);
2480 // Returns true if a particular operand is extendable for an instruction.
2481 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
2482 unsigned short OperandNum) const {
2483 // Constant extenders are allowed only for V4 and above.
2484 if (!Subtarget.hasV4TOps())
2487 const uint64_t F = MI->getDesc().TSFlags;
2489 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
2493 // Returns Operand Index for the constant extended instruction.
2494 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
2495 const uint64_t F = MI->getDesc().TSFlags;
2496 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
2499 // Returns the min value that doesn't need to be extended.
2500 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
2501 const uint64_t F = MI->getDesc().TSFlags;
2502 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
2503 & HexagonII::ExtentSignedMask;
2504 unsigned bits = (F >> HexagonII::ExtentBitsPos)
2505 & HexagonII::ExtentBitsMask;
2507 if (isSigned) // if value is signed
2508 return -1 << (bits - 1);
2513 // Returns the max value that doesn't need to be extended.
2514 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
2515 const uint64_t F = MI->getDesc().TSFlags;
2516 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
2517 & HexagonII::ExtentSignedMask;
2518 unsigned bits = (F >> HexagonII::ExtentBitsPos)
2519 & HexagonII::ExtentBitsMask;
2521 if (isSigned) // if value is signed
2522 return ~(-1 << (bits - 1));
2524 return ~(-1 << bits);
2527 // Returns true if an instruction can be converted into a non-extended
2528 // equivalent instruction.
2529 bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const {
2532 // Check if the instruction has a register form that uses register in place
2533 // of the extended operand, if so return that as the non-extended form.
2534 if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
2537 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
2538 // Check addressing mode and retreive non-ext equivalent instruction.
2540 switch (getAddrMode(MI)) {
2541 case HexagonII::Absolute :
2542 // Load/store with absolute addressing mode can be converted into
2543 // base+offset mode.
2544 NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
2546 case HexagonII::BaseImmOffset :
2547 // Load/store with base+offset addressing mode can be converted into
2548 // base+register offset addressing mode. However left shift operand should
2550 NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
2555 if (NonExtOpcode < 0)
2562 // Returns opcode of the non-extended equivalent instruction.
2563 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
2565 // Check if the instruction has a register form that uses register in place
2566 // of the extended operand, if so return that as the non-extended form.
2567 short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
2568 if (NonExtOpcode >= 0)
2569 return NonExtOpcode;
2571 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
2572 // Check addressing mode and retreive non-ext equivalent instruction.
2573 switch (getAddrMode(MI)) {
2574 case HexagonII::Absolute :
2575 return Hexagon::getBasedWithImmOffset(MI->getOpcode());
2576 case HexagonII::BaseImmOffset :
2577 return Hexagon::getBaseWithRegOffset(MI->getOpcode());