1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/raw_ostream.h"
32 #define DEBUG_TYPE "hexagon-instrinfo"
34 #define GET_INSTRINFO_CTOR_DTOR
35 #define GET_INSTRMAP_INFO
36 #include "HexagonGenInstrInfo.inc"
37 #include "HexagonGenDFAPacketizer.inc"
40 /// Constants for Hexagon instructions.
42 const int Hexagon_MEMW_OFFSET_MAX = 4095;
43 const int Hexagon_MEMW_OFFSET_MIN = -4096;
44 const int Hexagon_MEMD_OFFSET_MAX = 8191;
45 const int Hexagon_MEMD_OFFSET_MIN = -8192;
46 const int Hexagon_MEMH_OFFSET_MAX = 2047;
47 const int Hexagon_MEMH_OFFSET_MIN = -2048;
48 const int Hexagon_MEMB_OFFSET_MAX = 1023;
49 const int Hexagon_MEMB_OFFSET_MIN = -1024;
50 const int Hexagon_ADDI_OFFSET_MAX = 32767;
51 const int Hexagon_ADDI_OFFSET_MIN = -32768;
52 const int Hexagon_MEMD_AUTOINC_MAX = 56;
53 const int Hexagon_MEMD_AUTOINC_MIN = -64;
54 const int Hexagon_MEMW_AUTOINC_MAX = 28;
55 const int Hexagon_MEMW_AUTOINC_MIN = -32;
56 const int Hexagon_MEMH_AUTOINC_MAX = 14;
57 const int Hexagon_MEMH_AUTOINC_MIN = -16;
58 const int Hexagon_MEMB_AUTOINC_MAX = 7;
59 const int Hexagon_MEMB_AUTOINC_MIN = -8;
61 // Pin the vtable to this file.
62 void HexagonInstrInfo::anchor() {}
64 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
65 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
66 RI(ST), Subtarget(ST) {
70 /// isLoadFromStackSlot - If the specified machine instruction is a direct
71 /// load from a stack slot, return the virtual or physical register number of
72 /// the destination along with the FrameIndex of the loaded stack slot. If
73 /// not, return 0. This predicate must return 0 if the instruction has
74 /// any side effects other than loading from the stack slot.
75 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
76 int &FrameIndex) const {
79 switch (MI->getOpcode()) {
81 case Hexagon::L2_loadri_io:
82 case Hexagon::L2_loadrd_io:
83 case Hexagon::L2_loadrh_io:
84 case Hexagon::L2_loadrb_io:
85 case Hexagon::L2_loadrub_io:
86 if (MI->getOperand(2).isFI() &&
87 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
88 FrameIndex = MI->getOperand(2).getIndex();
89 return MI->getOperand(0).getReg();
97 /// isStoreToStackSlot - If the specified machine instruction is a direct
98 /// store to a stack slot, return the virtual or physical register number of
99 /// the source reg along with the FrameIndex of the loaded stack slot. If
100 /// not, return 0. This predicate must return 0 if the instruction has
101 /// any side effects other than storing to the stack slot.
102 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
103 int &FrameIndex) const {
104 switch (MI->getOpcode()) {
106 case Hexagon::S2_storeri_io:
107 case Hexagon::S2_storerd_io:
108 case Hexagon::S2_storerh_io:
109 case Hexagon::S2_storerb_io:
110 if (MI->getOperand(2).isFI() &&
111 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
112 FrameIndex = MI->getOperand(0).getIndex();
113 return MI->getOperand(2).getReg();
122 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
123 MachineBasicBlock *FBB,
124 const SmallVectorImpl<MachineOperand> &Cond,
127 int BOpc = Hexagon::J2_jump;
128 int BccOpc = Hexagon::J2_jumpt;
130 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
133 // Check if ReverseBranchCondition has asked to reverse this branch
134 // If we want to reverse the branch an odd number of times, we want
136 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
137 BccOpc = Hexagon::J2_jumpf;
143 // Due to a bug in TailMerging/CFG Optimization, we need to add a
144 // special case handling of a predicated jump followed by an
145 // unconditional jump. If not, Tail Merging and CFG Optimization go
146 // into an infinite loop.
147 MachineBasicBlock *NewTBB, *NewFBB;
148 SmallVector<MachineOperand, 4> Cond;
149 MachineInstr *Term = MBB.getFirstTerminator();
150 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
152 MachineBasicBlock *NextBB =
153 std::next(MachineFunction::iterator(&MBB));
154 if (NewTBB == NextBB) {
155 ReverseBranchCondition(Cond);
157 return InsertBranch(MBB, TBB, nullptr, Cond, DL);
160 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
163 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
168 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
169 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
175 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
176 MachineBasicBlock *&TBB,
177 MachineBasicBlock *&FBB,
178 SmallVectorImpl<MachineOperand> &Cond,
179 bool AllowModify) const {
183 // If the block has no terminators, it just falls into the block after it.
184 MachineBasicBlock::instr_iterator I = MBB.instr_end();
185 if (I == MBB.instr_begin())
188 // A basic block may looks like this:
198 // It has two succs but does not have a terminator
199 // Don't know how to handle it.
204 } while (I != MBB.instr_begin());
209 while (I->isDebugValue()) {
210 if (I == MBB.instr_begin())
215 // Delete the JMP if it's equivalent to a fall-through.
216 if (AllowModify && I->getOpcode() == Hexagon::J2_jump &&
217 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
218 DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
219 I->eraseFromParent();
221 if (I == MBB.instr_begin())
225 if (!isUnpredicatedTerminator(I))
228 // Get the last instruction in the block.
229 MachineInstr *LastInst = I;
230 MachineInstr *SecondLastInst = nullptr;
231 // Find one more terminator if present.
233 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(I)) {
237 // This is a third branch.
240 if (I == MBB.instr_begin())
245 int LastOpcode = LastInst->getOpcode();
247 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
248 bool LastOpcodeHasNot = PredOpcodeHasNot(LastOpcode);
250 // If there is only one terminator instruction, process it.
251 if (LastInst && !SecondLastInst) {
252 if (LastOpcode == Hexagon::J2_jump) {
253 TBB = LastInst->getOperand(0).getMBB();
256 if (LastOpcode == Hexagon::ENDLOOP0) {
257 TBB = LastInst->getOperand(0).getMBB();
258 Cond.push_back(LastInst->getOperand(0));
261 if (LastOpcodeHasJMP_c) {
262 TBB = LastInst->getOperand(1).getMBB();
263 if (LastOpcodeHasNot) {
264 Cond.push_back(MachineOperand::CreateImm(0));
266 Cond.push_back(LastInst->getOperand(0));
269 // Otherwise, don't know what this is.
273 int SecLastOpcode = SecondLastInst->getOpcode();
275 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
276 bool SecLastOpcodeHasNot = PredOpcodeHasNot(SecLastOpcode);
277 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
278 TBB = SecondLastInst->getOperand(1).getMBB();
279 if (SecLastOpcodeHasNot)
280 Cond.push_back(MachineOperand::CreateImm(0));
281 Cond.push_back(SecondLastInst->getOperand(0));
282 FBB = LastInst->getOperand(0).getMBB();
286 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
287 // executed, so remove it.
288 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
289 TBB = SecondLastInst->getOperand(0).getMBB();
292 I->eraseFromParent();
296 // If the block ends with an ENDLOOP, and JMP, handle it.
297 if (SecLastOpcode == Hexagon::ENDLOOP0 &&
298 LastOpcode == Hexagon::J2_jump) {
299 TBB = SecondLastInst->getOperand(0).getMBB();
300 Cond.push_back(SecondLastInst->getOperand(0));
301 FBB = LastInst->getOperand(0).getMBB();
305 // Otherwise, can't handle this.
310 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
311 int BOpc = Hexagon::J2_jump;
312 int BccOpc = Hexagon::J2_jumpt;
313 int BccOpcNot = Hexagon::J2_jumpf;
315 MachineBasicBlock::iterator I = MBB.end();
316 if (I == MBB.begin()) return 0;
318 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
319 I->getOpcode() != BccOpcNot)
322 // Remove the branch.
323 I->eraseFromParent();
327 if (I == MBB.begin()) return 1;
329 if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
332 // Remove the branch.
333 I->eraseFromParent();
338 /// \brief For a comparison instruction, return the source registers in
339 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
340 /// compares against in CmpValue. Return true if the comparison instruction
342 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
343 unsigned &SrcReg, unsigned &SrcReg2,
344 int &Mask, int &Value) const {
345 unsigned Opc = MI->getOpcode();
347 // Set mask and the first source register.
349 case Hexagon::C2_cmpeqp:
350 case Hexagon::C2_cmpeqi:
351 case Hexagon::C2_cmpeq:
352 case Hexagon::C2_cmpgtp:
353 case Hexagon::C2_cmpgtup:
354 case Hexagon::C2_cmpgtui:
355 case Hexagon::C2_cmpgtu:
356 case Hexagon::C2_cmpgti:
357 case Hexagon::C2_cmpgt:
358 SrcReg = MI->getOperand(1).getReg();
361 case Hexagon::A4_cmpbeqi:
362 case Hexagon::A4_cmpbeq:
363 case Hexagon::A4_cmpbgtui:
364 case Hexagon::A4_cmpbgtu:
365 case Hexagon::A4_cmpbgt:
366 SrcReg = MI->getOperand(1).getReg();
369 case Hexagon::CMPhEQri_V4:
370 case Hexagon::CMPhEQrr_shl_V4:
371 case Hexagon::CMPhEQrr_xor_V4:
372 case Hexagon::CMPhGTUri_V4:
373 case Hexagon::CMPhGTUrr_V4:
374 case Hexagon::CMPhGTrr_shl_V4:
375 SrcReg = MI->getOperand(1).getReg();
380 // Set the value/second source register.
382 case Hexagon::C2_cmpeqp:
383 case Hexagon::C2_cmpeq:
384 case Hexagon::C2_cmpgtp:
385 case Hexagon::C2_cmpgtup:
386 case Hexagon::C2_cmpgtu:
387 case Hexagon::C2_cmpgt:
388 case Hexagon::A4_cmpbeq:
389 case Hexagon::A4_cmpbgtu:
390 case Hexagon::A4_cmpbgt:
391 case Hexagon::CMPhEQrr_shl_V4:
392 case Hexagon::CMPhEQrr_xor_V4:
393 case Hexagon::CMPhGTUrr_V4:
394 case Hexagon::CMPhGTrr_shl_V4:
395 SrcReg2 = MI->getOperand(2).getReg();
398 case Hexagon::C2_cmpeqi:
399 case Hexagon::C2_cmpgtui:
400 case Hexagon::C2_cmpgti:
401 case Hexagon::A4_cmpbeqi:
402 case Hexagon::A4_cmpbgtui:
403 case Hexagon::CMPhEQri_V4:
404 case Hexagon::CMPhGTUri_V4:
406 Value = MI->getOperand(2).getImm();
414 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
415 MachineBasicBlock::iterator I, DebugLoc DL,
416 unsigned DestReg, unsigned SrcReg,
417 bool KillSrc) const {
418 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
419 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg).addReg(SrcReg);
422 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
423 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg).addReg(SrcReg);
426 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
427 // Map Pd = Ps to Pd = or(Ps, Ps).
428 BuildMI(MBB, I, DL, get(Hexagon::C2_or),
429 DestReg).addReg(SrcReg).addReg(SrcReg);
432 if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
433 Hexagon::IntRegsRegClass.contains(SrcReg)) {
434 // We can have an overlap between single and double reg: r1:0 = r0.
435 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
437 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
438 Hexagon::subreg_hireg))).addImm(0);
440 // r1:0 = r1 or no overlap.
441 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), (RI.getSubReg(DestReg,
442 Hexagon::subreg_loreg))).addReg(SrcReg);
443 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
444 Hexagon::subreg_hireg))).addImm(0);
448 if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
449 Hexagon::IntRegsRegClass.contains(SrcReg)) {
450 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg).addReg(SrcReg);
453 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
454 Hexagon::IntRegsRegClass.contains(DestReg)) {
455 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg).
456 addReg(SrcReg, getKillRegState(KillSrc));
459 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
460 Hexagon::PredRegsRegClass.contains(DestReg)) {
461 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg).
462 addReg(SrcReg, getKillRegState(KillSrc));
466 llvm_unreachable("Unimplemented");
470 void HexagonInstrInfo::
471 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
472 unsigned SrcReg, bool isKill, int FI,
473 const TargetRegisterClass *RC,
474 const TargetRegisterInfo *TRI) const {
476 DebugLoc DL = MBB.findDebugLoc(I);
477 MachineFunction &MF = *MBB.getParent();
478 MachineFrameInfo &MFI = *MF.getFrameInfo();
479 unsigned Align = MFI.getObjectAlignment(FI);
481 MachineMemOperand *MMO =
482 MF.getMachineMemOperand(
483 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
484 MachineMemOperand::MOStore,
485 MFI.getObjectSize(FI),
488 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
489 BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
490 .addFrameIndex(FI).addImm(0)
491 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
492 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
493 BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
494 .addFrameIndex(FI).addImm(0)
495 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
496 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
497 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
498 .addFrameIndex(FI).addImm(0)
499 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
501 llvm_unreachable("Unimplemented");
506 void HexagonInstrInfo::storeRegToAddr(
507 MachineFunction &MF, unsigned SrcReg,
509 SmallVectorImpl<MachineOperand> &Addr,
510 const TargetRegisterClass *RC,
511 SmallVectorImpl<MachineInstr*> &NewMIs) const
513 llvm_unreachable("Unimplemented");
517 void HexagonInstrInfo::
518 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
519 unsigned DestReg, int FI,
520 const TargetRegisterClass *RC,
521 const TargetRegisterInfo *TRI) const {
522 DebugLoc DL = MBB.findDebugLoc(I);
523 MachineFunction &MF = *MBB.getParent();
524 MachineFrameInfo &MFI = *MF.getFrameInfo();
525 unsigned Align = MFI.getObjectAlignment(FI);
527 MachineMemOperand *MMO =
528 MF.getMachineMemOperand(
529 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
530 MachineMemOperand::MOLoad,
531 MFI.getObjectSize(FI),
533 if (RC == &Hexagon::IntRegsRegClass) {
534 BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
535 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
536 } else if (RC == &Hexagon::DoubleRegsRegClass) {
537 BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
538 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
539 } else if (RC == &Hexagon::PredRegsRegClass) {
540 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
541 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
543 llvm_unreachable("Can't store this register to stack slot");
548 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
549 SmallVectorImpl<MachineOperand> &Addr,
550 const TargetRegisterClass *RC,
551 SmallVectorImpl<MachineInstr*> &NewMIs) const {
552 llvm_unreachable("Unimplemented");
556 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
558 const SmallVectorImpl<unsigned> &Ops,
560 // Hexagon_TODO: Implement.
564 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
566 MachineRegisterInfo &RegInfo = MF->getRegInfo();
567 const TargetRegisterClass *TRC;
569 TRC = &Hexagon::PredRegsRegClass;
570 } else if (VT == MVT::i32 || VT == MVT::f32) {
571 TRC = &Hexagon::IntRegsRegClass;
572 } else if (VT == MVT::i64 || VT == MVT::f64) {
573 TRC = &Hexagon::DoubleRegsRegClass;
575 llvm_unreachable("Cannot handle this register class");
578 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
582 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
583 // Constant extenders are allowed only for V4 and above.
584 if (!Subtarget.hasV4TOps())
587 const MCInstrDesc &MID = MI->getDesc();
588 const uint64_t F = MID.TSFlags;
589 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
592 // TODO: This is largely obsolete now. Will need to be removed
593 // in consecutive patches.
594 switch(MI->getOpcode()) {
595 // TFR_FI Remains a special case.
596 case Hexagon::TFR_FI:
604 // This returns true in two cases:
605 // - The OP code itself indicates that this is an extended instruction.
606 // - One of MOs has been marked with HMOTF_ConstExtended flag.
607 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
608 // First check if this is permanently extended op code.
609 const uint64_t F = MI->getDesc().TSFlags;
610 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
612 // Use MO operand flags to determine if one of MI's operands
613 // has HMOTF_ConstExtended flag set.
614 for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
615 E = MI->operands_end(); I != E; ++I) {
616 if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
622 bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
623 return MI->getDesc().isBranch();
626 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
627 if (isNewValueJump(MI))
630 if (isNewValueStore(MI))
636 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
637 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
640 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
641 bool isPred = MI->getDesc().isPredicable();
646 const int Opc = MI->getOpcode();
649 case Hexagon::A2_tfrsi:
650 return isInt<12>(MI->getOperand(1).getImm());
652 case Hexagon::S2_storerd_io:
653 return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
655 case Hexagon::S2_storeri_io:
656 case Hexagon::S2_storerinew_io:
657 return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
659 case Hexagon::S2_storerh_io:
660 case Hexagon::S2_storerhnew_io:
661 return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
663 case Hexagon::S2_storerb_io:
664 case Hexagon::S2_storerbnew_io:
665 return isUInt<6>(MI->getOperand(1).getImm());
667 case Hexagon::L2_loadrd_io:
668 return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
670 case Hexagon::L2_loadri_io:
671 return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
673 case Hexagon::L2_loadrh_io:
674 case Hexagon::L2_loadruh_io:
675 return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
677 case Hexagon::L2_loadrb_io:
678 case Hexagon::L2_loadrub_io:
679 return isUInt<6>(MI->getOperand(2).getImm());
681 case Hexagon::L2_loadrd_pi:
682 return isShiftedInt<4,3>(MI->getOperand(3).getImm());
684 case Hexagon::L2_loadri_pi:
685 return isShiftedInt<4,2>(MI->getOperand(3).getImm());
687 case Hexagon::L2_loadrh_pi:
688 case Hexagon::L2_loadruh_pi:
689 return isShiftedInt<4,1>(MI->getOperand(3).getImm());
691 case Hexagon::L2_loadrb_pi:
692 case Hexagon::L2_loadrub_pi:
693 return isInt<4>(MI->getOperand(3).getImm());
695 case Hexagon::S4_storeirb_io:
696 case Hexagon::S4_storeirh_io:
697 case Hexagon::S4_storeiri_io:
698 return (isUInt<6>(MI->getOperand(1).getImm()) &&
699 isInt<6>(MI->getOperand(2).getImm()));
701 case Hexagon::ADD_ri:
702 return isInt<8>(MI->getOperand(2).getImm());
704 case Hexagon::A2_aslh:
705 case Hexagon::A2_asrh:
706 case Hexagon::A2_sxtb:
707 case Hexagon::A2_sxth:
708 case Hexagon::A2_zxtb:
709 case Hexagon::A2_zxth:
710 return Subtarget.hasV4TOps();
716 // This function performs the following inversiones:
721 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
723 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
724 : Hexagon::getTruePredOpcode(Opc);
725 if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
726 return InvPredOpcode;
729 default: llvm_unreachable("Unexpected predicated instruction");
730 case Hexagon::C2_ccombinewt:
731 return Hexagon::C2_ccombinewf;
732 case Hexagon::C2_ccombinewf:
733 return Hexagon::C2_ccombinewt;
736 case Hexagon::L4_return_t:
737 return Hexagon::L4_return_f;
738 case Hexagon::L4_return_f:
739 return Hexagon::L4_return_t;
743 // New Value Store instructions.
744 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
745 const uint64_t F = MI->getDesc().TSFlags;
747 return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
750 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
751 const uint64_t F = get(Opcode).TSFlags;
753 return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
756 int HexagonInstrInfo::
757 getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
758 enum Hexagon::PredSense inPredSense;
759 inPredSense = invertPredicate ? Hexagon::PredSense_false :
760 Hexagon::PredSense_true;
761 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
762 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
765 // This switch case will be removed once all the instructions have been
766 // modified to use relation maps.
768 case Hexagon::TFRI_f:
769 return !invertPredicate ? Hexagon::TFRI_cPt_f :
770 Hexagon::TFRI_cNotPt_f;
771 case Hexagon::A2_combinew:
772 return !invertPredicate ? Hexagon::C2_ccombinewt :
773 Hexagon::C2_ccombinewf;
776 case Hexagon::STriw_f:
777 return !invertPredicate ? Hexagon::S2_pstorerit_io:
778 Hexagon::S2_pstorerif_io;
779 case Hexagon::STriw_indexed_f:
780 return !invertPredicate ? Hexagon::S2_pstorerit_io:
781 Hexagon::S2_pstorerif_io;
784 case Hexagon::L4_return:
785 return !invertPredicate ? Hexagon::L4_return_t:
786 Hexagon::L4_return_f;
788 llvm_unreachable("Unexpected predicable instruction");
792 bool HexagonInstrInfo::
793 PredicateInstruction(MachineInstr *MI,
794 const SmallVectorImpl<MachineOperand> &Cond) const {
795 int Opc = MI->getOpcode();
796 assert (isPredicable(MI) && "Expected predicable instruction");
797 bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
798 (Cond[0].getImm() == 0));
800 // This will change MI's opcode to its predicate version.
801 // However, its operand list is still the old one, i.e. the
802 // non-predicate one.
803 MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
806 unsigned int GAIdx = 0;
808 // Indicates whether the current MI has a GlobalAddress operand
809 bool hasGAOpnd = false;
810 std::vector<MachineOperand> tmpOpnds;
812 // Indicates whether we need to shift operands to right.
813 bool needShift = true;
815 // The predicate is ALWAYS the FIRST input operand !!!
816 if (MI->getNumOperands() == 0) {
817 // The non-predicate version of MI does not take any operands,
818 // i.e. no outs and no ins. In this condition, the predicate
819 // operand will be directly placed at Operands[0]. No operand
825 else if ( MI->getOperand(MI->getNumOperands()-1).isReg()
826 && MI->getOperand(MI->getNumOperands()-1).isDef()
827 && !MI->getOperand(MI->getNumOperands()-1).isImplicit()) {
828 // The non-predicate version of MI does not have any input operands.
829 // In this condition, we extend the length of Operands[] by one and
830 // copy the original last operand to the newly allocated slot.
831 // At this moment, it is just a place holder. Later, we will put
832 // predicate operand directly into it. No operand shift is needed.
833 // Example: r0=BARRIER (this is a faked insn used here for illustration)
834 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
836 oper = MI->getNumOperands() - 2;
839 // We need to right shift all input operands by one. Duplicate the
840 // last operand into the newly allocated slot.
841 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
846 // Operands[ MI->getNumOperands() - 2 ] has been copied into
847 // Operands[ MI->getNumOperands() - 1 ], so we start from
848 // Operands[ MI->getNumOperands() - 3 ].
849 // oper is a signed int.
850 // It is ok if "MI->getNumOperands()-3" is -3, -2, or -1.
851 for (oper = MI->getNumOperands() - 3; oper >= 0; --oper)
853 MachineOperand &MO = MI->getOperand(oper);
855 // Opnd[0] Opnd[1] Opnd[2] Opnd[3] Opnd[4] Opnd[5] Opnd[6] Opnd[7]
856 // <Def0> <Def1> <Use0> <Use1> <ImpDef0> <ImpDef1> <ImpUse0> <ImpUse1>
860 // Predicate Operand here
861 if (MO.isReg() && !MO.isUse() && !MO.isImplicit()) {
865 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
866 MO.isImplicit(), MO.isKill(),
867 MO.isDead(), MO.isUndef(),
870 else if (MO.isImm()) {
871 MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
873 else if (MO.isGlobal()) {
874 // MI can not have more than one GlobalAddress operand.
875 assert(hasGAOpnd == false && "MI can only have one GlobalAddress opnd");
877 // There is no member function called "ChangeToGlobalAddress" in the
878 // MachineOperand class (not like "ChangeToRegister" and
879 // "ChangeToImmediate"). So we have to remove them from Operands[] list
880 // first, and then add them back after we have inserted the predicate
881 // operand. tmpOpnds[] is to remember these operands before we remove
883 tmpOpnds.push_back(MO);
885 // Operands[oper] is a GlobalAddress operand;
886 // Operands[oper+1] has been copied into Operands[oper+2];
892 llvm_unreachable("Unexpected operand type");
897 int regPos = invertJump ? 1 : 0;
898 MachineOperand PredMO = Cond[regPos];
900 // [oper] now points to the last explicit Def. Predicate operand must be
901 // located at [oper+1]. See diagram above.
902 // This assumes that the predicate is always the first operand,
903 // i.e. Operands[0+numResults], in the set of inputs
904 // It is better to have an assert here to check this. But I don't know how
905 // to write this assert because findFirstPredOperandIdx() would return -1
906 if (oper < -1) oper = -1;
908 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
909 PredMO.isImplicit(), false,
910 PredMO.isDead(), PredMO.isUndef(),
913 MachineRegisterInfo &RegInfo = MI->getParent()->getParent()->getRegInfo();
914 RegInfo.clearKillFlags(PredMO.getReg());
920 // Operands[GAIdx] is the original GlobalAddress operand, which is
921 // already copied into tmpOpnds[0].
922 // Operands[GAIdx] now stores a copy of Operands[GAIdx-1]
923 // Operands[GAIdx+1] has already been copied into Operands[GAIdx+2],
924 // so we start from [GAIdx+2]
925 for (i = GAIdx + 2; i < MI->getNumOperands(); ++i)
926 tmpOpnds.push_back(MI->getOperand(i));
928 // Remove all operands in range [ (GAIdx+1) ... (MI->getNumOperands()-1) ]
929 // It is very important that we always remove from the end of Operands[]
930 // MI->getNumOperands() is at least 2 if program goes to here.
931 for (i = MI->getNumOperands() - 1; i > GAIdx; --i)
932 MI->RemoveOperand(i);
934 for (i = 0; i < tmpOpnds.size(); ++i)
935 MI->addOperand(tmpOpnds[i]);
944 isProfitableToIfCvt(MachineBasicBlock &MBB,
946 unsigned ExtraPredCycles,
947 const BranchProbability &Probability) const {
954 isProfitableToIfCvt(MachineBasicBlock &TMBB,
956 unsigned ExtraTCycles,
957 MachineBasicBlock &FMBB,
959 unsigned ExtraFCycles,
960 const BranchProbability &Probability) const {
964 // Returns true if an instruction is predicated irrespective of the predicate
965 // sense. For example, all of the following will return true.
966 // if (p0) R1 = add(R2, R3)
967 // if (!p0) R1 = add(R2, R3)
968 // if (p0.new) R1 = add(R2, R3)
969 // if (!p0.new) R1 = add(R2, R3)
970 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
971 const uint64_t F = MI->getDesc().TSFlags;
973 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
976 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
977 const uint64_t F = get(Opcode).TSFlags;
979 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
982 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
983 const uint64_t F = MI->getDesc().TSFlags;
985 assert(isPredicated(MI));
986 return (!((F >> HexagonII::PredicatedFalsePos) &
987 HexagonII::PredicatedFalseMask));
990 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
991 const uint64_t F = get(Opcode).TSFlags;
993 // Make sure that the instruction is predicated.
994 assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
995 return (!((F >> HexagonII::PredicatedFalsePos) &
996 HexagonII::PredicatedFalseMask));
999 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
1000 const uint64_t F = MI->getDesc().TSFlags;
1002 assert(isPredicated(MI));
1003 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1006 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
1007 const uint64_t F = get(Opcode).TSFlags;
1009 assert(isPredicated(Opcode));
1010 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1013 // Returns true, if a ST insn can be promoted to a new-value store.
1014 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
1015 const HexagonRegisterInfo& QRI = getRegisterInfo();
1016 const uint64_t F = MI->getDesc().TSFlags;
1018 return ((F >> HexagonII::mayNVStorePos) &
1019 HexagonII::mayNVStoreMask &
1020 QRI.Subtarget.hasV4TOps());
1024 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
1025 std::vector<MachineOperand> &Pred) const {
1026 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
1027 MachineOperand MO = MI->getOperand(oper);
1028 if (MO.isReg() && MO.isDef()) {
1029 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
1030 if (RC == &Hexagon::PredRegsRegClass) {
1042 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
1043 const SmallVectorImpl<MachineOperand> &Pred2) const {
1050 // We indicate that we want to reverse the branch by
1051 // inserting a 0 at the beginning of the Cond vector.
1053 bool HexagonInstrInfo::
1054 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1055 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
1056 Cond.erase(Cond.begin());
1058 Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
1064 bool HexagonInstrInfo::
1065 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
1066 const BranchProbability &Probability) const {
1067 return (NumInstrs <= 4);
1070 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
1071 switch (MI->getOpcode()) {
1072 default: return false;
1073 case Hexagon::L4_return:
1074 case Hexagon::L4_return_t:
1075 case Hexagon::L4_return_f:
1076 case Hexagon::L4_return_tnew_pnt:
1077 case Hexagon::L4_return_fnew_pnt:
1078 case Hexagon::L4_return_tnew_pt:
1079 case Hexagon::L4_return_fnew_pt:
1085 bool HexagonInstrInfo::
1086 isValidOffset(const int Opcode, const int Offset) const {
1087 // This function is to check whether the "Offset" is in the correct range of
1088 // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
1089 // inserted to calculate the final address. Due to this reason, the function
1090 // assumes that the "Offset" has correct alignment.
1091 // We used to assert if the offset was not properly aligned, however,
1092 // there are cases where a misaligned pointer recast can cause this
1093 // problem, and we need to allow for it. The front end warns of such
1094 // misaligns with respect to load size.
1098 case Hexagon::L2_loadri_io:
1099 case Hexagon::LDriw_f:
1100 case Hexagon::S2_storeri_io:
1101 case Hexagon::STriw_f:
1102 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
1103 (Offset <= Hexagon_MEMW_OFFSET_MAX);
1105 case Hexagon::L2_loadrd_io:
1106 case Hexagon::LDrid_f:
1107 case Hexagon::S2_storerd_io:
1108 case Hexagon::STrid_f:
1109 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
1110 (Offset <= Hexagon_MEMD_OFFSET_MAX);
1112 case Hexagon::L2_loadrh_io:
1113 case Hexagon::L2_loadruh_io:
1114 case Hexagon::S2_storerh_io:
1115 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
1116 (Offset <= Hexagon_MEMH_OFFSET_MAX);
1118 case Hexagon::L2_loadrb_io:
1119 case Hexagon::S2_storerb_io:
1120 case Hexagon::L2_loadrub_io:
1121 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
1122 (Offset <= Hexagon_MEMB_OFFSET_MAX);
1124 case Hexagon::ADD_ri:
1125 case Hexagon::TFR_FI:
1126 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
1127 (Offset <= Hexagon_ADDI_OFFSET_MAX);
1129 case Hexagon::L4_iadd_memopw_io:
1130 case Hexagon::L4_isub_memopw_io:
1131 case Hexagon::L4_add_memopw_io:
1132 case Hexagon::L4_sub_memopw_io:
1133 case Hexagon::L4_and_memopw_io:
1134 case Hexagon::L4_or_memopw_io:
1135 return (0 <= Offset && Offset <= 255);
1137 case Hexagon::L4_iadd_memoph_io:
1138 case Hexagon::L4_isub_memoph_io:
1139 case Hexagon::L4_add_memoph_io:
1140 case Hexagon::L4_sub_memoph_io:
1141 case Hexagon::L4_and_memoph_io:
1142 case Hexagon::L4_or_memoph_io:
1143 return (0 <= Offset && Offset <= 127);
1145 case Hexagon::L4_iadd_memopb_io:
1146 case Hexagon::L4_isub_memopb_io:
1147 case Hexagon::L4_add_memopb_io:
1148 case Hexagon::L4_sub_memopb_io:
1149 case Hexagon::L4_and_memopb_io:
1150 case Hexagon::L4_or_memopb_io:
1151 return (0 <= Offset && Offset <= 63);
1153 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
1154 // any size. Later pass knows how to handle it.
1155 case Hexagon::STriw_pred:
1156 case Hexagon::LDriw_pred:
1159 case Hexagon::J2_loop0i:
1160 return isUInt<10>(Offset);
1162 // INLINEASM is very special.
1163 case Hexagon::INLINEASM:
1167 llvm_unreachable("No offset range is defined for this opcode. "
1168 "Please define it in the above switch statement!");
1173 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
1175 bool HexagonInstrInfo::
1176 isValidAutoIncImm(const EVT VT, const int Offset) const {
1178 if (VT == MVT::i64) {
1179 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
1180 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
1181 (Offset & 0x7) == 0);
1183 if (VT == MVT::i32) {
1184 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
1185 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
1186 (Offset & 0x3) == 0);
1188 if (VT == MVT::i16) {
1189 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
1190 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
1191 (Offset & 0x1) == 0);
1193 if (VT == MVT::i8) {
1194 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
1195 Offset <= Hexagon_MEMB_AUTOINC_MAX);
1197 llvm_unreachable("Not an auto-inc opc!");
1201 bool HexagonInstrInfo::
1202 isMemOp(const MachineInstr *MI) const {
1203 // return MI->getDesc().mayLoad() && MI->getDesc().mayStore();
1205 switch (MI->getOpcode())
1207 default: return false;
1208 case Hexagon::L4_iadd_memopw_io:
1209 case Hexagon::L4_isub_memopw_io:
1210 case Hexagon::L4_add_memopw_io:
1211 case Hexagon::L4_sub_memopw_io:
1212 case Hexagon::L4_and_memopw_io:
1213 case Hexagon::L4_or_memopw_io:
1214 case Hexagon::L4_iadd_memoph_io:
1215 case Hexagon::L4_isub_memoph_io:
1216 case Hexagon::L4_add_memoph_io:
1217 case Hexagon::L4_sub_memoph_io:
1218 case Hexagon::L4_and_memoph_io:
1219 case Hexagon::L4_or_memoph_io:
1220 case Hexagon::L4_iadd_memopb_io:
1221 case Hexagon::L4_isub_memopb_io:
1222 case Hexagon::L4_add_memopb_io:
1223 case Hexagon::L4_sub_memopb_io:
1224 case Hexagon::L4_and_memopb_io:
1225 case Hexagon::L4_or_memopb_io:
1226 case Hexagon::L4_ior_memopb_io:
1227 case Hexagon::L4_ior_memoph_io:
1228 case Hexagon::L4_ior_memopw_io:
1229 case Hexagon::L4_iand_memopb_io:
1230 case Hexagon::L4_iand_memoph_io:
1231 case Hexagon::L4_iand_memopw_io:
1238 bool HexagonInstrInfo::
1239 isSpillPredRegOp(const MachineInstr *MI) const {
1240 switch (MI->getOpcode()) {
1241 default: return false;
1242 case Hexagon::STriw_pred :
1243 case Hexagon::LDriw_pred :
1248 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
1249 switch (MI->getOpcode()) {
1250 default: return false;
1251 case Hexagon::C2_cmpeq:
1252 case Hexagon::C2_cmpeqi:
1253 case Hexagon::C2_cmpgt:
1254 case Hexagon::C2_cmpgti:
1255 case Hexagon::C2_cmpgtu:
1256 case Hexagon::C2_cmpgtui:
1261 bool HexagonInstrInfo::
1262 isConditionalTransfer (const MachineInstr *MI) const {
1263 switch (MI->getOpcode()) {
1264 default: return false;
1265 case Hexagon::A2_tfrt:
1266 case Hexagon::A2_tfrf:
1267 case Hexagon::C2_cmoveit:
1268 case Hexagon::C2_cmoveif:
1269 case Hexagon::A2_tfrtnew:
1270 case Hexagon::A2_tfrfnew:
1271 case Hexagon::C2_cmovenewit:
1272 case Hexagon::C2_cmovenewif:
1277 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
1278 switch (MI->getOpcode())
1280 default: return false;
1281 case Hexagon::A2_paddf:
1282 case Hexagon::A2_paddfnew:
1283 case Hexagon::A2_paddt:
1284 case Hexagon::A2_paddtnew:
1285 case Hexagon::A2_pandf:
1286 case Hexagon::A2_pandfnew:
1287 case Hexagon::A2_pandt:
1288 case Hexagon::A2_pandtnew:
1289 case Hexagon::A4_paslhf:
1290 case Hexagon::A4_paslhfnew:
1291 case Hexagon::A4_paslht:
1292 case Hexagon::A4_paslhtnew:
1293 case Hexagon::A4_pasrhf:
1294 case Hexagon::A4_pasrhfnew:
1295 case Hexagon::A4_pasrht:
1296 case Hexagon::A4_pasrhtnew:
1297 case Hexagon::A2_porf:
1298 case Hexagon::A2_porfnew:
1299 case Hexagon::A2_port:
1300 case Hexagon::A2_portnew:
1301 case Hexagon::A2_psubf:
1302 case Hexagon::A2_psubfnew:
1303 case Hexagon::A2_psubt:
1304 case Hexagon::A2_psubtnew:
1305 case Hexagon::A2_pxorf:
1306 case Hexagon::A2_pxorfnew:
1307 case Hexagon::A2_pxort:
1308 case Hexagon::A2_pxortnew:
1309 case Hexagon::A4_psxthf:
1310 case Hexagon::A4_psxthfnew:
1311 case Hexagon::A4_psxtht:
1312 case Hexagon::A4_psxthtnew:
1313 case Hexagon::A4_psxtbf:
1314 case Hexagon::A4_psxtbfnew:
1315 case Hexagon::A4_psxtbt:
1316 case Hexagon::A4_psxtbtnew:
1317 case Hexagon::A4_pzxtbf:
1318 case Hexagon::A4_pzxtbfnew:
1319 case Hexagon::A4_pzxtbt:
1320 case Hexagon::A4_pzxtbtnew:
1321 case Hexagon::A4_pzxthf:
1322 case Hexagon::A4_pzxthfnew:
1323 case Hexagon::A4_pzxtht:
1324 case Hexagon::A4_pzxthtnew:
1325 case Hexagon::ADD_ri_cPt:
1326 case Hexagon::ADD_ri_cNotPt:
1327 case Hexagon::C2_ccombinewt:
1328 case Hexagon::C2_ccombinewf:
1333 bool HexagonInstrInfo::
1334 isConditionalLoad (const MachineInstr* MI) const {
1335 const HexagonRegisterInfo& QRI = getRegisterInfo();
1336 switch (MI->getOpcode())
1338 default: return false;
1339 case Hexagon::L2_ploadrdt_io :
1340 case Hexagon::L2_ploadrdf_io:
1341 case Hexagon::L2_ploadrit_io:
1342 case Hexagon::L2_ploadrif_io:
1343 case Hexagon::L2_ploadrht_io:
1344 case Hexagon::L2_ploadrhf_io:
1345 case Hexagon::L2_ploadrbt_io:
1346 case Hexagon::L2_ploadrbf_io:
1347 case Hexagon::L2_ploadruht_io:
1348 case Hexagon::L2_ploadruhf_io:
1349 case Hexagon::L2_ploadrubt_io:
1350 case Hexagon::L2_ploadrubf_io:
1352 case Hexagon::L2_ploadrdt_pi:
1353 case Hexagon::L2_ploadrdf_pi:
1354 case Hexagon::L2_ploadrit_pi:
1355 case Hexagon::L2_ploadrif_pi:
1356 case Hexagon::L2_ploadrht_pi:
1357 case Hexagon::L2_ploadrhf_pi:
1358 case Hexagon::L2_ploadrbt_pi:
1359 case Hexagon::L2_ploadrbf_pi:
1360 case Hexagon::L2_ploadruht_pi:
1361 case Hexagon::L2_ploadruhf_pi:
1362 case Hexagon::L2_ploadrubt_pi:
1363 case Hexagon::L2_ploadrubf_pi:
1364 return QRI.Subtarget.hasV4TOps();
1365 case Hexagon::L4_ploadrdt_rr:
1366 case Hexagon::L4_ploadrdf_rr:
1367 case Hexagon::L4_ploadrbt_rr:
1368 case Hexagon::L4_ploadrbf_rr:
1369 case Hexagon::L4_ploadrubt_rr:
1370 case Hexagon::L4_ploadrubf_rr:
1371 case Hexagon::L4_ploadrht_rr:
1372 case Hexagon::L4_ploadrhf_rr:
1373 case Hexagon::L4_ploadruht_rr:
1374 case Hexagon::L4_ploadruhf_rr:
1375 case Hexagon::L4_ploadrit_rr:
1376 case Hexagon::L4_ploadrif_rr:
1377 return QRI.Subtarget.hasV4TOps();
1381 // Returns true if an instruction is a conditional store.
1383 // Note: It doesn't include conditional new-value stores as they can't be
1384 // converted to .new predicate.
1386 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
1388 // / \ (not OK. it will cause new-value store to be
1389 // / X conditional on p0.new while R2 producer is
1392 // p.new store p.old NV store
1393 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
1399 // [if (p0)memw(R0+#0)=R2]
1401 // The above diagram shows the steps involoved in the conversion of a predicated
1402 // store instruction to its .new predicated new-value form.
1404 // The following set of instructions further explains the scenario where
1405 // conditional new-value store becomes invalid when promoted to .new predicate
1408 // { 1) if (p0) r0 = add(r1, r2)
1409 // 2) p0 = cmp.eq(r3, #0) }
1411 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
1412 // the first two instructions because in instr 1, r0 is conditional on old value
1413 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
1414 // is not valid for new-value stores.
1415 bool HexagonInstrInfo::
1416 isConditionalStore (const MachineInstr* MI) const {
1417 const HexagonRegisterInfo& QRI = getRegisterInfo();
1418 switch (MI->getOpcode())
1420 default: return false;
1421 case Hexagon::S4_storeirbt_io:
1422 case Hexagon::S4_storeirbf_io:
1423 case Hexagon::S4_pstorerbt_rr:
1424 case Hexagon::S4_pstorerbf_rr:
1425 case Hexagon::S2_pstorerbt_io:
1426 case Hexagon::S2_pstorerbf_io:
1427 case Hexagon::S2_pstorerbt_pi:
1428 case Hexagon::S2_pstorerbf_pi:
1429 case Hexagon::S2_pstorerdt_io:
1430 case Hexagon::S2_pstorerdf_io:
1431 case Hexagon::S4_pstorerdt_rr:
1432 case Hexagon::S4_pstorerdf_rr:
1433 case Hexagon::S2_pstorerdt_pi:
1434 case Hexagon::S2_pstorerdf_pi:
1435 case Hexagon::S2_pstorerht_io:
1436 case Hexagon::S2_pstorerhf_io:
1437 case Hexagon::S4_storeirht_io:
1438 case Hexagon::S4_storeirhf_io:
1439 case Hexagon::S4_pstorerht_rr:
1440 case Hexagon::S4_pstorerhf_rr:
1441 case Hexagon::S2_pstorerht_pi:
1442 case Hexagon::S2_pstorerhf_pi:
1443 case Hexagon::S2_pstorerit_io:
1444 case Hexagon::S2_pstorerif_io:
1445 case Hexagon::S4_storeirit_io:
1446 case Hexagon::S4_storeirif_io:
1447 case Hexagon::S4_pstorerit_rr:
1448 case Hexagon::S4_pstorerif_rr:
1449 case Hexagon::S2_pstorerit_pi:
1450 case Hexagon::S2_pstorerif_pi:
1451 return QRI.Subtarget.hasV4TOps();
1453 // V4 global address store before promoting to dot new.
1454 case Hexagon::S4_pstorerdt_abs:
1455 case Hexagon::S4_pstorerdf_abs:
1456 case Hexagon::S4_pstorerbt_abs:
1457 case Hexagon::S4_pstorerbf_abs:
1458 case Hexagon::S4_pstorerht_abs:
1459 case Hexagon::S4_pstorerhf_abs:
1460 case Hexagon::S4_pstorerit_abs:
1461 case Hexagon::S4_pstorerif_abs:
1462 return QRI.Subtarget.hasV4TOps();
1464 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
1465 // from the "Conditional Store" list. Because a predicated new value store
1466 // would NOT be promoted to a double dot new store. See diagram below:
1467 // This function returns yes for those stores that are predicated but not
1468 // yet promoted to predicate dot new instructions.
1470 // +---------------------+
1471 // /-----| if (p0) memw(..)=r0 |---------\~
1472 // || +---------------------+ ||
1473 // promote || /\ /\ || promote
1475 // \||/ demote || \||/
1477 // +-------------------------+ || +-------------------------+
1478 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
1479 // +-------------------------+ || +-------------------------+
1482 // promote || \/ NOT possible
1486 // +-----------------------------+
1487 // | if (p0.new) memw(..)=r0.new |
1488 // +-----------------------------+
1489 // Double Dot New Store
1495 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
1496 if (isNewValue(MI) && isBranch(MI))
1501 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
1502 return (getAddrMode(MI) == HexagonII::PostInc);
1505 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
1506 const uint64_t F = MI->getDesc().TSFlags;
1507 return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
1510 // Returns true, if any one of the operands is a dot new
1511 // insn, whether it is predicated dot new or register dot new.
1512 bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
1513 return (isNewValueInst(MI) ||
1514 (isPredicated(MI) && isPredicatedNew(MI)));
1517 // Returns the most basic instruction for the .new predicated instructions and
1518 // new-value stores.
1519 // For example, all of the following instructions will be converted back to the
1520 // same instruction:
1521 // 1) if (p0.new) memw(R0+#0) = R1.new --->
1522 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
1523 // 3) if (p0.new) memw(R0+#0) = R1 --->
1526 int HexagonInstrInfo::GetDotOldOp(const int opc) const {
1528 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
1529 NewOp = Hexagon::getPredOldOpcode(NewOp);
1530 assert(NewOp >= 0 &&
1531 "Couldn't change predicate new instruction to its old form.");
1534 if (isNewValueStore(NewOp)) { // Convert into non-new-value format
1535 NewOp = Hexagon::getNonNVStore(NewOp);
1536 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
1541 // Return the new value instruction for a given store.
1542 int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
1543 int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
1544 if (NVOpcode >= 0) // Valid new-value store instruction.
1547 switch (MI->getOpcode()) {
1548 default: llvm_unreachable("Unknown .new type");
1549 // store new value byte
1550 case Hexagon::STrib_shl_V4:
1551 return Hexagon::STrib_shl_nv_V4;
1553 case Hexagon::STrih_shl_V4:
1554 return Hexagon::STrih_shl_nv_V4;
1556 case Hexagon::STriw_f:
1557 return Hexagon::S2_storerinew_io;
1559 case Hexagon::STriw_indexed_f:
1560 return Hexagon::S4_storerinew_rr;
1562 case Hexagon::STriw_shl_V4:
1563 return Hexagon::STriw_shl_nv_V4;
1569 // Return .new predicate version for an instruction.
1570 int HexagonInstrInfo::GetDotNewPredOp(MachineInstr *MI,
1571 const MachineBranchProbabilityInfo
1574 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
1575 if (NewOpcode >= 0) // Valid predicate new instruction
1578 switch (MI->getOpcode()) {
1579 default: llvm_unreachable("Unknown .new type");
1581 case Hexagon::J2_jumpt:
1582 case Hexagon::J2_jumpf:
1583 return getDotNewPredJumpOp(MI, MBPI);
1585 case Hexagon::J2_jumprt:
1586 return Hexagon::J2_jumptnewpt;
1588 case Hexagon::J2_jumprf:
1589 return Hexagon::J2_jumprfnewpt;
1591 case Hexagon::JMPrett:
1592 return Hexagon::J2_jumprtnewpt;
1594 case Hexagon::JMPretf:
1595 return Hexagon::J2_jumprfnewpt;
1598 // Conditional combine
1599 case Hexagon::C2_ccombinewt:
1600 return Hexagon::C2_ccombinewnewt;
1601 case Hexagon::C2_ccombinewf:
1602 return Hexagon::C2_ccombinewnewf;
1607 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
1608 const uint64_t F = MI->getDesc().TSFlags;
1610 return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
1613 /// immediateExtend - Changes the instruction in place to one using an immediate
1615 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
1616 assert((isExtendable(MI)||isConstExtended(MI)) &&
1617 "Instruction must be extendable");
1618 // Find which operand is extendable.
1619 short ExtOpNum = getCExtOpNum(MI);
1620 MachineOperand &MO = MI->getOperand(ExtOpNum);
1621 // This needs to be something we understand.
1622 assert((MO.isMBB() || MO.isImm()) &&
1623 "Branch with unknown extendable field type");
1624 // Mark given operand as extended.
1625 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
1628 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
1629 const TargetSubtargetInfo &STI) const {
1630 const InstrItineraryData *II = STI.getInstrItineraryData();
1631 return static_cast<const HexagonSubtarget &>(STI).createDFAPacketizer(II);
1634 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1635 const MachineBasicBlock *MBB,
1636 const MachineFunction &MF) const {
1637 // Debug info is never a scheduling boundary. It's necessary to be explicit
1638 // due to the special treatment of IT instructions below, otherwise a
1639 // dbg_value followed by an IT will result in the IT instruction being
1640 // considered a scheduling hazard, which is wrong. It should be the actual
1641 // instruction preceding the dbg_value instruction(s), just like it is
1642 // when debug info is not present.
1643 if (MI->isDebugValue())
1646 // Terminators and labels can't be scheduled around.
1647 if (MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm())
1653 bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const {
1655 // Constant extenders are allowed only for V4 and above.
1656 if (!Subtarget.hasV4TOps())
1659 const uint64_t F = MI->getDesc().TSFlags;
1660 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
1661 if (isExtended) // Instruction must be extended.
1664 unsigned isExtendable = (F >> HexagonII::ExtendablePos)
1665 & HexagonII::ExtendableMask;
1669 short ExtOpNum = getCExtOpNum(MI);
1670 const MachineOperand &MO = MI->getOperand(ExtOpNum);
1671 // Use MO operand flags to determine if MO
1672 // has the HMOTF_ConstExtended flag set.
1673 if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
1675 // If this is a Machine BB address we are talking about, and it is
1676 // not marked as extended, say so.
1680 // We could be using an instruction with an extendable immediate and shoehorn
1681 // a global address into it. If it is a global address it will be constant
1682 // extended. We do this for COMBINE.
1683 // We currently only handle isGlobal() because it is the only kind of
1684 // object we are going to end up with here for now.
1685 // In the future we probably should add isSymbol(), etc.
1686 if (MO.isGlobal() || MO.isSymbol())
1689 // If the extendable operand is not 'Immediate' type, the instruction should
1690 // have 'isExtended' flag set.
1691 assert(MO.isImm() && "Extendable operand must be Immediate type");
1693 int MinValue = getMinValue(MI);
1694 int MaxValue = getMaxValue(MI);
1695 int ImmValue = MO.getImm();
1697 return (ImmValue < MinValue || ImmValue > MaxValue);
1700 // Returns the opcode to use when converting MI, which is a conditional jump,
1701 // into a conditional instruction which uses the .new value of the predicate.
1702 // We also use branch probabilities to add a hint to the jump.
1704 HexagonInstrInfo::getDotNewPredJumpOp(MachineInstr *MI,
1706 MachineBranchProbabilityInfo *MBPI) const {
1708 // We assume that block can have at most two successors.
1710 MachineBasicBlock *Src = MI->getParent();
1711 MachineOperand *BrTarget = &MI->getOperand(1);
1712 MachineBasicBlock *Dst = BrTarget->getMBB();
1714 const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
1715 if (Prediction >= BranchProbability(1,2))
1718 switch (MI->getOpcode()) {
1719 case Hexagon::J2_jumpt:
1720 return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
1721 case Hexagon::J2_jumpf:
1722 return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
1725 llvm_unreachable("Unexpected jump instruction.");
1728 // Returns true if a particular operand is extendable for an instruction.
1729 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
1730 unsigned short OperandNum) const {
1731 // Constant extenders are allowed only for V4 and above.
1732 if (!Subtarget.hasV4TOps())
1735 const uint64_t F = MI->getDesc().TSFlags;
1737 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
1741 // Returns Operand Index for the constant extended instruction.
1742 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
1743 const uint64_t F = MI->getDesc().TSFlags;
1744 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
1747 // Returns the min value that doesn't need to be extended.
1748 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
1749 const uint64_t F = MI->getDesc().TSFlags;
1750 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1751 & HexagonII::ExtentSignedMask;
1752 unsigned bits = (F >> HexagonII::ExtentBitsPos)
1753 & HexagonII::ExtentBitsMask;
1755 if (isSigned) // if value is signed
1756 return -1U << (bits - 1);
1761 // Returns the max value that doesn't need to be extended.
1762 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
1763 const uint64_t F = MI->getDesc().TSFlags;
1764 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1765 & HexagonII::ExtentSignedMask;
1766 unsigned bits = (F >> HexagonII::ExtentBitsPos)
1767 & HexagonII::ExtentBitsMask;
1769 if (isSigned) // if value is signed
1770 return ~(-1U << (bits - 1));
1772 return ~(-1U << bits);
1775 // Returns true if an instruction can be converted into a non-extended
1776 // equivalent instruction.
1777 bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const {
1780 // Check if the instruction has a register form that uses register in place
1781 // of the extended operand, if so return that as the non-extended form.
1782 if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
1785 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1786 // Check addressing mode and retrieve non-ext equivalent instruction.
1788 switch (getAddrMode(MI)) {
1789 case HexagonII::Absolute :
1790 // Load/store with absolute addressing mode can be converted into
1791 // base+offset mode.
1792 NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
1794 case HexagonII::BaseImmOffset :
1795 // Load/store with base+offset addressing mode can be converted into
1796 // base+register offset addressing mode. However left shift operand should
1798 NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
1803 if (NonExtOpcode < 0)
1810 // Returns opcode of the non-extended equivalent instruction.
1811 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
1813 // Check if the instruction has a register form that uses register in place
1814 // of the extended operand, if so return that as the non-extended form.
1815 short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
1816 if (NonExtOpcode >= 0)
1817 return NonExtOpcode;
1819 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1820 // Check addressing mode and retrieve non-ext equivalent instruction.
1821 switch (getAddrMode(MI)) {
1822 case HexagonII::Absolute :
1823 return Hexagon::getBasedWithImmOffset(MI->getOpcode());
1824 case HexagonII::BaseImmOffset :
1825 return Hexagon::getBaseWithRegOffset(MI->getOpcode());
1833 bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const {
1834 return (Opcode == Hexagon::J2_jumpt) ||
1835 (Opcode == Hexagon::J2_jumpf) ||
1836 (Opcode == Hexagon::J2_jumptnewpt) ||
1837 (Opcode == Hexagon::J2_jumpfnewpt) ||
1838 (Opcode == Hexagon::J2_jumpt) ||
1839 (Opcode == Hexagon::J2_jumpf);
1842 bool HexagonInstrInfo::PredOpcodeHasNot(Opcode_t Opcode) const {
1843 return (Opcode == Hexagon::J2_jumpf) ||
1844 (Opcode == Hexagon::J2_jumpfnewpt) ||
1845 (Opcode == Hexagon::J2_jumpfnew);