1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
28 #define GET_INSTRINFO_CTOR
29 #define GET_INSTRMAP_INFO
30 #include "HexagonGenInstrInfo.inc"
31 #include "HexagonGenDFAPacketizer.inc"
36 /// Constants for Hexagon instructions.
38 const int Hexagon_MEMW_OFFSET_MAX = 4095;
39 const int Hexagon_MEMW_OFFSET_MIN = -4096;
40 const int Hexagon_MEMD_OFFSET_MAX = 8191;
41 const int Hexagon_MEMD_OFFSET_MIN = -8192;
42 const int Hexagon_MEMH_OFFSET_MAX = 2047;
43 const int Hexagon_MEMH_OFFSET_MIN = -2048;
44 const int Hexagon_MEMB_OFFSET_MAX = 1023;
45 const int Hexagon_MEMB_OFFSET_MIN = -1024;
46 const int Hexagon_ADDI_OFFSET_MAX = 32767;
47 const int Hexagon_ADDI_OFFSET_MIN = -32768;
48 const int Hexagon_MEMD_AUTOINC_MAX = 56;
49 const int Hexagon_MEMD_AUTOINC_MIN = -64;
50 const int Hexagon_MEMW_AUTOINC_MAX = 28;
51 const int Hexagon_MEMW_AUTOINC_MIN = -32;
52 const int Hexagon_MEMH_AUTOINC_MAX = 14;
53 const int Hexagon_MEMH_AUTOINC_MIN = -16;
54 const int Hexagon_MEMB_AUTOINC_MAX = 7;
55 const int Hexagon_MEMB_AUTOINC_MIN = -8;
58 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
59 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
60 RI(ST, *this), Subtarget(ST) {
64 /// isLoadFromStackSlot - If the specified machine instruction is a direct
65 /// load from a stack slot, return the virtual or physical register number of
66 /// the destination along with the FrameIndex of the loaded stack slot. If
67 /// not, return 0. This predicate must return 0 if the instruction has
68 /// any side effects other than loading from the stack slot.
69 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
70 int &FrameIndex) const {
73 switch (MI->getOpcode()) {
80 if (MI->getOperand(2).isFI() &&
81 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
82 FrameIndex = MI->getOperand(2).getIndex();
83 return MI->getOperand(0).getReg();
91 /// isStoreToStackSlot - If the specified machine instruction is a direct
92 /// store to a stack slot, return the virtual or physical register number of
93 /// the source reg along with the FrameIndex of the loaded stack slot. If
94 /// not, return 0. This predicate must return 0 if the instruction has
95 /// any side effects other than storing to the stack slot.
96 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
97 int &FrameIndex) const {
98 switch (MI->getOpcode()) {
104 if (MI->getOperand(2).isFI() &&
105 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
106 FrameIndex = MI->getOperand(0).getIndex();
107 return MI->getOperand(2).getReg();
116 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
117 MachineBasicBlock *FBB,
118 const SmallVectorImpl<MachineOperand> &Cond,
121 int BOpc = Hexagon::JMP;
122 int BccOpc = Hexagon::JMP_t;
124 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
127 // Check if ReverseBranchCondition has asked to reverse this branch
128 // If we want to reverse the branch an odd number of times, we want
130 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
131 BccOpc = Hexagon::JMP_f;
137 // Due to a bug in TailMerging/CFG Optimization, we need to add a
138 // special case handling of a predicated jump followed by an
139 // unconditional jump. If not, Tail Merging and CFG Optimization go
140 // into an infinite loop.
141 MachineBasicBlock *NewTBB, *NewFBB;
142 SmallVector<MachineOperand, 4> Cond;
143 MachineInstr *Term = MBB.getFirstTerminator();
144 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
146 MachineBasicBlock *NextBB =
147 llvm::next(MachineFunction::iterator(&MBB));
148 if (NewTBB == NextBB) {
149 ReverseBranchCondition(Cond);
151 return InsertBranch(MBB, TBB, 0, Cond, DL);
154 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
157 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
162 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
163 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
169 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
170 MachineBasicBlock *&TBB,
171 MachineBasicBlock *&FBB,
172 SmallVectorImpl<MachineOperand> &Cond,
173 bool AllowModify) const {
177 // If the block has no terminators, it just falls into the block after it.
178 MachineBasicBlock::instr_iterator I = MBB.instr_end();
179 if (I == MBB.instr_begin())
182 // A basic block may looks like this:
192 // It has two succs but does not have a terminator
193 // Don't know how to handle it.
198 } while (I != MBB.instr_begin());
203 while (I->isDebugValue()) {
204 if (I == MBB.instr_begin())
209 // Delete the JMP if it's equivalent to a fall-through.
210 if (AllowModify && I->getOpcode() == Hexagon::JMP &&
211 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
212 DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
213 I->eraseFromParent();
215 if (I == MBB.instr_begin())
219 if (!isUnpredicatedTerminator(I))
222 // Get the last instruction in the block.
223 MachineInstr *LastInst = I;
224 MachineInstr *SecondLastInst = NULL;
225 // Find one more terminator if present.
227 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(I)) {
231 // This is a third branch.
234 if (I == MBB.instr_begin())
239 int LastOpcode = LastInst->getOpcode();
241 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
242 bool LastOpcodeHasNot = PredOpcodeHasNot(LastOpcode);
244 // If there is only one terminator instruction, process it.
245 if (LastInst && !SecondLastInst) {
246 if (LastOpcode == Hexagon::JMP) {
247 TBB = LastInst->getOperand(0).getMBB();
250 if (LastOpcode == Hexagon::ENDLOOP0) {
251 TBB = LastInst->getOperand(0).getMBB();
252 Cond.push_back(LastInst->getOperand(0));
255 if (LastOpcodeHasJMP_c) {
256 TBB = LastInst->getOperand(1).getMBB();
257 if (LastOpcodeHasNot) {
258 Cond.push_back(MachineOperand::CreateImm(0));
260 Cond.push_back(LastInst->getOperand(0));
263 // Otherwise, don't know what this is.
267 int SecLastOpcode = SecondLastInst->getOpcode();
269 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
270 bool SecLastOpcodeHasNot = PredOpcodeHasNot(SecLastOpcode);
271 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::JMP)) {
272 TBB = SecondLastInst->getOperand(1).getMBB();
273 if (SecLastOpcodeHasNot)
274 Cond.push_back(MachineOperand::CreateImm(0));
275 Cond.push_back(SecondLastInst->getOperand(0));
276 FBB = LastInst->getOperand(0).getMBB();
280 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
281 // executed, so remove it.
282 if (SecLastOpcode == Hexagon::JMP && LastOpcode == Hexagon::JMP) {
283 TBB = SecondLastInst->getOperand(0).getMBB();
286 I->eraseFromParent();
290 // If the block ends with an ENDLOOP, and JMP, handle it.
291 if (SecLastOpcode == Hexagon::ENDLOOP0 &&
292 LastOpcode == Hexagon::JMP) {
293 TBB = SecondLastInst->getOperand(0).getMBB();
294 Cond.push_back(SecondLastInst->getOperand(0));
295 FBB = LastInst->getOperand(0).getMBB();
299 // Otherwise, can't handle this.
304 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
305 int BOpc = Hexagon::JMP;
306 int BccOpc = Hexagon::JMP_t;
307 int BccOpcNot = Hexagon::JMP_f;
309 MachineBasicBlock::iterator I = MBB.end();
310 if (I == MBB.begin()) return 0;
312 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
313 I->getOpcode() != BccOpcNot)
316 // Remove the branch.
317 I->eraseFromParent();
321 if (I == MBB.begin()) return 1;
323 if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
326 // Remove the branch.
327 I->eraseFromParent();
332 /// \brief For a comparison instruction, return the source registers in
333 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
334 /// compares against in CmpValue. Return true if the comparison instruction
336 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
337 unsigned &SrcReg, unsigned &SrcReg2,
338 int &Mask, int &Value) const {
339 unsigned Opc = MI->getOpcode();
341 // Set mask and the first source register.
343 case Hexagon::CMPEHexagon4rr:
344 case Hexagon::CMPEQri:
345 case Hexagon::CMPEQrr:
346 case Hexagon::CMPGT64rr:
347 case Hexagon::CMPGTU64rr:
348 case Hexagon::CMPGTUri:
349 case Hexagon::CMPGTUrr:
350 case Hexagon::CMPGTri:
351 case Hexagon::CMPGTrr:
352 SrcReg = MI->getOperand(1).getReg();
355 case Hexagon::CMPbEQri_V4:
356 case Hexagon::CMPbEQrr_sbsb_V4:
357 case Hexagon::CMPbEQrr_ubub_V4:
358 case Hexagon::CMPbGTUri_V4:
359 case Hexagon::CMPbGTUrr_V4:
360 case Hexagon::CMPbGTrr_V4:
361 SrcReg = MI->getOperand(1).getReg();
364 case Hexagon::CMPhEQri_V4:
365 case Hexagon::CMPhEQrr_shl_V4:
366 case Hexagon::CMPhEQrr_xor_V4:
367 case Hexagon::CMPhGTUri_V4:
368 case Hexagon::CMPhGTUrr_V4:
369 case Hexagon::CMPhGTrr_shl_V4:
370 SrcReg = MI->getOperand(1).getReg();
375 // Set the value/second source register.
377 case Hexagon::CMPEHexagon4rr:
378 case Hexagon::CMPEQrr:
379 case Hexagon::CMPGT64rr:
380 case Hexagon::CMPGTU64rr:
381 case Hexagon::CMPGTUrr:
382 case Hexagon::CMPGTrr:
383 case Hexagon::CMPbEQrr_sbsb_V4:
384 case Hexagon::CMPbEQrr_ubub_V4:
385 case Hexagon::CMPbGTUrr_V4:
386 case Hexagon::CMPbGTrr_V4:
387 case Hexagon::CMPhEQrr_shl_V4:
388 case Hexagon::CMPhEQrr_xor_V4:
389 case Hexagon::CMPhGTUrr_V4:
390 case Hexagon::CMPhGTrr_shl_V4:
391 SrcReg2 = MI->getOperand(2).getReg();
394 case Hexagon::CMPEQri:
395 case Hexagon::CMPGTUri:
396 case Hexagon::CMPGTri:
397 case Hexagon::CMPbEQri_V4:
398 case Hexagon::CMPbGTUri_V4:
399 case Hexagon::CMPhEQri_V4:
400 case Hexagon::CMPhGTUri_V4:
402 Value = MI->getOperand(2).getImm();
410 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
411 MachineBasicBlock::iterator I, DebugLoc DL,
412 unsigned DestReg, unsigned SrcReg,
413 bool KillSrc) const {
414 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
415 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
418 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
419 BuildMI(MBB, I, DL, get(Hexagon::TFR64), DestReg).addReg(SrcReg);
422 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
423 // Map Pd = Ps to Pd = or(Ps, Ps).
424 BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
425 DestReg).addReg(SrcReg).addReg(SrcReg);
428 if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
429 Hexagon::IntRegsRegClass.contains(SrcReg)) {
430 // We can have an overlap between single and double reg: r1:0 = r0.
431 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
433 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
434 Hexagon::subreg_hireg))).addImm(0);
436 // r1:0 = r1 or no overlap.
437 BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
438 Hexagon::subreg_loreg))).addReg(SrcReg);
439 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
440 Hexagon::subreg_hireg))).addImm(0);
444 if (Hexagon::CRRegsRegClass.contains(DestReg) &&
445 Hexagon::IntRegsRegClass.contains(SrcReg)) {
446 BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
449 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
450 Hexagon::IntRegsRegClass.contains(DestReg)) {
451 BuildMI(MBB, I, DL, get(Hexagon::TFR_RsPd), DestReg).
452 addReg(SrcReg, getKillRegState(KillSrc));
455 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
456 Hexagon::PredRegsRegClass.contains(DestReg)) {
457 BuildMI(MBB, I, DL, get(Hexagon::TFR_PdRs), DestReg).
458 addReg(SrcReg, getKillRegState(KillSrc));
462 llvm_unreachable("Unimplemented");
466 void HexagonInstrInfo::
467 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
468 unsigned SrcReg, bool isKill, int FI,
469 const TargetRegisterClass *RC,
470 const TargetRegisterInfo *TRI) const {
472 DebugLoc DL = MBB.findDebugLoc(I);
473 MachineFunction &MF = *MBB.getParent();
474 MachineFrameInfo &MFI = *MF.getFrameInfo();
475 unsigned Align = MFI.getObjectAlignment(FI);
477 MachineMemOperand *MMO =
478 MF.getMachineMemOperand(
479 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
480 MachineMemOperand::MOStore,
481 MFI.getObjectSize(FI),
484 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
485 BuildMI(MBB, I, DL, get(Hexagon::STriw))
486 .addFrameIndex(FI).addImm(0)
487 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
488 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
489 BuildMI(MBB, I, DL, get(Hexagon::STrid))
490 .addFrameIndex(FI).addImm(0)
491 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
492 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
493 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
494 .addFrameIndex(FI).addImm(0)
495 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
497 llvm_unreachable("Unimplemented");
502 void HexagonInstrInfo::storeRegToAddr(
503 MachineFunction &MF, unsigned SrcReg,
505 SmallVectorImpl<MachineOperand> &Addr,
506 const TargetRegisterClass *RC,
507 SmallVectorImpl<MachineInstr*> &NewMIs) const
509 llvm_unreachable("Unimplemented");
513 void HexagonInstrInfo::
514 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
515 unsigned DestReg, int FI,
516 const TargetRegisterClass *RC,
517 const TargetRegisterInfo *TRI) const {
518 DebugLoc DL = MBB.findDebugLoc(I);
519 MachineFunction &MF = *MBB.getParent();
520 MachineFrameInfo &MFI = *MF.getFrameInfo();
521 unsigned Align = MFI.getObjectAlignment(FI);
523 MachineMemOperand *MMO =
524 MF.getMachineMemOperand(
525 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
526 MachineMemOperand::MOLoad,
527 MFI.getObjectSize(FI),
529 if (RC == &Hexagon::IntRegsRegClass) {
530 BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)
531 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
532 } else if (RC == &Hexagon::DoubleRegsRegClass) {
533 BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
534 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
535 } else if (RC == &Hexagon::PredRegsRegClass) {
536 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
537 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
539 llvm_unreachable("Can't store this register to stack slot");
544 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
545 SmallVectorImpl<MachineOperand> &Addr,
546 const TargetRegisterClass *RC,
547 SmallVectorImpl<MachineInstr*> &NewMIs) const {
548 llvm_unreachable("Unimplemented");
552 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
554 const SmallVectorImpl<unsigned> &Ops,
556 // Hexagon_TODO: Implement.
561 HexagonInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
562 int FrameIx, uint64_t Offset,
565 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Hexagon::DBG_VALUE))
566 .addImm(0).addImm(Offset).addMetadata(MDPtr);
570 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
572 MachineRegisterInfo &RegInfo = MF->getRegInfo();
573 const TargetRegisterClass *TRC;
575 TRC = &Hexagon::PredRegsRegClass;
576 } else if (VT == MVT::i32 || VT == MVT::f32) {
577 TRC = &Hexagon::IntRegsRegClass;
578 } else if (VT == MVT::i64 || VT == MVT::f64) {
579 TRC = &Hexagon::DoubleRegsRegClass;
581 llvm_unreachable("Cannot handle this register class");
584 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
588 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
589 // Constant extenders are allowed only for V4 and above.
590 if (!Subtarget.hasV4TOps())
593 const MCInstrDesc &MID = MI->getDesc();
594 const uint64_t F = MID.TSFlags;
595 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
598 // TODO: This is largely obsolete now. Will need to be removed
599 // in consecutive patches.
600 switch(MI->getOpcode()) {
601 // TFR_FI Remains a special case.
602 case Hexagon::TFR_FI:
610 // This returns true in two cases:
611 // - The OP code itself indicates that this is an extended instruction.
612 // - One of MOs has been marked with HMOTF_ConstExtended flag.
613 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
614 // First check if this is permanently extended op code.
615 const uint64_t F = MI->getDesc().TSFlags;
616 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
618 // Use MO operand flags to determine if one of MI's operands
619 // has HMOTF_ConstExtended flag set.
620 for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
621 E = MI->operands_end(); I != E; ++I) {
622 if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
628 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
629 switch (MI->getOpcode()) {
630 default: return false;
632 case Hexagon::JMP_EQriPt_nv_V4:
633 case Hexagon::JMP_EQriPnt_nv_V4:
634 case Hexagon::JMP_EQriNotPt_nv_V4:
635 case Hexagon::JMP_EQriNotPnt_nv_V4:
636 case Hexagon::JMP_EQriPt_ie_nv_V4:
637 case Hexagon::JMP_EQriPnt_ie_nv_V4:
638 case Hexagon::JMP_EQriNotPt_ie_nv_V4:
639 case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
641 // JMP_EQri - with -1
642 case Hexagon::JMP_EQriPtneg_nv_V4:
643 case Hexagon::JMP_EQriPntneg_nv_V4:
644 case Hexagon::JMP_EQriNotPtneg_nv_V4:
645 case Hexagon::JMP_EQriNotPntneg_nv_V4:
646 case Hexagon::JMP_EQriPtneg_ie_nv_V4:
647 case Hexagon::JMP_EQriPntneg_ie_nv_V4:
648 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
649 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
652 case Hexagon::JMP_EQrrPt_nv_V4:
653 case Hexagon::JMP_EQrrPnt_nv_V4:
654 case Hexagon::JMP_EQrrNotPt_nv_V4:
655 case Hexagon::JMP_EQrrNotPnt_nv_V4:
656 case Hexagon::JMP_EQrrPt_ie_nv_V4:
657 case Hexagon::JMP_EQrrPnt_ie_nv_V4:
658 case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
659 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
662 case Hexagon::JMP_GTriPt_nv_V4:
663 case Hexagon::JMP_GTriPnt_nv_V4:
664 case Hexagon::JMP_GTriNotPt_nv_V4:
665 case Hexagon::JMP_GTriNotPnt_nv_V4:
666 case Hexagon::JMP_GTriPt_ie_nv_V4:
667 case Hexagon::JMP_GTriPnt_ie_nv_V4:
668 case Hexagon::JMP_GTriNotPt_ie_nv_V4:
669 case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
671 // JMP_GTri - with -1
672 case Hexagon::JMP_GTriPtneg_nv_V4:
673 case Hexagon::JMP_GTriPntneg_nv_V4:
674 case Hexagon::JMP_GTriNotPtneg_nv_V4:
675 case Hexagon::JMP_GTriNotPntneg_nv_V4:
676 case Hexagon::JMP_GTriPtneg_ie_nv_V4:
677 case Hexagon::JMP_GTriPntneg_ie_nv_V4:
678 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
679 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
682 case Hexagon::JMP_GTrrPt_nv_V4:
683 case Hexagon::JMP_GTrrPnt_nv_V4:
684 case Hexagon::JMP_GTrrNotPt_nv_V4:
685 case Hexagon::JMP_GTrrNotPnt_nv_V4:
686 case Hexagon::JMP_GTrrPt_ie_nv_V4:
687 case Hexagon::JMP_GTrrPnt_ie_nv_V4:
688 case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
689 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
692 case Hexagon::JMP_GTrrdnPt_nv_V4:
693 case Hexagon::JMP_GTrrdnPnt_nv_V4:
694 case Hexagon::JMP_GTrrdnNotPt_nv_V4:
695 case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
696 case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
697 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
698 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
699 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
702 case Hexagon::JMP_GTUriPt_nv_V4:
703 case Hexagon::JMP_GTUriPnt_nv_V4:
704 case Hexagon::JMP_GTUriNotPt_nv_V4:
705 case Hexagon::JMP_GTUriNotPnt_nv_V4:
706 case Hexagon::JMP_GTUriPt_ie_nv_V4:
707 case Hexagon::JMP_GTUriPnt_ie_nv_V4:
708 case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
709 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
712 case Hexagon::JMP_GTUrrPt_nv_V4:
713 case Hexagon::JMP_GTUrrPnt_nv_V4:
714 case Hexagon::JMP_GTUrrNotPt_nv_V4:
715 case Hexagon::JMP_GTUrrNotPnt_nv_V4:
716 case Hexagon::JMP_GTUrrPt_ie_nv_V4:
717 case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
718 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
719 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
722 case Hexagon::JMP_GTUrrdnPt_nv_V4:
723 case Hexagon::JMP_GTUrrdnPnt_nv_V4:
724 case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
725 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
726 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
727 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
728 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
729 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
734 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
735 switch (MI->getOpcode()) {
736 default: return false;
738 case Hexagon::STrib_nv_V4:
739 case Hexagon::STrib_indexed_nv_V4:
740 case Hexagon::STrib_indexed_shl_nv_V4:
741 case Hexagon::STrib_shl_nv_V4:
742 case Hexagon::STb_GP_nv_V4:
743 case Hexagon::POST_STbri_nv_V4:
744 case Hexagon::STrib_cPt_nv_V4:
745 case Hexagon::STrib_cdnPt_nv_V4:
746 case Hexagon::STrib_cNotPt_nv_V4:
747 case Hexagon::STrib_cdnNotPt_nv_V4:
748 case Hexagon::STrib_indexed_cPt_nv_V4:
749 case Hexagon::STrib_indexed_cdnPt_nv_V4:
750 case Hexagon::STrib_indexed_cNotPt_nv_V4:
751 case Hexagon::STrib_indexed_cdnNotPt_nv_V4:
752 case Hexagon::STrib_indexed_shl_cPt_nv_V4:
753 case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
754 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4:
755 case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
756 case Hexagon::POST_STbri_cPt_nv_V4:
757 case Hexagon::POST_STbri_cdnPt_nv_V4:
758 case Hexagon::POST_STbri_cNotPt_nv_V4:
759 case Hexagon::POST_STbri_cdnNotPt_nv_V4:
760 case Hexagon::STb_GP_cPt_nv_V4:
761 case Hexagon::STb_GP_cNotPt_nv_V4:
762 case Hexagon::STb_GP_cdnPt_nv_V4:
763 case Hexagon::STb_GP_cdnNotPt_nv_V4:
764 case Hexagon::STrib_abs_nv_V4:
765 case Hexagon::STrib_abs_cPt_nv_V4:
766 case Hexagon::STrib_abs_cdnPt_nv_V4:
767 case Hexagon::STrib_abs_cNotPt_nv_V4:
768 case Hexagon::STrib_abs_cdnNotPt_nv_V4:
771 case Hexagon::STrih_nv_V4:
772 case Hexagon::STrih_indexed_nv_V4:
773 case Hexagon::STrih_indexed_shl_nv_V4:
774 case Hexagon::STrih_shl_nv_V4:
775 case Hexagon::STh_GP_nv_V4:
776 case Hexagon::POST_SThri_nv_V4:
777 case Hexagon::STrih_cPt_nv_V4:
778 case Hexagon::STrih_cdnPt_nv_V4:
779 case Hexagon::STrih_cNotPt_nv_V4:
780 case Hexagon::STrih_cdnNotPt_nv_V4:
781 case Hexagon::STrih_indexed_cPt_nv_V4:
782 case Hexagon::STrih_indexed_cdnPt_nv_V4:
783 case Hexagon::STrih_indexed_cNotPt_nv_V4:
784 case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
785 case Hexagon::STrih_indexed_shl_cPt_nv_V4:
786 case Hexagon::STrih_indexed_shl_cdnPt_nv_V4:
787 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4:
788 case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4:
789 case Hexagon::POST_SThri_cPt_nv_V4:
790 case Hexagon::POST_SThri_cdnPt_nv_V4:
791 case Hexagon::POST_SThri_cNotPt_nv_V4:
792 case Hexagon::POST_SThri_cdnNotPt_nv_V4:
793 case Hexagon::STh_GP_cPt_nv_V4:
794 case Hexagon::STh_GP_cNotPt_nv_V4:
795 case Hexagon::STh_GP_cdnPt_nv_V4:
796 case Hexagon::STh_GP_cdnNotPt_nv_V4:
797 case Hexagon::STrih_abs_nv_V4:
798 case Hexagon::STrih_abs_cPt_nv_V4:
799 case Hexagon::STrih_abs_cdnPt_nv_V4:
800 case Hexagon::STrih_abs_cNotPt_nv_V4:
801 case Hexagon::STrih_abs_cdnNotPt_nv_V4:
804 case Hexagon::STriw_nv_V4:
805 case Hexagon::STriw_indexed_nv_V4:
806 case Hexagon::STriw_indexed_shl_nv_V4:
807 case Hexagon::STriw_shl_nv_V4:
808 case Hexagon::STw_GP_nv_V4:
809 case Hexagon::POST_STwri_nv_V4:
810 case Hexagon::STriw_cPt_nv_V4:
811 case Hexagon::STriw_cdnPt_nv_V4:
812 case Hexagon::STriw_cNotPt_nv_V4:
813 case Hexagon::STriw_cdnNotPt_nv_V4:
814 case Hexagon::STriw_indexed_cPt_nv_V4:
815 case Hexagon::STriw_indexed_cdnPt_nv_V4:
816 case Hexagon::STriw_indexed_cNotPt_nv_V4:
817 case Hexagon::STriw_indexed_cdnNotPt_nv_V4:
818 case Hexagon::STriw_indexed_shl_cPt_nv_V4:
819 case Hexagon::STriw_indexed_shl_cdnPt_nv_V4:
820 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4:
821 case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4:
822 case Hexagon::POST_STwri_cPt_nv_V4:
823 case Hexagon::POST_STwri_cdnPt_nv_V4:
824 case Hexagon::POST_STwri_cNotPt_nv_V4:
825 case Hexagon::POST_STwri_cdnNotPt_nv_V4:
826 case Hexagon::STw_GP_cPt_nv_V4:
827 case Hexagon::STw_GP_cNotPt_nv_V4:
828 case Hexagon::STw_GP_cdnPt_nv_V4:
829 case Hexagon::STw_GP_cdnNotPt_nv_V4:
830 case Hexagon::STriw_abs_nv_V4:
831 case Hexagon::STriw_abs_cPt_nv_V4:
832 case Hexagon::STriw_abs_cdnPt_nv_V4:
833 case Hexagon::STriw_abs_cNotPt_nv_V4:
834 case Hexagon::STriw_abs_cdnNotPt_nv_V4:
839 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
840 switch (MI->getOpcode())
842 default: return false;
844 case Hexagon::POST_LDrib:
845 case Hexagon::POST_LDrib_cPt:
846 case Hexagon::POST_LDrib_cNotPt:
847 case Hexagon::POST_LDrib_cdnPt_V4:
848 case Hexagon::POST_LDrib_cdnNotPt_V4:
850 // Load unsigned byte
851 case Hexagon::POST_LDriub:
852 case Hexagon::POST_LDriub_cPt:
853 case Hexagon::POST_LDriub_cNotPt:
854 case Hexagon::POST_LDriub_cdnPt_V4:
855 case Hexagon::POST_LDriub_cdnNotPt_V4:
858 case Hexagon::POST_LDrih:
859 case Hexagon::POST_LDrih_cPt:
860 case Hexagon::POST_LDrih_cNotPt:
861 case Hexagon::POST_LDrih_cdnPt_V4:
862 case Hexagon::POST_LDrih_cdnNotPt_V4:
864 // Load unsigned halfword
865 case Hexagon::POST_LDriuh:
866 case Hexagon::POST_LDriuh_cPt:
867 case Hexagon::POST_LDriuh_cNotPt:
868 case Hexagon::POST_LDriuh_cdnPt_V4:
869 case Hexagon::POST_LDriuh_cdnNotPt_V4:
872 case Hexagon::POST_LDriw:
873 case Hexagon::POST_LDriw_cPt:
874 case Hexagon::POST_LDriw_cNotPt:
875 case Hexagon::POST_LDriw_cdnPt_V4:
876 case Hexagon::POST_LDriw_cdnNotPt_V4:
879 case Hexagon::POST_LDrid:
880 case Hexagon::POST_LDrid_cPt:
881 case Hexagon::POST_LDrid_cNotPt:
882 case Hexagon::POST_LDrid_cdnPt_V4:
883 case Hexagon::POST_LDrid_cdnNotPt_V4:
886 case Hexagon::POST_STbri:
887 case Hexagon::POST_STbri_cPt:
888 case Hexagon::POST_STbri_cNotPt:
889 case Hexagon::POST_STbri_cdnPt_V4:
890 case Hexagon::POST_STbri_cdnNotPt_V4:
893 case Hexagon::POST_SThri:
894 case Hexagon::POST_SThri_cPt:
895 case Hexagon::POST_SThri_cNotPt:
896 case Hexagon::POST_SThri_cdnPt_V4:
897 case Hexagon::POST_SThri_cdnNotPt_V4:
900 case Hexagon::POST_STwri:
901 case Hexagon::POST_STwri_cPt:
902 case Hexagon::POST_STwri_cNotPt:
903 case Hexagon::POST_STwri_cdnPt_V4:
904 case Hexagon::POST_STwri_cdnNotPt_V4:
907 case Hexagon::POST_STdri:
908 case Hexagon::POST_STdri_cPt:
909 case Hexagon::POST_STdri_cNotPt:
910 case Hexagon::POST_STdri_cdnPt_V4:
911 case Hexagon::POST_STdri_cdnNotPt_V4:
916 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
917 if (isNewValueJump(MI))
920 if (isNewValueStore(MI))
926 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
927 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
930 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
931 bool isPred = MI->getDesc().isPredicable();
936 const int Opc = MI->getOpcode();
940 return isInt<12>(MI->getOperand(1).getImm());
943 case Hexagon::STrid_indexed:
944 return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
947 case Hexagon::STriw_indexed:
948 case Hexagon::STriw_nv_V4:
949 return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
952 case Hexagon::STrih_indexed:
953 case Hexagon::STrih_nv_V4:
954 return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
957 case Hexagon::STrib_indexed:
958 case Hexagon::STrib_nv_V4:
959 return isUInt<6>(MI->getOperand(1).getImm());
962 case Hexagon::LDrid_indexed:
963 return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
966 case Hexagon::LDriw_indexed:
967 return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
970 case Hexagon::LDriuh:
971 case Hexagon::LDrih_indexed:
972 case Hexagon::LDriuh_indexed:
973 return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
976 case Hexagon::LDriub:
977 case Hexagon::LDrib_indexed:
978 case Hexagon::LDriub_indexed:
979 return isUInt<6>(MI->getOperand(2).getImm());
981 case Hexagon::POST_LDrid:
982 return isShiftedInt<4,3>(MI->getOperand(3).getImm());
984 case Hexagon::POST_LDriw:
985 return isShiftedInt<4,2>(MI->getOperand(3).getImm());
987 case Hexagon::POST_LDrih:
988 case Hexagon::POST_LDriuh:
989 return isShiftedInt<4,1>(MI->getOperand(3).getImm());
991 case Hexagon::POST_LDrib:
992 case Hexagon::POST_LDriub:
993 return isInt<4>(MI->getOperand(3).getImm());
995 case Hexagon::STrib_imm_V4:
996 case Hexagon::STrih_imm_V4:
997 case Hexagon::STriw_imm_V4:
998 return (isUInt<6>(MI->getOperand(1).getImm()) &&
999 isInt<6>(MI->getOperand(2).getImm()));
1001 case Hexagon::ADD_ri:
1002 return isInt<8>(MI->getOperand(2).getImm());
1010 return Subtarget.hasV4TOps();
1016 // This function performs the following inversiones:
1021 // however, these inversiones are NOT included:
1023 // cdnPt -X-> cdnNotPt
1024 // cdnNotPt -X-> cdnPt
1025 // cPt_nv -X-> cNotPt_nv (new value stores)
1026 // cNotPt_nv -X-> cPt_nv (new value stores)
1028 // because only the following transformations are allowed:
1030 // cNotPt ---> cdnNotPt
1032 // cNotPt ---> cNotPt_nv
1034 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
1036 default: llvm_unreachable("Unexpected predicated instruction");
1037 case Hexagon::TFR_cPt:
1038 return Hexagon::TFR_cNotPt;
1039 case Hexagon::TFR_cNotPt:
1040 return Hexagon::TFR_cPt;
1042 case Hexagon::TFRI_cPt:
1043 return Hexagon::TFRI_cNotPt;
1044 case Hexagon::TFRI_cNotPt:
1045 return Hexagon::TFRI_cPt;
1047 case Hexagon::JMP_t:
1048 return Hexagon::JMP_f;
1049 case Hexagon::JMP_f:
1050 return Hexagon::JMP_t;
1052 case Hexagon::ADD_ri_cPt:
1053 return Hexagon::ADD_ri_cNotPt;
1054 case Hexagon::ADD_ri_cNotPt:
1055 return Hexagon::ADD_ri_cPt;
1057 case Hexagon::ADD_rr_cPt:
1058 return Hexagon::ADD_rr_cNotPt;
1059 case Hexagon::ADD_rr_cNotPt:
1060 return Hexagon::ADD_rr_cPt;
1062 case Hexagon::XOR_rr_cPt:
1063 return Hexagon::XOR_rr_cNotPt;
1064 case Hexagon::XOR_rr_cNotPt:
1065 return Hexagon::XOR_rr_cPt;
1067 case Hexagon::AND_rr_cPt:
1068 return Hexagon::AND_rr_cNotPt;
1069 case Hexagon::AND_rr_cNotPt:
1070 return Hexagon::AND_rr_cPt;
1072 case Hexagon::OR_rr_cPt:
1073 return Hexagon::OR_rr_cNotPt;
1074 case Hexagon::OR_rr_cNotPt:
1075 return Hexagon::OR_rr_cPt;
1077 case Hexagon::SUB_rr_cPt:
1078 return Hexagon::SUB_rr_cNotPt;
1079 case Hexagon::SUB_rr_cNotPt:
1080 return Hexagon::SUB_rr_cPt;
1082 case Hexagon::COMBINE_rr_cPt:
1083 return Hexagon::COMBINE_rr_cNotPt;
1084 case Hexagon::COMBINE_rr_cNotPt:
1085 return Hexagon::COMBINE_rr_cPt;
1087 case Hexagon::ASLH_cPt_V4:
1088 return Hexagon::ASLH_cNotPt_V4;
1089 case Hexagon::ASLH_cNotPt_V4:
1090 return Hexagon::ASLH_cPt_V4;
1092 case Hexagon::ASRH_cPt_V4:
1093 return Hexagon::ASRH_cNotPt_V4;
1094 case Hexagon::ASRH_cNotPt_V4:
1095 return Hexagon::ASRH_cPt_V4;
1097 case Hexagon::SXTB_cPt_V4:
1098 return Hexagon::SXTB_cNotPt_V4;
1099 case Hexagon::SXTB_cNotPt_V4:
1100 return Hexagon::SXTB_cPt_V4;
1102 case Hexagon::SXTH_cPt_V4:
1103 return Hexagon::SXTH_cNotPt_V4;
1104 case Hexagon::SXTH_cNotPt_V4:
1105 return Hexagon::SXTH_cPt_V4;
1107 case Hexagon::ZXTB_cPt_V4:
1108 return Hexagon::ZXTB_cNotPt_V4;
1109 case Hexagon::ZXTB_cNotPt_V4:
1110 return Hexagon::ZXTB_cPt_V4;
1112 case Hexagon::ZXTH_cPt_V4:
1113 return Hexagon::ZXTH_cNotPt_V4;
1114 case Hexagon::ZXTH_cNotPt_V4:
1115 return Hexagon::ZXTH_cPt_V4;
1118 case Hexagon::JMPR_t:
1119 return Hexagon::JMPR_f;
1120 case Hexagon::JMPR_f:
1121 return Hexagon::JMPR_t;
1123 // V4 indexed+scaled load.
1124 case Hexagon::LDrid_indexed_shl_cPt_V4:
1125 return Hexagon::LDrid_indexed_shl_cNotPt_V4;
1126 case Hexagon::LDrid_indexed_shl_cNotPt_V4:
1127 return Hexagon::LDrid_indexed_shl_cPt_V4;
1129 case Hexagon::LDrib_indexed_shl_cPt_V4:
1130 return Hexagon::LDrib_indexed_shl_cNotPt_V4;
1131 case Hexagon::LDrib_indexed_shl_cNotPt_V4:
1132 return Hexagon::LDrib_indexed_shl_cPt_V4;
1134 case Hexagon::LDriub_indexed_shl_cPt_V4:
1135 return Hexagon::LDriub_indexed_shl_cNotPt_V4;
1136 case Hexagon::LDriub_indexed_shl_cNotPt_V4:
1137 return Hexagon::LDriub_indexed_shl_cPt_V4;
1139 case Hexagon::LDrih_indexed_shl_cPt_V4:
1140 return Hexagon::LDrih_indexed_shl_cNotPt_V4;
1141 case Hexagon::LDrih_indexed_shl_cNotPt_V4:
1142 return Hexagon::LDrih_indexed_shl_cPt_V4;
1144 case Hexagon::LDriuh_indexed_shl_cPt_V4:
1145 return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1146 case Hexagon::LDriuh_indexed_shl_cNotPt_V4:
1147 return Hexagon::LDriuh_indexed_shl_cPt_V4;
1149 case Hexagon::LDriw_indexed_shl_cPt_V4:
1150 return Hexagon::LDriw_indexed_shl_cNotPt_V4;
1151 case Hexagon::LDriw_indexed_shl_cNotPt_V4:
1152 return Hexagon::LDriw_indexed_shl_cPt_V4;
1155 case Hexagon::POST_STbri_cPt:
1156 return Hexagon::POST_STbri_cNotPt;
1157 case Hexagon::POST_STbri_cNotPt:
1158 return Hexagon::POST_STbri_cPt;
1160 case Hexagon::STrib_cPt:
1161 return Hexagon::STrib_cNotPt;
1162 case Hexagon::STrib_cNotPt:
1163 return Hexagon::STrib_cPt;
1165 case Hexagon::STrib_indexed_cPt:
1166 return Hexagon::STrib_indexed_cNotPt;
1167 case Hexagon::STrib_indexed_cNotPt:
1168 return Hexagon::STrib_indexed_cPt;
1170 case Hexagon::STrib_imm_cPt_V4:
1171 return Hexagon::STrib_imm_cNotPt_V4;
1172 case Hexagon::STrib_imm_cNotPt_V4:
1173 return Hexagon::STrib_imm_cPt_V4;
1175 case Hexagon::STrib_indexed_shl_cPt_V4:
1176 return Hexagon::STrib_indexed_shl_cNotPt_V4;
1177 case Hexagon::STrib_indexed_shl_cNotPt_V4:
1178 return Hexagon::STrib_indexed_shl_cPt_V4;
1181 case Hexagon::POST_SThri_cPt:
1182 return Hexagon::POST_SThri_cNotPt;
1183 case Hexagon::POST_SThri_cNotPt:
1184 return Hexagon::POST_SThri_cPt;
1186 case Hexagon::STrih_cPt:
1187 return Hexagon::STrih_cNotPt;
1188 case Hexagon::STrih_cNotPt:
1189 return Hexagon::STrih_cPt;
1191 case Hexagon::STrih_indexed_cPt:
1192 return Hexagon::STrih_indexed_cNotPt;
1193 case Hexagon::STrih_indexed_cNotPt:
1194 return Hexagon::STrih_indexed_cPt;
1196 case Hexagon::STrih_imm_cPt_V4:
1197 return Hexagon::STrih_imm_cNotPt_V4;
1198 case Hexagon::STrih_imm_cNotPt_V4:
1199 return Hexagon::STrih_imm_cPt_V4;
1201 case Hexagon::STrih_indexed_shl_cPt_V4:
1202 return Hexagon::STrih_indexed_shl_cNotPt_V4;
1203 case Hexagon::STrih_indexed_shl_cNotPt_V4:
1204 return Hexagon::STrih_indexed_shl_cPt_V4;
1207 case Hexagon::POST_STwri_cPt:
1208 return Hexagon::POST_STwri_cNotPt;
1209 case Hexagon::POST_STwri_cNotPt:
1210 return Hexagon::POST_STwri_cPt;
1212 case Hexagon::STriw_cPt:
1213 return Hexagon::STriw_cNotPt;
1214 case Hexagon::STriw_cNotPt:
1215 return Hexagon::STriw_cPt;
1217 case Hexagon::STriw_indexed_cPt:
1218 return Hexagon::STriw_indexed_cNotPt;
1219 case Hexagon::STriw_indexed_cNotPt:
1220 return Hexagon::STriw_indexed_cPt;
1222 case Hexagon::STriw_indexed_shl_cPt_V4:
1223 return Hexagon::STriw_indexed_shl_cNotPt_V4;
1224 case Hexagon::STriw_indexed_shl_cNotPt_V4:
1225 return Hexagon::STriw_indexed_shl_cPt_V4;
1227 case Hexagon::STriw_imm_cPt_V4:
1228 return Hexagon::STriw_imm_cNotPt_V4;
1229 case Hexagon::STriw_imm_cNotPt_V4:
1230 return Hexagon::STriw_imm_cPt_V4;
1233 case Hexagon::POST_STdri_cPt:
1234 return Hexagon::POST_STdri_cNotPt;
1235 case Hexagon::POST_STdri_cNotPt:
1236 return Hexagon::POST_STdri_cPt;
1238 case Hexagon::STrid_cPt:
1239 return Hexagon::STrid_cNotPt;
1240 case Hexagon::STrid_cNotPt:
1241 return Hexagon::STrid_cPt;
1243 case Hexagon::STrid_indexed_cPt:
1244 return Hexagon::STrid_indexed_cNotPt;
1245 case Hexagon::STrid_indexed_cNotPt:
1246 return Hexagon::STrid_indexed_cPt;
1248 case Hexagon::STrid_indexed_shl_cPt_V4:
1249 return Hexagon::STrid_indexed_shl_cNotPt_V4;
1250 case Hexagon::STrid_indexed_shl_cNotPt_V4:
1251 return Hexagon::STrid_indexed_shl_cPt_V4;
1253 // V4 Store to global address.
1254 case Hexagon::STd_GP_cPt_V4:
1255 return Hexagon::STd_GP_cNotPt_V4;
1256 case Hexagon::STd_GP_cNotPt_V4:
1257 return Hexagon::STd_GP_cPt_V4;
1259 case Hexagon::STb_GP_cPt_V4:
1260 return Hexagon::STb_GP_cNotPt_V4;
1261 case Hexagon::STb_GP_cNotPt_V4:
1262 return Hexagon::STb_GP_cPt_V4;
1264 case Hexagon::STh_GP_cPt_V4:
1265 return Hexagon::STh_GP_cNotPt_V4;
1266 case Hexagon::STh_GP_cNotPt_V4:
1267 return Hexagon::STh_GP_cPt_V4;
1269 case Hexagon::STw_GP_cPt_V4:
1270 return Hexagon::STw_GP_cNotPt_V4;
1271 case Hexagon::STw_GP_cNotPt_V4:
1272 return Hexagon::STw_GP_cPt_V4;
1275 case Hexagon::LDrid_cPt:
1276 return Hexagon::LDrid_cNotPt;
1277 case Hexagon::LDrid_cNotPt:
1278 return Hexagon::LDrid_cPt;
1280 case Hexagon::LDriw_cPt:
1281 return Hexagon::LDriw_cNotPt;
1282 case Hexagon::LDriw_cNotPt:
1283 return Hexagon::LDriw_cPt;
1285 case Hexagon::LDrih_cPt:
1286 return Hexagon::LDrih_cNotPt;
1287 case Hexagon::LDrih_cNotPt:
1288 return Hexagon::LDrih_cPt;
1290 case Hexagon::LDriuh_cPt:
1291 return Hexagon::LDriuh_cNotPt;
1292 case Hexagon::LDriuh_cNotPt:
1293 return Hexagon::LDriuh_cPt;
1295 case Hexagon::LDrib_cPt:
1296 return Hexagon::LDrib_cNotPt;
1297 case Hexagon::LDrib_cNotPt:
1298 return Hexagon::LDrib_cPt;
1300 case Hexagon::LDriub_cPt:
1301 return Hexagon::LDriub_cNotPt;
1302 case Hexagon::LDriub_cNotPt:
1303 return Hexagon::LDriub_cPt;
1306 case Hexagon::LDrid_indexed_cPt:
1307 return Hexagon::LDrid_indexed_cNotPt;
1308 case Hexagon::LDrid_indexed_cNotPt:
1309 return Hexagon::LDrid_indexed_cPt;
1311 case Hexagon::LDriw_indexed_cPt:
1312 return Hexagon::LDriw_indexed_cNotPt;
1313 case Hexagon::LDriw_indexed_cNotPt:
1314 return Hexagon::LDriw_indexed_cPt;
1316 case Hexagon::LDrih_indexed_cPt:
1317 return Hexagon::LDrih_indexed_cNotPt;
1318 case Hexagon::LDrih_indexed_cNotPt:
1319 return Hexagon::LDrih_indexed_cPt;
1321 case Hexagon::LDriuh_indexed_cPt:
1322 return Hexagon::LDriuh_indexed_cNotPt;
1323 case Hexagon::LDriuh_indexed_cNotPt:
1324 return Hexagon::LDriuh_indexed_cPt;
1326 case Hexagon::LDrib_indexed_cPt:
1327 return Hexagon::LDrib_indexed_cNotPt;
1328 case Hexagon::LDrib_indexed_cNotPt:
1329 return Hexagon::LDrib_indexed_cPt;
1331 case Hexagon::LDriub_indexed_cPt:
1332 return Hexagon::LDriub_indexed_cNotPt;
1333 case Hexagon::LDriub_indexed_cNotPt:
1334 return Hexagon::LDriub_indexed_cPt;
1337 case Hexagon::POST_LDrid_cPt:
1338 return Hexagon::POST_LDrid_cNotPt;
1339 case Hexagon::POST_LDriw_cNotPt:
1340 return Hexagon::POST_LDriw_cPt;
1342 case Hexagon::POST_LDrih_cPt:
1343 return Hexagon::POST_LDrih_cNotPt;
1344 case Hexagon::POST_LDrih_cNotPt:
1345 return Hexagon::POST_LDrih_cPt;
1347 case Hexagon::POST_LDriuh_cPt:
1348 return Hexagon::POST_LDriuh_cNotPt;
1349 case Hexagon::POST_LDriuh_cNotPt:
1350 return Hexagon::POST_LDriuh_cPt;
1352 case Hexagon::POST_LDrib_cPt:
1353 return Hexagon::POST_LDrib_cNotPt;
1354 case Hexagon::POST_LDrib_cNotPt:
1355 return Hexagon::POST_LDrib_cPt;
1357 case Hexagon::POST_LDriub_cPt:
1358 return Hexagon::POST_LDriub_cNotPt;
1359 case Hexagon::POST_LDriub_cNotPt:
1360 return Hexagon::POST_LDriub_cPt;
1363 case Hexagon::DEALLOC_RET_cPt_V4:
1364 return Hexagon::DEALLOC_RET_cNotPt_V4;
1365 case Hexagon::DEALLOC_RET_cNotPt_V4:
1366 return Hexagon::DEALLOC_RET_cPt_V4;
1369 // JMPEQ_ri - with -1.
1370 case Hexagon::JMP_EQriPtneg_nv_V4:
1371 return Hexagon::JMP_EQriNotPtneg_nv_V4;
1372 case Hexagon::JMP_EQriNotPtneg_nv_V4:
1373 return Hexagon::JMP_EQriPtneg_nv_V4;
1375 case Hexagon::JMP_EQriPntneg_nv_V4:
1376 return Hexagon::JMP_EQriNotPntneg_nv_V4;
1377 case Hexagon::JMP_EQriNotPntneg_nv_V4:
1378 return Hexagon::JMP_EQriPntneg_nv_V4;
1381 case Hexagon::JMP_EQriPt_nv_V4:
1382 return Hexagon::JMP_EQriNotPt_nv_V4;
1383 case Hexagon::JMP_EQriNotPt_nv_V4:
1384 return Hexagon::JMP_EQriPt_nv_V4;
1386 case Hexagon::JMP_EQriPnt_nv_V4:
1387 return Hexagon::JMP_EQriNotPnt_nv_V4;
1388 case Hexagon::JMP_EQriNotPnt_nv_V4:
1389 return Hexagon::JMP_EQriPnt_nv_V4;
1392 case Hexagon::JMP_EQrrPt_nv_V4:
1393 return Hexagon::JMP_EQrrNotPt_nv_V4;
1394 case Hexagon::JMP_EQrrNotPt_nv_V4:
1395 return Hexagon::JMP_EQrrPt_nv_V4;
1397 case Hexagon::JMP_EQrrPnt_nv_V4:
1398 return Hexagon::JMP_EQrrNotPnt_nv_V4;
1399 case Hexagon::JMP_EQrrNotPnt_nv_V4:
1400 return Hexagon::JMP_EQrrPnt_nv_V4;
1402 // JMPGT_ri - with -1.
1403 case Hexagon::JMP_GTriPtneg_nv_V4:
1404 return Hexagon::JMP_GTriNotPtneg_nv_V4;
1405 case Hexagon::JMP_GTriNotPtneg_nv_V4:
1406 return Hexagon::JMP_GTriPtneg_nv_V4;
1408 case Hexagon::JMP_GTriPntneg_nv_V4:
1409 return Hexagon::JMP_GTriNotPntneg_nv_V4;
1410 case Hexagon::JMP_GTriNotPntneg_nv_V4:
1411 return Hexagon::JMP_GTriPntneg_nv_V4;
1414 case Hexagon::JMP_GTriPt_nv_V4:
1415 return Hexagon::JMP_GTriNotPt_nv_V4;
1416 case Hexagon::JMP_GTriNotPt_nv_V4:
1417 return Hexagon::JMP_GTriPt_nv_V4;
1419 case Hexagon::JMP_GTriPnt_nv_V4:
1420 return Hexagon::JMP_GTriNotPnt_nv_V4;
1421 case Hexagon::JMP_GTriNotPnt_nv_V4:
1422 return Hexagon::JMP_GTriPnt_nv_V4;
1425 case Hexagon::JMP_GTrrPt_nv_V4:
1426 return Hexagon::JMP_GTrrNotPt_nv_V4;
1427 case Hexagon::JMP_GTrrNotPt_nv_V4:
1428 return Hexagon::JMP_GTrrPt_nv_V4;
1430 case Hexagon::JMP_GTrrPnt_nv_V4:
1431 return Hexagon::JMP_GTrrNotPnt_nv_V4;
1432 case Hexagon::JMP_GTrrNotPnt_nv_V4:
1433 return Hexagon::JMP_GTrrPnt_nv_V4;
1436 case Hexagon::JMP_GTrrdnPt_nv_V4:
1437 return Hexagon::JMP_GTrrdnNotPt_nv_V4;
1438 case Hexagon::JMP_GTrrdnNotPt_nv_V4:
1439 return Hexagon::JMP_GTrrdnPt_nv_V4;
1441 case Hexagon::JMP_GTrrdnPnt_nv_V4:
1442 return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
1443 case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
1444 return Hexagon::JMP_GTrrdnPnt_nv_V4;
1447 case Hexagon::JMP_GTUriPt_nv_V4:
1448 return Hexagon::JMP_GTUriNotPt_nv_V4;
1449 case Hexagon::JMP_GTUriNotPt_nv_V4:
1450 return Hexagon::JMP_GTUriPt_nv_V4;
1452 case Hexagon::JMP_GTUriPnt_nv_V4:
1453 return Hexagon::JMP_GTUriNotPnt_nv_V4;
1454 case Hexagon::JMP_GTUriNotPnt_nv_V4:
1455 return Hexagon::JMP_GTUriPnt_nv_V4;
1458 case Hexagon::JMP_GTUrrPt_nv_V4:
1459 return Hexagon::JMP_GTUrrNotPt_nv_V4;
1460 case Hexagon::JMP_GTUrrNotPt_nv_V4:
1461 return Hexagon::JMP_GTUrrPt_nv_V4;
1463 case Hexagon::JMP_GTUrrPnt_nv_V4:
1464 return Hexagon::JMP_GTUrrNotPnt_nv_V4;
1465 case Hexagon::JMP_GTUrrNotPnt_nv_V4:
1466 return Hexagon::JMP_GTUrrPnt_nv_V4;
1469 case Hexagon::JMP_GTUrrdnPt_nv_V4:
1470 return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
1471 case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
1472 return Hexagon::JMP_GTUrrdnPt_nv_V4;
1474 case Hexagon::JMP_GTUrrdnPnt_nv_V4:
1475 return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
1476 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
1477 return Hexagon::JMP_GTUrrdnPnt_nv_V4;
1482 int HexagonInstrInfo::
1483 getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
1484 enum Hexagon::PredSense inPredSense;
1485 inPredSense = invertPredicate ? Hexagon::PredSense_false :
1486 Hexagon::PredSense_true;
1487 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
1488 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
1491 // This switch case will be removed once all the instructions have been
1492 // modified to use relation maps.
1495 return !invertPredicate ? Hexagon::TFR_cPt :
1496 Hexagon::TFR_cNotPt;
1497 case Hexagon::TFRI_f:
1498 return !invertPredicate ? Hexagon::TFRI_cPt_f :
1499 Hexagon::TFRI_cNotPt_f;
1501 return !invertPredicate ? Hexagon::TFRI_cPt :
1502 Hexagon::TFRI_cNotPt;
1504 return !invertPredicate ? Hexagon::JMP_t :
1506 case Hexagon::JMP_EQrrPt_nv_V4:
1507 return !invertPredicate ? Hexagon::JMP_EQrrPt_nv_V4 :
1508 Hexagon::JMP_EQrrNotPt_nv_V4;
1509 case Hexagon::JMP_EQriPt_nv_V4:
1510 return !invertPredicate ? Hexagon::JMP_EQriPt_nv_V4 :
1511 Hexagon::JMP_EQriNotPt_nv_V4;
1512 case Hexagon::COMBINE_rr:
1513 return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
1514 Hexagon::COMBINE_rr_cNotPt;
1516 return !invertPredicate ? Hexagon::ASLH_cPt_V4 :
1517 Hexagon::ASLH_cNotPt_V4;
1519 return !invertPredicate ? Hexagon::ASRH_cPt_V4 :
1520 Hexagon::ASRH_cNotPt_V4;
1522 return !invertPredicate ? Hexagon::SXTB_cPt_V4 :
1523 Hexagon::SXTB_cNotPt_V4;
1525 return !invertPredicate ? Hexagon::SXTH_cPt_V4 :
1526 Hexagon::SXTH_cNotPt_V4;
1528 return !invertPredicate ? Hexagon::ZXTB_cPt_V4 :
1529 Hexagon::ZXTB_cNotPt_V4;
1531 return !invertPredicate ? Hexagon::ZXTH_cPt_V4 :
1532 Hexagon::ZXTH_cNotPt_V4;
1535 return !invertPredicate ? Hexagon::JMPR_t :
1538 // V4 indexed+scaled load.
1539 case Hexagon::LDrid_indexed_shl_V4:
1540 return !invertPredicate ? Hexagon::LDrid_indexed_shl_cPt_V4 :
1541 Hexagon::LDrid_indexed_shl_cNotPt_V4;
1542 case Hexagon::LDrib_indexed_shl_V4:
1543 return !invertPredicate ? Hexagon::LDrib_indexed_shl_cPt_V4 :
1544 Hexagon::LDrib_indexed_shl_cNotPt_V4;
1545 case Hexagon::LDriub_indexed_shl_V4:
1546 return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
1547 Hexagon::LDriub_indexed_shl_cNotPt_V4;
1548 case Hexagon::LDrih_indexed_shl_V4:
1549 return !invertPredicate ? Hexagon::LDrih_indexed_shl_cPt_V4 :
1550 Hexagon::LDrih_indexed_shl_cNotPt_V4;
1551 case Hexagon::LDriuh_indexed_shl_V4:
1552 return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
1553 Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1554 case Hexagon::LDriw_indexed_shl_V4:
1555 return !invertPredicate ? Hexagon::LDriw_indexed_shl_cPt_V4 :
1556 Hexagon::LDriw_indexed_shl_cNotPt_V4;
1558 // V4 Load from global address
1559 case Hexagon::LDd_GP_V4:
1560 return !invertPredicate ? Hexagon::LDd_GP_cPt_V4 :
1561 Hexagon::LDd_GP_cNotPt_V4;
1562 case Hexagon::LDb_GP_V4:
1563 return !invertPredicate ? Hexagon::LDb_GP_cPt_V4 :
1564 Hexagon::LDb_GP_cNotPt_V4;
1565 case Hexagon::LDub_GP_V4:
1566 return !invertPredicate ? Hexagon::LDub_GP_cPt_V4 :
1567 Hexagon::LDub_GP_cNotPt_V4;
1568 case Hexagon::LDh_GP_V4:
1569 return !invertPredicate ? Hexagon::LDh_GP_cPt_V4 :
1570 Hexagon::LDh_GP_cNotPt_V4;
1571 case Hexagon::LDuh_GP_V4:
1572 return !invertPredicate ? Hexagon::LDuh_GP_cPt_V4 :
1573 Hexagon::LDuh_GP_cNotPt_V4;
1574 case Hexagon::LDw_GP_V4:
1575 return !invertPredicate ? Hexagon::LDw_GP_cPt_V4 :
1576 Hexagon::LDw_GP_cNotPt_V4;
1579 case Hexagon::POST_STbri:
1580 return !invertPredicate ? Hexagon::POST_STbri_cPt :
1581 Hexagon::POST_STbri_cNotPt;
1582 case Hexagon::STrib:
1583 return !invertPredicate ? Hexagon::STrib_cPt :
1584 Hexagon::STrib_cNotPt;
1585 case Hexagon::STrib_indexed:
1586 return !invertPredicate ? Hexagon::STrib_indexed_cPt :
1587 Hexagon::STrib_indexed_cNotPt;
1588 case Hexagon::STrib_imm_V4:
1589 return !invertPredicate ? Hexagon::STrib_imm_cPt_V4 :
1590 Hexagon::STrib_imm_cNotPt_V4;
1591 case Hexagon::STrib_indexed_shl_V4:
1592 return !invertPredicate ? Hexagon::STrib_indexed_shl_cPt_V4 :
1593 Hexagon::STrib_indexed_shl_cNotPt_V4;
1595 case Hexagon::POST_SThri:
1596 return !invertPredicate ? Hexagon::POST_SThri_cPt :
1597 Hexagon::POST_SThri_cNotPt;
1598 case Hexagon::STrih:
1599 return !invertPredicate ? Hexagon::STrih_cPt :
1600 Hexagon::STrih_cNotPt;
1601 case Hexagon::STrih_indexed:
1602 return !invertPredicate ? Hexagon::STrih_indexed_cPt :
1603 Hexagon::STrih_indexed_cNotPt;
1604 case Hexagon::STrih_imm_V4:
1605 return !invertPredicate ? Hexagon::STrih_imm_cPt_V4 :
1606 Hexagon::STrih_imm_cNotPt_V4;
1607 case Hexagon::STrih_indexed_shl_V4:
1608 return !invertPredicate ? Hexagon::STrih_indexed_shl_cPt_V4 :
1609 Hexagon::STrih_indexed_shl_cNotPt_V4;
1611 case Hexagon::POST_STwri:
1612 return !invertPredicate ? Hexagon::POST_STwri_cPt :
1613 Hexagon::POST_STwri_cNotPt;
1614 case Hexagon::STriw:
1615 return !invertPredicate ? Hexagon::STriw_cPt :
1616 Hexagon::STriw_cNotPt;
1617 case Hexagon::STriw_indexed:
1618 return !invertPredicate ? Hexagon::STriw_indexed_cPt :
1619 Hexagon::STriw_indexed_cNotPt;
1620 case Hexagon::STriw_indexed_shl_V4:
1621 return !invertPredicate ? Hexagon::STriw_indexed_shl_cPt_V4 :
1622 Hexagon::STriw_indexed_shl_cNotPt_V4;
1623 case Hexagon::STriw_imm_V4:
1624 return !invertPredicate ? Hexagon::STriw_imm_cPt_V4 :
1625 Hexagon::STriw_imm_cNotPt_V4;
1627 case Hexagon::POST_STdri:
1628 return !invertPredicate ? Hexagon::POST_STdri_cPt :
1629 Hexagon::POST_STdri_cNotPt;
1630 case Hexagon::STrid:
1631 return !invertPredicate ? Hexagon::STrid_cPt :
1632 Hexagon::STrid_cNotPt;
1633 case Hexagon::STrid_indexed:
1634 return !invertPredicate ? Hexagon::STrid_indexed_cPt :
1635 Hexagon::STrid_indexed_cNotPt;
1636 case Hexagon::STrid_indexed_shl_V4:
1637 return !invertPredicate ? Hexagon::STrid_indexed_shl_cPt_V4 :
1638 Hexagon::STrid_indexed_shl_cNotPt_V4;
1640 // V4 Store to global address
1641 case Hexagon::STd_GP_V4:
1642 return !invertPredicate ? Hexagon::STd_GP_cPt_V4 :
1643 Hexagon::STd_GP_cNotPt_V4;
1644 case Hexagon::STb_GP_V4:
1645 return !invertPredicate ? Hexagon::STb_GP_cPt_V4 :
1646 Hexagon::STb_GP_cNotPt_V4;
1647 case Hexagon::STh_GP_V4:
1648 return !invertPredicate ? Hexagon::STh_GP_cPt_V4 :
1649 Hexagon::STh_GP_cNotPt_V4;
1650 case Hexagon::STw_GP_V4:
1651 return !invertPredicate ? Hexagon::STw_GP_cPt_V4 :
1652 Hexagon::STw_GP_cNotPt_V4;
1655 case Hexagon::LDrid:
1656 return !invertPredicate ? Hexagon::LDrid_cPt :
1657 Hexagon::LDrid_cNotPt;
1658 case Hexagon::LDriw:
1659 return !invertPredicate ? Hexagon::LDriw_cPt :
1660 Hexagon::LDriw_cNotPt;
1661 case Hexagon::LDrih:
1662 return !invertPredicate ? Hexagon::LDrih_cPt :
1663 Hexagon::LDrih_cNotPt;
1664 case Hexagon::LDriuh:
1665 return !invertPredicate ? Hexagon::LDriuh_cPt :
1666 Hexagon::LDriuh_cNotPt;
1667 case Hexagon::LDrib:
1668 return !invertPredicate ? Hexagon::LDrib_cPt :
1669 Hexagon::LDrib_cNotPt;
1670 case Hexagon::LDriub:
1671 return !invertPredicate ? Hexagon::LDriub_cPt :
1672 Hexagon::LDriub_cNotPt;
1674 case Hexagon::LDrid_indexed:
1675 return !invertPredicate ? Hexagon::LDrid_indexed_cPt :
1676 Hexagon::LDrid_indexed_cNotPt;
1677 case Hexagon::LDriw_indexed:
1678 return !invertPredicate ? Hexagon::LDriw_indexed_cPt :
1679 Hexagon::LDriw_indexed_cNotPt;
1680 case Hexagon::LDrih_indexed:
1681 return !invertPredicate ? Hexagon::LDrih_indexed_cPt :
1682 Hexagon::LDrih_indexed_cNotPt;
1683 case Hexagon::LDriuh_indexed:
1684 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt :
1685 Hexagon::LDriuh_indexed_cNotPt;
1686 case Hexagon::LDrib_indexed:
1687 return !invertPredicate ? Hexagon::LDrib_indexed_cPt :
1688 Hexagon::LDrib_indexed_cNotPt;
1689 case Hexagon::LDriub_indexed:
1690 return !invertPredicate ? Hexagon::LDriub_indexed_cPt :
1691 Hexagon::LDriub_indexed_cNotPt;
1692 // Post Increment Load.
1693 case Hexagon::POST_LDrid:
1694 return !invertPredicate ? Hexagon::POST_LDrid_cPt :
1695 Hexagon::POST_LDrid_cNotPt;
1696 case Hexagon::POST_LDriw:
1697 return !invertPredicate ? Hexagon::POST_LDriw_cPt :
1698 Hexagon::POST_LDriw_cNotPt;
1699 case Hexagon::POST_LDrih:
1700 return !invertPredicate ? Hexagon::POST_LDrih_cPt :
1701 Hexagon::POST_LDrih_cNotPt;
1702 case Hexagon::POST_LDriuh:
1703 return !invertPredicate ? Hexagon::POST_LDriuh_cPt :
1704 Hexagon::POST_LDriuh_cNotPt;
1705 case Hexagon::POST_LDrib:
1706 return !invertPredicate ? Hexagon::POST_LDrib_cPt :
1707 Hexagon::POST_LDrib_cNotPt;
1708 case Hexagon::POST_LDriub:
1709 return !invertPredicate ? Hexagon::POST_LDriub_cPt :
1710 Hexagon::POST_LDriub_cNotPt;
1712 case Hexagon::DEALLOC_RET_V4:
1713 return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
1714 Hexagon::DEALLOC_RET_cNotPt_V4;
1716 llvm_unreachable("Unexpected predicable instruction");
1720 bool HexagonInstrInfo::
1721 PredicateInstruction(MachineInstr *MI,
1722 const SmallVectorImpl<MachineOperand> &Cond) const {
1723 int Opc = MI->getOpcode();
1724 assert (isPredicable(MI) && "Expected predicable instruction");
1725 bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
1726 (Cond[0].getImm() == 0));
1728 // This will change MI's opcode to its predicate version.
1729 // However, its operand list is still the old one, i.e. the
1730 // non-predicate one.
1731 MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
1734 unsigned int GAIdx = 0;
1736 // Indicates whether the current MI has a GlobalAddress operand
1737 bool hasGAOpnd = false;
1738 std::vector<MachineOperand> tmpOpnds;
1740 // Indicates whether we need to shift operands to right.
1741 bool needShift = true;
1743 // The predicate is ALWAYS the FIRST input operand !!!
1744 if (MI->getNumOperands() == 0) {
1745 // The non-predicate version of MI does not take any operands,
1746 // i.e. no outs and no ins. In this condition, the predicate
1747 // operand will be directly placed at Operands[0]. No operand
1753 else if ( MI->getOperand(MI->getNumOperands()-1).isReg()
1754 && MI->getOperand(MI->getNumOperands()-1).isDef()
1755 && !MI->getOperand(MI->getNumOperands()-1).isImplicit()) {
1756 // The non-predicate version of MI does not have any input operands.
1757 // In this condition, we extend the length of Operands[] by one and
1758 // copy the original last operand to the newly allocated slot.
1759 // At this moment, it is just a place holder. Later, we will put
1760 // predicate operand directly into it. No operand shift is needed.
1761 // Example: r0=BARRIER (this is a faked insn used here for illustration)
1762 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
1764 oper = MI->getNumOperands() - 2;
1767 // We need to right shift all input operands by one. Duplicate the
1768 // last operand into the newly allocated slot.
1769 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
1774 // Operands[ MI->getNumOperands() - 2 ] has been copied into
1775 // Operands[ MI->getNumOperands() - 1 ], so we start from
1776 // Operands[ MI->getNumOperands() - 3 ].
1777 // oper is a signed int.
1778 // It is ok if "MI->getNumOperands()-3" is -3, -2, or -1.
1779 for (oper = MI->getNumOperands() - 3; oper >= 0; --oper)
1781 MachineOperand &MO = MI->getOperand(oper);
1783 // Opnd[0] Opnd[1] Opnd[2] Opnd[3] Opnd[4] Opnd[5] Opnd[6] Opnd[7]
1784 // <Def0> <Def1> <Use0> <Use1> <ImpDef0> <ImpDef1> <ImpUse0> <ImpUse1>
1788 // Predicate Operand here
1789 if (MO.isReg() && !MO.isUse() && !MO.isImplicit()) {
1793 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
1794 MO.isImplicit(), MO.isKill(),
1795 MO.isDead(), MO.isUndef(),
1798 else if (MO.isImm()) {
1799 MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
1801 else if (MO.isGlobal()) {
1802 // MI can not have more than one GlobalAddress operand.
1803 assert(hasGAOpnd == false && "MI can only have one GlobalAddress opnd");
1805 // There is no member function called "ChangeToGlobalAddress" in the
1806 // MachineOperand class (not like "ChangeToRegister" and
1807 // "ChangeToImmediate"). So we have to remove them from Operands[] list
1808 // first, and then add them back after we have inserted the predicate
1809 // operand. tmpOpnds[] is to remember these operands before we remove
1811 tmpOpnds.push_back(MO);
1813 // Operands[oper] is a GlobalAddress operand;
1814 // Operands[oper+1] has been copied into Operands[oper+2];
1820 assert(false && "Unexpected operand type");
1825 int regPos = invertJump ? 1 : 0;
1826 MachineOperand PredMO = Cond[regPos];
1828 // [oper] now points to the last explicit Def. Predicate operand must be
1829 // located at [oper+1]. See diagram above.
1830 // This assumes that the predicate is always the first operand,
1831 // i.e. Operands[0+numResults], in the set of inputs
1832 // It is better to have an assert here to check this. But I don't know how
1833 // to write this assert because findFirstPredOperandIdx() would return -1
1834 if (oper < -1) oper = -1;
1836 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
1837 PredMO.isImplicit(), false,
1838 PredMO.isDead(), PredMO.isUndef(),
1841 MachineRegisterInfo &RegInfo = MI->getParent()->getParent()->getRegInfo();
1842 RegInfo.clearKillFlags(PredMO.getReg());
1848 // Operands[GAIdx] is the original GlobalAddress operand, which is
1849 // already copied into tmpOpnds[0].
1850 // Operands[GAIdx] now stores a copy of Operands[GAIdx-1]
1851 // Operands[GAIdx+1] has already been copied into Operands[GAIdx+2],
1852 // so we start from [GAIdx+2]
1853 for (i = GAIdx + 2; i < MI->getNumOperands(); ++i)
1854 tmpOpnds.push_back(MI->getOperand(i));
1856 // Remove all operands in range [ (GAIdx+1) ... (MI->getNumOperands()-1) ]
1857 // It is very important that we always remove from the end of Operands[]
1858 // MI->getNumOperands() is at least 2 if program goes to here.
1859 for (i = MI->getNumOperands() - 1; i > GAIdx; --i)
1860 MI->RemoveOperand(i);
1862 for (i = 0; i < tmpOpnds.size(); ++i)
1863 MI->addOperand(tmpOpnds[i]);
1872 isProfitableToIfCvt(MachineBasicBlock &MBB,
1874 unsigned ExtraPredCycles,
1875 const BranchProbability &Probability) const {
1882 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1883 unsigned NumTCycles,
1884 unsigned ExtraTCycles,
1885 MachineBasicBlock &FMBB,
1886 unsigned NumFCycles,
1887 unsigned ExtraFCycles,
1888 const BranchProbability &Probability) const {
1893 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
1894 const uint64_t F = MI->getDesc().TSFlags;
1896 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1899 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
1900 const uint64_t F = MI->getDesc().TSFlags;
1902 assert(isPredicated(MI));
1903 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1907 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
1908 std::vector<MachineOperand> &Pred) const {
1909 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
1910 MachineOperand MO = MI->getOperand(oper);
1911 if (MO.isReg() && MO.isDef()) {
1912 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
1913 if (RC == &Hexagon::PredRegsRegClass) {
1925 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
1926 const SmallVectorImpl<MachineOperand> &Pred2) const {
1933 // We indicate that we want to reverse the branch by
1934 // inserting a 0 at the beginning of the Cond vector.
1936 bool HexagonInstrInfo::
1937 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1938 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
1939 Cond.erase(Cond.begin());
1941 Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
1947 bool HexagonInstrInfo::
1948 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
1949 const BranchProbability &Probability) const {
1950 return (NumInstrs <= 4);
1953 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
1954 switch (MI->getOpcode()) {
1955 default: return false;
1956 case Hexagon::DEALLOC_RET_V4 :
1957 case Hexagon::DEALLOC_RET_cPt_V4 :
1958 case Hexagon::DEALLOC_RET_cNotPt_V4 :
1959 case Hexagon::DEALLOC_RET_cdnPnt_V4 :
1960 case Hexagon::DEALLOC_RET_cNotdnPnt_V4 :
1961 case Hexagon::DEALLOC_RET_cdnPt_V4 :
1962 case Hexagon::DEALLOC_RET_cNotdnPt_V4 :
1968 bool HexagonInstrInfo::
1969 isValidOffset(const int Opcode, const int Offset) const {
1970 // This function is to check whether the "Offset" is in the correct range of
1971 // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
1972 // inserted to calculate the final address. Due to this reason, the function
1973 // assumes that the "Offset" has correct alignment.
1974 // We used to assert if the offset was not properly aligned, however,
1975 // there are cases where a misaligned pointer recast can cause this
1976 // problem, and we need to allow for it. The front end warns of such
1977 // misaligns with respect to load size.
1981 case Hexagon::LDriw:
1982 case Hexagon::LDriw_indexed:
1983 case Hexagon::LDriw_f:
1984 case Hexagon::STriw_indexed:
1985 case Hexagon::STriw:
1986 case Hexagon::STriw_f:
1987 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
1988 (Offset <= Hexagon_MEMW_OFFSET_MAX);
1990 case Hexagon::LDrid:
1991 case Hexagon::LDrid_indexed:
1992 case Hexagon::LDrid_f:
1993 case Hexagon::STrid:
1994 case Hexagon::STrid_indexed:
1995 case Hexagon::STrid_f:
1996 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
1997 (Offset <= Hexagon_MEMD_OFFSET_MAX);
1999 case Hexagon::LDrih:
2000 case Hexagon::LDriuh:
2001 case Hexagon::STrih:
2002 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2003 (Offset <= Hexagon_MEMH_OFFSET_MAX);
2005 case Hexagon::LDrib:
2006 case Hexagon::STrib:
2007 case Hexagon::LDriub:
2008 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2009 (Offset <= Hexagon_MEMB_OFFSET_MAX);
2011 case Hexagon::ADD_ri:
2012 case Hexagon::TFR_FI:
2013 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2014 (Offset <= Hexagon_ADDI_OFFSET_MAX);
2016 case Hexagon::MemOPw_ADDi_V4 :
2017 case Hexagon::MemOPw_SUBi_V4 :
2018 case Hexagon::MemOPw_ADDr_V4 :
2019 case Hexagon::MemOPw_SUBr_V4 :
2020 case Hexagon::MemOPw_ANDr_V4 :
2021 case Hexagon::MemOPw_ORr_V4 :
2022 return (0 <= Offset && Offset <= 255);
2024 case Hexagon::MemOPh_ADDi_V4 :
2025 case Hexagon::MemOPh_SUBi_V4 :
2026 case Hexagon::MemOPh_ADDr_V4 :
2027 case Hexagon::MemOPh_SUBr_V4 :
2028 case Hexagon::MemOPh_ANDr_V4 :
2029 case Hexagon::MemOPh_ORr_V4 :
2030 return (0 <= Offset && Offset <= 127);
2032 case Hexagon::MemOPb_ADDi_V4 :
2033 case Hexagon::MemOPb_SUBi_V4 :
2034 case Hexagon::MemOPb_ADDr_V4 :
2035 case Hexagon::MemOPb_SUBr_V4 :
2036 case Hexagon::MemOPb_ANDr_V4 :
2037 case Hexagon::MemOPb_ORr_V4 :
2038 return (0 <= Offset && Offset <= 63);
2040 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
2041 // any size. Later pass knows how to handle it.
2042 case Hexagon::STriw_pred:
2043 case Hexagon::LDriw_pred:
2046 case Hexagon::LOOP0_i:
2047 return isUInt<10>(Offset);
2049 // INLINEASM is very special.
2050 case Hexagon::INLINEASM:
2054 llvm_unreachable("No offset range is defined for this opcode. "
2055 "Please define it in the above switch statement!");
2060 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2062 bool HexagonInstrInfo::
2063 isValidAutoIncImm(const EVT VT, const int Offset) const {
2065 if (VT == MVT::i64) {
2066 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
2067 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
2068 (Offset & 0x7) == 0);
2070 if (VT == MVT::i32) {
2071 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
2072 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
2073 (Offset & 0x3) == 0);
2075 if (VT == MVT::i16) {
2076 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
2077 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
2078 (Offset & 0x1) == 0);
2080 if (VT == MVT::i8) {
2081 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
2082 Offset <= Hexagon_MEMB_AUTOINC_MAX);
2084 llvm_unreachable("Not an auto-inc opc!");
2088 bool HexagonInstrInfo::
2089 isMemOp(const MachineInstr *MI) const {
2090 switch (MI->getOpcode())
2092 default: return false;
2093 case Hexagon::MemOPw_ADDi_V4 :
2094 case Hexagon::MemOPw_SUBi_V4 :
2095 case Hexagon::MemOPw_ADDr_V4 :
2096 case Hexagon::MemOPw_SUBr_V4 :
2097 case Hexagon::MemOPw_ANDr_V4 :
2098 case Hexagon::MemOPw_ORr_V4 :
2099 case Hexagon::MemOPh_ADDi_V4 :
2100 case Hexagon::MemOPh_SUBi_V4 :
2101 case Hexagon::MemOPh_ADDr_V4 :
2102 case Hexagon::MemOPh_SUBr_V4 :
2103 case Hexagon::MemOPh_ANDr_V4 :
2104 case Hexagon::MemOPh_ORr_V4 :
2105 case Hexagon::MemOPb_ADDi_V4 :
2106 case Hexagon::MemOPb_SUBi_V4 :
2107 case Hexagon::MemOPb_ADDr_V4 :
2108 case Hexagon::MemOPb_SUBr_V4 :
2109 case Hexagon::MemOPb_ANDr_V4 :
2110 case Hexagon::MemOPb_ORr_V4 :
2111 case Hexagon::MemOPb_SETBITi_V4:
2112 case Hexagon::MemOPh_SETBITi_V4:
2113 case Hexagon::MemOPw_SETBITi_V4:
2114 case Hexagon::MemOPb_CLRBITi_V4:
2115 case Hexagon::MemOPh_CLRBITi_V4:
2116 case Hexagon::MemOPw_CLRBITi_V4:
2123 bool HexagonInstrInfo::
2124 isSpillPredRegOp(const MachineInstr *MI) const {
2125 switch (MI->getOpcode()) {
2126 default: return false;
2127 case Hexagon::STriw_pred :
2128 case Hexagon::LDriw_pred :
2133 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
2134 switch (MI->getOpcode()) {
2135 default: return false;
2136 case Hexagon::CMPEQrr:
2137 case Hexagon::CMPEQri:
2138 case Hexagon::CMPGTrr:
2139 case Hexagon::CMPGTri:
2140 case Hexagon::CMPGTUrr:
2141 case Hexagon::CMPGTUri:
2146 bool HexagonInstrInfo::
2147 isConditionalTransfer (const MachineInstr *MI) const {
2148 switch (MI->getOpcode()) {
2149 default: return false;
2150 case Hexagon::TFR_cPt:
2151 case Hexagon::TFR_cNotPt:
2152 case Hexagon::TFRI_cPt:
2153 case Hexagon::TFRI_cNotPt:
2154 case Hexagon::TFR_cdnPt:
2155 case Hexagon::TFR_cdnNotPt:
2156 case Hexagon::TFRI_cdnPt:
2157 case Hexagon::TFRI_cdnNotPt:
2162 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
2163 const HexagonRegisterInfo& QRI = getRegisterInfo();
2164 switch (MI->getOpcode())
2166 default: return false;
2167 case Hexagon::ADD_ri_cPt:
2168 case Hexagon::ADD_ri_cNotPt:
2169 case Hexagon::ADD_rr_cPt:
2170 case Hexagon::ADD_rr_cNotPt:
2171 case Hexagon::XOR_rr_cPt:
2172 case Hexagon::XOR_rr_cNotPt:
2173 case Hexagon::AND_rr_cPt:
2174 case Hexagon::AND_rr_cNotPt:
2175 case Hexagon::OR_rr_cPt:
2176 case Hexagon::OR_rr_cNotPt:
2177 case Hexagon::SUB_rr_cPt:
2178 case Hexagon::SUB_rr_cNotPt:
2179 case Hexagon::COMBINE_rr_cPt:
2180 case Hexagon::COMBINE_rr_cNotPt:
2182 case Hexagon::ASLH_cPt_V4:
2183 case Hexagon::ASLH_cNotPt_V4:
2184 case Hexagon::ASRH_cPt_V4:
2185 case Hexagon::ASRH_cNotPt_V4:
2186 case Hexagon::SXTB_cPt_V4:
2187 case Hexagon::SXTB_cNotPt_V4:
2188 case Hexagon::SXTH_cPt_V4:
2189 case Hexagon::SXTH_cNotPt_V4:
2190 case Hexagon::ZXTB_cPt_V4:
2191 case Hexagon::ZXTB_cNotPt_V4:
2192 case Hexagon::ZXTH_cPt_V4:
2193 case Hexagon::ZXTH_cNotPt_V4:
2194 return QRI.Subtarget.hasV4TOps();
2198 bool HexagonInstrInfo::
2199 isConditionalLoad (const MachineInstr* MI) const {
2200 const HexagonRegisterInfo& QRI = getRegisterInfo();
2201 switch (MI->getOpcode())
2203 default: return false;
2204 case Hexagon::LDrid_cPt :
2205 case Hexagon::LDrid_cNotPt :
2206 case Hexagon::LDrid_indexed_cPt :
2207 case Hexagon::LDrid_indexed_cNotPt :
2208 case Hexagon::LDriw_cPt :
2209 case Hexagon::LDriw_cNotPt :
2210 case Hexagon::LDriw_indexed_cPt :
2211 case Hexagon::LDriw_indexed_cNotPt :
2212 case Hexagon::LDrih_cPt :
2213 case Hexagon::LDrih_cNotPt :
2214 case Hexagon::LDrih_indexed_cPt :
2215 case Hexagon::LDrih_indexed_cNotPt :
2216 case Hexagon::LDrib_cPt :
2217 case Hexagon::LDrib_cNotPt :
2218 case Hexagon::LDrib_indexed_cPt :
2219 case Hexagon::LDrib_indexed_cNotPt :
2220 case Hexagon::LDriuh_cPt :
2221 case Hexagon::LDriuh_cNotPt :
2222 case Hexagon::LDriuh_indexed_cPt :
2223 case Hexagon::LDriuh_indexed_cNotPt :
2224 case Hexagon::LDriub_cPt :
2225 case Hexagon::LDriub_cNotPt :
2226 case Hexagon::LDriub_indexed_cPt :
2227 case Hexagon::LDriub_indexed_cNotPt :
2229 case Hexagon::POST_LDrid_cPt :
2230 case Hexagon::POST_LDrid_cNotPt :
2231 case Hexagon::POST_LDriw_cPt :
2232 case Hexagon::POST_LDriw_cNotPt :
2233 case Hexagon::POST_LDrih_cPt :
2234 case Hexagon::POST_LDrih_cNotPt :
2235 case Hexagon::POST_LDrib_cPt :
2236 case Hexagon::POST_LDrib_cNotPt :
2237 case Hexagon::POST_LDriuh_cPt :
2238 case Hexagon::POST_LDriuh_cNotPt :
2239 case Hexagon::POST_LDriub_cPt :
2240 case Hexagon::POST_LDriub_cNotPt :
2241 return QRI.Subtarget.hasV4TOps();
2242 case Hexagon::LDrid_indexed_shl_cPt_V4 :
2243 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
2244 case Hexagon::LDrib_indexed_shl_cPt_V4 :
2245 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
2246 case Hexagon::LDriub_indexed_shl_cPt_V4 :
2247 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
2248 case Hexagon::LDrih_indexed_shl_cPt_V4 :
2249 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
2250 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
2251 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
2252 case Hexagon::LDriw_indexed_shl_cPt_V4 :
2253 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
2254 return QRI.Subtarget.hasV4TOps();
2258 // Returns true if an instruction is a conditional store.
2260 // Note: It doesn't include conditional new-value stores as they can't be
2261 // converted to .new predicate.
2263 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
2265 // / \ (not OK. it will cause new-value store to be
2266 // / X conditional on p0.new while R2 producer is
2269 // p.new store p.old NV store
2270 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
2276 // [if (p0)memw(R0+#0)=R2]
2278 // The above diagram shows the steps involoved in the conversion of a predicated
2279 // store instruction to its .new predicated new-value form.
2281 // The following set of instructions further explains the scenario where
2282 // conditional new-value store becomes invalid when promoted to .new predicate
2285 // { 1) if (p0) r0 = add(r1, r2)
2286 // 2) p0 = cmp.eq(r3, #0) }
2288 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
2289 // the first two instructions because in instr 1, r0 is conditional on old value
2290 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
2291 // is not valid for new-value stores.
2292 bool HexagonInstrInfo::
2293 isConditionalStore (const MachineInstr* MI) const {
2294 const HexagonRegisterInfo& QRI = getRegisterInfo();
2295 switch (MI->getOpcode())
2297 default: return false;
2298 case Hexagon::STrib_imm_cPt_V4 :
2299 case Hexagon::STrib_imm_cNotPt_V4 :
2300 case Hexagon::STrib_indexed_shl_cPt_V4 :
2301 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
2302 case Hexagon::STrib_cPt :
2303 case Hexagon::STrib_cNotPt :
2304 case Hexagon::POST_STbri_cPt :
2305 case Hexagon::POST_STbri_cNotPt :
2306 case Hexagon::STrid_indexed_cPt :
2307 case Hexagon::STrid_indexed_cNotPt :
2308 case Hexagon::STrid_indexed_shl_cPt_V4 :
2309 case Hexagon::POST_STdri_cPt :
2310 case Hexagon::POST_STdri_cNotPt :
2311 case Hexagon::STrih_cPt :
2312 case Hexagon::STrih_cNotPt :
2313 case Hexagon::STrih_indexed_cPt :
2314 case Hexagon::STrih_indexed_cNotPt :
2315 case Hexagon::STrih_imm_cPt_V4 :
2316 case Hexagon::STrih_imm_cNotPt_V4 :
2317 case Hexagon::STrih_indexed_shl_cPt_V4 :
2318 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
2319 case Hexagon::POST_SThri_cPt :
2320 case Hexagon::POST_SThri_cNotPt :
2321 case Hexagon::STriw_cPt :
2322 case Hexagon::STriw_cNotPt :
2323 case Hexagon::STriw_indexed_cPt :
2324 case Hexagon::STriw_indexed_cNotPt :
2325 case Hexagon::STriw_imm_cPt_V4 :
2326 case Hexagon::STriw_imm_cNotPt_V4 :
2327 case Hexagon::STriw_indexed_shl_cPt_V4 :
2328 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
2329 case Hexagon::POST_STwri_cPt :
2330 case Hexagon::POST_STwri_cNotPt :
2331 return QRI.Subtarget.hasV4TOps();
2333 // V4 global address store before promoting to dot new.
2334 case Hexagon::STd_GP_cPt_V4 :
2335 case Hexagon::STd_GP_cNotPt_V4 :
2336 case Hexagon::STb_GP_cPt_V4 :
2337 case Hexagon::STb_GP_cNotPt_V4 :
2338 case Hexagon::STh_GP_cPt_V4 :
2339 case Hexagon::STh_GP_cNotPt_V4 :
2340 case Hexagon::STw_GP_cPt_V4 :
2341 case Hexagon::STw_GP_cNotPt_V4 :
2342 return QRI.Subtarget.hasV4TOps();
2344 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
2345 // from the "Conditional Store" list. Because a predicated new value store
2346 // would NOT be promoted to a double dot new store. See diagram below:
2347 // This function returns yes for those stores that are predicated but not
2348 // yet promoted to predicate dot new instructions.
2350 // +---------------------+
2351 // /-----| if (p0) memw(..)=r0 |---------\~
2352 // || +---------------------+ ||
2353 // promote || /\ /\ || promote
2355 // \||/ demote || \||/
2357 // +-------------------------+ || +-------------------------+
2358 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
2359 // +-------------------------+ || +-------------------------+
2362 // promote || \/ NOT possible
2366 // +-----------------------------+
2367 // | if (p0.new) memw(..)=r0.new |
2368 // +-----------------------------+
2369 // Double Dot New Store
2374 // Returns true, if any one of the operands is a dot new
2375 // insn, whether it is predicated dot new or register dot new.
2376 bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
2377 return (isNewValueInst(MI) ||
2378 (isPredicated(MI) && isPredicatedNew(MI)));
2381 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
2382 const uint64_t F = MI->getDesc().TSFlags;
2384 return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
2387 /// immediateExtend - Changes the instruction in place to one using an immediate
2389 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
2390 assert((isExtendable(MI)||isConstExtended(MI)) &&
2391 "Instruction must be extendable");
2392 // Find which operand is extendable.
2393 short ExtOpNum = getCExtOpNum(MI);
2394 MachineOperand &MO = MI->getOperand(ExtOpNum);
2395 // This needs to be something we understand.
2396 assert((MO.isMBB() || MO.isImm()) &&
2397 "Branch with unknown extendable field type");
2398 // Mark given operand as extended.
2399 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
2402 DFAPacketizer *HexagonInstrInfo::
2403 CreateTargetScheduleState(const TargetMachine *TM,
2404 const ScheduleDAG *DAG) const {
2405 const InstrItineraryData *II = TM->getInstrItineraryData();
2406 return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II);
2409 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
2410 const MachineBasicBlock *MBB,
2411 const MachineFunction &MF) const {
2412 // Debug info is never a scheduling boundary. It's necessary to be explicit
2413 // due to the special treatment of IT instructions below, otherwise a
2414 // dbg_value followed by an IT will result in the IT instruction being
2415 // considered a scheduling hazard, which is wrong. It should be the actual
2416 // instruction preceding the dbg_value instruction(s), just like it is
2417 // when debug info is not present.
2418 if (MI->isDebugValue())
2421 // Terminators and labels can't be scheduled around.
2422 if (MI->getDesc().isTerminator() || MI->isLabel() || MI->isInlineAsm())
2428 bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const {
2430 // Constant extenders are allowed only for V4 and above.
2431 if (!Subtarget.hasV4TOps())
2434 const uint64_t F = MI->getDesc().TSFlags;
2435 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
2436 if (isExtended) // Instruction must be extended.
2439 unsigned isExtendable = (F >> HexagonII::ExtendablePos)
2440 & HexagonII::ExtendableMask;
2444 short ExtOpNum = getCExtOpNum(MI);
2445 const MachineOperand &MO = MI->getOperand(ExtOpNum);
2446 // Use MO operand flags to determine if MO
2447 // has the HMOTF_ConstExtended flag set.
2448 if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
2450 // If this is a Machine BB address we are talking about, and it is
2451 // not marked as extended, say so.
2455 // We could be using an instruction with an extendable immediate and shoehorn
2456 // a global address into it. If it is a global address it will be constant
2457 // extended. We do this for COMBINE.
2458 // We currently only handle isGlobal() because it is the only kind of
2459 // object we are going to end up with here for now.
2460 // In the future we probably should add isSymbol(), etc.
2461 if (MO.isGlobal() || MO.isSymbol())
2464 // If the extendable operand is not 'Immediate' type, the instruction should
2465 // have 'isExtended' flag set.
2466 assert(MO.isImm() && "Extendable operand must be Immediate type");
2468 int MinValue = getMinValue(MI);
2469 int MaxValue = getMaxValue(MI);
2470 int ImmValue = MO.getImm();
2472 return (ImmValue < MinValue || ImmValue > MaxValue);
2475 // Returns the opcode to use when converting MI, which is a conditional jump,
2476 // into a conditional instruction which uses the .new value of the predicate.
2477 // We also use branch probabilities to add a hint to the jump.
2479 HexagonInstrInfo::getDotNewPredJumpOp(MachineInstr *MI,
2481 MachineBranchProbabilityInfo *MBPI) const {
2483 // We assume that block can have at most two successors.
2485 MachineBasicBlock *Src = MI->getParent();
2486 MachineOperand *BrTarget = &MI->getOperand(1);
2487 MachineBasicBlock *Dst = BrTarget->getMBB();
2489 const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
2490 if (Prediction >= BranchProbability(1,2))
2493 switch (MI->getOpcode()) {
2494 case Hexagon::JMP_t:
2495 return taken ? Hexagon::JMP_tnew_t : Hexagon::JMP_tnew_nt;
2496 case Hexagon::JMP_f:
2497 return taken ? Hexagon::JMP_fnew_t : Hexagon::JMP_fnew_nt;
2500 llvm_unreachable("Unexpected jump instruction.");
2503 // Returns true if a particular operand is extendable for an instruction.
2504 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
2505 unsigned short OperandNum) const {
2506 // Constant extenders are allowed only for V4 and above.
2507 if (!Subtarget.hasV4TOps())
2510 const uint64_t F = MI->getDesc().TSFlags;
2512 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
2516 // Returns Operand Index for the constant extended instruction.
2517 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
2518 const uint64_t F = MI->getDesc().TSFlags;
2519 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
2522 // Returns the min value that doesn't need to be extended.
2523 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
2524 const uint64_t F = MI->getDesc().TSFlags;
2525 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
2526 & HexagonII::ExtentSignedMask;
2527 unsigned bits = (F >> HexagonII::ExtentBitsPos)
2528 & HexagonII::ExtentBitsMask;
2530 if (isSigned) // if value is signed
2531 return -1 << (bits - 1);
2536 // Returns the max value that doesn't need to be extended.
2537 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
2538 const uint64_t F = MI->getDesc().TSFlags;
2539 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
2540 & HexagonII::ExtentSignedMask;
2541 unsigned bits = (F >> HexagonII::ExtentBitsPos)
2542 & HexagonII::ExtentBitsMask;
2544 if (isSigned) // if value is signed
2545 return ~(-1 << (bits - 1));
2547 return ~(-1 << bits);
2550 // Returns true if an instruction can be converted into a non-extended
2551 // equivalent instruction.
2552 bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const {
2555 // Check if the instruction has a register form that uses register in place
2556 // of the extended operand, if so return that as the non-extended form.
2557 if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
2560 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
2561 // Check addressing mode and retreive non-ext equivalent instruction.
2563 switch (getAddrMode(MI)) {
2564 case HexagonII::Absolute :
2565 // Load/store with absolute addressing mode can be converted into
2566 // base+offset mode.
2567 NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
2569 case HexagonII::BaseImmOffset :
2570 // Load/store with base+offset addressing mode can be converted into
2571 // base+register offset addressing mode. However left shift operand should
2573 NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
2578 if (NonExtOpcode < 0)
2585 // Returns opcode of the non-extended equivalent instruction.
2586 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
2588 // Check if the instruction has a register form that uses register in place
2589 // of the extended operand, if so return that as the non-extended form.
2590 short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
2591 if (NonExtOpcode >= 0)
2592 return NonExtOpcode;
2594 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
2595 // Check addressing mode and retreive non-ext equivalent instruction.
2596 switch (getAddrMode(MI)) {
2597 case HexagonII::Absolute :
2598 return Hexagon::getBasedWithImmOffset(MI->getOpcode());
2599 case HexagonII::BaseImmOffset :
2600 return Hexagon::getBaseWithRegOffset(MI->getOpcode());
2608 bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const {
2609 return (Opcode == Hexagon::JMP_t) ||
2610 (Opcode == Hexagon::JMP_f) ||
2611 (Opcode == Hexagon::JMP_tnew_t) ||
2612 (Opcode == Hexagon::JMP_fnew_t) ||
2613 (Opcode == Hexagon::JMP_tnew_nt) ||
2614 (Opcode == Hexagon::JMP_fnew_nt);
2617 bool HexagonInstrInfo::PredOpcodeHasNot(Opcode_t Opcode) const {
2618 return (Opcode == Hexagon::JMP_f) ||
2619 (Opcode == Hexagon::JMP_fnew_t) ||
2620 (Opcode == Hexagon::JMP_fnew_nt);