1 //=- HexagonInstrInfo.h - Hexagon Instruction Information ---------*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef HexagonINSTRUCTIONINFO_H
15 #define HexagonINSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "llvm/Target/TargetFrameLowering.h"
19 #include "HexagonRegisterInfo.h"
22 #define GET_INSTRINFO_HEADER
23 #include "HexagonGenInstrInfo.inc"
27 class HexagonInstrInfo : public HexagonGenInstrInfo {
28 const HexagonRegisterInfo RI;
29 const HexagonSubtarget& Subtarget;
31 explicit HexagonInstrInfo(HexagonSubtarget &ST);
33 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
34 /// such, whenever a client has an instance of instruction info, it should
35 /// always be able to get register info as well (through this method).
37 virtual const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
39 /// isLoadFromStackSlot - If the specified machine instruction is a direct
40 /// load from a stack slot, return the virtual or physical register number of
41 /// the destination along with the FrameIndex of the loaded stack slot. If
42 /// not, return 0. This predicate must return 0 if the instruction has
43 /// any side effects other than loading from the stack slot.
44 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
45 int &FrameIndex) const;
47 /// isStoreToStackSlot - If the specified machine instruction is a direct
48 /// store to a stack slot, return the virtual or physical register number of
49 /// the source reg along with the FrameIndex of the loaded stack slot. If
50 /// not, return 0. This predicate must return 0 if the instruction has
51 /// any side effects other than storing to the stack slot.
52 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
53 int &FrameIndex) const;
56 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
57 MachineBasicBlock *&FBB,
58 SmallVectorImpl<MachineOperand> &Cond,
59 bool AllowModify) const;
61 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
63 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
64 MachineBasicBlock *FBB,
65 const SmallVectorImpl<MachineOperand> &Cond,
68 virtual void copyPhysReg(MachineBasicBlock &MBB,
69 MachineBasicBlock::iterator I, DebugLoc DL,
70 unsigned DestReg, unsigned SrcReg,
73 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
74 MachineBasicBlock::iterator MBBI,
75 unsigned SrcReg, bool isKill, int FrameIndex,
76 const TargetRegisterClass *RC,
77 const TargetRegisterInfo *TRI) const;
79 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
80 SmallVectorImpl<MachineOperand> &Addr,
81 const TargetRegisterClass *RC,
82 SmallVectorImpl<MachineInstr*> &NewMIs) const;
84 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
85 MachineBasicBlock::iterator MBBI,
86 unsigned DestReg, int FrameIndex,
87 const TargetRegisterClass *RC,
88 const TargetRegisterInfo *TRI) const;
90 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
91 SmallVectorImpl<MachineOperand> &Addr,
92 const TargetRegisterClass *RC,
93 SmallVectorImpl<MachineInstr*> &NewMIs) const;
95 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
97 const SmallVectorImpl<unsigned> &Ops,
98 int FrameIndex) const;
100 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
102 const SmallVectorImpl<unsigned> &Ops,
103 MachineInstr* LoadMI) const {
107 unsigned createVR(MachineFunction* MF, MVT VT) const;
109 virtual bool isPredicable(MachineInstr *MI) const;
111 PredicateInstruction(MachineInstr *MI,
112 const SmallVectorImpl<MachineOperand> &Cond) const;
114 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
115 unsigned ExtraPredCycles,
116 const BranchProbability &Probability) const;
118 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
119 unsigned NumTCycles, unsigned ExtraTCycles,
120 MachineBasicBlock &FMBB,
121 unsigned NumFCycles, unsigned ExtraFCycles,
122 const BranchProbability &Probability) const;
124 virtual bool isPredicated(const MachineInstr *MI) const;
125 virtual bool DefinesPredicate(MachineInstr *MI,
126 std::vector<MachineOperand> &Pred) const;
128 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
129 const SmallVectorImpl<MachineOperand> &Pred2) const;
132 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
135 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles,
136 const BranchProbability &Probability) const;
138 bool isValidOffset(const int Opcode, const int Offset) const;
139 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
140 bool isMemOp(const MachineInstr *MI) const;
141 bool isSpillPredRegOp(const MachineInstr *MI) const;
142 bool isU6_3Immediate(const int value) const;
143 bool isU6_2Immediate(const int value) const;
144 bool isU6_1Immediate(const int value) const;
145 bool isU6_0Immediate(const int value) const;
146 bool isS4_3Immediate(const int value) const;
147 bool isS4_2Immediate(const int value) const;
148 bool isS4_1Immediate(const int value) const;
149 bool isS4_0Immediate(const int value) const;
150 bool isS12_Immediate(const int value) const;
151 bool isU6_Immediate(const int value) const;
152 bool isS8_Immediate(const int value) const;
153 bool isS6_Immediate(const int value) const;
155 bool isConditionalALU32 (const MachineInstr* MI) const;
156 bool isConditionalLoad (const MachineInstr* MI) const;
157 bool isDeallocRet(const MachineInstr *MI) const;
160 int getMatchingCondBranchOpcode(int Opc, bool sense) const;