1 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef HexagonINSTRUCTIONINFO_H
15 #define HexagonINSTRUCTIONINFO_H
17 #include "HexagonRegisterInfo.h"
18 #include "MCTargetDesc/HexagonBaseInfo.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Target/TargetFrameLowering.h"
21 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
23 #define GET_INSTRINFO_HEADER
24 #include "HexagonGenInstrInfo.inc"
28 class HexagonInstrInfo : public HexagonGenInstrInfo {
29 const HexagonRegisterInfo RI;
30 const HexagonSubtarget& Subtarget;
31 typedef unsigned Opcode_t;
34 explicit HexagonInstrInfo(HexagonSubtarget &ST);
36 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
37 /// such, whenever a client has an instance of instruction info, it should
38 /// always be able to get register info as well (through this method).
40 virtual const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
42 /// isLoadFromStackSlot - If the specified machine instruction is a direct
43 /// load from a stack slot, return the virtual or physical register number of
44 /// the destination along with the FrameIndex of the loaded stack slot. If
45 /// not, return 0. This predicate must return 0 if the instruction has
46 /// any side effects other than loading from the stack slot.
47 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
48 int &FrameIndex) const;
50 /// isStoreToStackSlot - If the specified machine instruction is a direct
51 /// store to a stack slot, return the virtual or physical register number of
52 /// the source reg along with the FrameIndex of the loaded stack slot. If
53 /// not, return 0. This predicate must return 0 if the instruction has
54 /// any side effects other than storing to the stack slot.
55 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
56 int &FrameIndex) const;
59 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
60 MachineBasicBlock *&FBB,
61 SmallVectorImpl<MachineOperand> &Cond,
62 bool AllowModify) const;
64 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
66 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
67 MachineBasicBlock *FBB,
68 const SmallVectorImpl<MachineOperand> &Cond,
71 virtual bool analyzeCompare(const MachineInstr *MI,
72 unsigned &SrcReg, unsigned &SrcReg2,
73 int &Mask, int &Value) const;
75 virtual void copyPhysReg(MachineBasicBlock &MBB,
76 MachineBasicBlock::iterator I, DebugLoc DL,
77 unsigned DestReg, unsigned SrcReg,
80 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator MBBI,
82 unsigned SrcReg, bool isKill, int FrameIndex,
83 const TargetRegisterClass *RC,
84 const TargetRegisterInfo *TRI) const;
86 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
87 SmallVectorImpl<MachineOperand> &Addr,
88 const TargetRegisterClass *RC,
89 SmallVectorImpl<MachineInstr*> &NewMIs) const;
91 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator MBBI,
93 unsigned DestReg, int FrameIndex,
94 const TargetRegisterClass *RC,
95 const TargetRegisterInfo *TRI) const;
97 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
98 SmallVectorImpl<MachineOperand> &Addr,
99 const TargetRegisterClass *RC,
100 SmallVectorImpl<MachineInstr*> &NewMIs) const;
102 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
104 const SmallVectorImpl<unsigned> &Ops,
105 int FrameIndex) const;
107 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
109 const SmallVectorImpl<unsigned> &Ops,
110 MachineInstr* LoadMI) const {
114 unsigned createVR(MachineFunction* MF, MVT VT) const;
116 virtual bool isBranch(const MachineInstr *MI) const;
117 virtual bool isPredicable(MachineInstr *MI) const;
119 PredicateInstruction(MachineInstr *MI,
120 const SmallVectorImpl<MachineOperand> &Cond) const;
122 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
123 unsigned ExtraPredCycles,
124 const BranchProbability &Probability) const;
126 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
127 unsigned NumTCycles, unsigned ExtraTCycles,
128 MachineBasicBlock &FMBB,
129 unsigned NumFCycles, unsigned ExtraFCycles,
130 const BranchProbability &Probability) const;
132 virtual bool isPredicated(const MachineInstr *MI) const;
133 virtual bool isPredicated(unsigned Opcode) const;
134 virtual bool isPredicatedTrue(const MachineInstr *MI) const;
135 virtual bool isPredicatedTrue(unsigned Opcode) const;
136 virtual bool isPredicatedNew(const MachineInstr *MI) const;
137 virtual bool isPredicatedNew(unsigned Opcode) const;
138 virtual bool DefinesPredicate(MachineInstr *MI,
139 std::vector<MachineOperand> &Pred) const;
141 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
142 const SmallVectorImpl<MachineOperand> &Pred2) const;
145 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
148 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles,
149 const BranchProbability &Probability) const;
151 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
156 virtual DFAPacketizer*
157 CreateTargetScheduleState(const TargetMachine *TM,
158 const ScheduleDAG *DAG) const;
160 virtual bool isSchedulingBoundary(const MachineInstr *MI,
161 const MachineBasicBlock *MBB,
162 const MachineFunction &MF) const;
163 bool isValidOffset(const int Opcode, const int Offset) const;
164 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
165 bool isMemOp(const MachineInstr *MI) const;
166 bool isSpillPredRegOp(const MachineInstr *MI) const;
167 bool isU6_3Immediate(const int value) const;
168 bool isU6_2Immediate(const int value) const;
169 bool isU6_1Immediate(const int value) const;
170 bool isU6_0Immediate(const int value) const;
171 bool isS4_3Immediate(const int value) const;
172 bool isS4_2Immediate(const int value) const;
173 bool isS4_1Immediate(const int value) const;
174 bool isS4_0Immediate(const int value) const;
175 bool isS12_Immediate(const int value) const;
176 bool isU6_Immediate(const int value) const;
177 bool isS8_Immediate(const int value) const;
178 bool isS6_Immediate(const int value) const;
180 bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
181 bool isConditionalTransfer(const MachineInstr* MI) const;
182 bool isConditionalALU32 (const MachineInstr* MI) const;
183 bool isConditionalLoad (const MachineInstr* MI) const;
184 bool isConditionalStore(const MachineInstr* MI) const;
185 bool isNewValueInst(const MachineInstr* MI) const;
186 bool isNewValue(const MachineInstr* MI) const;
187 bool isDotNewInst(const MachineInstr* MI) const;
188 bool isDeallocRet(const MachineInstr *MI) const;
189 unsigned getInvertedPredicatedOpcode(const int Opc) const;
190 bool isExtendable(const MachineInstr* MI) const;
191 bool isExtended(const MachineInstr* MI) const;
192 bool isPostIncrement(const MachineInstr* MI) const;
193 bool isNewValueStore(const MachineInstr* MI) const;
194 bool isNewValueJump(const MachineInstr* MI) const;
195 bool isNewValueJumpCandidate(const MachineInstr *MI) const;
198 void immediateExtend(MachineInstr *MI) const;
199 bool isConstExtended(MachineInstr *MI) const;
200 int getDotNewPredJumpOp(MachineInstr *MI,
201 const MachineBranchProbabilityInfo *MBPI) const;
202 unsigned getAddrMode(const MachineInstr* MI) const;
203 bool isOperandExtended(const MachineInstr *MI,
204 unsigned short OperandNum) const;
205 unsigned short getCExtOpNum(const MachineInstr *MI) const;
206 int getMinValue(const MachineInstr *MI) const;
207 int getMaxValue(const MachineInstr *MI) const;
208 bool NonExtEquivalentExists (const MachineInstr *MI) const;
209 short getNonExtOpcode(const MachineInstr *MI) const;
210 bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
211 bool PredOpcodeHasNot(Opcode_t Opcode) const;
214 int getMatchingCondBranchOpcode(int Opc, bool sense) const;