1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
17 //===----------------------------------------------------------------------===//
18 // Classes used for relation maps.
19 //===----------------------------------------------------------------------===//
20 // PredRel - Filter class used to relate non-predicated instructions with their
23 // PredNewRel - Filter class used to relate predicated instructions with their
24 // predicate-new forms.
25 class PredNewRel: PredRel;
26 // ImmRegRel - Filter class used to relate instructions having reg-reg form
27 // with their reg-imm counterparts.
29 // NewValueRel - Filter class used to relate regular store instructions with
30 // their new-value store form.
31 class NewValueRel: PredNewRel;
32 // NewValueRel - Filter class used to relate load/store instructions having
33 // different addressing modes with each other.
34 class AddrModeRel: NewValueRel;
36 //===----------------------------------------------------------------------===//
37 // Hexagon Instruction Predicate Definitions.
38 //===----------------------------------------------------------------------===//
39 def HasV2T : Predicate<"Subtarget.hasV2TOps()">;
40 def HasV2TOnly : Predicate<"Subtarget.hasV2TOpsOnly()">;
41 def NoV2T : Predicate<"!Subtarget.hasV2TOps()">;
42 def HasV3T : Predicate<"Subtarget.hasV3TOps()">;
43 def HasV3TOnly : Predicate<"Subtarget.hasV3TOpsOnly()">;
44 def NoV3T : Predicate<"!Subtarget.hasV3TOps()">;
45 def HasV4T : Predicate<"Subtarget.hasV4TOps()">;
46 def NoV4T : Predicate<"!Subtarget.hasV4TOps()">;
47 def HasV5T : Predicate<"Subtarget.hasV5TOps()">;
48 def NoV5T : Predicate<"!Subtarget.hasV5TOps()">;
49 def UseMEMOP : Predicate<"Subtarget.useMemOps()">;
50 def IEEERndNearV5T : Predicate<"Subtarget.modeIEEERndNear()">;
53 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
54 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>;
55 def ADDRriS11_0 : ComplexPattern<i32, 2, "SelectADDRriS11_0", [frameindex], []>;
56 def ADDRriS11_1 : ComplexPattern<i32, 2, "SelectADDRriS11_1", [frameindex], []>;
57 def ADDRriS11_2 : ComplexPattern<i32, 2, "SelectADDRriS11_2", [frameindex], []>;
58 def ADDRriS11_3 : ComplexPattern<i32, 2, "SelectADDRriS11_3", [frameindex], []>;
59 def ADDRriU6_0 : ComplexPattern<i32, 2, "SelectADDRriU6_0", [frameindex], []>;
60 def ADDRriU6_1 : ComplexPattern<i32, 2, "SelectADDRriU6_1", [frameindex], []>;
61 def ADDRriU6_2 : ComplexPattern<i32, 2, "SelectADDRriU6_2", [frameindex], []>;
64 def MEMrr : Operand<i32> {
65 let PrintMethod = "printMEMrrOperand";
66 let MIOperandInfo = (ops IntRegs, IntRegs);
70 def MEMri : Operand<i32> {
71 let PrintMethod = "printMEMriOperand";
72 let MIOperandInfo = (ops IntRegs, IntRegs);
75 def MEMri_s11_2 : Operand<i32>,
76 ComplexPattern<i32, 2, "SelectMEMriS11_2", []> {
77 let PrintMethod = "printMEMriOperand";
78 let MIOperandInfo = (ops IntRegs, s11Imm);
81 def FrameIndex : Operand<i32> {
82 let PrintMethod = "printFrameIndexOperand";
83 let MIOperandInfo = (ops IntRegs, s11Imm);
86 let PrintMethod = "printGlobalOperand" in
87 def globaladdress : Operand<i32>;
89 let PrintMethod = "printJumpTable" in
90 def jumptablebase : Operand<i32>;
92 def brtarget : Operand<OtherVT>;
93 def calltarget : Operand<i32>;
95 def bblabel : Operand<i32>;
96 def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf , [], "BasicBlockSDNode">;
98 def symbolHi32 : Operand<i32> {
99 let PrintMethod = "printSymbolHi";
101 def symbolLo32 : Operand<i32> {
102 let PrintMethod = "printSymbolLo";
105 // Multi-class for logical operators.
106 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
107 def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
108 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
109 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),
110 (i32 IntRegs:$c)))]>;
111 def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
112 !strconcat("$dst = ", !strconcat(OpcStr, "(#$b, $c)")),
113 [(set (i32 IntRegs:$dst), (OpNode s10Imm:$b,
114 (i32 IntRegs:$c)))]>;
117 // Multi-class for compare ops.
118 let isCompare = 1 in {
119 multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
120 def rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
121 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
122 [(set (i1 PredRegs:$dst),
123 (OpNode (i64 DoubleRegs:$b), (i64 DoubleRegs:$c)))]>;
125 multiclass CMP32_rr<string OpcStr, PatFrag OpNode> {
126 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
127 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
128 [(set (i1 PredRegs:$dst),
129 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
132 multiclass CMP32_rr_ri_s10<string OpcStr, PatFrag OpNode> {
133 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
134 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
135 [(set (i1 PredRegs:$dst),
136 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
137 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Imm:$c),
138 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
139 [(set (i1 PredRegs:$dst),
140 (OpNode (i32 IntRegs:$b), s10ImmPred:$c))]>;
143 multiclass CMP32_rr_ri_u9<string OpcStr, PatFrag OpNode> {
144 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
145 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
146 [(set (i1 PredRegs:$dst),
147 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
148 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Imm:$c),
149 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
150 [(set (i1 PredRegs:$dst),
151 (OpNode (i32 IntRegs:$b), u9ImmPred:$c))]>;
154 multiclass CMP32_ri_u8<string OpcStr, PatFrag OpNode> {
155 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u8Imm:$c),
156 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
157 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
161 multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
162 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Imm:$c),
163 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
164 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
169 //===----------------------------------------------------------------------===//
170 // ALU32/ALU (Instructions with register-register form)
171 //===----------------------------------------------------------------------===//
172 multiclass ALU32_Pbase<string mnemonic, bit isNot,
175 let PNewValue = #!if(isPredNew, "new", "") in
176 def #NAME# : ALU32_rr<(outs IntRegs:$dst),
177 (ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
178 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
179 ") $dst = ")#mnemonic#"($src2, $src3)",
183 multiclass ALU32_Pred<string mnemonic, bit PredNot> {
184 let PredSense = #!if(PredNot, "false", "true") in {
185 defm _c#NAME# : ALU32_Pbase<mnemonic, PredNot, 0>;
187 defm _cdn#NAME# : ALU32_Pbase<mnemonic, PredNot, 1>;
191 let InputType = "reg" in
192 multiclass ALU32_base<string mnemonic, string CextOp, SDNode OpNode> {
193 let CextOpcode = CextOp, BaseOpcode = CextOp#_rr in {
194 let isPredicable = 1 in
195 def #NAME# : ALU32_rr<(outs IntRegs:$dst),
196 (ins IntRegs:$src1, IntRegs:$src2),
197 "$dst = "#mnemonic#"($src1, $src2)",
198 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
199 (i32 IntRegs:$src2)))]>;
201 let neverHasSideEffects = 1, isPredicated = 1 in {
202 defm Pt : ALU32_Pred<mnemonic, 0>;
203 defm NotPt : ALU32_Pred<mnemonic, 1>;
208 let isCommutable = 1 in {
209 defm ADD_rr : ALU32_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
210 defm AND_rr : ALU32_base<"and", "AND", and>, ImmRegRel, PredNewRel;
211 defm XOR_rr : ALU32_base<"xor", "XOR", xor>, ImmRegRel, PredNewRel;
212 defm OR_rr : ALU32_base<"or", "OR", or>, ImmRegRel, PredNewRel;
215 defm SUB_rr : ALU32_base<"sub", "SUB", sub>, ImmRegRel, PredNewRel;
217 //===----------------------------------------------------------------------===//
218 // ALU32/ALU (ADD with register-immediate form)
219 //===----------------------------------------------------------------------===//
220 multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
221 let PNewValue = #!if(isPredNew, "new", "") in
222 def #NAME# : ALU32_ri<(outs IntRegs:$dst),
223 (ins PredRegs:$src1, IntRegs:$src2, s8Imm: $src3),
224 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
225 ") $dst = ")#mnemonic#"($src2, #$src3)",
229 multiclass ALU32ri_Pred<string mnemonic, bit PredNot> {
230 let PredSense = #!if(PredNot, "false", "true") in {
231 defm _c#NAME# : ALU32ri_Pbase<mnemonic, PredNot, 0>;
233 defm _cdn#NAME# : ALU32ri_Pbase<mnemonic, PredNot, 1>;
237 let InputType = "imm" in
238 multiclass ALU32ri_base<string mnemonic, string CextOp, SDNode OpNode> {
239 let CextOpcode = CextOp, BaseOpcode = CextOp#_ri in {
240 let isPredicable = 1 in
241 def #NAME# : ALU32_ri<(outs IntRegs:$dst),
242 (ins IntRegs:$src1, s16Imm:$src2),
243 "$dst = "#mnemonic#"($src1, #$src2)",
244 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
245 (s16ImmPred:$src2)))]>;
247 let neverHasSideEffects = 1, isPredicated = 1 in {
248 defm Pt : ALU32ri_Pred<mnemonic, 0>;
249 defm NotPt : ALU32ri_Pred<mnemonic, 1>;
254 defm ADD_ri : ALU32ri_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
256 def OR_ri : ALU32_ri<(outs IntRegs:$dst),
257 (ins IntRegs:$src1, s10Imm:$src2),
258 "$dst = or($src1, #$src2)",
259 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
260 s10ImmPred:$src2))]>;
262 def NOT_rr : ALU32_rr<(outs IntRegs:$dst),
265 [(set (i32 IntRegs:$dst), (not (i32 IntRegs:$src1)))]>;
267 def AND_ri : ALU32_ri<(outs IntRegs:$dst),
268 (ins IntRegs:$src1, s10Imm:$src2),
269 "$dst = and($src1, #$src2)",
270 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
271 s10ImmPred:$src2))]>;
274 def NEG : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
276 [(set (i32 IntRegs:$dst), (ineg (i32 IntRegs:$src1)))]>;
278 let neverHasSideEffects = 1 in
279 def NOP : ALU32_rr<(outs), (ins),
283 // Rd32=sub(#s10,Rs32)
284 def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
285 (ins s10Imm:$src1, IntRegs:$src2),
286 "$dst = sub(#$src1, $src2)",
287 [(set IntRegs:$dst, (sub s10ImmPred:$src1, IntRegs:$src2))]>;
290 multiclass TFR_Pred<bit PredNot> {
291 let PredSense = #!if(PredNot, "false", "true") in {
292 def _c#NAME# : ALU32_rr<(outs IntRegs:$dst),
293 (ins PredRegs:$src1, IntRegs:$src2),
294 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
297 let PNewValue = "new" in
298 def _cdn#NAME# : ALU32_rr<(outs IntRegs:$dst),
299 (ins PredRegs:$src1, IntRegs:$src2),
300 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
305 let InputType = "reg", neverHasSideEffects = 1 in
306 multiclass TFR_base<string CextOp> {
307 let CextOpcode = CextOp, BaseOpcode = CextOp in {
308 let isPredicable = 1 in
309 def #NAME# : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
313 let isPredicated = 1 in {
314 defm Pt : TFR_Pred<0>;
315 defm NotPt : TFR_Pred<1>;
320 multiclass TFR64_Pred<bit PredNot> {
321 let PredSense = #!if(PredNot, "false", "true") in {
322 def _c#NAME# : ALU32_rr<(outs DoubleRegs:$dst),
323 (ins PredRegs:$src1, DoubleRegs:$src2),
324 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
327 let PNewValue = "new" in
328 def _cdn#NAME# : ALU32_rr<(outs DoubleRegs:$dst),
329 (ins PredRegs:$src1, DoubleRegs:$src2),
330 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
335 let InputType = "reg", neverHasSideEffects = 1 in
336 multiclass TFR64_base<string CextOp> {
337 let CextOpcode = CextOp, BaseOpcode = CextOp in {
338 let isPredicable = 1 in
339 def #NAME# : ALU32_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
343 let isPredicated = 1 in {
344 defm Pt : TFR64_Pred<0>;
345 defm NotPt : TFR64_Pred<1>;
351 multiclass TFRI_Pred<bit PredNot> {
352 let PredSense = #!if(PredNot, "false", "true") in {
353 def _c#NAME# : ALU32_ri<(outs IntRegs:$dst),
354 (ins PredRegs:$src1, s12Ext:$src2),
355 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = #$src2",
359 let PNewValue = "new" in
360 def _cdn#NAME# : ALU32_rr<(outs IntRegs:$dst),
361 (ins PredRegs:$src1, s12Ext:$src2),
362 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = #$src2",
367 let InputType = "imm", isExtendable = 1, isExtentSigned = 1 in
368 multiclass TFRI_base<string CextOp> {
369 let CextOpcode = CextOp, BaseOpcode = CextOp#I in {
370 let opExtendable = 1, opExtentBits = 16, isMoveImm = 1, isPredicable = 1,
371 isReMaterializable = 1 in
372 def #NAME# : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
374 [(set (i32 IntRegs:$dst), s16ExtPred:$src1)]>;
376 let opExtendable = 2, opExtentBits = 12, neverHasSideEffects = 1,
377 isPredicated = 1 in {
378 defm Pt : TFRI_Pred<0>;
379 defm NotPt : TFRI_Pred<1>;
384 defm TFRI : TFRI_base<"TFR">, ImmRegRel, PredNewRel;
385 defm TFR : TFR_base<"TFR">, ImmRegRel, PredNewRel;
386 defm TFR64 : TFR64_base<"TFR64">, ImmRegRel, PredNewRel;
388 // Transfer control register.
389 let neverHasSideEffects = 1 in
390 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
393 //===----------------------------------------------------------------------===//
395 //===----------------------------------------------------------------------===//
398 //===----------------------------------------------------------------------===//
400 //===----------------------------------------------------------------------===//
403 let isPredicable = 1, neverHasSideEffects = 1 in
404 def COMBINE_rr : ALU32_rr<(outs DoubleRegs:$dst),
405 (ins IntRegs:$src1, IntRegs:$src2),
406 "$dst = combine($src1, $src2)",
409 let neverHasSideEffects = 1 in
410 def COMBINE_ii : ALU32_ii<(outs DoubleRegs:$dst),
411 (ins s8Imm:$src1, s8Imm:$src2),
412 "$dst = combine(#$src1, #$src2)",
416 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
419 "$dst = vmux($src1, $src2, $src3)",
422 def MUX_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
423 IntRegs:$src2, IntRegs:$src3),
424 "$dst = mux($src1, $src2, $src3)",
425 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
427 (i32 IntRegs:$src3))))]>;
429 def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Imm:$src2,
431 "$dst = mux($src1, #$src2, $src3)",
432 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
434 (i32 IntRegs:$src3))))]>;
436 def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
438 "$dst = mux($src1, $src2, #$src3)",
439 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
441 s8ImmPred:$src3)))]>;
443 def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Imm:$src2,
445 "$dst = mux($src1, #$src2, #$src3)",
446 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
448 s8ImmPred:$src3)))]>;
451 let isPredicable = 1 in
452 def ASLH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
453 "$dst = aslh($src1)",
454 [(set (i32 IntRegs:$dst), (shl 16, (i32 IntRegs:$src1)))]>;
456 let isPredicable = 1 in
457 def ASRH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
458 "$dst = asrh($src1)",
459 [(set (i32 IntRegs:$dst), (sra 16, (i32 IntRegs:$src1)))]>;
462 let isPredicable = 1 in
463 def SXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
464 "$dst = sxtb($src1)",
465 [(set (i32 IntRegs:$dst), (sext_inreg (i32 IntRegs:$src1), i8))]>;
467 let isPredicable = 1 in
468 def SXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
469 "$dst = sxth($src1)",
470 [(set (i32 IntRegs:$dst), (sext_inreg (i32 IntRegs:$src1), i16))]>;
473 let isPredicable = 1, neverHasSideEffects = 1 in
474 def ZXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
475 "$dst = zxtb($src1)",
478 let isPredicable = 1, neverHasSideEffects = 1 in
479 def ZXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
480 "$dst = zxth($src1)",
482 //===----------------------------------------------------------------------===//
484 //===----------------------------------------------------------------------===//
487 //===----------------------------------------------------------------------===//
489 //===----------------------------------------------------------------------===//
491 // Conditional combine.
493 let neverHasSideEffects = 1, isPredicated = 1 in
494 def COMBINE_rr_cPt : ALU32_rr<(outs DoubleRegs:$dst),
495 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
496 "if ($src1) $dst = combine($src2, $src3)",
499 let neverHasSideEffects = 1, isPredicated = 1 in
500 def COMBINE_rr_cNotPt : ALU32_rr<(outs DoubleRegs:$dst),
501 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
502 "if (!$src1) $dst = combine($src2, $src3)",
505 let neverHasSideEffects = 1, isPredicated = 1 in
506 def COMBINE_rr_cdnPt : ALU32_rr<(outs DoubleRegs:$dst),
507 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
508 "if ($src1.new) $dst = combine($src2, $src3)",
511 let neverHasSideEffects = 1, isPredicated = 1 in
512 def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst),
513 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
514 "if (!$src1.new) $dst = combine($src2, $src3)",
518 defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", setugt>;
519 defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", setgt>;
520 defm CMPLT : CMP32_rr<"cmp.lt", setlt>;
521 defm CMPLTU : CMP32_rr<"cmp.ltu", setult>;
522 defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", seteq>;
523 defm CMPGE : CMP32_ri_s8<"cmp.ge", setge>;
524 defm CMPGEU : CMP32_ri_u8<"cmp.geu", setuge>;
525 //===----------------------------------------------------------------------===//
527 //===----------------------------------------------------------------------===//
530 //===----------------------------------------------------------------------===//
532 //===----------------------------------------------------------------------===//
534 def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
536 "$dst = add($src1, $src2)",
537 [(set (i64 DoubleRegs:$dst), (add (i64 DoubleRegs:$src1),
538 (i64 DoubleRegs:$src2)))]>;
543 defm CMPEHexagon4 : CMP64_rr<"cmp.eq", seteq>;
544 defm CMPGT64 : CMP64_rr<"cmp.gt", setgt>;
545 defm CMPGTU64 : CMP64_rr<"cmp.gtu", setugt>;
547 // Logical operations.
548 def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
550 "$dst = and($src1, $src2)",
551 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
552 (i64 DoubleRegs:$src2)))]>;
554 def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
556 "$dst = or($src1, $src2)",
557 [(set (i64 DoubleRegs:$dst), (or (i64 DoubleRegs:$src1),
558 (i64 DoubleRegs:$src2)))]>;
560 def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
562 "$dst = xor($src1, $src2)",
563 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
564 (i64 DoubleRegs:$src2)))]>;
567 def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
568 "$dst = max($src2, $src1)",
569 [(set (i32 IntRegs:$dst),
570 (i32 (select (i1 (setlt (i32 IntRegs:$src2),
571 (i32 IntRegs:$src1))),
572 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
574 def MAXUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
575 "$dst = maxu($src2, $src1)",
576 [(set (i32 IntRegs:$dst),
577 (i32 (select (i1 (setult (i32 IntRegs:$src2),
578 (i32 IntRegs:$src1))),
579 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
581 def MAXd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
583 "$dst = max($src2, $src1)",
584 [(set (i64 DoubleRegs:$dst),
585 (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
586 (i64 DoubleRegs:$src1))),
587 (i64 DoubleRegs:$src1),
588 (i64 DoubleRegs:$src2))))]>;
590 def MAXUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
592 "$dst = maxu($src2, $src1)",
593 [(set (i64 DoubleRegs:$dst),
594 (i64 (select (i1 (setult (i64 DoubleRegs:$src2),
595 (i64 DoubleRegs:$src1))),
596 (i64 DoubleRegs:$src1),
597 (i64 DoubleRegs:$src2))))]>;
600 def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
601 "$dst = min($src2, $src1)",
602 [(set (i32 IntRegs:$dst),
603 (i32 (select (i1 (setgt (i32 IntRegs:$src2),
604 (i32 IntRegs:$src1))),
605 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
607 def MINUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
608 "$dst = minu($src2, $src1)",
609 [(set (i32 IntRegs:$dst),
610 (i32 (select (i1 (setugt (i32 IntRegs:$src2),
611 (i32 IntRegs:$src1))),
612 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
614 def MINd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
616 "$dst = min($src2, $src1)",
617 [(set (i64 DoubleRegs:$dst),
618 (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
619 (i64 DoubleRegs:$src1))),
620 (i64 DoubleRegs:$src1),
621 (i64 DoubleRegs:$src2))))]>;
623 def MINUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
625 "$dst = minu($src2, $src1)",
626 [(set (i64 DoubleRegs:$dst),
627 (i64 (select (i1 (setugt (i64 DoubleRegs:$src2),
628 (i64 DoubleRegs:$src1))),
629 (i64 DoubleRegs:$src1),
630 (i64 DoubleRegs:$src2))))]>;
633 def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
635 "$dst = sub($src1, $src2)",
636 [(set (i64 DoubleRegs:$dst), (sub (i64 DoubleRegs:$src1),
637 (i64 DoubleRegs:$src2)))]>;
639 // Subtract halfword.
641 //===----------------------------------------------------------------------===//
643 //===----------------------------------------------------------------------===//
645 //===----------------------------------------------------------------------===//
647 //===----------------------------------------------------------------------===//
649 //===----------------------------------------------------------------------===//
651 //===----------------------------------------------------------------------===//
653 //===----------------------------------------------------------------------===//
655 //===----------------------------------------------------------------------===//
657 //===----------------------------------------------------------------------===//
659 //===----------------------------------------------------------------------===//
661 //===----------------------------------------------------------------------===//
663 //===----------------------------------------------------------------------===//
664 // Logical reductions on predicates.
666 // Looping instructions.
668 // Pipelined looping instructions.
670 // Logical operations on predicates.
671 def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
672 "$dst = and($src1, $src2)",
673 [(set (i1 PredRegs:$dst), (and (i1 PredRegs:$src1),
674 (i1 PredRegs:$src2)))]>;
676 let neverHasSideEffects = 1 in
677 def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
679 "$dst = and($src1, !$src2)",
682 def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
683 "$dst = any8($src1)",
686 def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
687 "$dst = all8($src1)",
690 def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
692 "$dst = vitpack($src1, $src2)",
695 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
698 "$dst = valignb($src1, $src2, $src3)",
701 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
704 "$dst = vspliceb($src1, $src2, $src3)",
707 def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
708 "$dst = mask($src1)",
711 def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
713 [(set (i1 PredRegs:$dst), (not (i1 PredRegs:$src1)))]>;
715 def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
716 "$dst = or($src1, $src2)",
717 [(set (i1 PredRegs:$dst), (or (i1 PredRegs:$src1),
718 (i1 PredRegs:$src2)))]>;
720 def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
721 "$dst = xor($src1, $src2)",
722 [(set (i1 PredRegs:$dst), (xor (i1 PredRegs:$src1),
723 (i1 PredRegs:$src2)))]>;
726 // User control register transfer.
727 //===----------------------------------------------------------------------===//
729 //===----------------------------------------------------------------------===//
732 //===----------------------------------------------------------------------===//
734 //===----------------------------------------------------------------------===//
736 let isBranch = 1, isTerminator=1, isBarrier = 1, isPredicable = 1 in {
737 def JMP : JInst< (outs),
738 (ins brtarget:$offset),
744 let isBranch = 1, isTerminator=1, Defs = [PC],
745 isPredicated = 1 in {
746 def JMP_c : JInst< (outs),
747 (ins PredRegs:$src, brtarget:$offset),
748 "if ($src) jump $offset",
749 [(brcond (i1 PredRegs:$src), bb:$offset)]>;
753 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
754 isPredicated = 1 in {
755 def JMP_cNot : JInst< (outs),
756 (ins PredRegs:$src, brtarget:$offset),
757 "if (!$src) jump $offset",
761 let isTerminator = 1, isBranch = 1, neverHasSideEffects = 1, Defs = [PC],
762 isPredicated = 1 in {
763 def BRCOND : JInst < (outs), (ins PredRegs:$pred, brtarget:$dst),
764 "if ($pred) jump $dst",
768 // Jump to address conditioned on new predicate.
770 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
771 isPredicated = 1 in {
772 def JMP_cdnPt : JInst< (outs),
773 (ins PredRegs:$src, brtarget:$offset),
774 "if ($src.new) jump:t $offset",
779 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
780 isPredicated = 1 in {
781 def JMP_cdnNotPt : JInst< (outs),
782 (ins PredRegs:$src, brtarget:$offset),
783 "if (!$src.new) jump:t $offset",
788 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
789 isPredicated = 1 in {
790 def JMP_cdnPnt : JInst< (outs),
791 (ins PredRegs:$src, brtarget:$offset),
792 "if ($src.new) jump:nt $offset",
797 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
798 isPredicated = 1 in {
799 def JMP_cdnNotPnt : JInst< (outs),
800 (ins PredRegs:$src, brtarget:$offset),
801 "if (!$src.new) jump:nt $offset",
804 //===----------------------------------------------------------------------===//
806 //===----------------------------------------------------------------------===//
808 //===----------------------------------------------------------------------===//
810 //===----------------------------------------------------------------------===//
811 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
812 [SDNPHasChain, SDNPOptInGlue]>;
814 // Jump to address from register.
815 let isPredicable =1, isReturn = 1, isTerminator = 1, isBarrier = 1,
816 Defs = [PC], Uses = [R31] in {
817 def JMPR: JRInst<(outs), (ins),
822 // Jump to address from register.
823 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
824 Defs = [PC], Uses = [R31] in {
825 def JMPR_cPt: JRInst<(outs), (ins PredRegs:$src1),
826 "if ($src1) jumpr r31",
830 // Jump to address from register.
831 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
832 Defs = [PC], Uses = [R31] in {
833 def JMPR_cNotPt: JRInst<(outs), (ins PredRegs:$src1),
834 "if (!$src1) jumpr r31",
838 //===----------------------------------------------------------------------===//
840 //===----------------------------------------------------------------------===//
842 //===----------------------------------------------------------------------===//
844 //===----------------------------------------------------------------------===//
846 // Load -- MEMri operand
847 multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
848 bit isNot, bit isPredNew> {
849 let PNewValue = #!if(isPredNew, "new", "") in
850 def #NAME# : LDInst2<(outs RC:$dst),
851 (ins PredRegs:$src1, MEMri:$addr),
852 #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
853 ") ")#"$dst = "#mnemonic#"($addr)",
857 multiclass LD_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
858 let PredSense = #!if(PredNot, "false", "true") in {
859 defm _c#NAME# : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
861 defm _cdn#NAME# : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
865 let isExtendable = 1, neverHasSideEffects = 1 in
866 multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
867 bits<5> ImmBits, bits<5> PredImmBits> {
869 let CextOpcode = CextOp, BaseOpcode = CextOp in {
870 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
872 def #NAME# : LDInst2<(outs RC:$dst), (ins MEMri:$addr),
873 "$dst = "#mnemonic#"($addr)",
876 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
877 isPredicated = 1 in {
878 defm Pt : LD_MEMri_Pred<mnemonic, RC, 0 >;
879 defm NotPt : LD_MEMri_Pred<mnemonic, RC, 1 >;
884 let addrMode = BaseImmOffset, isMEMri = "true" in {
885 defm LDrib: LD_MEMri < "memb", "LDrib", IntRegs, 11, 6>, AddrModeRel;
886 defm LDriub: LD_MEMri < "memub" , "LDriub", IntRegs, 11, 6>, AddrModeRel;
887 defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
888 defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel;
889 defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;
890 defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;
893 def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
894 (LDrib ADDRriS11_0:$addr) >;
896 def : Pat < (i32 (zextloadi8 ADDRriS11_0:$addr)),
897 (LDriub ADDRriS11_0:$addr) >;
899 def : Pat < (i32 (sextloadi16 ADDRriS11_1:$addr)),
900 (LDrih ADDRriS11_1:$addr) >;
902 def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)),
903 (LDriuh ADDRriS11_1:$addr) >;
905 def : Pat < (i32 (load ADDRriS11_2:$addr)),
906 (LDriw ADDRriS11_2:$addr) >;
908 def : Pat < (i64 (load ADDRriS11_3:$addr)),
909 (LDrid ADDRriS11_3:$addr) >;
912 // Load - Base with Immediate offset addressing mode
913 multiclass LD_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
914 bit isNot, bit isPredNew> {
915 let PNewValue = #!if(isPredNew, "new", "") in
916 def #NAME# : LDInst2<(outs RC:$dst),
917 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
918 #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
919 ") ")#"$dst = "#mnemonic#"($src2+#$src3)",
923 multiclass LD_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
925 let PredSense = #!if(PredNot, "false", "true") in {
926 defm _c#NAME# : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
928 defm _cdn#NAME# : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
932 let isExtendable = 1, neverHasSideEffects = 1 in
933 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
934 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
935 bits<5> PredImmBits> {
937 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
938 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
939 isPredicable = 1, AddedComplexity = 20 in
940 def #NAME# : LDInst2<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
941 "$dst = "#mnemonic#"($src1+#$offset)",
944 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
945 isPredicated = 1 in {
946 defm Pt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 0 >;
947 defm NotPt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 1 >;
952 let addrMode = BaseImmOffset in {
953 defm LDrib_indexed: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext,
955 defm LDriub_indexed: LD_Idxd <"memub" , "LDriub", IntRegs, s11_0Ext, u6_0Ext,
957 defm LDrih_indexed: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
959 defm LDriuh_indexed: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext,
961 defm LDriw_indexed: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
963 defm LDrid_indexed: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,
967 let AddedComplexity = 20 in {
968 def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
969 (LDrib_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
971 def : Pat < (i32 (zextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
972 (LDriub_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
974 def : Pat < (i32 (sextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
975 (LDrih_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
977 def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
978 (LDriuh_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
980 def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
981 (LDriw_indexed IntRegs:$src1, s11_2ExtPred:$offset) >;
983 def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
984 (LDrid_indexed IntRegs:$src1, s11_3ExtPred:$offset) >;
987 let neverHasSideEffects = 1 in
988 def LDrid_GP : LDInst2<(outs DoubleRegs:$dst),
989 (ins globaladdress:$global, u16Imm:$offset),
990 "$dst = memd(#$global+$offset)",
994 let neverHasSideEffects = 1 in
995 def LDd_GP : LDInst2<(outs DoubleRegs:$dst),
996 (ins globaladdress:$global),
997 "$dst = memd(#$global)",
1001 //===----------------------------------------------------------------------===//
1002 // Post increment load
1003 // Make sure that in post increment load, the first operand is always the post
1004 // increment operand.
1005 //===----------------------------------------------------------------------===//
1007 multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1008 bit isNot, bit isPredNew> {
1009 let PNewValue = #!if(isPredNew, "new", "") in
1010 def #NAME# : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1011 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1012 #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1013 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1018 multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,
1019 Operand ImmOp, bit PredNot> {
1020 let PredSense = #!if(PredNot, "false", "true") in {
1021 defm _c#NAME# : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1023 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1024 defm _cdn#NAME#_V4 : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1028 multiclass LD_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1031 let BaseOpcode = "POST_"#BaseOp in {
1032 let isPredicable = 1 in
1033 def #NAME# : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1034 (ins IntRegs:$src1, ImmOp:$offset),
1035 "$dst = "#mnemonic#"($src1++#$offset)",
1039 let isPredicated = 1 in {
1040 defm Pt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1041 defm NotPt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1046 let hasCtrlDep = 1, neverHasSideEffects = 1 in {
1047 defm POST_LDrib : LD_PostInc<"memb", "LDrib", IntRegs, s4_0Imm>,
1049 defm POST_LDriub : LD_PostInc<"memub", "LDriub", IntRegs, s4_0Imm>,
1051 defm POST_LDrih : LD_PostInc<"memh", "LDrih", IntRegs, s4_1Imm>,
1053 defm POST_LDriuh : LD_PostInc<"memuh", "LDriuh", IntRegs, s4_1Imm>,
1055 defm POST_LDriw : LD_PostInc<"memw", "LDriw", IntRegs, s4_2Imm>,
1057 defm POST_LDrid : LD_PostInc<"memd", "LDrid", DoubleRegs, s4_3Imm>,
1061 // Load byte any-extend.
1062 def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
1063 (i32 (LDrib ADDRriS11_0:$addr)) >;
1065 // Indexed load byte any-extend.
1066 let AddedComplexity = 20 in
1067 def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1068 (i32 (LDrib_indexed IntRegs:$src1, s11_0ImmPred:$offset)) >;
1070 let neverHasSideEffects = 1 in
1071 def LDrib_GP : LDInst2<(outs IntRegs:$dst),
1072 (ins globaladdress:$global, u16Imm:$offset),
1073 "$dst = memb(#$global+$offset)",
1077 let neverHasSideEffects = 1 in
1078 def LDb_GP : LDInst2<(outs IntRegs:$dst),
1079 (ins globaladdress:$global),
1080 "$dst = memb(#$global)",
1084 let neverHasSideEffects = 1 in
1085 def LDub_GP : LDInst2<(outs IntRegs:$dst),
1086 (ins globaladdress:$global),
1087 "$dst = memub(#$global)",
1091 def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
1092 (i32 (LDrih ADDRriS11_1:$addr))>;
1094 let AddedComplexity = 20 in
1095 def : Pat < (i32 (extloadi16 (add IntRegs:$src1, s11_1ImmPred:$offset))),
1096 (i32 (LDrih_indexed IntRegs:$src1, s11_1ImmPred:$offset)) >;
1098 let neverHasSideEffects = 1 in
1099 def LDrih_GP : LDInst2<(outs IntRegs:$dst),
1100 (ins globaladdress:$global, u16Imm:$offset),
1101 "$dst = memh(#$global+$offset)",
1105 let neverHasSideEffects = 1 in
1106 def LDh_GP : LDInst2<(outs IntRegs:$dst),
1107 (ins globaladdress:$global),
1108 "$dst = memh(#$global)",
1112 let neverHasSideEffects = 1 in
1113 def LDuh_GP : LDInst2<(outs IntRegs:$dst),
1114 (ins globaladdress:$global),
1115 "$dst = memuh(#$global)",
1119 def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
1120 (i32 (LDriub ADDRriS11_0:$addr))>;
1122 let AddedComplexity = 20 in
1123 def : Pat < (i32 (zextloadi1 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1124 (i32 (LDriub_indexed IntRegs:$src1, s11_0ImmPred:$offset))>;
1126 let neverHasSideEffects = 1 in
1127 def LDriub_GP : LDInst2<(outs IntRegs:$dst),
1128 (ins globaladdress:$global, u16Imm:$offset),
1129 "$dst = memub(#$global+$offset)",
1133 // Load unsigned halfword.
1134 let neverHasSideEffects = 1 in
1135 def LDriuh_GP : LDInst2<(outs IntRegs:$dst),
1136 (ins globaladdress:$global, u16Imm:$offset),
1137 "$dst = memuh(#$global+$offset)",
1142 let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1143 def LDriw_pred : LDInst<(outs PredRegs:$dst),
1145 "Error; should not emit",
1149 let neverHasSideEffects = 1 in
1150 def LDriw_GP : LDInst2<(outs IntRegs:$dst),
1151 (ins globaladdress:$global, u16Imm:$offset),
1152 "$dst = memw(#$global+$offset)",
1156 let neverHasSideEffects = 1 in
1157 def LDw_GP : LDInst2<(outs IntRegs:$dst),
1158 (ins globaladdress:$global),
1159 "$dst = memw(#$global)",
1163 // Deallocate stack frame.
1164 let Defs = [R29, R30, R31], Uses = [R29], neverHasSideEffects = 1 in {
1165 def DEALLOCFRAME : LDInst2<(outs), (ins i32imm:$amt1),
1170 // Load and unpack bytes to halfwords.
1171 //===----------------------------------------------------------------------===//
1173 //===----------------------------------------------------------------------===//
1175 //===----------------------------------------------------------------------===//
1177 //===----------------------------------------------------------------------===//
1178 //===----------------------------------------------------------------------===//
1180 //===----------------------------------------------------------------------===//
1182 //===----------------------------------------------------------------------===//
1184 //===----------------------------------------------------------------------===//
1185 //===----------------------------------------------------------------------===//
1187 //===----------------------------------------------------------------------===//
1189 //===----------------------------------------------------------------------===//
1191 //===----------------------------------------------------------------------===//
1192 // Multiply and use lower result.
1194 def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1195 "$dst =+ mpyi($src1, #$src2)",
1196 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1197 u8ImmPred:$src2))]>;
1200 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, n8Imm:$src2),
1201 "$dst =- mpyi($src1, #$src2)",
1202 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1203 n8ImmPred:$src2))]>;
1206 // s9 is NOT the same as m9 - but it works.. so far.
1207 // Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
1208 // depending on the value of m9. See Arch Spec.
1209 def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Imm:$src2),
1210 "$dst = mpyi($src1, #$src2)",
1211 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1212 s9ImmPred:$src2))]>;
1215 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1216 "$dst = mpyi($src1, $src2)",
1217 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1218 (i32 IntRegs:$src2)))]>;
1221 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
1222 (ins IntRegs:$src1, IntRegs:$src2, u8Imm:$src3),
1223 "$dst += mpyi($src2, #$src3)",
1224 [(set (i32 IntRegs:$dst),
1225 (add (mul (i32 IntRegs:$src2), u8ImmPred:$src3),
1226 (i32 IntRegs:$src1)))],
1230 def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
1231 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1232 "$dst += mpyi($src2, $src3)",
1233 [(set (i32 IntRegs:$dst),
1234 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1235 (i32 IntRegs:$src1)))],
1239 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
1240 (ins IntRegs:$src1, IntRegs:$src2, u8Imm:$src3),
1241 "$dst -= mpyi($src2, #$src3)",
1242 [(set (i32 IntRegs:$dst),
1243 (sub (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1244 u8ImmPred:$src3)))],
1247 // Multiply and use upper result.
1248 // Rd=mpy(Rs,Rt.H):<<1:rnd:sat
1249 // Rd=mpy(Rs,Rt.L):<<1:rnd:sat
1251 def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1252 "$dst = mpy($src1, $src2)",
1253 [(set (i32 IntRegs:$dst), (mulhs (i32 IntRegs:$src1),
1254 (i32 IntRegs:$src2)))]>;
1256 // Rd=mpy(Rs,Rt):rnd
1258 def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1259 "$dst = mpyu($src1, $src2)",
1260 [(set (i32 IntRegs:$dst), (mulhu (i32 IntRegs:$src1),
1261 (i32 IntRegs:$src2)))]>;
1263 // Multiply and use full result.
1265 def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1266 "$dst = mpyu($src1, $src2)",
1267 [(set (i64 DoubleRegs:$dst),
1268 (mul (i64 (anyext (i32 IntRegs:$src1))),
1269 (i64 (anyext (i32 IntRegs:$src2)))))]>;
1272 def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1273 "$dst = mpy($src1, $src2)",
1274 [(set (i64 DoubleRegs:$dst),
1275 (mul (i64 (sext (i32 IntRegs:$src1))),
1276 (i64 (sext (i32 IntRegs:$src2)))))]>;
1278 // Multiply and accumulate, use full result.
1279 // Rxx[+-]=mpy(Rs,Rt)
1281 def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
1282 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1283 "$dst += mpy($src2, $src3)",
1284 [(set (i64 DoubleRegs:$dst),
1285 (add (mul (i64 (sext (i32 IntRegs:$src2))),
1286 (i64 (sext (i32 IntRegs:$src3)))),
1287 (i64 DoubleRegs:$src1)))],
1291 def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
1292 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1293 "$dst -= mpy($src2, $src3)",
1294 [(set (i64 DoubleRegs:$dst),
1295 (sub (i64 DoubleRegs:$src1),
1296 (mul (i64 (sext (i32 IntRegs:$src2))),
1297 (i64 (sext (i32 IntRegs:$src3))))))],
1300 // Rxx[+-]=mpyu(Rs,Rt)
1302 def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1303 IntRegs:$src2, IntRegs:$src3),
1304 "$dst += mpyu($src2, $src3)",
1305 [(set (i64 DoubleRegs:$dst),
1306 (add (mul (i64 (anyext (i32 IntRegs:$src2))),
1307 (i64 (anyext (i32 IntRegs:$src3)))),
1308 (i64 DoubleRegs:$src1)))], "$src1 = $dst">;
1311 def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
1312 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1313 "$dst += mpyu($src2, $src3)",
1314 [(set (i64 DoubleRegs:$dst),
1315 (sub (i64 DoubleRegs:$src1),
1316 (mul (i64 (anyext (i32 IntRegs:$src2))),
1317 (i64 (anyext (i32 IntRegs:$src3))))))],
1321 def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1322 IntRegs:$src2, IntRegs:$src3),
1323 "$dst += add($src2, $src3)",
1324 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1325 (i32 IntRegs:$src3)),
1326 (i32 IntRegs:$src1)))],
1329 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1330 IntRegs:$src2, s8Imm:$src3),
1331 "$dst += add($src2, #$src3)",
1332 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1334 (i32 IntRegs:$src1)))],
1337 def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1338 IntRegs:$src2, IntRegs:$src3),
1339 "$dst -= add($src2, $src3)",
1340 [(set (i32 IntRegs:$dst),
1341 (sub (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1342 (i32 IntRegs:$src3))))],
1345 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1346 IntRegs:$src2, s8Imm:$src3),
1347 "$dst -= add($src2, #$src3)",
1348 [(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
1349 (add (i32 IntRegs:$src2),
1350 s8ImmPred:$src3)))],
1353 //===----------------------------------------------------------------------===//
1355 //===----------------------------------------------------------------------===//
1357 //===----------------------------------------------------------------------===//
1359 //===----------------------------------------------------------------------===//
1360 //===----------------------------------------------------------------------===//
1362 //===----------------------------------------------------------------------===//
1364 //===----------------------------------------------------------------------===//
1366 //===----------------------------------------------------------------------===//
1367 //===----------------------------------------------------------------------===//
1369 //===----------------------------------------------------------------------===//
1371 //===----------------------------------------------------------------------===//
1373 //===----------------------------------------------------------------------===//
1374 //===----------------------------------------------------------------------===//
1376 //===----------------------------------------------------------------------===//
1378 //===----------------------------------------------------------------------===//
1380 //===----------------------------------------------------------------------===//
1382 /// Assumptions::: ****** DO NOT IGNORE ********
1383 /// 1. Make sure that in post increment store, the zero'th operand is always the
1384 /// post increment operand.
1385 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
1388 // Store doubleword.
1390 let neverHasSideEffects = 1 in
1391 def STrid_GP : STInst2<(outs),
1392 (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),
1393 "memd(#$global+$offset) = $src",
1397 let neverHasSideEffects = 1 in
1398 def STd_GP : STInst2<(outs),
1399 (ins globaladdress:$global, DoubleRegs:$src),
1400 "memd(#$global) = $src",
1404 let hasCtrlDep = 1, isPredicable = 1 in
1405 def POST_STdri : STInstPI<(outs IntRegs:$dst),
1406 (ins DoubleRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1407 "memd($src2++#$offset) = $src1",
1409 (post_store (i64 DoubleRegs:$src1), (i32 IntRegs:$src2),
1410 s4_3ImmPred:$offset))],
1413 // if ([!]Pv) memd(Rx++#s4:3)=Rtt
1414 // if (Pv) memd(Rx++#s4:3)=Rtt
1415 let AddedComplexity = 10, neverHasSideEffects = 1,
1417 def POST_STdri_cPt : STInst2PI<(outs IntRegs:$dst),
1418 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1420 "if ($src1) memd($src3++#$offset) = $src2",
1424 // if (!Pv) memd(Rx++#s4:3)=Rtt
1425 let AddedComplexity = 10, neverHasSideEffects = 1, isPredicated = 1,
1427 def POST_STdri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1428 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1430 "if (!$src1) memd($src3++#$offset) = $src2",
1434 //===----------------------------------------------------------------------===//
1435 // multiclass for the store instructions with MEMri operand.
1436 //===----------------------------------------------------------------------===//
1437 multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot,
1439 let PNewValue = #!if(isPredNew, "new", "") in
1440 def #NAME# : STInst2<(outs),
1441 (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
1442 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1443 ") ")#mnemonic#"($addr) = $src2",
1447 multiclass ST_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1448 let PredSense = #!if(PredNot, "false", "true") in {
1449 defm _c#NAME# : ST_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
1452 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1453 defm _cdn#NAME#_V4 : ST_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
1457 let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1458 multiclass ST_MEMri<string mnemonic, string CextOp, RegisterClass RC,
1459 bits<5> ImmBits, bits<5> PredImmBits> {
1461 let CextOpcode = CextOp, BaseOpcode = CextOp in {
1462 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1464 def #NAME# : STInst2<(outs),
1465 (ins MEMri:$addr, RC:$src),
1466 #mnemonic#"($addr) = $src",
1469 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
1470 isPredicated = 1 in {
1471 defm Pt : ST_MEMri_Pred<mnemonic, RC, 0>;
1472 defm NotPt : ST_MEMri_Pred<mnemonic, RC, 1>;
1477 let addrMode = BaseImmOffset, isMEMri = "true" in {
1478 defm STrib: ST_MEMri < "memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
1479 defm STrih: ST_MEMri < "memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
1480 defm STriw: ST_MEMri < "memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
1482 let isNVStorable = 0 in
1483 defm STrid: ST_MEMri < "memd", "STrid", DoubleRegs, 14, 9>, AddrModeRel;
1486 def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
1487 (STrib ADDRriS11_0:$addr, (i32 IntRegs:$src1))>;
1489 def : Pat<(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr),
1490 (STrih ADDRriS11_1:$addr, (i32 IntRegs:$src1))>;
1492 def : Pat<(store (i32 IntRegs:$src1), ADDRriS11_2:$addr),
1493 (STriw ADDRriS11_2:$addr, (i32 IntRegs:$src1))>;
1495 def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
1496 (STrid ADDRriS11_3:$addr, (i64 DoubleRegs:$src1))>;
1499 //===----------------------------------------------------------------------===//
1500 // multiclass for the store instructions with base+immediate offset
1502 //===----------------------------------------------------------------------===//
1503 multiclass ST_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
1504 bit isNot, bit isPredNew> {
1505 let PNewValue = #!if(isPredNew, "new", "") in
1506 def #NAME# : STInst2<(outs),
1507 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
1508 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1509 ") ")#mnemonic#"($src2+#$src3) = $src4",
1513 multiclass ST_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
1515 let PredSense = #!if(PredNot, "false", "true"), isPredicated = 1 in {
1516 defm _c#NAME# : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
1519 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1520 defm _cdn#NAME#_V4 : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
1524 let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1525 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1526 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
1527 bits<5> PredImmBits> {
1529 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1530 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1532 def #NAME# : STInst2<(outs),
1533 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1534 #mnemonic#"($src1+#$src2) = $src3",
1537 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits in {
1538 defm Pt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 0>;
1539 defm NotPt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 1>;
1544 let addrMode = BaseImmOffset, InputType = "reg" in {
1545 defm STrib_indexed: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext,
1546 u6_0Ext, 11, 6>, AddrModeRel, ImmRegRel;
1547 defm STrih_indexed: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext,
1548 u6_1Ext, 12, 7>, AddrModeRel, ImmRegRel;
1549 defm STriw_indexed: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext,
1550 u6_2Ext, 13, 8>, AddrModeRel, ImmRegRel;
1551 let isNVStorable = 0 in
1552 defm STrid_indexed: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
1553 u6_3Ext, 14, 9>, AddrModeRel;
1556 let AddedComplexity = 10 in {
1557 def : Pat<(truncstorei8 (i32 IntRegs:$src1), (add IntRegs:$src2,
1558 s11_0ExtPred:$offset)),
1559 (STrib_indexed IntRegs:$src2, s11_0ImmPred:$offset,
1560 (i32 IntRegs:$src1))>;
1562 def : Pat<(truncstorei16 (i32 IntRegs:$src1), (add IntRegs:$src2,
1563 s11_1ExtPred:$offset)),
1564 (STrih_indexed IntRegs:$src2, s11_1ImmPred:$offset,
1565 (i32 IntRegs:$src1))>;
1567 def : Pat<(store (i32 IntRegs:$src1), (add IntRegs:$src2,
1568 s11_2ExtPred:$offset)),
1569 (STriw_indexed IntRegs:$src2, s11_2ImmPred:$offset,
1570 (i32 IntRegs:$src1))>;
1572 def : Pat<(store (i64 DoubleRegs:$src1), (add IntRegs:$src2,
1573 s11_3ExtPred:$offset)),
1574 (STrid_indexed IntRegs:$src2, s11_3ImmPred:$offset,
1575 (i64 DoubleRegs:$src1))>;
1578 // memb(gp+#u16:0)=Rt
1579 let neverHasSideEffects = 1 in
1580 def STrib_GP : STInst2<(outs),
1581 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1582 "memb(#$global+$offset) = $src",
1587 let neverHasSideEffects = 1 in
1588 def STb_GP : STInst2<(outs),
1589 (ins globaladdress:$global, IntRegs:$src),
1590 "memb(#$global) = $src",
1594 // memb(Rx++#s4:0)=Rt
1595 let hasCtrlDep = 1, isPredicable = 1 in
1596 def POST_STbri : STInstPI<(outs IntRegs:$dst), (ins IntRegs:$src1,
1599 "memb($src2++#$offset) = $src1",
1601 (post_truncsti8 (i32 IntRegs:$src1), (i32 IntRegs:$src2),
1602 s4_0ImmPred:$offset))],
1605 // if ([!]Pv) memb(Rx++#s4:0)=Rt
1606 // if (Pv) memb(Rx++#s4:0)=Rt
1607 let hasCtrlDep = 1, isPredicated = 1 in
1608 def POST_STbri_cPt : STInst2PI<(outs IntRegs:$dst),
1609 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1610 "if ($src1) memb($src3++#$offset) = $src2",
1613 // if (!Pv) memb(Rx++#s4:0)=Rt
1614 let hasCtrlDep = 1, isPredicated = 1 in
1615 def POST_STbri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1616 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1617 "if (!$src1) memb($src3++#$offset) = $src2",
1620 let neverHasSideEffects = 1 in
1621 def STrih_GP : STInst2<(outs),
1622 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1623 "memh(#$global+$offset) = $src",
1627 let neverHasSideEffects = 1 in
1628 def STh_GP : STInst2<(outs),
1629 (ins globaladdress:$global, IntRegs:$src),
1630 "memh(#$global) = $src",
1634 // memh(Rx++#s4:1)=Rt.H
1635 // memh(Rx++#s4:1)=Rt
1636 let hasCtrlDep = 1, isPredicable = 1 in
1637 def POST_SThri : STInstPI<(outs IntRegs:$dst),
1638 (ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1639 "memh($src2++#$offset) = $src1",
1641 (post_truncsti16 (i32 IntRegs:$src1), (i32 IntRegs:$src2),
1642 s4_1ImmPred:$offset))],
1645 // if ([!]Pv) memh(Rx++#s4:1)=Rt
1646 // if (Pv) memh(Rx++#s4:1)=Rt
1647 let hasCtrlDep = 1, isPredicated = 1 in
1648 def POST_SThri_cPt : STInst2PI<(outs IntRegs:$dst),
1649 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1650 "if ($src1) memh($src3++#$offset) = $src2",
1653 // if (!Pv) memh(Rx++#s4:1)=Rt
1654 let hasCtrlDep = 1, isPredicated = 1 in
1655 def POST_SThri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1656 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1657 "if (!$src1) memh($src3++#$offset) = $src2",
1663 let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1664 def STriw_pred : STInst2<(outs),
1665 (ins MEMri:$addr, PredRegs:$src1),
1666 "Error; should not emit",
1669 let neverHasSideEffects = 1 in
1670 def STriw_GP : STInst2<(outs),
1671 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1672 "memw(#$global+$offset) = $src",
1676 let neverHasSideEffects = 1 in
1677 def STw_GP : STInst2<(outs),
1678 (ins globaladdress:$global, IntRegs:$src),
1679 "memw(#$global) = $src",
1683 let hasCtrlDep = 1, isPredicable = 1 in
1684 def POST_STwri : STInstPI<(outs IntRegs:$dst),
1685 (ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1686 "memw($src2++#$offset) = $src1",
1688 (post_store (i32 IntRegs:$src1), (i32 IntRegs:$src2),
1689 s4_2ImmPred:$offset))],
1692 // if ([!]Pv) memw(Rx++#s4:2)=Rt
1693 // if (Pv) memw(Rx++#s4:2)=Rt
1694 let hasCtrlDep = 1, isPredicated = 1 in
1695 def POST_STwri_cPt : STInst2PI<(outs IntRegs:$dst),
1696 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
1697 "if ($src1) memw($src3++#$offset) = $src2",
1700 // if (!Pv) memw(Rx++#s4:2)=Rt
1701 let hasCtrlDep = 1, isPredicated = 1 in
1702 def POST_STwri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1703 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
1704 "if (!$src1) memw($src3++#$offset) = $src2",
1709 // Allocate stack frame.
1710 let Defs = [R29, R30], Uses = [R31, R30], neverHasSideEffects = 1 in {
1711 def ALLOCFRAME : STInst2<(outs),
1713 "allocframe(#$amt)",
1716 //===----------------------------------------------------------------------===//
1718 //===----------------------------------------------------------------------===//
1720 //===----------------------------------------------------------------------===//
1722 //===----------------------------------------------------------------------===//
1724 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
1725 "$dst = not($src1)",
1726 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
1729 // Sign extend word to doubleword.
1730 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
1731 "$dst = sxtw($src1)",
1732 [(set (i64 DoubleRegs:$dst), (sext (i32 IntRegs:$src1)))]>;
1733 //===----------------------------------------------------------------------===//
1735 //===----------------------------------------------------------------------===//
1737 //===----------------------------------------------------------------------===//
1739 //===----------------------------------------------------------------------===//
1741 def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1742 "$dst = clrbit($src1, #$src2)",
1743 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
1745 (shl 1, u5ImmPred:$src2))))]>;
1747 def CLRBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1748 "$dst = clrbit($src1, #$src2)",
1751 // Map from r0 = and(r1, 2147483647) to r0 = clrbit(r1, #31).
1752 def : Pat <(and (i32 IntRegs:$src1), 2147483647),
1753 (CLRBIT_31 (i32 IntRegs:$src1), 31)>;
1756 def SETBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1757 "$dst = setbit($src1, #$src2)",
1758 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
1759 (shl 1, u5ImmPred:$src2)))]>;
1761 // Map from r0 = or(r1, -2147483648) to r0 = setbit(r1, #31).
1762 def SETBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1763 "$dst = setbit($src1, #$src2)",
1766 def : Pat <(or (i32 IntRegs:$src1), -2147483648),
1767 (SETBIT_31 (i32 IntRegs:$src1), 31)>;
1770 def TOGBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1771 "$dst = setbit($src1, #$src2)",
1772 [(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
1773 (shl 1, u5ImmPred:$src2)))]>;
1775 // Map from r0 = xor(r1, -2147483648) to r0 = togglebit(r1, #31).
1776 def TOGBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1777 "$dst = togglebit($src1, #$src2)",
1780 def : Pat <(xor (i32 IntRegs:$src1), -2147483648),
1781 (TOGBIT_31 (i32 IntRegs:$src1), 31)>;
1783 // Predicate transfer.
1784 let neverHasSideEffects = 1 in
1785 def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
1786 "$dst = $src1 /* Should almost never emit this. */",
1789 def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1),
1790 "$dst = $src1 /* Should almost never emit this. */",
1791 [(set (i1 PredRegs:$dst), (trunc (i32 IntRegs:$src1)))]>;
1792 //===----------------------------------------------------------------------===//
1794 //===----------------------------------------------------------------------===//
1796 //===----------------------------------------------------------------------===//
1798 //===----------------------------------------------------------------------===//
1799 // Shift by immediate.
1800 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1801 "$dst = asr($src1, #$src2)",
1802 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1803 u5ImmPred:$src2))]>;
1805 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1806 "$dst = asr($src1, #$src2)",
1807 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1808 u6ImmPred:$src2))]>;
1810 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1811 "$dst = asl($src1, #$src2)",
1812 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1813 u5ImmPred:$src2))]>;
1815 def ASLd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1816 "$dst = asl($src1, #$src2)",
1817 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1818 u6ImmPred:$src2))]>;
1820 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1821 "$dst = lsr($src1, #$src2)",
1822 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1823 u5ImmPred:$src2))]>;
1825 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1826 "$dst = lsr($src1, #$src2)",
1827 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1828 u6ImmPred:$src2))]>;
1830 // Shift by immediate and add.
1831 let AddedComplexity = 100 in
1832 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
1834 "$dst = addasl($src1, $src2, #$src3)",
1835 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
1836 (shl (i32 IntRegs:$src2),
1837 u3ImmPred:$src3)))]>;
1839 // Shift by register.
1840 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1841 "$dst = asl($src1, $src2)",
1842 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1843 (i32 IntRegs:$src2)))]>;
1845 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1846 "$dst = asr($src1, $src2)",
1847 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1848 (i32 IntRegs:$src2)))]>;
1850 def LSL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1851 "$dst = lsl($src1, $src2)",
1852 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1853 (i32 IntRegs:$src2)))]>;
1855 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1856 "$dst = lsr($src1, $src2)",
1857 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1858 (i32 IntRegs:$src2)))]>;
1860 def ASLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1861 "$dst = asl($src1, $src2)",
1862 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1863 (i32 IntRegs:$src2)))]>;
1865 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1866 "$dst = lsl($src1, $src2)",
1867 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1868 (i32 IntRegs:$src2)))]>;
1870 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1872 "$dst = asr($src1, $src2)",
1873 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1874 (i32 IntRegs:$src2)))]>;
1876 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1878 "$dst = lsr($src1, $src2)",
1879 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1880 (i32 IntRegs:$src2)))]>;
1882 //===----------------------------------------------------------------------===//
1884 //===----------------------------------------------------------------------===//
1886 //===----------------------------------------------------------------------===//
1888 //===----------------------------------------------------------------------===//
1889 //===----------------------------------------------------------------------===//
1891 //===----------------------------------------------------------------------===//
1893 //===----------------------------------------------------------------------===//
1895 //===----------------------------------------------------------------------===//
1896 //===----------------------------------------------------------------------===//
1898 //===----------------------------------------------------------------------===//
1900 //===----------------------------------------------------------------------===//
1902 //===----------------------------------------------------------------------===//
1904 //===----------------------------------------------------------------------===//
1906 //===----------------------------------------------------------------------===//
1907 def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
1908 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
1911 let hasSideEffects = 1, isHexagonSolo = 1 in
1912 def BARRIER : SYSInst<(outs), (ins),
1914 [(HexagonBARRIER)]>;
1916 //===----------------------------------------------------------------------===//
1918 //===----------------------------------------------------------------------===//
1920 // TFRI64 - assembly mapped.
1921 let isReMaterializable = 1 in
1922 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
1924 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
1926 // Pseudo instruction to encode a set of conditional transfers.
1927 // This instruction is used instead of a mux and trades-off codesize
1928 // for performance. We conduct this transformation optimistically in
1929 // the hope that these instructions get promoted to dot-new transfers.
1930 let AddedComplexity = 100, isPredicated = 1 in
1931 def TFR_condset_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
1934 "Error; should not emit",
1935 [(set (i32 IntRegs:$dst),
1936 (i32 (select (i1 PredRegs:$src1),
1937 (i32 IntRegs:$src2),
1938 (i32 IntRegs:$src3))))]>;
1939 let AddedComplexity = 100, isPredicated = 1 in
1940 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
1941 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
1942 "Error; should not emit",
1943 [(set (i32 IntRegs:$dst),
1944 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
1945 s12ImmPred:$src3)))]>;
1947 let AddedComplexity = 100, isPredicated = 1 in
1948 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
1949 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
1950 "Error; should not emit",
1951 [(set (i32 IntRegs:$dst),
1952 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
1953 (i32 IntRegs:$src3))))]>;
1955 let AddedComplexity = 100, isPredicated = 1 in
1956 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
1957 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
1958 "Error; should not emit",
1959 [(set (i32 IntRegs:$dst),
1960 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
1961 s12ImmPred:$src3)))]>;
1963 // Generate frameindex addresses.
1964 let isReMaterializable = 1 in
1965 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
1966 "$dst = add($src1)",
1967 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
1972 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
1973 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
1974 "loop0($offset, #$src2)",
1978 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
1979 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
1980 "loop0($offset, $src2)",
1984 let isBranch = 1, isTerminator = 1, neverHasSideEffects = 1,
1985 Defs = [PC, LC0], Uses = [SA0, LC0] in {
1986 def ENDLOOP0 : Marker<(outs), (ins brtarget:$offset),
1991 // Support for generating global address.
1992 // Taken from X86InstrInfo.td.
1993 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [
1997 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
1998 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
2000 // HI/LO Instructions
2001 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2002 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
2003 "$dst.l = #LO($global)",
2006 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2007 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
2008 "$dst.h = #HI($global)",
2011 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2012 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2013 "$dst.l = #LO($imm_value)",
2017 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2018 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2019 "$dst.h = #HI($imm_value)",
2022 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2023 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2024 "$dst.l = #LO($jt)",
2027 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2028 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2029 "$dst.h = #HI($jt)",
2033 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2034 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2035 "$dst.l = #LO($label)",
2038 let isReMaterializable = 1, isMoveImm = 1 , neverHasSideEffects = 1 in
2039 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2040 "$dst.h = #HI($label)",
2043 // This pattern is incorrect. When we add small data, we should change
2044 // this pattern to use memw(#foo).
2045 // This is for sdata.
2046 let isMoveImm = 1 in
2047 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2048 "$dst = CONST32(#$global)",
2049 [(set (i32 IntRegs:$dst),
2050 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
2052 // This is for non-sdata.
2053 let isReMaterializable = 1, isMoveImm = 1 in
2054 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2055 "$dst = CONST32(#$global)",
2056 [(set (i32 IntRegs:$dst),
2057 (HexagonCONST32 tglobaladdr:$global))]>;
2059 let isReMaterializable = 1, isMoveImm = 1 in
2060 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2061 "$dst = CONST32(#$jt)",
2062 [(set (i32 IntRegs:$dst),
2063 (HexagonCONST32 tjumptable:$jt))]>;
2065 let isReMaterializable = 1, isMoveImm = 1 in
2066 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2067 "$dst = CONST32(#$global)",
2068 [(set (i32 IntRegs:$dst),
2069 (HexagonCONST32_GP tglobaladdr:$global))]>;
2071 let isReMaterializable = 1, isMoveImm = 1 in
2072 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
2073 "$dst = CONST32(#$global)",
2074 [(set (i32 IntRegs:$dst), imm:$global) ]>;
2076 let isReMaterializable = 1, isMoveImm = 1 in
2077 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
2078 "$dst = CONST32($label)",
2079 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
2081 let isReMaterializable = 1, isMoveImm = 1 in
2082 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
2083 "$dst = CONST64(#$global)",
2084 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
2086 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
2087 "$dst = xor($dst, $dst)",
2088 [(set (i1 PredRegs:$dst), 0)]>;
2090 def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2091 "$dst = mpy($src1, $src2)",
2092 [(set (i32 IntRegs:$dst),
2093 (trunc (i64 (srl (i64 (mul (i64 (sext (i32 IntRegs:$src1))),
2094 (i64 (sext (i32 IntRegs:$src2))))),
2097 // Pseudo instructions.
2098 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
2100 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
2101 SDTCisVT<1, i32> ]>;
2103 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
2104 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2106 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
2107 [SDNPHasChain, SDNPOutGlue]>;
2109 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2111 def call : SDNode<"HexagonISD::CALL", SDT_SPCall,
2112 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
2114 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
2115 // Optional Flag and Variable Arguments.
2116 // Its 1 Operand has pointer type.
2117 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
2118 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
2120 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
2121 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
2122 "Should never be emitted",
2123 [(callseq_start timm:$amt)]>;
2126 let Defs = [R29, R30, R31], Uses = [R29] in {
2127 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2128 "Should never be emitted",
2129 [(callseq_end timm:$amt1, timm:$amt2)]>;
2132 let isCall = 1, neverHasSideEffects = 1,
2133 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2134 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2135 def CALL : JInst<(outs), (ins calltarget:$dst),
2139 // Call subroutine from register.
2140 let isCall = 1, neverHasSideEffects = 1,
2141 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2142 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2143 def CALLR : JRInst<(outs), (ins IntRegs:$dst),
2149 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2150 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst),
2151 "jump $dst // TAILCALL", []>;
2153 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2154 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst),
2155 "jump $dst // TAILCALL", []>;
2158 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2159 def TCRETURNR : JInst<(outs), (ins IntRegs:$dst),
2160 "jumpr $dst // TAILCALL", []>;
2162 // Map call instruction.
2163 def : Pat<(call (i32 IntRegs:$dst)),
2164 (CALLR (i32 IntRegs:$dst))>, Requires<[HasV2TOnly]>;
2165 def : Pat<(call tglobaladdr:$dst),
2166 (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
2167 def : Pat<(call texternalsym:$dst),
2168 (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>;
2170 def : Pat<(HexagonTCRet tglobaladdr:$dst),
2171 (TCRETURNtg tglobaladdr:$dst)>;
2172 def : Pat<(HexagonTCRet texternalsym:$dst),
2173 (TCRETURNtext texternalsym:$dst)>;
2174 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
2175 (TCRETURNR (i32 IntRegs:$dst))>;
2177 // Atomic load and store support
2178 // 8 bit atomic load
2179 def : Pat<(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
2180 (i32 (LDub_GP tglobaladdr:$global))>,
2183 def : Pat<(atomic_load_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2184 u16ImmPred:$offset)),
2185 (i32 (LDriub_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2188 def : Pat<(atomic_load_8 ADDRriS11_0:$src1),
2189 (i32 (LDriub ADDRriS11_0:$src1))>;
2191 def : Pat<(atomic_load_8 (add (i32 IntRegs:$src1), s11_0ImmPred:$offset)),
2192 (i32 (LDriub_indexed (i32 IntRegs:$src1), s11_0ImmPred:$offset))>;
2196 // 16 bit atomic load
2197 def : Pat<(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
2198 (i32 (LDuh_GP tglobaladdr:$global))>,
2201 def : Pat<(atomic_load_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2202 u16ImmPred:$offset)),
2203 (i32 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2206 def : Pat<(atomic_load_16 ADDRriS11_1:$src1),
2207 (i32 (LDriuh ADDRriS11_1:$src1))>;
2209 def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)),
2210 (i32 (LDriuh_indexed (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
2214 // 32 bit atomic load
2215 def : Pat<(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
2216 (i32 (LDw_GP tglobaladdr:$global))>,
2219 def : Pat<(atomic_load_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2220 u16ImmPred:$offset)),
2221 (i32 (LDriw_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2224 def : Pat<(atomic_load_32 ADDRriS11_2:$src1),
2225 (i32 (LDriw ADDRriS11_2:$src1))>;
2227 def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),
2228 (i32 (LDriw_indexed (i32 IntRegs:$src1), s11_2ImmPred:$offset))>;
2231 // 64 bit atomic load
2232 def : Pat<(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
2233 (i64 (LDd_GP tglobaladdr:$global))>,
2236 def : Pat<(atomic_load_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2237 u16ImmPred:$offset)),
2238 (i64 (LDrid_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2241 def : Pat<(atomic_load_64 ADDRriS11_3:$src1),
2242 (i64 (LDrid ADDRriS11_3:$src1))>;
2244 def : Pat<(atomic_load_64 (add (i32 IntRegs:$src1), s11_3ImmPred:$offset)),
2245 (i64 (LDrid_indexed (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
2248 // 64 bit atomic store
2249 def : Pat<(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
2250 (i64 DoubleRegs:$src1)),
2251 (STd_GP tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2254 def : Pat<(atomic_store_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2255 u16ImmPred:$offset),
2256 (i64 DoubleRegs:$src1)),
2257 (STrid_GP tglobaladdr:$global, u16ImmPred:$offset,
2258 (i64 DoubleRegs:$src1))>, Requires<[NoV4T]>;
2260 // 8 bit atomic store
2261 def : Pat<(atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
2262 (i32 IntRegs:$src1)),
2263 (STb_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2266 def : Pat<(atomic_store_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2267 u16ImmPred:$offset),
2268 (i32 IntRegs:$src1)),
2269 (STrib_GP tglobaladdr:$global, u16ImmPred:$offset,
2270 (i32 IntRegs:$src1))>, Requires<[NoV4T]>;
2272 def : Pat<(atomic_store_8 ADDRriS11_0:$src2, (i32 IntRegs:$src1)),
2273 (STrib ADDRriS11_0:$src2, (i32 IntRegs:$src1))>;
2275 def : Pat<(atomic_store_8 (add (i32 IntRegs:$src2), s11_0ImmPred:$offset),
2276 (i32 IntRegs:$src1)),
2277 (STrib_indexed (i32 IntRegs:$src2), s11_0ImmPred:$offset,
2278 (i32 IntRegs:$src1))>;
2281 // 16 bit atomic store
2282 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
2283 (i32 IntRegs:$src1)),
2284 (STh_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2287 def : Pat<(atomic_store_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2288 u16ImmPred:$offset),
2289 (i32 IntRegs:$src1)),
2290 (STrih_GP tglobaladdr:$global, u16ImmPred:$offset,
2291 (i32 IntRegs:$src1))>, Requires<[NoV4T]>;
2293 def : Pat<(atomic_store_16 ADDRriS11_1:$src2, (i32 IntRegs:$src1)),
2294 (STrih ADDRriS11_1:$src2, (i32 IntRegs:$src1))>;
2296 def : Pat<(atomic_store_16 (i32 IntRegs:$src1),
2297 (add (i32 IntRegs:$src2), s11_1ImmPred:$offset)),
2298 (STrih_indexed (i32 IntRegs:$src2), s11_1ImmPred:$offset,
2299 (i32 IntRegs:$src1))>;
2302 // 32 bit atomic store
2303 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
2304 (i32 IntRegs:$src1)),
2305 (STw_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2308 def : Pat<(atomic_store_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2309 u16ImmPred:$offset),
2310 (i32 IntRegs:$src1)),
2311 (STriw_GP tglobaladdr:$global, u16ImmPred:$offset,
2312 (i32 IntRegs:$src1))>,
2315 def : Pat<(atomic_store_32 ADDRriS11_2:$src2, (i32 IntRegs:$src1)),
2316 (STriw ADDRriS11_2:$src2, (i32 IntRegs:$src1))>;
2318 def : Pat<(atomic_store_32 (add (i32 IntRegs:$src2), s11_2ImmPred:$offset),
2319 (i32 IntRegs:$src1)),
2320 (STriw_indexed (i32 IntRegs:$src2), s11_2ImmPred:$offset,
2321 (i32 IntRegs:$src1))>;
2326 def : Pat<(atomic_store_64 ADDRriS11_3:$src2, (i64 DoubleRegs:$src1)),
2327 (STrid ADDRriS11_3:$src2, (i64 DoubleRegs:$src1))>;
2329 def : Pat<(atomic_store_64 (add (i32 IntRegs:$src2), s11_3ImmPred:$offset),
2330 (i64 DoubleRegs:$src1)),
2331 (STrid_indexed (i32 IntRegs:$src2), s11_3ImmPred:$offset,
2332 (i64 DoubleRegs:$src1))>;
2334 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
2335 def : Pat <(and (i32 IntRegs:$src1), 65535),
2336 (ZXTH (i32 IntRegs:$src1))>;
2338 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
2339 def : Pat <(and (i32 IntRegs:$src1), 255),
2340 (ZXTB (i32 IntRegs:$src1))>;
2342 // Map Add(p1, true) to p1 = not(p1).
2343 // Add(p1, false) should never be produced,
2344 // if it does, it got to be mapped to NOOP.
2345 def : Pat <(add (i1 PredRegs:$src1), -1),
2346 (NOT_p (i1 PredRegs:$src1))>;
2348 // Map from p0 = setlt(r0, r1) r2 = mux(p0, r3, r4) =>
2349 // p0 = cmp.lt(r0, r1), r0 = mux(p0, r2, r1).
2350 def : Pat <(select (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2351 (i32 IntRegs:$src3),
2352 (i32 IntRegs:$src4)),
2353 (i32 (TFR_condset_rr (CMPLTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2354 (i32 IntRegs:$src4), (i32 IntRegs:$src3)))>,
2355 Requires<[HasV2TOnly]>;
2357 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
2358 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
2359 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
2362 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
2363 // => r0 = TFR_condset_ri(p0, r1, #i)
2364 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
2365 (i32 IntRegs:$src3)),
2366 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
2367 s12ImmPred:$src2))>;
2369 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
2370 // => r0 = TFR_condset_ir(p0, #i, r1)
2371 def : Pat <(select (not PredRegs:$src1), IntRegs:$src2, s12ImmPred:$src3),
2372 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
2373 (i32 IntRegs:$src2)))>;
2375 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
2376 def : Pat <(brcond (not PredRegs:$src1), bb:$offset),
2377 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
2379 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
2380 def : Pat <(and PredRegs:$src1, (not PredRegs:$src2)),
2381 (i1 (AND_pnotp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2383 // Map from store(globaladdress + x) -> memd(#foo + x).
2384 let AddedComplexity = 100 in
2385 def : Pat <(store (i64 DoubleRegs:$src1),
2386 (add (HexagonCONST32_GP tglobaladdr:$global),
2387 u16ImmPred:$offset)),
2388 (STrid_GP tglobaladdr:$global, u16ImmPred:$offset,
2389 (i64 DoubleRegs:$src1))>, Requires<[NoV4T]>;
2391 // Map from store(globaladdress) -> memd(#foo).
2392 let AddedComplexity = 100 in
2393 def : Pat <(store (i64 DoubleRegs:$src1),
2394 (HexagonCONST32_GP tglobaladdr:$global)),
2395 (STd_GP tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2398 // Map from store(globaladdress + x) -> memw(#foo + x).
2399 let AddedComplexity = 100 in
2400 def : Pat <(store (i32 IntRegs:$src1),
2401 (add (HexagonCONST32_GP tglobaladdr:$global),
2402 u16ImmPred:$offset)),
2403 (STriw_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2406 // Map from store(globaladdress) -> memw(#foo + 0).
2407 let AddedComplexity = 100 in
2408 def : Pat <(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2409 (STriw_GP tglobaladdr:$global, 0, (i32 IntRegs:$src1))>;
2411 // Map from store(globaladdress) -> memw(#foo).
2412 let AddedComplexity = 100 in
2413 def : Pat <(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2414 (STriw_GP tglobaladdr:$global, 0, (i32 IntRegs:$src1))>,
2417 // Map from store(globaladdress + x) -> memh(#foo + x).
2418 let AddedComplexity = 100 in
2419 def : Pat <(truncstorei16 (i32 IntRegs:$src1),
2420 (add (HexagonCONST32_GP tglobaladdr:$global),
2421 u16ImmPred:$offset)),
2422 (STrih_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2425 // Map from store(globaladdress) -> memh(#foo).
2426 let AddedComplexity = 100 in
2427 def : Pat <(truncstorei16 (i32 IntRegs:$src1),
2428 (HexagonCONST32_GP tglobaladdr:$global)),
2429 (STh_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2432 // Map from store(globaladdress + x) -> memb(#foo + x).
2433 let AddedComplexity = 100 in
2434 def : Pat <(truncstorei8 (i32 IntRegs:$src1),
2435 (add (HexagonCONST32_GP tglobaladdr:$global),
2436 u16ImmPred:$offset)),
2437 (STrib_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2440 // Map from store(globaladdress) -> memb(#foo).
2441 let AddedComplexity = 100 in
2442 def : Pat <(truncstorei8 (i32 IntRegs:$src1),
2443 (HexagonCONST32_GP tglobaladdr:$global)),
2444 (STb_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2447 // Map from load(globaladdress + x) -> memw(#foo + x).
2448 let AddedComplexity = 100 in
2449 def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global),
2450 u16ImmPred:$offset))),
2451 (i32 (LDriw_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2454 // Map from load(globaladdress) -> memw(#foo).
2455 let AddedComplexity = 100 in
2456 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
2457 (i32 (LDw_GP tglobaladdr:$global))>,
2460 // Map from load(globaladdress + x) -> memd(#foo + x).
2461 let AddedComplexity = 100 in
2462 def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),
2463 u16ImmPred:$offset))),
2464 (i64 (LDrid_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2467 // Map from load(globaladdress) -> memw(#foo + 0).
2468 let AddedComplexity = 100 in
2469 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
2470 (i64 (LDd_GP tglobaladdr:$global))>,
2473 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd.
2474 let AddedComplexity = 100 in
2475 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
2476 (i1 (TFR_PdRs (i32 (LDb_GP tglobaladdr:$global))))>,
2479 // Map from load(globaladdress + x) -> memh(#foo + x).
2480 let AddedComplexity = 100 in
2481 def : Pat <(i32 (extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2482 u16ImmPred:$offset))),
2483 (i32 (LDrih_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2486 // Map from load(globaladdress + x) -> memh(#foo + x).
2487 let AddedComplexity = 100 in
2488 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2489 (i32 (LDrih_GP tglobaladdr:$global, 0))>,
2492 // Map from load(globaladdress + x) -> memuh(#foo + x).
2493 let AddedComplexity = 100 in
2494 def : Pat <(i32 (zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2495 u16ImmPred:$offset))),
2496 (i32 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2499 // Map from load(globaladdress) -> memuh(#foo).
2500 let AddedComplexity = 100 in
2501 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2502 (i32 (LDriuh_GP tglobaladdr:$global, 0))>,
2505 // Map from load(globaladdress) -> memh(#foo).
2506 let AddedComplexity = 100 in
2507 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2508 (i32 (LDh_GP tglobaladdr:$global))>,
2511 // Map from load(globaladdress) -> memuh(#foo).
2512 let AddedComplexity = 100 in
2513 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2514 (i32 (LDuh_GP tglobaladdr:$global))>,
2517 // Map from load(globaladdress + x) -> memb(#foo + x).
2518 let AddedComplexity = 100 in
2519 def : Pat <(i32 (extloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2520 u16ImmPred:$offset))),
2521 (i32 (LDrib_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2524 // Map from load(globaladdress + x) -> memb(#foo + x).
2525 let AddedComplexity = 100 in
2526 def : Pat <(i32 (sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2527 u16ImmPred:$offset))),
2528 (i32 (LDrib_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2531 // Map from load(globaladdress + x) -> memub(#foo + x).
2532 let AddedComplexity = 100 in
2533 def : Pat <(i32 (zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2534 u16ImmPred:$offset))),
2535 (i32 (LDriub_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2538 // Map from load(globaladdress) -> memb(#foo).
2539 let AddedComplexity = 100 in
2540 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2541 (i32 (LDb_GP tglobaladdr:$global))>,
2544 // Map from load(globaladdress) -> memb(#foo).
2545 let AddedComplexity = 100 in
2546 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2547 (i32 (LDb_GP tglobaladdr:$global))>,
2550 // Map from load(globaladdress) -> memub(#foo).
2551 let AddedComplexity = 100 in
2552 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2553 (i32 (LDub_GP tglobaladdr:$global))>,
2556 // When the Interprocedural Global Variable optimizer realizes that a
2557 // certain global variable takes only two constant values, it shrinks the
2558 // global to a boolean. Catch those loads here in the following 3 patterns.
2559 let AddedComplexity = 100 in
2560 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2561 (i32 (LDb_GP tglobaladdr:$global))>,
2564 let AddedComplexity = 100 in
2565 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2566 (i32 (LDb_GP tglobaladdr:$global))>,
2569 let AddedComplexity = 100 in
2570 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2571 (i32 (LDub_GP tglobaladdr:$global))>,
2574 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
2575 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
2576 (i32 (AND_rr (i32 (LDrib ADDRriS11_0:$addr)), (TFRI 0x1)))>;
2578 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
2579 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
2580 (i64 (SXTW (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
2582 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
2583 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
2584 (i64 (SXTW (i32 (SXTH (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2585 subreg_loreg))))))>;
2587 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
2588 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
2589 (i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2590 subreg_loreg))))))>;
2592 // We want to prevent emitting pnot's as much as possible.
2593 // Map brcond with an unsupported setcc to a JMP_cNot.
2594 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2596 (JMP_cNot (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2599 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
2601 (JMP_cNot (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
2603 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
2604 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
2606 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
2607 (JMP_c (i1 PredRegs:$src1), bb:$offset)>;
2609 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
2611 (JMP_cNot (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2), bb:$offset)>;
2613 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2615 (JMP_c (CMPLTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)), bb:$offset)>;
2617 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2619 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
2622 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2624 (JMP_cNot (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2627 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2629 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2632 // Map from a 64-bit select to an emulated 64-bit mux.
2633 // Hexagon does not support 64-bit MUXes; so emulate with combines.
2634 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
2635 (i64 DoubleRegs:$src3)),
2636 (i64 (COMBINE_rr (i32 (MUX_rr (i1 PredRegs:$src1),
2637 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2639 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2641 (i32 (MUX_rr (i1 PredRegs:$src1),
2642 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2644 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2645 subreg_loreg))))))>;
2647 // Map from a 1-bit select to logical ops.
2648 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
2649 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
2650 (i1 PredRegs:$src3)),
2651 (OR_pp (AND_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
2652 (AND_pp (NOT_p (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
2654 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
2655 def : Pat<(i1 (load ADDRriS11_2:$addr)),
2656 (i1 (TFR_PdRs (i32 (LDrib ADDRriS11_2:$addr))))>;
2658 // Map for truncating from 64 immediates to 32 bit immediates.
2659 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
2660 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
2662 // Map for truncating from i64 immediates to i1 bit immediates.
2663 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
2664 (i1 (TFR_PdRs (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2667 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
2668 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2669 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2672 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
2673 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2674 (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2676 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
2677 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2678 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2681 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
2682 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2683 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2686 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
2687 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2688 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2690 let AddedComplexity = 100 in
2691 // Map from i1 = constant<-1>; memw(CONST32(#foo)) = i1 -> r0 = 1;
2693 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
2694 (STb_GP tglobaladdr:$global, (TFRI 1))>,
2697 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
2698 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2699 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2701 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
2702 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
2703 (STrib ADDRriS11_2:$addr, (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0)) )>;
2705 // Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs).
2706 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
2707 // Better way to do this?
2708 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
2709 (i64 (SXTW (i32 IntRegs:$src1)))>;
2711 // Map cmple -> cmpgt.
2712 // rs <= rt -> !(rs > rt).
2713 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ImmPred:$src2)),
2714 (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), s10ImmPred:$src2)))>;
2716 // rs <= rt -> !(rs > rt).
2717 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2718 (i1 (NOT_p (CMPGTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2720 // Rss <= Rtt -> !(Rss > Rtt).
2721 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2722 (i1 (NOT_p (CMPGT64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2724 // Map cmpne -> cmpeq.
2725 // Hexagon_TODO: We should improve on this.
2726 // rs != rt -> !(rs == rt).
2727 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
2728 (i1 (NOT_p(i1 (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2))))>;
2730 // Map cmpne(Rs) -> !cmpeqe(Rs).
2731 // rs != rt -> !(rs == rt).
2732 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2733 (i1 (NOT_p (i1 (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
2735 // Convert setne back to xor for hexagon since we compute w/ pred registers.
2736 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
2737 (i1 (XOR_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2739 // Map cmpne(Rss) -> !cmpew(Rss).
2740 // rs != rt -> !(rs == rt).
2741 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2742 (i1 (NOT_p (i1 (CMPEHexagon4rr (i64 DoubleRegs:$src1),
2743 (i64 DoubleRegs:$src2)))))>;
2745 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
2746 // rs >= rt -> !(rt > rs).
2747 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2748 (i1 (NOT_p (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
2750 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ImmPred:$src2)),
2751 (i1 (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2))>;
2753 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
2754 // rss >= rtt -> !(rtt > rss).
2755 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2756 (i1 (NOT_p (i1 (CMPGT64rr (i64 DoubleRegs:$src2),
2757 (i64 DoubleRegs:$src1)))))>;
2759 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
2760 // rs < rt -> !(rs >= rt).
2761 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
2762 (i1 (NOT_p (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2)))>;
2764 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
2765 // rs < rt -> rt > rs.
2766 // We can let assembler map it, or we can do in the compiler itself.
2767 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2768 (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2770 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
2771 // rss < rtt -> (rtt > rss).
2772 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2773 (i1 (CMPGT64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2775 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
2776 // rs < rt -> rt > rs.
2777 // We can let assembler map it, or we can do in the compiler itself.
2778 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2779 (i1 (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2781 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
2782 // rs < rt -> rt > rs.
2783 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2784 (i1 (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2786 // Generate cmpgeu(Rs, #u8)
2787 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ImmPred:$src2)),
2788 (i1 (CMPGEUri (i32 IntRegs:$src1), u8ImmPred:$src2))>;
2790 // Generate cmpgtu(Rs, #u9)
2791 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ImmPred:$src2)),
2792 (i1 (CMPGTUri (i32 IntRegs:$src1), u9ImmPred:$src2))>;
2794 // Map from Rs >= Rt -> !(Rt > Rs).
2795 // rs >= rt -> !(rt > rs).
2796 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2797 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
2799 // Map from Rs >= Rt -> !(Rt > Rs).
2800 // rs >= rt -> !(rt > rs).
2801 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2802 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
2804 // Map from cmpleu(Rs, Rs) -> !cmpgtu(Rs, Rs).
2805 // Map from (Rs <= Rt) -> !(Rs > Rt).
2806 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2807 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2809 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
2810 // Map from (Rs <= Rt) -> !(Rs > Rt).
2811 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2812 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2816 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
2817 (i32 (MUX_ii (i1 PredRegs:$src1), -1, 0))>;
2820 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
2821 (i64 (COMBINE_rr (TFRI -1), (MUX_ii (i1 PredRegs:$src1), -1, 0)))>;
2823 // Convert sign-extended load back to load and sign extend.
2825 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
2826 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2828 // Convert any-extended load back to load and sign extend.
2830 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
2831 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2833 // Convert sign-extended load back to load and sign extend.
2835 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
2836 (i64 (SXTW (LDrih ADDRriS11_1:$src1)))>;
2838 // Convert sign-extended load back to load and sign extend.
2840 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
2841 (i64 (SXTW (LDriw ADDRriS11_2:$src1)))>;
2846 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2847 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2850 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
2851 (i64 (COMBINE_rr (TFRI 0), (MUX_ii (i1 PredRegs:$src1), 1, 0)))>;
2854 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
2855 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>;
2858 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
2859 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>;
2862 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
2863 (i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>;
2866 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
2867 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>;
2869 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
2870 (i32 (LDriw ADDRriS11_0:$src1))>;
2872 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2873 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2874 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2876 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2877 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
2878 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2880 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
2881 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
2882 (i64 (SXTW (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))))>;
2885 // Any extended 64-bit load.
2886 // anyext i32 -> i64
2887 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
2888 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>;
2890 // anyext i16 -> i64.
2891 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
2892 (i64 (COMBINE_rr (TFRI 0), (LDrih ADDRriS11_2:$src1)))>;
2894 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
2895 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
2896 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>;
2898 // Multiply 64-bit unsigned and use upper result.
2899 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2914 (COMBINE_rr (TFRI 0),
2920 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2922 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2923 subreg_loreg)))), 32)),
2925 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2926 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2927 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2928 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2929 32)), subreg_loreg)))),
2930 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2931 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2933 // Multiply 64-bit signed and use upper result.
2934 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2938 (COMBINE_rr (TFRI 0),
2948 (COMBINE_rr (TFRI 0),
2954 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2956 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2957 subreg_loreg)))), 32)),
2959 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2960 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2961 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2962 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2963 32)), subreg_loreg)))),
2964 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2965 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2967 // Hexagon specific ISD nodes.
2968 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
2969 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
2970 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
2971 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
2972 SDTHexagonADJDYNALLOC>;
2973 // Needed to tag these instructions for stack layout.
2974 let usesCustomInserter = 1 in
2975 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
2977 "$dst = add($src1, #$src2)",
2978 [(set (i32 IntRegs:$dst),
2979 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
2980 s16ImmPred:$src2))]>;
2982 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
2983 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
2984 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
2986 [(set (i32 IntRegs:$dst),
2987 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
2989 let AddedComplexity = 100 in
2990 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
2991 (COPY (i32 IntRegs:$src1))>;
2993 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2994 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
2996 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
2997 def BR_JT : JRInst<(outs), (ins IntRegs:$src),
2999 [(HexagonBR_JT (i32 IntRegs:$src))]>;
3001 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
3003 def : Pat<(HexagonWrapperJT tjumptable:$dst),
3004 (i32 (CONST32_set_jt tjumptable:$dst))>;
3008 // Multi-class for logical operators :
3009 // Shift by immediate/register and accumulate/logical
3010 multiclass xtype_imm<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
3011 def _ri : SInst_acc<(outs IntRegs:$dst),
3012 (ins IntRegs:$src1, IntRegs:$src2, u5Imm:$src3),
3013 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
3014 [(set (i32 IntRegs:$dst),
3015 (OpNode2 (i32 IntRegs:$src1),
3016 (OpNode1 (i32 IntRegs:$src2),
3017 u5ImmPred:$src3)))],
3020 def d_ri : SInst_acc<(outs DoubleRegs:$dst),
3021 (ins DoubleRegs:$src1, DoubleRegs:$src2, u6Imm:$src3),
3022 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
3023 [(set (i64 DoubleRegs:$dst), (OpNode2 (i64 DoubleRegs:$src1),
3024 (OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
3028 // Multi-class for logical operators :
3029 // Shift by register and accumulate/logical (32/64 bits)
3030 multiclass xtype_reg<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
3031 def _rr : SInst_acc<(outs IntRegs:$dst),
3032 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
3033 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
3034 [(set (i32 IntRegs:$dst),
3035 (OpNode2 (i32 IntRegs:$src1),
3036 (OpNode1 (i32 IntRegs:$src2),
3037 (i32 IntRegs:$src3))))],
3040 def d_rr : SInst_acc<(outs DoubleRegs:$dst),
3041 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3042 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
3043 [(set (i64 DoubleRegs:$dst),
3044 (OpNode2 (i64 DoubleRegs:$src1),
3045 (OpNode1 (i64 DoubleRegs:$src2),
3046 (i32 IntRegs:$src3))))],
3051 multiclass basic_xtype_imm<string OpcStr, SDNode OpNode> {
3052 let AddedComplexity = 100 in
3053 defm _ADD : xtype_imm< !strconcat("+= ", OpcStr), OpNode, add>;
3054 defm _SUB : xtype_imm< !strconcat("-= ", OpcStr), OpNode, sub>;
3055 defm _AND : xtype_imm< !strconcat("&= ", OpcStr), OpNode, and>;
3056 defm _OR : xtype_imm< !strconcat("|= ", OpcStr), OpNode, or>;
3059 multiclass basic_xtype_reg<string OpcStr, SDNode OpNode> {
3060 let AddedComplexity = 100 in
3061 defm _ADD : xtype_reg< !strconcat("+= ", OpcStr), OpNode, add>;
3062 defm _SUB : xtype_reg< !strconcat("-= ", OpcStr), OpNode, sub>;
3063 defm _AND : xtype_reg< !strconcat("&= ", OpcStr), OpNode, and>;
3064 defm _OR : xtype_reg< !strconcat("|= ", OpcStr), OpNode, or>;
3067 multiclass xtype_xor_imm<string OpcStr, SDNode OpNode> {
3068 let AddedComplexity = 100 in
3069 defm _XOR : xtype_imm< !strconcat("^= ", OpcStr), OpNode, xor>;
3072 defm ASL : basic_xtype_imm<"asl", shl>, basic_xtype_reg<"asl", shl>,
3073 xtype_xor_imm<"asl", shl>;
3075 defm LSR : basic_xtype_imm<"lsr", srl>, basic_xtype_reg<"lsr", srl>,
3076 xtype_xor_imm<"lsr", srl>;
3078 defm ASR : basic_xtype_imm<"asr", sra>, basic_xtype_reg<"asr", sra>;
3079 defm LSL : basic_xtype_reg<"lsl", shl>;
3081 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
3082 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
3083 (i32 (MPYI_rin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
3085 //===----------------------------------------------------------------------===//
3086 // V3 Instructions +
3087 //===----------------------------------------------------------------------===//
3089 include "HexagonInstrInfoV3.td"
3091 //===----------------------------------------------------------------------===//
3092 // V3 Instructions -
3093 //===----------------------------------------------------------------------===//
3095 //===----------------------------------------------------------------------===//
3096 // V4 Instructions +
3097 //===----------------------------------------------------------------------===//
3099 include "HexagonInstrInfoV4.td"
3101 //===----------------------------------------------------------------------===//
3102 // V4 Instructions -
3103 //===----------------------------------------------------------------------===//
3105 //===----------------------------------------------------------------------===//
3106 // V5 Instructions +
3107 //===----------------------------------------------------------------------===//
3109 include "HexagonInstrInfoV5.td"
3111 //===----------------------------------------------------------------------===//
3112 // V5 Instructions -
3113 //===----------------------------------------------------------------------===//
3115 //===----------------------------------------------------------------------===//
3116 // Generate mapping table to relate non-predicate instructions with their
3117 // predicated formats - true and false.
3120 def getPredOpcode : InstrMapping {
3121 let FilterClass = "PredRel";
3122 // Instructions with the same BaseOpcode and isNVStore values form a row.
3123 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue"];
3124 // Instructions with the same predicate sense form a column.
3125 let ColFields = ["PredSense"];
3126 // The key column is the unpredicated instructions.
3128 // Value columns are PredSense=true and PredSense=false
3129 let ValueCols = [["true"], ["false"]];
3132 //===----------------------------------------------------------------------===//
3133 // Generate mapping table to relate predicated instructions with their .new
3136 def getPredNewOpcode : InstrMapping {
3137 let FilterClass = "PredNewRel";
3138 let RowFields = ["BaseOpcode", "PredSense", "isNVStore"];
3139 let ColFields = ["PNewValue"];
3141 let ValueCols = [["new"]];