1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
16 include "HexagonInstrEnc.td"
17 // Pattern fragment that combines the value type and the register class
18 // into a single parameter.
19 // The pat frags in the definitions below need to have a named register,
20 // otherwise i32 will be assumed regardless of the register class. The
21 // name of the register does not matter.
22 def I1 : PatLeaf<(i1 PredRegs:$R)>;
23 def I32 : PatLeaf<(i32 IntRegs:$R)>;
24 def I64 : PatLeaf<(i64 DoubleRegs:$R)>;
25 def F32 : PatLeaf<(f32 IntRegs:$R)>;
26 def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
28 // Pattern fragments to extract the low and high subregisters from a
30 def LoReg: OutPatFrag<(ops node:$Rs),
31 (EXTRACT_SUBREG (i64 $Rs), subreg_loreg)>;
32 def HiReg: OutPatFrag<(ops node:$Rs),
33 (EXTRACT_SUBREG (i64 $Rs), subreg_hireg)>;
35 // SDNode for converting immediate C to C-1.
36 def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
37 // Return the byte immediate const-1 as an SDNode.
38 int32_t imm = N->getSExtValue();
39 return XformSToSM1Imm(imm, SDLoc(N));
42 // SDNode for converting immediate C to C-2.
43 def DEC2_CONST_SIGNED : SDNodeXForm<imm, [{
44 // Return the byte immediate const-2 as an SDNode.
45 int32_t imm = N->getSExtValue();
46 return XformSToSM2Imm(imm, SDLoc(N));
49 // SDNode for converting immediate C to C-3.
50 def DEC3_CONST_SIGNED : SDNodeXForm<imm, [{
51 // Return the byte immediate const-3 as an SDNode.
52 int32_t imm = N->getSExtValue();
53 return XformSToSM3Imm(imm, SDLoc(N));
56 // SDNode for converting immediate C to C-1.
57 def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
58 // Return the byte immediate const-1 as an SDNode.
59 uint32_t imm = N->getZExtValue();
60 return XformUToUM1Imm(imm, SDLoc(N));
63 //===----------------------------------------------------------------------===//
65 //===----------------------------------------------------------------------===//
66 let hasSideEffects = 0, isCompare = 1, InputType = "imm", isExtendable = 1,
68 class T_CMP <string mnemonic, bits<2> MajOp, bit isNot, Operand ImmOp>
69 : ALU32Inst <(outs PredRegs:$dst),
70 (ins IntRegs:$src1, ImmOp:$src2),
71 "$dst = "#!if(isNot, "!","")#mnemonic#"($src1, #$src2)",
72 [], "",ALU32_2op_tc_2early_SLOT0123 >, ImmRegRel {
76 let CextOpcode = mnemonic;
77 let opExtentBits = !if(!eq(mnemonic, "cmp.gtu"), 9, 10);
78 let isExtentSigned = !if(!eq(mnemonic, "cmp.gtu"), 0, 1);
82 let Inst{27-24} = 0b0101;
83 let Inst{23-22} = MajOp;
84 let Inst{21} = !if(!eq(mnemonic, "cmp.gtu"), 0, src2{9});
85 let Inst{20-16} = src1;
86 let Inst{13-5} = src2{8-0};
92 def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10Ext>;
93 def C2_cmpgti : T_CMP <"cmp.gt", 0b01, 0, s10Ext>;
94 def C2_cmpgtui : T_CMP <"cmp.gtu", 0b10, 0, u9Ext>;
96 class T_CMP_pat <InstHexagon MI, PatFrag OpNode, PatLeaf ImmPred>
97 : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)),
98 (MI IntRegs:$src1, ImmPred:$src2)>;
100 def : T_CMP_pat <C2_cmpeqi, seteq, s10ImmPred>;
101 def : T_CMP_pat <C2_cmpgti, setgt, s10ImmPred>;
102 def : T_CMP_pat <C2_cmpgtui, setugt, u9ImmPred>;
104 //===----------------------------------------------------------------------===//
106 //===----------------------------------------------------------------------===//
109 def SDT_Int32Leaf : SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>;
110 def SDT_Int32Unary : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
112 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
113 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
115 def HexagonCOMBINE : SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>;
116 def HexagonPACKHL : SDNode<"HexagonISD::PACKHL", SDTHexagonI64I32I32>;
118 let hasSideEffects = 0, hasNewValue = 1, InputType = "reg" in
119 class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev,
121 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
122 "$Rd = "#mnemonic#"($Rs, $Rt)",
123 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredRel {
124 let isCommutable = IsComm;
125 let BaseOpcode = mnemonic#_rr;
126 let CextOpcode = mnemonic;
134 let Inst{26-24} = MajOp;
135 let Inst{23-21} = MinOp;
136 let Inst{20-16} = !if(OpsRev,Rt,Rs);
137 let Inst{12-8} = !if(OpsRev,Rs,Rt);
141 let hasSideEffects = 0, hasNewValue = 1 in
142 class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp,
143 bit OpsRev, bit PredNot, bit PredNew>
144 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
145 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") "#
146 "$Rd = "#mnemonic#"($Rs, $Rt)",
147 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
148 let isPredicated = 1;
149 let isPredicatedFalse = PredNot;
150 let isPredicatedNew = PredNew;
151 let BaseOpcode = mnemonic#_rr;
152 let CextOpcode = mnemonic;
161 let Inst{26-24} = MajOp;
162 let Inst{23-21} = MinOp;
163 let Inst{20-16} = !if(OpsRev,Rt,Rs);
164 let Inst{13} = PredNew;
165 let Inst{12-8} = !if(OpsRev,Rs,Rt);
166 let Inst{7} = PredNot;
171 class T_ALU32_combineh<string Op1, string Op2, bits<3> MajOp, bits<3> MinOp,
173 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, 0> {
174 let AsmString = "$Rd = combine($Rs"#Op1#", $Rt"#Op2#")";
177 def A2_combine_hh : T_ALU32_combineh<".h", ".h", 0b011, 0b100, 1>;
178 def A2_combine_hl : T_ALU32_combineh<".h", ".l", 0b011, 0b101, 1>;
179 def A2_combine_lh : T_ALU32_combineh<".l", ".h", 0b011, 0b110, 1>;
180 def A2_combine_ll : T_ALU32_combineh<".l", ".l", 0b011, 0b111, 1>;
182 class T_ALU32_3op_sfx<string mnemonic, string suffix, bits<3> MajOp,
183 bits<3> MinOp, bit OpsRev, bit IsComm>
184 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, IsComm> {
185 let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix;
188 def A2_svaddh : T_ALU32_3op<"vaddh", 0b110, 0b000, 0, 1>;
189 def A2_svsubh : T_ALU32_3op<"vsubh", 0b110, 0b100, 1, 0>;
191 let Defs = [USR_OVF], Itinerary = ALU32_3op_tc_2_SLOT0123 in {
192 def A2_svaddhs : T_ALU32_3op_sfx<"vaddh", ":sat", 0b110, 0b001, 0, 1>;
193 def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>;
194 def A2_svadduhs : T_ALU32_3op_sfx<"vadduh", ":sat", 0b110, 0b011, 0, 1>;
195 def A2_svsubhs : T_ALU32_3op_sfx<"vsubh", ":sat", 0b110, 0b101, 1, 0>;
196 def A2_subsat : T_ALU32_3op_sfx<"sub", ":sat", 0b110, 0b110, 1, 0>;
197 def A2_svsubuhs : T_ALU32_3op_sfx<"vsubuh", ":sat", 0b110, 0b111, 1, 0>;
200 let Itinerary = ALU32_3op_tc_2_SLOT0123 in
201 def A2_svavghs : T_ALU32_3op_sfx<"vavgh", ":rnd", 0b111, 0b001, 0, 1>;
203 def A2_svavgh : T_ALU32_3op<"vavgh", 0b111, 0b000, 0, 1>;
204 def A2_svnavgh : T_ALU32_3op<"vnavgh", 0b111, 0b011, 1, 0>;
206 multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,
208 def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>;
209 def f : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 0>;
210 def tnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 1>;
211 def fnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 1>;
214 multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp,
215 bit OpsRev, bit IsComm> {
216 let isPredicable = 1 in
217 def A2_#NAME : T_ALU32_3op <mnemonic, MajOp, MinOp, OpsRev, IsComm>;
218 defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>;
221 defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
222 defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>;
223 defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>;
224 defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>;
225 defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>;
227 // Pats for instruction selection.
228 class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
229 : Pat<(ResT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
230 (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
232 def: BinOp32_pat<add, A2_add, i32>;
233 def: BinOp32_pat<and, A2_and, i32>;
234 def: BinOp32_pat<or, A2_or, i32>;
235 def: BinOp32_pat<sub, A2_sub, i32>;
236 def: BinOp32_pat<xor, A2_xor, i32>;
238 // A few special cases producing register pairs:
239 let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0 in {
240 def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>;
242 let isPredicable = 1 in
243 def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>;
245 // Conditional combinew uses "newt/f" instead of "t/fnew".
246 def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>;
247 def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>;
248 def C2_ccombinewnewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 1>;
249 def C2_ccombinewnewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 1>;
252 def: BinOp32_pat<HexagonCOMBINE, A2_combinew, i64>;
253 def: BinOp32_pat<HexagonPACKHL, S2_packhl, i64>;
255 let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in
256 class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm>
257 : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
258 "$Pd = "#mnemonic#"($Rs, $Rt)",
259 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
260 let CextOpcode = mnemonic;
261 let isCommutable = IsComm;
267 let Inst{27-24} = 0b0010;
268 let Inst{22-21} = MinOp;
269 let Inst{20-16} = Rs;
272 let Inst{3-2} = 0b00;
276 let Itinerary = ALU32_3op_tc_2early_SLOT0123 in {
277 def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>;
278 def C2_cmpgt : T_ALU32_3op_cmp< "cmp.gt", 0b10, 0, 0>;
279 def C2_cmpgtu : T_ALU32_3op_cmp< "cmp.gtu", 0b11, 0, 0>;
282 // Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones
283 // that reverse the order of the operands.
284 class RevCmp<PatFrag F> : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment>;
286 // Pats for compares. They use PatFrags as operands, not SDNodes,
287 // since seteq/setgt/etc. are defined as ParFrags.
288 class T_cmp32_rr_pat<InstHexagon MI, PatFrag Op, ValueType VT>
289 : Pat<(VT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
290 (VT (MI IntRegs:$Rs, IntRegs:$Rt))>;
292 def: T_cmp32_rr_pat<C2_cmpeq, seteq, i1>;
293 def: T_cmp32_rr_pat<C2_cmpgt, setgt, i1>;
294 def: T_cmp32_rr_pat<C2_cmpgtu, setugt, i1>;
296 def: T_cmp32_rr_pat<C2_cmpgt, RevCmp<setlt>, i1>;
297 def: T_cmp32_rr_pat<C2_cmpgtu, RevCmp<setult>, i1>;
299 let CextOpcode = "MUX", InputType = "reg", hasNewValue = 1 in
300 def C2_mux: ALU32_rr<(outs IntRegs:$Rd),
301 (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
302 "$Rd = mux($Pu, $Rs, $Rt)", [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
308 let CextOpcode = "mux";
309 let InputType = "reg";
310 let hasSideEffects = 0;
313 let Inst{27-24} = 0b0100;
314 let Inst{20-16} = Rs;
320 def: Pat<(i32 (select (i1 PredRegs:$Pu), (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
321 (C2_mux PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt)>;
323 // Combines the two immediates into a double register.
324 // Increase complexity to make it greater than any complexity of a combine
325 // that involves a register.
327 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
328 isExtentSigned = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 1,
329 AddedComplexity = 75 in
330 def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8),
331 "$Rdd = combine(#$s8, #$S8)",
332 [(set (i64 DoubleRegs:$Rdd),
333 (i64 (HexagonCOMBINE(i32 s32ImmPred:$s8), (i32 s8ImmPred:$S8))))]> {
339 let Inst{27-23} = 0b11000;
340 let Inst{22-16} = S8{7-1};
341 let Inst{13} = S8{0};
346 //===----------------------------------------------------------------------===//
347 // Template class for predicated ADD of a reg and an Immediate value.
348 //===----------------------------------------------------------------------===//
349 let hasNewValue = 1, hasSideEffects = 0 in
350 class T_Addri_Pred <bit PredNot, bit PredNew>
351 : ALU32_ri <(outs IntRegs:$Rd),
352 (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
353 !if(PredNot, "if (!$Pu", "if ($Pu")#!if(PredNew,".new) $Rd = ",
354 ") $Rd = ")#"add($Rs, #$s8)"> {
360 let isPredicatedNew = PredNew;
363 let Inst{27-24} = 0b0100;
364 let Inst{23} = PredNot;
365 let Inst{22-21} = Pu;
366 let Inst{20-16} = Rs;
367 let Inst{13} = PredNew;
372 //===----------------------------------------------------------------------===//
373 // A2_addi: Add a signed immediate to a register.
374 //===----------------------------------------------------------------------===//
375 let hasNewValue = 1, hasSideEffects = 0 in
376 class T_Addri <Operand immOp>
377 : ALU32_ri <(outs IntRegs:$Rd),
378 (ins IntRegs:$Rs, immOp:$s16),
379 "$Rd = add($Rs, #$s16)", [], "", ALU32_ADDI_tc_1_SLOT0123> {
386 let Inst{27-21} = s16{15-9};
387 let Inst{20-16} = Rs;
388 let Inst{13-5} = s16{8-0};
392 //===----------------------------------------------------------------------===//
393 // Multiclass for ADD of a register and an immediate value.
394 //===----------------------------------------------------------------------===//
395 multiclass Addri_Pred<string mnemonic, bit PredNot> {
396 let isPredicatedFalse = PredNot in {
397 def NAME : T_Addri_Pred<PredNot, 0>;
399 def NAME#new : T_Addri_Pred<PredNot, 1>;
403 let isExtendable = 1, isExtentSigned = 1, InputType = "imm" in
404 multiclass Addri_base<string mnemonic, SDNode OpNode> {
405 let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in {
406 let opExtendable = 2, opExtentBits = 16, isPredicable = 1 in
407 def A2_#NAME : T_Addri<s16Ext>;
409 let opExtendable = 3, opExtentBits = 8, isPredicated = 1 in {
410 defm A2_p#NAME#t : Addri_Pred<mnemonic, 0>;
411 defm A2_p#NAME#f : Addri_Pred<mnemonic, 1>;
416 defm addi : Addri_base<"add", add>, ImmRegRel, PredNewRel;
418 def: Pat<(i32 (add I32:$Rs, s32ImmPred:$s16)),
419 (i32 (A2_addi I32:$Rs, imm:$s16))>;
421 //===----------------------------------------------------------------------===//
422 // Template class used for the following ALU32 instructions.
425 //===----------------------------------------------------------------------===//
426 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
427 InputType = "imm", hasNewValue = 1 in
428 class T_ALU32ri_logical <string mnemonic, SDNode OpNode, bits<2> MinOp>
429 : ALU32_ri <(outs IntRegs:$Rd),
430 (ins IntRegs:$Rs, s10Ext:$s10),
431 "$Rd = "#mnemonic#"($Rs, #$s10)" ,
432 [(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s32ImmPred:$s10))]> {
436 let CextOpcode = mnemonic;
440 let Inst{27-24} = 0b0110;
441 let Inst{23-22} = MinOp;
442 let Inst{21} = s10{9};
443 let Inst{20-16} = Rs;
444 let Inst{13-5} = s10{8-0};
448 def A2_orir : T_ALU32ri_logical<"or", or, 0b10>, ImmRegRel;
449 def A2_andir : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel;
451 // Subtract register from immediate
452 // Rd32=sub(#s10,Rs32)
453 let isExtendable = 1, CextOpcode = "sub", opExtendable = 1, isExtentSigned = 1,
454 opExtentBits = 10, InputType = "imm", hasNewValue = 1, hasSideEffects = 0 in
455 def A2_subri: ALU32_ri <(outs IntRegs:$Rd), (ins s10Ext:$s10, IntRegs:$Rs),
456 "$Rd = sub(#$s10, $Rs)", []>, ImmRegRel {
463 let Inst{27-22} = 0b011001;
464 let Inst{21} = s10{9};
465 let Inst{20-16} = Rs;
466 let Inst{13-5} = s10{8-0};
471 let hasSideEffects = 0 in
472 def A2_nop: ALU32Inst <(outs), (ins), "nop" > {
474 let Inst{27-24} = 0b1111;
477 def: Pat<(sub s32ImmPred:$s10, IntRegs:$Rs),
478 (A2_subri imm:$s10, IntRegs:$Rs)>;
480 // Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
481 def: Pat<(not (i32 IntRegs:$src1)),
482 (A2_subri -1, IntRegs:$src1)>;
484 let hasSideEffects = 0, hasNewValue = 1 in
485 class T_tfr16<bit isHi>
486 : ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16Imm:$u16),
487 "$Rx"#!if(isHi, ".h", ".l")#" = #$u16",
488 [], "$src1 = $Rx" > {
493 let Inst{27-26} = 0b00;
494 let Inst{25-24} = !if(isHi, 0b10, 0b01);
495 let Inst{23-22} = u16{15-14};
497 let Inst{20-16} = Rx;
498 let Inst{13-0} = u16{13-0};
501 def A2_tfril: T_tfr16<0>;
502 def A2_tfrih: T_tfr16<1>;
504 // Conditional transfer is an alias to conditional "Rd = add(Rs, #0)".
505 let isPredicated = 1, hasNewValue = 1, opNewValue = 0 in
506 class T_tfr_pred<bit isPredNot, bit isPredNew>
507 : ALU32Inst<(outs IntRegs:$dst),
508 (ins PredRegs:$src1, IntRegs:$src2),
509 "if ("#!if(isPredNot, "!", "")#
510 "$src1"#!if(isPredNew, ".new", "")#
516 let isPredicatedFalse = isPredNot;
517 let isPredicatedNew = isPredNew;
520 let Inst{27-24} = 0b0100;
521 let Inst{23} = isPredNot;
522 let Inst{13} = isPredNew;
525 let Inst{22-21} = src1;
526 let Inst{20-16} = src2;
529 let isPredicable = 1 in
530 class T_tfr : ALU32Inst<(outs IntRegs:$dst), (ins IntRegs:$src),
537 let Inst{27-21} = 0b0000011;
538 let Inst{20-16} = src;
543 let InputType = "reg", hasNewValue = 1, hasSideEffects = 0 in
544 multiclass tfr_base<string CextOp> {
545 let CextOpcode = CextOp, BaseOpcode = CextOp in {
549 def t : T_tfr_pred<0, 0>;
550 def f : T_tfr_pred<1, 0>;
552 def tnew : T_tfr_pred<0, 1>;
553 def fnew : T_tfr_pred<1, 1>;
557 // Assembler mapped to C2_ccombinew[t|f|newt|newf].
558 // Please don't add bits to this instruction as it'll be converted into
559 // 'combine' before object code emission.
560 let isPredicated = 1 in
561 class T_tfrp_pred<bit PredNot, bit PredNew>
562 : ALU32_rr <(outs DoubleRegs:$dst),
563 (ins PredRegs:$src1, DoubleRegs:$src2),
564 "if ("#!if(PredNot, "!", "")#"$src1"
565 #!if(PredNew, ".new", "")#") $dst = $src2" > {
566 let isPredicatedFalse = PredNot;
567 let isPredicatedNew = PredNew;
570 // Assembler mapped to A2_combinew.
571 // Please don't add bits to this instruction as it'll be converted into
572 // 'combine' before object code emission.
573 class T_tfrp : ALU32Inst <(outs DoubleRegs:$dst),
574 (ins DoubleRegs:$src),
577 let hasSideEffects = 0 in
578 multiclass TFR64_base<string BaseName> {
579 let BaseOpcode = BaseName in {
580 let isPredicable = 1 in
583 def t : T_tfrp_pred <0, 0>;
584 def f : T_tfrp_pred <1, 0>;
586 def tnew : T_tfrp_pred <0, 1>;
587 def fnew : T_tfrp_pred <1, 1>;
591 let InputType = "imm", isExtendable = 1, isExtentSigned = 1, opExtentBits = 12,
592 isMoveImm = 1, opExtendable = 2, BaseOpcode = "TFRI", CextOpcode = "TFR",
593 hasSideEffects = 0, isPredicated = 1, hasNewValue = 1 in
594 class T_TFRI_Pred<bit PredNot, bit PredNew>
595 : ALU32_ri<(outs IntRegs:$Rd), (ins PredRegs:$Pu, s12Ext:$s12),
596 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") $Rd = #$s12",
597 [], "", ALU32_2op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
598 let isPredicatedFalse = PredNot;
599 let isPredicatedNew = PredNew;
606 let Inst{27-24} = 0b1110;
607 let Inst{23} = PredNot;
608 let Inst{22-21} = Pu;
610 let Inst{19-16,12-5} = s12;
611 let Inst{13} = PredNew;
615 def C2_cmoveit : T_TFRI_Pred<0, 0>;
616 def C2_cmoveif : T_TFRI_Pred<1, 0>;
617 def C2_cmovenewit : T_TFRI_Pred<0, 1>;
618 def C2_cmovenewif : T_TFRI_Pred<1, 1>;
620 let InputType = "imm", isExtendable = 1, isExtentSigned = 1,
621 CextOpcode = "TFR", BaseOpcode = "TFRI", hasNewValue = 1, opNewValue = 0,
622 isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16, isMoveImm = 1,
623 isPredicated = 0, isPredicable = 1, isReMaterializable = 1 in
624 def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16Ext:$s16), "$Rd = #$s16",
625 [(set (i32 IntRegs:$Rd), s32ImmPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>,
631 let Inst{27-24} = 0b1000;
632 let Inst{23-22,20-16,13-5} = s16;
636 defm A2_tfr : tfr_base<"TFR">, ImmRegRel, PredNewRel;
637 let isAsmParserOnly = 1 in
638 defm A2_tfrp : TFR64_base<"TFR64">, PredNewRel;
641 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
642 isAsmParserOnly = 1 in
643 def A2_tfrpi : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
645 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
647 // TODO: see if this instruction can be deleted..
648 let isExtendable = 1, opExtendable = 1, opExtentBits = 6,
649 isAsmParserOnly = 1 in {
650 def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u64Imm:$src1),
652 def TFRI64_V2_ext : ALU64_rr<(outs DoubleRegs:$dst),
653 (ins s8Ext:$src1, s8Imm:$src2),
654 "$dst = combine(##$src1, #$src2)">;
657 //===----------------------------------------------------------------------===//
659 //===----------------------------------------------------------------------===//
662 //===----------------------------------------------------------------------===//
664 //===----------------------------------------------------------------------===//
665 // Scalar mux register immediate.
666 let hasSideEffects = 0, isExtentSigned = 1, CextOpcode = "MUX",
667 InputType = "imm", hasNewValue = 1, isExtendable = 1, opExtentBits = 8 in
668 class T_MUX1 <bit MajOp, dag ins, string AsmStr>
669 : ALU32Inst <(outs IntRegs:$Rd), ins, AsmStr>, ImmRegRel {
676 let Inst{27-24} = 0b0011;
677 let Inst{23} = MajOp;
678 let Inst{22-21} = Pu;
679 let Inst{20-16} = Rs;
685 let opExtendable = 2 in
686 def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8Ext:$s8, IntRegs:$Rs),
687 "$Rd = mux($Pu, #$s8, $Rs)">;
689 let opExtendable = 3 in
690 def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
691 "$Rd = mux($Pu, $Rs, #$s8)">;
693 def : Pat<(i32 (select I1:$Pu, s32ImmPred:$s8, I32:$Rs)),
694 (C2_muxri I1:$Pu, s32ImmPred:$s8, I32:$Rs)>;
696 def : Pat<(i32 (select I1:$Pu, I32:$Rs, s32ImmPred:$s8)),
697 (C2_muxir I1:$Pu, I32:$Rs, s32ImmPred:$s8)>;
699 // C2_muxii: Scalar mux immediates.
700 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1,
701 opExtentBits = 8, opExtendable = 2 in
702 def C2_muxii: ALU32Inst <(outs IntRegs:$Rd),
703 (ins PredRegs:$Pu, s8Ext:$s8, s8Imm:$S8),
704 "$Rd = mux($Pu, #$s8, #$S8)" ,
705 [(set (i32 IntRegs:$Rd),
706 (i32 (select I1:$Pu, s32ImmPred:$s8, s8ImmPred:$S8)))] > {
714 let Inst{27-25} = 0b101;
715 let Inst{24-23} = Pu;
716 let Inst{22-16} = S8{7-1};
717 let Inst{13} = S8{0};
722 let isCodeGenOnly = 1, isPseudo = 1 in
723 def MUX64_rr : ALU64_rr<(outs DoubleRegs:$Rd),
724 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
725 ".error \"should not emit\" ", []>;
728 //===----------------------------------------------------------------------===//
729 // template class for non-predicated alu32_2op instructions
730 // - aslh, asrh, sxtb, sxth, zxth
731 //===----------------------------------------------------------------------===//
732 let hasNewValue = 1, opNewValue = 0 in
733 class T_ALU32_2op <string mnemonic, bits<3> minOp> :
734 ALU32Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rs),
735 "$Rd = "#mnemonic#"($Rs)", [] > {
741 let Inst{27-24} = 0b0000;
742 let Inst{23-21} = minOp;
745 let Inst{20-16} = Rs;
748 //===----------------------------------------------------------------------===//
749 // template class for predicated alu32_2op instructions
750 // - aslh, asrh, sxtb, sxth, zxtb, zxth
751 //===----------------------------------------------------------------------===//
752 let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
753 class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot,
755 ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
756 !if(isPredNot, "if (!$Pu", "if ($Pu")
757 #!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> {
764 let Inst{27-24} = 0b0000;
765 let Inst{23-21} = minOp;
767 let Inst{11} = isPredNot;
768 let Inst{10} = isPredNew;
771 let Inst{20-16} = Rs;
774 multiclass ALU32_2op_Pred<string mnemonic, bits<3> minOp, bit PredNot> {
775 let isPredicatedFalse = PredNot in {
776 def NAME : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 0>;
779 let isPredicatedNew = 1 in
780 def NAME#new : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 1>;
784 multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
785 let BaseOpcode = mnemonic in {
786 let isPredicable = 1, hasSideEffects = 0 in
787 def A2_#NAME : T_ALU32_2op<mnemonic, minOp>;
789 let isPredicated = 1, hasSideEffects = 0 in {
790 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
791 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
796 defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
797 defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel;
798 defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
799 defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
800 defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
802 // Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
803 // Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has
804 // predicated forms while 'and' doesn't. Since integrated assembler can't
805 // handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where
806 // immediate operand is set to '255'.
808 let hasNewValue = 1, opNewValue = 0 in
809 class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
810 "$Rd = zxtb($Rs)", [] > { // Rd = and(Rs,255)
817 let Inst{27-22} = 0b011000;
819 let Inst{20-16} = Rs;
820 let Inst{21} = s10{9};
821 let Inst{13-5} = s10{8-0};
824 //Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255)
825 multiclass ZXTB_base <string mnemonic, bits<3> minOp> {
826 let BaseOpcode = mnemonic in {
827 let isPredicable = 1, hasSideEffects = 0 in
828 def A2_#NAME : T_ZXTB;
830 let isPredicated = 1, hasSideEffects = 0 in {
831 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
832 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
837 defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
839 def: Pat<(shl I32:$src1, (i32 16)), (A2_aslh I32:$src1)>;
840 def: Pat<(sra I32:$src1, (i32 16)), (A2_asrh I32:$src1)>;
841 def: Pat<(sext_inreg I32:$src1, i8), (A2_sxtb I32:$src1)>;
842 def: Pat<(sext_inreg I32:$src1, i16), (A2_sxth I32:$src1)>;
844 //===----------------------------------------------------------------------===//
845 // Template class for vector add and avg
846 //===----------------------------------------------------------------------===//
848 class T_VectALU_64 <string opc, bits<3> majOp, bits<3> minOp,
849 bit isSat, bit isRnd, bit isCrnd, bit SwapOps >
850 : ALU64_rr < (outs DoubleRegs:$Rdd),
851 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
852 "$Rdd = "#opc#"($Rss, $Rtt)"#!if(isRnd, ":rnd", "")
853 #!if(isCrnd,":crnd","")
854 #!if(isSat, ":sat", ""),
855 [], "", ALU64_tc_2_SLOT23 > {
862 let Inst{27-24} = 0b0011;
863 let Inst{23-21} = majOp;
864 let Inst{20-16} = !if (SwapOps, Rtt, Rss);
865 let Inst{12-8} = !if (SwapOps, Rss, Rtt);
866 let Inst{7-5} = minOp;
870 // ALU64 - Vector add
871 // Rdd=vadd[u][bhw](Rss,Rtt)
872 let Itinerary = ALU64_tc_1_SLOT23 in {
873 def A2_vaddub : T_VectALU_64 < "vaddub", 0b000, 0b000, 0, 0, 0, 0>;
874 def A2_vaddh : T_VectALU_64 < "vaddh", 0b000, 0b010, 0, 0, 0, 0>;
875 def A2_vaddw : T_VectALU_64 < "vaddw", 0b000, 0b101, 0, 0, 0, 0>;
878 // Rdd=vadd[u][bhw](Rss,Rtt):sat
879 let Defs = [USR_OVF] in {
880 def A2_vaddubs : T_VectALU_64 < "vaddub", 0b000, 0b001, 1, 0, 0, 0>;
881 def A2_vaddhs : T_VectALU_64 < "vaddh", 0b000, 0b011, 1, 0, 0, 0>;
882 def A2_vadduhs : T_VectALU_64 < "vadduh", 0b000, 0b100, 1, 0, 0, 0>;
883 def A2_vaddws : T_VectALU_64 < "vaddw", 0b000, 0b110, 1, 0, 0, 0>;
886 // ALU64 - Vector average
887 // Rdd=vavg[u][bhw](Rss,Rtt)
888 let Itinerary = ALU64_tc_1_SLOT23 in {
889 def A2_vavgub : T_VectALU_64 < "vavgub", 0b010, 0b000, 0, 0, 0, 0>;
890 def A2_vavgh : T_VectALU_64 < "vavgh", 0b010, 0b010, 0, 0, 0, 0>;
891 def A2_vavguh : T_VectALU_64 < "vavguh", 0b010, 0b101, 0, 0, 0, 0>;
892 def A2_vavgw : T_VectALU_64 < "vavgw", 0b011, 0b000, 0, 0, 0, 0>;
893 def A2_vavguw : T_VectALU_64 < "vavguw", 0b011, 0b011, 0, 0, 0, 0>;
896 // Rdd=vavg[u][bhw](Rss,Rtt)[:rnd|:crnd]
897 def A2_vavgubr : T_VectALU_64 < "vavgub", 0b010, 0b001, 0, 1, 0, 0>;
898 def A2_vavghr : T_VectALU_64 < "vavgh", 0b010, 0b011, 0, 1, 0, 0>;
899 def A2_vavghcr : T_VectALU_64 < "vavgh", 0b010, 0b100, 0, 0, 1, 0>;
900 def A2_vavguhr : T_VectALU_64 < "vavguh", 0b010, 0b110, 0, 1, 0, 0>;
902 def A2_vavgwr : T_VectALU_64 < "vavgw", 0b011, 0b001, 0, 1, 0, 0>;
903 def A2_vavgwcr : T_VectALU_64 < "vavgw", 0b011, 0b010, 0, 0, 1, 0>;
904 def A2_vavguwr : T_VectALU_64 < "vavguw", 0b011, 0b100, 0, 1, 0, 0>;
906 // Rdd=vnavg[bh](Rss,Rtt)
907 let Itinerary = ALU64_tc_1_SLOT23 in {
908 def A2_vnavgh : T_VectALU_64 < "vnavgh", 0b100, 0b000, 0, 0, 0, 1>;
909 def A2_vnavgw : T_VectALU_64 < "vnavgw", 0b100, 0b011, 0, 0, 0, 1>;
912 // Rdd=vnavg[bh](Rss,Rtt)[:rnd|:crnd]:sat
913 let Defs = [USR_OVF] in {
914 def A2_vnavghr : T_VectALU_64 < "vnavgh", 0b100, 0b001, 1, 1, 0, 1>;
915 def A2_vnavghcr : T_VectALU_64 < "vnavgh", 0b100, 0b010, 1, 0, 1, 1>;
916 def A2_vnavgwr : T_VectALU_64 < "vnavgw", 0b100, 0b100, 1, 1, 0, 1>;
917 def A2_vnavgwcr : T_VectALU_64 < "vnavgw", 0b100, 0b110, 1, 0, 1, 1>;
920 // Rdd=vsub[u][bh](Rss,Rtt)
921 let Itinerary = ALU64_tc_1_SLOT23 in {
922 def A2_vsubub : T_VectALU_64 < "vsubub", 0b001, 0b000, 0, 0, 0, 1>;
923 def A2_vsubh : T_VectALU_64 < "vsubh", 0b001, 0b010, 0, 0, 0, 1>;
924 def A2_vsubw : T_VectALU_64 < "vsubw", 0b001, 0b101, 0, 0, 0, 1>;
927 // Rdd=vsub[u][bh](Rss,Rtt):sat
928 let Defs = [USR_OVF] in {
929 def A2_vsububs : T_VectALU_64 < "vsubub", 0b001, 0b001, 1, 0, 0, 1>;
930 def A2_vsubhs : T_VectALU_64 < "vsubh", 0b001, 0b011, 1, 0, 0, 1>;
931 def A2_vsubuhs : T_VectALU_64 < "vsubuh", 0b001, 0b100, 1, 0, 0, 1>;
932 def A2_vsubws : T_VectALU_64 < "vsubw", 0b001, 0b110, 1, 0, 0, 1>;
935 // Rdd=vmax[u][bhw](Rss,Rtt)
936 def A2_vmaxb : T_VectALU_64 < "vmaxb", 0b110, 0b110, 0, 0, 0, 1>;
937 def A2_vmaxub : T_VectALU_64 < "vmaxub", 0b110, 0b000, 0, 0, 0, 1>;
938 def A2_vmaxh : T_VectALU_64 < "vmaxh", 0b110, 0b001, 0, 0, 0, 1>;
939 def A2_vmaxuh : T_VectALU_64 < "vmaxuh", 0b110, 0b010, 0, 0, 0, 1>;
940 def A2_vmaxw : T_VectALU_64 < "vmaxw", 0b110, 0b011, 0, 0, 0, 1>;
941 def A2_vmaxuw : T_VectALU_64 < "vmaxuw", 0b101, 0b101, 0, 0, 0, 1>;
943 // Rdd=vmin[u][bhw](Rss,Rtt)
944 def A2_vminb : T_VectALU_64 < "vminb", 0b110, 0b111, 0, 0, 0, 1>;
945 def A2_vminub : T_VectALU_64 < "vminub", 0b101, 0b000, 0, 0, 0, 1>;
946 def A2_vminh : T_VectALU_64 < "vminh", 0b101, 0b001, 0, 0, 0, 1>;
947 def A2_vminuh : T_VectALU_64 < "vminuh", 0b101, 0b010, 0, 0, 0, 1>;
948 def A2_vminw : T_VectALU_64 < "vminw", 0b101, 0b011, 0, 0, 0, 1>;
949 def A2_vminuw : T_VectALU_64 < "vminuw", 0b101, 0b100, 0, 0, 0, 1>;
951 //===----------------------------------------------------------------------===//
952 // Template class for vector compare
953 //===----------------------------------------------------------------------===//
954 let hasSideEffects = 0 in
955 class T_vcmp <string Str, bits<4> minOp>
956 : ALU64_rr <(outs PredRegs:$Pd),
957 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
958 "$Pd = "#Str#"($Rss, $Rtt)", [],
959 "", ALU64_tc_2early_SLOT23> {
966 let Inst{27-23} = 0b00100;
967 let Inst{13} = minOp{3};
968 let Inst{7-5} = minOp{2-0};
970 let Inst{20-16} = Rss;
971 let Inst{12-8} = Rtt;
974 class T_vcmp_pat<InstHexagon MI, PatFrag Op, ValueType T>
975 : Pat<(i1 (Op (T DoubleRegs:$Rss), (T DoubleRegs:$Rtt))),
976 (i1 (MI DoubleRegs:$Rss, DoubleRegs:$Rtt))>;
978 // Vector compare bytes
979 def A2_vcmpbeq : T_vcmp <"vcmpb.eq", 0b0110>;
980 def A2_vcmpbgtu : T_vcmp <"vcmpb.gtu", 0b0111>;
982 // Vector compare halfwords
983 def A2_vcmpheq : T_vcmp <"vcmph.eq", 0b0011>;
984 def A2_vcmphgt : T_vcmp <"vcmph.gt", 0b0100>;
985 def A2_vcmphgtu : T_vcmp <"vcmph.gtu", 0b0101>;
987 // Vector compare words
988 def A2_vcmpweq : T_vcmp <"vcmpw.eq", 0b0000>;
989 def A2_vcmpwgt : T_vcmp <"vcmpw.gt", 0b0001>;
990 def A2_vcmpwgtu : T_vcmp <"vcmpw.gtu", 0b0010>;
992 def: T_vcmp_pat<A2_vcmpbeq, seteq, v8i8>;
993 def: T_vcmp_pat<A2_vcmpbgtu, setugt, v8i8>;
994 def: T_vcmp_pat<A2_vcmpheq, seteq, v4i16>;
995 def: T_vcmp_pat<A2_vcmphgt, setgt, v4i16>;
996 def: T_vcmp_pat<A2_vcmphgtu, setugt, v4i16>;
997 def: T_vcmp_pat<A2_vcmpweq, seteq, v2i32>;
998 def: T_vcmp_pat<A2_vcmpwgt, setgt, v2i32>;
999 def: T_vcmp_pat<A2_vcmpwgtu, setugt, v2i32>;
1001 //===----------------------------------------------------------------------===//
1003 //===----------------------------------------------------------------------===//
1006 //===----------------------------------------------------------------------===//
1008 //===----------------------------------------------------------------------===//
1009 // No bits needed. If cmp.ge is found the assembler parser will
1010 // transform it to cmp.gt subtracting 1 from the immediate.
1011 let isPseudo = 1 in {
1012 def C2_cmpgei: ALU32Inst <
1013 (outs PredRegs:$Pd), (ins IntRegs:$Rs, s8Ext:$s8),
1014 "$Pd = cmp.ge($Rs, #$s8)">;
1015 def C2_cmpgeui: ALU32Inst <
1016 (outs PredRegs:$Pd), (ins IntRegs:$Rs, u8Ext:$s8),
1017 "$Pd = cmp.geu($Rs, #$s8)">;
1021 //===----------------------------------------------------------------------===//
1023 //===----------------------------------------------------------------------===//
1026 //===----------------------------------------------------------------------===//
1028 //===----------------------------------------------------------------------===//
1030 //===----------------------------------------------------------------------===//
1032 // Add/Subtract halfword
1033 // Rd=add(Rt.L,Rs.[HL])[:sat]
1034 // Rd=sub(Rt.L,Rs.[HL])[:sat]
1035 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
1036 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
1037 //===----------------------------------------------------------------------===//
1039 let hasNewValue = 1, opNewValue = 0 in
1040 class T_XTYPE_ADD_SUB <bits<2> LHbits, bit isSat, bit hasShift, bit isSub>
1041 : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1042 "$Rd = "#!if(isSub,"sub","add")#"($Rt."
1043 #!if(hasShift, !if(LHbits{1},"h","l"),"l") #", $Rs."
1044 #!if(hasShift, !if(LHbits{0},"h)","l)"), !if(LHbits{1},"h)","l)"))
1045 #!if(isSat,":sat","")
1046 #!if(hasShift,":<<16",""), [], "", ALU64_tc_1_SLOT23> {
1050 let IClass = 0b1101;
1052 let Inst{27-23} = 0b01010;
1053 let Inst{22} = hasShift;
1054 let Inst{21} = isSub;
1055 let Inst{7} = isSat;
1056 let Inst{6-5} = LHbits;
1058 let Inst{12-8} = Rt;
1059 let Inst{20-16} = Rs;
1062 //Rd=sub(Rt.L,Rs.[LH])
1063 def A2_subh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 1>;
1064 def A2_subh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 1>;
1066 //Rd=add(Rt.L,Rs.[LH])
1067 def A2_addh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 0>;
1068 def A2_addh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 0>;
1070 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF] in {
1071 //Rd=sub(Rt.L,Rs.[LH]):sat
1072 def A2_subh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 1>;
1073 def A2_subh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 1>;
1075 //Rd=add(Rt.L,Rs.[LH]):sat
1076 def A2_addh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 0>;
1077 def A2_addh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 0>;
1080 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
1081 def A2_subh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 1>;
1082 def A2_subh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 1>;
1083 def A2_subh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 1>;
1084 def A2_subh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 1>;
1086 //Rd=add(Rt.[LH],Rs.[LH]):<<16
1087 def A2_addh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 0>;
1088 def A2_addh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 0>;
1089 def A2_addh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 0>;
1090 def A2_addh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 0>;
1092 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF] in {
1093 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
1094 def A2_subh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 1>;
1095 def A2_subh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 1>;
1096 def A2_subh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 1>;
1097 def A2_subh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 1>;
1099 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
1100 def A2_addh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 0>;
1101 def A2_addh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 0>;
1102 def A2_addh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 0>;
1103 def A2_addh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 0>;
1107 def: Pat<(sext_inreg (add I32:$src1, I32:$src2), i16),
1108 (A2_addh_l16_ll I32:$src1, I32:$src2)>;
1110 def: Pat<(sra (add (shl I32:$src1, (i32 16)), I32:$src2), (i32 16)),
1111 (A2_addh_l16_hl I32:$src1, I32:$src2)>;
1113 def: Pat<(shl (add I32:$src1, I32:$src2), (i32 16)),
1114 (A2_addh_h16_ll I32:$src1, I32:$src2)>;
1116 // Subtract halfword.
1117 def: Pat<(sext_inreg (sub I32:$src1, I32:$src2), i16),
1118 (A2_subh_l16_ll I32:$src1, I32:$src2)>;
1120 def: Pat<(shl (sub I32:$src1, I32:$src2), (i32 16)),
1121 (A2_subh_h16_ll I32:$src1, I32:$src2)>;
1123 let hasSideEffects = 0, hasNewValue = 1 in
1124 def S2_parityp: ALU64Inst<(outs IntRegs:$Rd),
1125 (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1126 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1131 let IClass = 0b1101;
1132 let Inst{27-24} = 0b0000;
1133 let Inst{20-16} = Rs;
1134 let Inst{12-8} = Rt;
1138 let hasNewValue = 1, opNewValue = 0, hasSideEffects = 0 in
1139 class T_XTYPE_MIN_MAX < bit isMax, bit isUnsigned >
1140 : ALU64Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1141 "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
1142 #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
1147 let IClass = 0b1101;
1149 let Inst{27-23} = 0b01011;
1150 let Inst{22-21} = !if(isMax, 0b10, 0b01);
1151 let Inst{7} = isUnsigned;
1153 let Inst{12-8} = !if(isMax, Rs, Rt);
1154 let Inst{20-16} = !if(isMax, Rt, Rs);
1157 def A2_min : T_XTYPE_MIN_MAX < 0, 0 >;
1158 def A2_minu : T_XTYPE_MIN_MAX < 0, 1 >;
1159 def A2_max : T_XTYPE_MIN_MAX < 1, 0 >;
1160 def A2_maxu : T_XTYPE_MIN_MAX < 1, 1 >;
1162 // Here, depending on the operand being selected, we'll either generate a
1163 // min or max instruction.
1165 // (a>b)?a:b --> max(a,b) => Here check performed is '>' and the value selected
1166 // is the larger of two. So, the corresponding HexagonInst is passed in 'Inst'.
1167 // (a>b)?b:a --> min(a,b) => Here check performed is '>' but the smaller value
1168 // is selected and the corresponding HexagonInst is passed in 'SwapInst'.
1170 multiclass T_MinMax_pats <PatFrag Op, RegisterClass RC, ValueType VT,
1171 InstHexagon Inst, InstHexagon SwapInst> {
1172 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1173 (VT RC:$src1), (VT RC:$src2)),
1174 (Inst RC:$src1, RC:$src2)>;
1175 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1176 (VT RC:$src2), (VT RC:$src1)),
1177 (SwapInst RC:$src1, RC:$src2)>;
1181 multiclass MinMax_pats <PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
1182 defm: T_MinMax_pats<Op, IntRegs, i32, Inst, SwapInst>;
1184 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1185 (i32 PositiveHalfWord:$src2))),
1186 (i32 PositiveHalfWord:$src1),
1187 (i32 PositiveHalfWord:$src2))), i16),
1188 (Inst IntRegs:$src1, IntRegs:$src2)>;
1190 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1191 (i32 PositiveHalfWord:$src2))),
1192 (i32 PositiveHalfWord:$src2),
1193 (i32 PositiveHalfWord:$src1))), i16),
1194 (SwapInst IntRegs:$src1, IntRegs:$src2)>;
1197 let AddedComplexity = 200 in {
1198 defm: MinMax_pats<setge, A2_max, A2_min>;
1199 defm: MinMax_pats<setgt, A2_max, A2_min>;
1200 defm: MinMax_pats<setle, A2_min, A2_max>;
1201 defm: MinMax_pats<setlt, A2_min, A2_max>;
1202 defm: MinMax_pats<setuge, A2_maxu, A2_minu>;
1203 defm: MinMax_pats<setugt, A2_maxu, A2_minu>;
1204 defm: MinMax_pats<setule, A2_minu, A2_maxu>;
1205 defm: MinMax_pats<setult, A2_minu, A2_maxu>;
1208 class T_cmp64_rr<string mnemonic, bits<3> MinOp, bit IsComm>
1209 : ALU64_rr<(outs PredRegs:$Pd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1210 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", ALU64_tc_2early_SLOT23> {
1212 let isCommutable = IsComm;
1213 let hasSideEffects = 0;
1219 let IClass = 0b1101;
1220 let Inst{27-21} = 0b0010100;
1221 let Inst{20-16} = Rs;
1222 let Inst{12-8} = Rt;
1223 let Inst{7-5} = MinOp;
1227 def C2_cmpeqp : T_cmp64_rr<"cmp.eq", 0b000, 1>;
1228 def C2_cmpgtp : T_cmp64_rr<"cmp.gt", 0b010, 0>;
1229 def C2_cmpgtup : T_cmp64_rr<"cmp.gtu", 0b100, 0>;
1231 class T_cmp64_rr_pat<InstHexagon MI, PatFrag CmpOp>
1232 : Pat<(i1 (CmpOp (i64 DoubleRegs:$Rs), (i64 DoubleRegs:$Rt))),
1233 (i1 (MI DoubleRegs:$Rs, DoubleRegs:$Rt))>;
1235 def: T_cmp64_rr_pat<C2_cmpeqp, seteq>;
1236 def: T_cmp64_rr_pat<C2_cmpgtp, setgt>;
1237 def: T_cmp64_rr_pat<C2_cmpgtup, setugt>;
1238 def: T_cmp64_rr_pat<C2_cmpgtp, RevCmp<setlt>>;
1239 def: T_cmp64_rr_pat<C2_cmpgtup, RevCmp<setult>>;
1241 def C2_vmux : ALU64_rr<(outs DoubleRegs:$Rd),
1242 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
1243 "$Rd = vmux($Pu, $Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
1244 let hasSideEffects = 0;
1251 let IClass = 0b1101;
1252 let Inst{27-24} = 0b0001;
1253 let Inst{20-16} = Rs;
1254 let Inst{12-8} = Rt;
1259 class T_ALU64_rr<string mnemonic, string suffix, bits<4> RegType,
1260 bits<3> MajOp, bits<3> MinOp, bit OpsRev, bit IsComm,
1262 : ALU64_rr<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1263 "$Rd = " #mnemonic# "($Rs, " #Op2Pfx# "$Rt)" #suffix, [],
1264 "", ALU64_tc_1_SLOT23> {
1265 let hasSideEffects = 0;
1266 let isCommutable = IsComm;
1272 let IClass = 0b1101;
1273 let Inst{27-24} = RegType;
1274 let Inst{23-21} = MajOp;
1275 let Inst{20-16} = !if (OpsRev,Rt,Rs);
1276 let Inst{12-8} = !if (OpsRev,Rs,Rt);
1277 let Inst{7-5} = MinOp;
1281 class T_ALU64_arith<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit IsSat,
1282 bit OpsRev, bit IsComm>
1283 : T_ALU64_rr<mnemonic, !if(IsSat,":sat",""), 0b0011, MajOp, MinOp, OpsRev,
1286 def A2_addp : T_ALU64_arith<"add", 0b000, 0b111, 0, 0, 1>;
1287 def A2_subp : T_ALU64_arith<"sub", 0b001, 0b111, 0, 1, 0>;
1289 def: Pat<(i64 (add I64:$Rs, I64:$Rt)), (A2_addp I64:$Rs, I64:$Rt)>;
1290 def: Pat<(i64 (sub I64:$Rs, I64:$Rt)), (A2_subp I64:$Rs, I64:$Rt)>;
1292 class T_ALU64_logical<string mnemonic, bits<3> MinOp, bit OpsRev, bit IsComm,
1294 : T_ALU64_rr<mnemonic, "", 0b0011, 0b111, MinOp, OpsRev, IsComm,
1297 def A2_andp : T_ALU64_logical<"and", 0b000, 0, 1, 0>;
1298 def A2_orp : T_ALU64_logical<"or", 0b010, 0, 1, 0>;
1299 def A2_xorp : T_ALU64_logical<"xor", 0b100, 0, 1, 0>;
1301 def: Pat<(i64 (and I64:$Rs, I64:$Rt)), (A2_andp I64:$Rs, I64:$Rt)>;
1302 def: Pat<(i64 (or I64:$Rs, I64:$Rt)), (A2_orp I64:$Rs, I64:$Rt)>;
1303 def: Pat<(i64 (xor I64:$Rs, I64:$Rt)), (A2_xorp I64:$Rs, I64:$Rt)>;
1305 //===----------------------------------------------------------------------===//
1307 //===----------------------------------------------------------------------===//
1309 //===----------------------------------------------------------------------===//
1311 //===----------------------------------------------------------------------===//
1313 //===----------------------------------------------------------------------===//
1315 //===----------------------------------------------------------------------===//
1317 //===----------------------------------------------------------------------===//
1319 //===----------------------------------------------------------------------===//
1321 //===----------------------------------------------------------------------===//
1323 //===----------------------------------------------------------------------===//
1325 //===----------------------------------------------------------------------===//
1327 //===----------------------------------------------------------------------===//
1328 // Logical reductions on predicates.
1330 // Looping instructions.
1332 // Pipelined looping instructions.
1334 // Logical operations on predicates.
1335 let hasSideEffects = 0 in
1336 class T_LOGICAL_1OP<string MnOp, bits<2> OpBits>
1337 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps),
1338 "$Pd = " # MnOp # "($Ps)", [], "", CR_tc_2early_SLOT23> {
1342 let IClass = 0b0110;
1343 let Inst{27-23} = 0b10111;
1344 let Inst{22-21} = OpBits;
1346 let Inst{17-16} = Ps;
1351 def C2_any8 : T_LOGICAL_1OP<"any8", 0b00>;
1352 def C2_all8 : T_LOGICAL_1OP<"all8", 0b01>;
1353 def C2_not : T_LOGICAL_1OP<"not", 0b10>;
1355 def: Pat<(i1 (not (i1 PredRegs:$Ps))),
1356 (C2_not PredRegs:$Ps)>;
1358 let hasSideEffects = 0 in
1359 class T_LOGICAL_2OP<string MnOp, bits<3> OpBits, bit IsNeg, bit Rev>
1360 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps, PredRegs:$Pt),
1361 "$Pd = " # MnOp # "($Ps, " # !if (IsNeg,"!","") # "$Pt)",
1362 [], "", CR_tc_2early_SLOT23> {
1367 let IClass = 0b0110;
1368 let Inst{27-24} = 0b1011;
1369 let Inst{23-21} = OpBits;
1371 let Inst{17-16} = !if(Rev,Pt,Ps); // Rs and Rt are reversed for some
1372 let Inst{13} = 0b0; // instructions.
1373 let Inst{9-8} = !if(Rev,Ps,Pt);
1377 def C2_and : T_LOGICAL_2OP<"and", 0b000, 0, 1>;
1378 def C2_or : T_LOGICAL_2OP<"or", 0b001, 0, 1>;
1379 def C2_xor : T_LOGICAL_2OP<"xor", 0b010, 0, 0>;
1380 def C2_andn : T_LOGICAL_2OP<"and", 0b011, 1, 1>;
1381 def C2_orn : T_LOGICAL_2OP<"or", 0b111, 1, 1>;
1383 def: Pat<(i1 (and I1:$Ps, I1:$Pt)), (C2_and I1:$Ps, I1:$Pt)>;
1384 def: Pat<(i1 (or I1:$Ps, I1:$Pt)), (C2_or I1:$Ps, I1:$Pt)>;
1385 def: Pat<(i1 (xor I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>;
1386 def: Pat<(i1 (and I1:$Ps, (not I1:$Pt))), (C2_andn I1:$Ps, I1:$Pt)>;
1387 def: Pat<(i1 (or I1:$Ps, (not I1:$Pt))), (C2_orn I1:$Ps, I1:$Pt)>;
1389 let hasSideEffects = 0, hasNewValue = 1 in
1390 def C2_vitpack : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps, PredRegs:$Pt),
1391 "$Rd = vitpack($Ps, $Pt)", [], "", S_2op_tc_1_SLOT23> {
1396 let IClass = 0b1000;
1397 let Inst{27-24} = 0b1001;
1398 let Inst{22-21} = 0b00;
1399 let Inst{17-16} = Ps;
1404 let hasSideEffects = 0 in
1405 def C2_mask : SInst<(outs DoubleRegs:$Rd), (ins PredRegs:$Pt),
1406 "$Rd = mask($Pt)", [], "", S_2op_tc_1_SLOT23> {
1410 let IClass = 0b1000;
1411 let Inst{27-24} = 0b0110;
1416 // User control register transfer.
1417 //===----------------------------------------------------------------------===//
1419 //===----------------------------------------------------------------------===//
1421 //===----------------------------------------------------------------------===//
1423 //===----------------------------------------------------------------------===//
1425 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
1426 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1427 def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>;
1429 class CondStr<string CReg, bit True, bit New> {
1430 string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") ";
1432 class JumpOpcStr<string Mnemonic, bit New, bit Taken> {
1433 string S = Mnemonic # !if(Taken, ":t", !if(New, ":nt", ""));
1436 let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0,
1438 isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
1439 opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in
1440 class T_JMP<string ExtStr>
1441 : JInst<(outs), (ins brtarget:$dst),
1442 "jump " # ExtStr # "$dst",
1443 [], "", J_tc_2early_SLOT23> {
1445 let IClass = 0b0101;
1447 let Inst{27-25} = 0b100;
1448 let Inst{24-16} = dst{23-15};
1449 let Inst{13-1} = dst{14-2};
1452 let isBranch = 1, Defs = [PC], hasSideEffects = 0, isPredicated = 1,
1453 isExtendable = 1, opExtendable = 1, isExtentSigned = 1,
1454 opExtentBits = 17, opExtentAlign = 2, InputType = "imm" in
1455 class T_JMP_c<bit PredNot, bit isPredNew, bit isTak, string ExtStr>
1456 : JInst<(outs), (ins PredRegs:$src, brtarget:$dst),
1457 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
1458 JumpOpcStr<"jump", isPredNew, isTak>.S # " " #
1460 [], "", J_tc_2early_SLOT23>, ImmRegRel {
1461 let isTaken = isTak;
1462 let isPredicatedFalse = PredNot;
1463 let isPredicatedNew = isPredNew;
1467 let IClass = 0b0101;
1469 let Inst{27-24} = 0b1100;
1470 let Inst{21} = PredNot;
1471 let Inst{12} = isTak;
1472 let Inst{11} = isPredNew;
1473 let Inst{9-8} = src;
1474 let Inst{23-22} = dst{16-15};
1475 let Inst{20-16} = dst{14-10};
1476 let Inst{13} = dst{9};
1477 let Inst{7-1} = dst{8-2};
1480 multiclass JMP_Pred<bit PredNot, string ExtStr> {
1481 def NAME : T_JMP_c<PredNot, 0, 0, ExtStr>; // not taken
1483 def NAME#newpt : T_JMP_c<PredNot, 1, 1, ExtStr>; // taken
1484 def NAME#new : T_JMP_c<PredNot, 1, 0, ExtStr>; // not taken
1487 multiclass JMP_base<string BaseOp, string ExtStr> {
1488 let BaseOpcode = BaseOp in {
1489 def NAME : T_JMP<ExtStr>;
1490 defm t : JMP_Pred<0, ExtStr>;
1491 defm f : JMP_Pred<1, ExtStr>;
1495 // Jumps to address stored in a register, JUMPR_MISC
1496 // if ([[!]P[.new]]) jumpr[:t/nt] Rs
1497 let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC],
1498 isPredicable = 1, hasSideEffects = 0, InputType = "reg" in
1500 : JRInst<(outs), (ins IntRegs:$dst),
1501 "jumpr $dst", [], "", J_tc_2early_SLOT2> {
1504 let IClass = 0b0101;
1505 let Inst{27-21} = 0b0010100;
1506 let Inst{20-16} = dst;
1509 let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1,
1510 hasSideEffects = 0, InputType = "reg" in
1511 class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>
1512 : JRInst <(outs), (ins PredRegs:$src, IntRegs:$dst),
1513 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
1514 JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst", [],
1515 "", J_tc_2early_SLOT2> {
1517 let isTaken = isTak;
1518 let isPredicatedFalse = PredNot;
1519 let isPredicatedNew = isPredNew;
1523 let IClass = 0b0101;
1525 let Inst{27-22} = 0b001101;
1526 let Inst{21} = PredNot;
1527 let Inst{20-16} = dst;
1528 let Inst{12} = isTak;
1529 let Inst{11} = isPredNew;
1530 let Inst{9-8} = src;
1533 multiclass JMPR_Pred<bit PredNot> {
1534 def NAME : T_JMPr_c<PredNot, 0, 0>; // not taken
1536 def NAME#newpt : T_JMPr_c<PredNot, 1, 1>; // taken
1537 def NAME#new : T_JMPr_c<PredNot, 1, 0>; // not taken
1540 multiclass JMPR_base<string BaseOp> {
1541 let BaseOpcode = BaseOp in {
1543 defm t : JMPR_Pred<0>;
1544 defm f : JMPR_Pred<1>;
1548 let isCall = 1, hasSideEffects = 1 in
1549 class JUMPR_MISC_CALLR<bit isPred, bit isPredNot,
1550 dag InputDag = (ins IntRegs:$Rs)>
1551 : JRInst<(outs), InputDag,
1552 !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs",
1553 "if ($Pu) callr $Rs"),
1555 [], "", J_tc_2early_SLOT2> {
1558 let isPredicated = isPred;
1559 let isPredicatedFalse = isPredNot;
1561 let IClass = 0b0101;
1562 let Inst{27-25} = 0b000;
1563 let Inst{24-23} = !if (isPred, 0b10, 0b01);
1565 let Inst{21} = isPredNot;
1566 let Inst{9-8} = !if (isPred, Pu, 0b00);
1567 let Inst{20-16} = Rs;
1571 let Defs = VolatileV3.Regs in {
1572 def J2_callrt : JUMPR_MISC_CALLR<1, 0, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1573 def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1576 let isTerminator = 1, hasSideEffects = 0 in {
1577 defm J2_jump : JMP_base<"JMP", "">, PredNewRel;
1579 // Deal with explicit assembly
1580 // - never extened a jump #, always extend a jump ##
1581 let isAsmParserOnly = 1 in {
1582 defm J2_jump_ext : JMP_base<"JMP", "##">;
1583 defm J2_jump_noext : JMP_base<"JMP", "#">;
1586 defm J2_jumpr : JMPR_base<"JMPr">, PredNewRel;
1588 let isReturn = 1, isCodeGenOnly = 1 in
1589 defm JMPret : JMPR_base<"JMPret">, PredNewRel;
1592 def: Pat<(br bb:$dst),
1593 (J2_jump brtarget:$dst)>;
1595 (JMPret (i32 R31))>;
1596 def: Pat<(brcond (i1 PredRegs:$src1), bb:$offset),
1597 (J2_jumpt PredRegs:$src1, bb:$offset)>;
1599 // A return through builtin_eh_return.
1600 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
1601 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
1602 def EH_RETURN_JMPR : T_JMPr;
1604 def: Pat<(eh_return),
1605 (EH_RETURN_JMPR (i32 R31))>;
1606 def: Pat<(brind (i32 IntRegs:$dst)),
1607 (J2_jumpr IntRegs:$dst)>;
1609 //===----------------------------------------------------------------------===//
1611 //===----------------------------------------------------------------------===//
1613 //===----------------------------------------------------------------------===//
1615 //===----------------------------------------------------------------------===//
1617 // Load - Base with Immediate offset addressing mode
1618 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, AddedComplexity = 20 in
1619 class T_load_io <string mnemonic, RegisterClass RC, bits<4> MajOp,
1621 : LDInst<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1622 "$dst = "#mnemonic#"($src1 + #$offset)", []>, AddrModeRel {
1627 bits<11> offsetBits;
1629 string ImmOpStr = !cast<string>(ImmOp);
1630 let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), offset{13-3},
1631 !if (!eq(ImmOpStr, "s11_2Ext"), offset{12-2},
1632 !if (!eq(ImmOpStr, "s11_1Ext"), offset{11-1},
1633 /* s11_0Ext */ offset{10-0})));
1634 let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14,
1635 !if (!eq(ImmOpStr, "s11_2Ext"), 13,
1636 !if (!eq(ImmOpStr, "s11_1Ext"), 12,
1637 /* s11_0Ext */ 11)));
1638 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
1640 let IClass = 0b1001;
1643 let Inst{26-25} = offsetBits{10-9};
1644 let Inst{24-21} = MajOp;
1645 let Inst{20-16} = src1;
1646 let Inst{13-5} = offsetBits{8-0};
1647 let Inst{4-0} = dst;
1650 let opExtendable = 3, isExtentSigned = 0, isPredicated = 1 in
1651 class T_pload_io <string mnemonic, RegisterClass RC, bits<4>MajOp,
1652 Operand ImmOp, bit isNot, bit isPredNew>
1653 : LDInst<(outs RC:$dst),
1654 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1655 "if ("#!if(isNot, "!$src1", "$src1")
1656 #!if(isPredNew, ".new", "")
1657 #") $dst = "#mnemonic#"($src2 + #$offset)",
1658 [],"", V2LDST_tc_ld_SLOT01> , AddrModeRel {
1664 string ImmOpStr = !cast<string>(ImmOp);
1666 let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), offset{8-3},
1667 !if (!eq(ImmOpStr, "u6_2Ext"), offset{7-2},
1668 !if (!eq(ImmOpStr, "u6_1Ext"), offset{6-1},
1669 /* u6_0Ext */ offset{5-0})));
1670 let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9,
1671 !if (!eq(ImmOpStr, "u6_2Ext"), 8,
1672 !if (!eq(ImmOpStr, "u6_1Ext"), 7,
1674 let hasNewValue = !if (!eq(ImmOpStr, "u6_3Ext"), 0, 1);
1675 let isPredicatedNew = isPredNew;
1676 let isPredicatedFalse = isNot;
1678 let IClass = 0b0100;
1682 let Inst{26} = isNot;
1683 let Inst{25} = isPredNew;
1684 let Inst{24-21} = MajOp;
1685 let Inst{20-16} = src2;
1687 let Inst{12-11} = src1;
1688 let Inst{10-5} = offsetBits;
1689 let Inst{4-0} = dst;
1692 let isExtendable = 1, hasSideEffects = 0, addrMode = BaseImmOffset in
1693 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1694 Operand ImmOp, Operand predImmOp, bits<4>MajOp> {
1695 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1696 let isPredicable = 1 in
1697 def L2_#NAME#_io : T_load_io <mnemonic, RC, MajOp, ImmOp>;
1700 def L2_p#NAME#t_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 0>;
1701 def L2_p#NAME#f_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 0>;
1704 def L2_p#NAME#tnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 1>;
1705 def L2_p#NAME#fnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 1>;
1709 let accessSize = ByteAccess in {
1710 defm loadrb: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext, 0b1000>;
1711 defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>;
1714 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1715 defm loadrh: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, 0b1010>;
1716 defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>;
1719 let accessSize = WordAccess, opExtentAlign = 2 in
1720 defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>;
1722 let accessSize = DoubleWordAccess, opExtentAlign = 3 in
1723 defm loadrd: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, 0b1110>;
1725 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1726 def L2_loadbsw2_io: T_load_io<"membh", IntRegs, 0b0001, s11_1Ext>;
1727 def L2_loadbzw2_io: T_load_io<"memubh", IntRegs, 0b0011, s11_1Ext>;
1730 let accessSize = WordAccess, opExtentAlign = 2 in {
1731 def L2_loadbzw4_io: T_load_io<"memubh", DoubleRegs, 0b0101, s11_2Ext>;
1732 def L2_loadbsw4_io: T_load_io<"membh", DoubleRegs, 0b0111, s11_2Ext>;
1735 let addrMode = BaseImmOffset, isExtendable = 1, hasSideEffects = 0,
1736 opExtendable = 3, isExtentSigned = 1 in
1737 class T_loadalign_io <string str, bits<4> MajOp, Operand ImmOp>
1738 : LDInst<(outs DoubleRegs:$dst),
1739 (ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1740 "$dst = "#str#"($src2 + #$offset)", [],
1741 "$src1 = $dst">, AddrModeRel {
1746 bits<11> offsetBits;
1748 let offsetBits = !if (!eq(!cast<string>(ImmOp), "s11_1Ext"), offset{11-1},
1749 /* s11_0Ext */ offset{10-0});
1750 let IClass = 0b1001;
1753 let Inst{26-25} = offsetBits{10-9};
1754 let Inst{24-21} = MajOp;
1755 let Inst{20-16} = src2;
1756 let Inst{13-5} = offsetBits{8-0};
1757 let Inst{4-0} = dst;
1760 let accessSize = HalfWordAccess, opExtentBits = 12, opExtentAlign = 1 in
1761 def L2_loadalignh_io: T_loadalign_io <"memh_fifo", 0b0010, s11_1Ext>;
1763 let accessSize = ByteAccess, opExtentBits = 11 in
1764 def L2_loadalignb_io: T_loadalign_io <"memb_fifo", 0b0100, s11_0Ext>;
1766 // Patterns to select load-indexed (i.e. load from base+offset).
1767 multiclass Loadx_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
1769 def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>;
1770 def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))),
1771 (VT (MI AddrFI:$fi, imm:$Off))>;
1772 def: Pat<(VT (Load (add (i32 IntRegs:$Rs), ImmPred:$Off))),
1773 (VT (MI IntRegs:$Rs, imm:$Off))>;
1774 def: Pat<(VT (Load (i32 IntRegs:$Rs))), (VT (MI IntRegs:$Rs, 0))>;
1777 let AddedComplexity = 20 in {
1778 defm: Loadx_pat<load, i32, s30_2ImmPred, L2_loadri_io>;
1779 defm: Loadx_pat<load, i64, s29_3ImmPred, L2_loadrd_io>;
1780 defm: Loadx_pat<atomic_load_8 , i32, s32_0ImmPred, L2_loadrub_io>;
1781 defm: Loadx_pat<atomic_load_16, i32, s31_1ImmPred, L2_loadruh_io>;
1782 defm: Loadx_pat<atomic_load_32, i32, s30_2ImmPred, L2_loadri_io>;
1783 defm: Loadx_pat<atomic_load_64, i64, s29_3ImmPred, L2_loadrd_io>;
1785 defm: Loadx_pat<extloadi1, i32, s32_0ImmPred, L2_loadrub_io>;
1786 defm: Loadx_pat<extloadi8, i32, s32_0ImmPred, L2_loadrub_io>;
1787 defm: Loadx_pat<extloadi16, i32, s31_1ImmPred, L2_loadruh_io>;
1788 defm: Loadx_pat<sextloadi8, i32, s32_0ImmPred, L2_loadrb_io>;
1789 defm: Loadx_pat<sextloadi16, i32, s31_1ImmPred, L2_loadrh_io>;
1790 defm: Loadx_pat<zextloadi1, i32, s32_0ImmPred, L2_loadrub_io>;
1791 defm: Loadx_pat<zextloadi8, i32, s32_0ImmPred, L2_loadrub_io>;
1792 defm: Loadx_pat<zextloadi16, i32, s31_1ImmPred, L2_loadruh_io>;
1796 // Sign-extending loads of i1 need to replicate the lowest bit throughout
1797 // the 32-bit value. Since the loaded value can only be 0 or 1, 0-v should
1799 let AddedComplexity = 20 in
1800 def: Pat<(i32 (sextloadi1 (i32 IntRegs:$Rs))),
1801 (A2_subri 0, (L2_loadrub_io IntRegs:$Rs, 0))>;
1803 //===----------------------------------------------------------------------===//
1804 // Post increment load
1805 //===----------------------------------------------------------------------===//
1806 //===----------------------------------------------------------------------===//
1807 // Template class for non-predicated post increment loads with immediate offset.
1808 //===----------------------------------------------------------------------===//
1809 let hasSideEffects = 0, addrMode = PostInc in
1810 class T_load_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
1812 : LDInstPI <(outs RC:$dst, IntRegs:$dst2),
1813 (ins IntRegs:$src1, ImmOp:$offset),
1814 "$dst = "#mnemonic#"($src1++#$offset)" ,
1823 string ImmOpStr = !cast<string>(ImmOp);
1824 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
1825 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1826 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1827 /* s4_0Imm */ offset{3-0})));
1828 let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
1830 let IClass = 0b1001;
1832 let Inst{27-25} = 0b101;
1833 let Inst{24-21} = MajOp;
1834 let Inst{20-16} = src1;
1835 let Inst{13-12} = 0b00;
1836 let Inst{8-5} = offsetBits;
1837 let Inst{4-0} = dst;
1840 //===----------------------------------------------------------------------===//
1841 // Template class for predicated post increment loads with immediate offset.
1842 //===----------------------------------------------------------------------===//
1843 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
1844 class T_pload_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
1845 bits<4> MajOp, bit isPredNot, bit isPredNew >
1846 : LDInst <(outs RC:$dst, IntRegs:$dst2),
1847 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1848 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1849 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1859 let isPredicatedNew = isPredNew;
1860 let isPredicatedFalse = isPredNot;
1862 string ImmOpStr = !cast<string>(ImmOp);
1863 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
1864 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1865 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1866 /* s4_0Imm */ offset{3-0})));
1867 let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
1869 let IClass = 0b1001;
1871 let Inst{27-25} = 0b101;
1872 let Inst{24-21} = MajOp;
1873 let Inst{20-16} = src2;
1875 let Inst{12} = isPredNew;
1876 let Inst{11} = isPredNot;
1877 let Inst{10-9} = src1;
1878 let Inst{8-5} = offsetBits;
1879 let Inst{4-0} = dst;
1882 //===----------------------------------------------------------------------===//
1883 // Multiclass for post increment loads with immediate offset.
1884 //===----------------------------------------------------------------------===//
1886 multiclass LD_PostInc <string mnemonic, string BaseOp, RegisterClass RC,
1887 Operand ImmOp, bits<4> MajOp> {
1888 let BaseOpcode = "POST_"#BaseOp in {
1889 let isPredicable = 1 in
1890 def L2_#NAME#_pi : T_load_pi < mnemonic, RC, ImmOp, MajOp>;
1893 def L2_p#NAME#t_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 0>;
1894 def L2_p#NAME#f_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 0>;
1897 def L2_p#NAME#tnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 1>;
1898 def L2_p#NAME#fnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 1>;
1902 // post increment byte loads with immediate offset
1903 let accessSize = ByteAccess in {
1904 defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>;
1905 defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>;
1908 // post increment halfword loads with immediate offset
1909 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1910 defm loadrh : LD_PostInc <"memh", "LDrih", IntRegs, s4_1Imm, 0b1010>;
1911 defm loadruh : LD_PostInc <"memuh", "LDriuh", IntRegs, s4_1Imm, 0b1011>;
1914 // post increment word loads with immediate offset
1915 let accessSize = WordAccess, opExtentAlign = 2 in
1916 defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>;
1918 // post increment doubleword loads with immediate offset
1919 let accessSize = DoubleWordAccess, opExtentAlign = 3 in
1920 defm loadrd : LD_PostInc <"memd", "LDrid", DoubleRegs, s4_3Imm, 0b1110>;
1922 // Rd=memb[u]h(Rx++#s4:1)
1923 // Rdd=memb[u]h(Rx++#s4:2)
1924 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1925 def L2_loadbsw2_pi : T_load_pi <"membh", IntRegs, s4_1Imm, 0b0001>;
1926 def L2_loadbzw2_pi : T_load_pi <"memubh", IntRegs, s4_1Imm, 0b0011>;
1928 let accessSize = WordAccess, opExtentAlign = 2, hasNewValue = 0 in {
1929 def L2_loadbsw4_pi : T_load_pi <"membh", DoubleRegs, s4_2Imm, 0b0111>;
1930 def L2_loadbzw4_pi : T_load_pi <"memubh", DoubleRegs, s4_2Imm, 0b0101>;
1933 //===----------------------------------------------------------------------===//
1934 // Template class for post increment fifo loads with immediate offset.
1935 //===----------------------------------------------------------------------===//
1936 let hasSideEffects = 0, addrMode = PostInc in
1937 class T_loadalign_pi <string mnemonic, Operand ImmOp, bits<4> MajOp >
1938 : LDInstPI <(outs DoubleRegs:$dst, IntRegs:$dst2),
1939 (ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1940 "$dst = "#mnemonic#"($src2++#$offset)" ,
1941 [], "$src2 = $dst2, $src1 = $dst" > ,
1948 let offsetBits = !if (!eq(!cast<string>(ImmOp), "s4_1Imm"), offset{4-1},
1949 /* s4_0Imm */ offset{3-0});
1950 let IClass = 0b1001;
1952 let Inst{27-25} = 0b101;
1953 let Inst{24-21} = MajOp;
1954 let Inst{20-16} = src2;
1955 let Inst{13-12} = 0b00;
1956 let Inst{8-5} = offsetBits;
1957 let Inst{4-0} = dst;
1960 // Ryy=memh_fifo(Rx++#s4:1)
1961 // Ryy=memb_fifo(Rx++#s4:0)
1962 let accessSize = ByteAccess in
1963 def L2_loadalignb_pi : T_loadalign_pi <"memb_fifo", s4_0Imm, 0b0100>;
1965 let accessSize = HalfWordAccess, opExtentAlign = 1 in
1966 def L2_loadalignh_pi : T_loadalign_pi <"memh_fifo", s4_1Imm, 0b0010>;
1968 //===----------------------------------------------------------------------===//
1969 // Template class for post increment loads with register offset.
1970 //===----------------------------------------------------------------------===//
1971 let hasSideEffects = 0, addrMode = PostInc in
1972 class T_load_pr <string mnemonic, RegisterClass RC, bits<4> MajOp,
1973 MemAccessSize AccessSz>
1974 : LDInstPI <(outs RC:$dst, IntRegs:$_dst_),
1975 (ins IntRegs:$src1, ModRegs:$src2),
1976 "$dst = "#mnemonic#"($src1++$src2)" ,
1977 [], "$src1 = $_dst_" > {
1982 let accessSize = AccessSz;
1983 let IClass = 0b1001;
1985 let Inst{27-25} = 0b110;
1986 let Inst{24-21} = MajOp;
1987 let Inst{20-16} = src1;
1988 let Inst{13} = src2;
1991 let Inst{4-0} = dst;
1994 let hasNewValue = 1 in {
1995 def L2_loadrb_pr : T_load_pr <"memb", IntRegs, 0b1000, ByteAccess>;
1996 def L2_loadrub_pr : T_load_pr <"memub", IntRegs, 0b1001, ByteAccess>;
1997 def L2_loadrh_pr : T_load_pr <"memh", IntRegs, 0b1010, HalfWordAccess>;
1998 def L2_loadruh_pr : T_load_pr <"memuh", IntRegs, 0b1011, HalfWordAccess>;
1999 def L2_loadri_pr : T_load_pr <"memw", IntRegs, 0b1100, WordAccess>;
2001 def L2_loadbzw2_pr : T_load_pr <"memubh", IntRegs, 0b0011, HalfWordAccess>;
2004 def L2_loadrd_pr : T_load_pr <"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
2005 def L2_loadbzw4_pr : T_load_pr <"memubh", DoubleRegs, 0b0101, WordAccess>;
2008 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
2009 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
2010 def LDriw_pred : LDInst<(outs PredRegs:$dst),
2011 (ins IntRegs:$addr, s11_2Ext:$off),
2012 ".error \"should not emit\"", []>;
2014 let Defs = [R29, R30, R31], Uses = [R30], hasSideEffects = 0 in
2015 def L2_deallocframe : LDInst<(outs), (ins),
2018 let IClass = 0b1001;
2020 let Inst{27-16} = 0b000000011110;
2022 let Inst{4-0} = 0b11110;
2025 // Load / Post increment circular addressing mode.
2026 let Uses = [CS], hasSideEffects = 0 in
2027 class T_load_pcr<string mnemonic, RegisterClass RC, bits<4> MajOp>
2028 : LDInst <(outs RC:$dst, IntRegs:$_dst_),
2029 (ins IntRegs:$Rz, ModRegs:$Mu),
2030 "$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [],
2036 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
2037 let IClass = 0b1001;
2039 let Inst{27-25} = 0b100;
2040 let Inst{24-21} = MajOp;
2041 let Inst{20-16} = Rz;
2046 let Inst{4-0} = dst;
2049 let accessSize = ByteAccess in {
2050 def L2_loadrb_pcr : T_load_pcr <"memb", IntRegs, 0b1000>;
2051 def L2_loadrub_pcr : T_load_pcr <"memub", IntRegs, 0b1001>;
2054 let accessSize = HalfWordAccess in {
2055 def L2_loadrh_pcr : T_load_pcr <"memh", IntRegs, 0b1010>;
2056 def L2_loadruh_pcr : T_load_pcr <"memuh", IntRegs, 0b1011>;
2057 def L2_loadbsw2_pcr : T_load_pcr <"membh", IntRegs, 0b0001>;
2058 def L2_loadbzw2_pcr : T_load_pcr <"memubh", IntRegs, 0b0011>;
2061 let accessSize = WordAccess in {
2062 def L2_loadri_pcr : T_load_pcr <"memw", IntRegs, 0b1100>;
2063 let hasNewValue = 0 in {
2064 def L2_loadbzw4_pcr : T_load_pcr <"memubh", DoubleRegs, 0b0101>;
2065 def L2_loadbsw4_pcr : T_load_pcr <"membh", DoubleRegs, 0b0111>;
2069 let accessSize = DoubleWordAccess in
2070 def L2_loadrd_pcr : T_load_pcr <"memd", DoubleRegs, 0b1110>;
2072 // Load / Post increment circular addressing mode.
2073 let Uses = [CS], hasSideEffects = 0 in
2074 class T_loadalign_pcr<string mnemonic, bits<4> MajOp, MemAccessSize AccessSz >
2075 : LDInst <(outs DoubleRegs:$dst, IntRegs:$_dst_),
2076 (ins DoubleRegs:$_src_, IntRegs:$Rz, ModRegs:$Mu),
2077 "$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [],
2078 "$Rz = $_dst_, $dst = $_src_" > {
2083 let accessSize = AccessSz;
2084 let IClass = 0b1001;
2086 let Inst{27-25} = 0b100;
2087 let Inst{24-21} = MajOp;
2088 let Inst{20-16} = Rz;
2093 let Inst{4-0} = dst;
2096 def L2_loadalignb_pcr : T_loadalign_pcr <"memb_fifo", 0b0100, ByteAccess>;
2097 def L2_loadalignh_pcr : T_loadalign_pcr <"memh_fifo", 0b0010, HalfWordAccess>;
2099 //===----------------------------------------------------------------------===//
2100 // Circular loads with immediate offset.
2101 //===----------------------------------------------------------------------===//
2102 let Uses = [CS], mayLoad = 1, hasSideEffects = 0 in
2103 class T_load_pci <string mnemonic, RegisterClass RC,
2104 Operand ImmOp, bits<4> MajOp>
2105 : LDInstPI<(outs RC:$dst, IntRegs:$_dst_),
2106 (ins IntRegs:$Rz, ImmOp:$offset, ModRegs:$Mu),
2107 "$dst = "#mnemonic#"($Rz ++ #$offset:circ($Mu))", [],
2115 string ImmOpStr = !cast<string>(ImmOp);
2116 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
2117 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
2118 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
2119 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
2120 /* s4_0Imm */ offset{3-0})));
2121 let IClass = 0b1001;
2122 let Inst{27-25} = 0b100;
2123 let Inst{24-21} = MajOp;
2124 let Inst{20-16} = Rz;
2128 let Inst{8-5} = offsetBits;
2129 let Inst{4-0} = dst;
2132 // Byte variants of circ load
2133 let accessSize = ByteAccess in {
2134 def L2_loadrb_pci : T_load_pci <"memb", IntRegs, s4_0Imm, 0b1000>;
2135 def L2_loadrub_pci : T_load_pci <"memub", IntRegs, s4_0Imm, 0b1001>;
2138 // Half word variants of circ load
2139 let accessSize = HalfWordAccess in {
2140 def L2_loadrh_pci : T_load_pci <"memh", IntRegs, s4_1Imm, 0b1010>;
2141 def L2_loadruh_pci : T_load_pci <"memuh", IntRegs, s4_1Imm, 0b1011>;
2142 def L2_loadbzw2_pci : T_load_pci <"memubh", IntRegs, s4_1Imm, 0b0011>;
2143 def L2_loadbsw2_pci : T_load_pci <"membh", IntRegs, s4_1Imm, 0b0001>;
2146 // Word variants of circ load
2147 let accessSize = WordAccess in
2148 def L2_loadri_pci : T_load_pci <"memw", IntRegs, s4_2Imm, 0b1100>;
2150 let accessSize = WordAccess, hasNewValue = 0 in {
2151 def L2_loadbzw4_pci : T_load_pci <"memubh", DoubleRegs, s4_2Imm, 0b0101>;
2152 def L2_loadbsw4_pci : T_load_pci <"membh", DoubleRegs, s4_2Imm, 0b0111>;
2155 let accessSize = DoubleWordAccess, hasNewValue = 0 in
2156 def L2_loadrd_pci : T_load_pci <"memd", DoubleRegs, s4_3Imm, 0b1110>;
2158 //===----------------------------------------------------------------------===//
2159 // Circular loads - Pseudo
2161 // Please note that the input operand order in the pseudo instructions
2162 // doesn't match with the real instructions. Pseudo instructions operand
2163 // order should mimics the ordering in the intrinsics. Also, 'src2' doesn't
2164 // appear in the AsmString because it's same as 'dst'.
2165 //===----------------------------------------------------------------------===//
2166 let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0, isPseudo = 1 in
2167 class T_load_pci_pseudo <string opc, RegisterClass RC>
2168 : LDInstPI<(outs IntRegs:$_dst_, RC:$dst),
2169 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4Imm:$src4),
2170 ".error \"$dst = "#opc#"($src1++#$src4:circ($src3))\"",
2171 [], "$src1 = $_dst_">;
2173 def L2_loadrb_pci_pseudo : T_load_pci_pseudo <"memb", IntRegs>;
2174 def L2_loadrub_pci_pseudo : T_load_pci_pseudo <"memub", IntRegs>;
2175 def L2_loadrh_pci_pseudo : T_load_pci_pseudo <"memh", IntRegs>;
2176 def L2_loadruh_pci_pseudo : T_load_pci_pseudo <"memuh", IntRegs>;
2177 def L2_loadri_pci_pseudo : T_load_pci_pseudo <"memw", IntRegs>;
2178 def L2_loadrd_pci_pseudo : T_load_pci_pseudo <"memd", DoubleRegs>;
2181 // TODO: memb_fifo and memh_fifo must take destination register as input.
2182 // One-off circ loads - not enough in common to break into a class.
2183 let accessSize = ByteAccess in
2184 def L2_loadalignb_pci : T_load_pci <"memb_fifo", DoubleRegs, s4_0Imm, 0b0100>;
2186 let accessSize = HalfWordAccess, opExtentAlign = 1 in
2187 def L2_loadalignh_pci : T_load_pci <"memh_fifo", DoubleRegs, s4_1Imm, 0b0010>;
2189 // L[24]_load[wd]_locked: Load word/double with lock.
2191 class T_load_locked <string mnemonic, RegisterClass RC>
2192 : LD0Inst <(outs RC:$dst),
2194 "$dst = "#mnemonic#"($src)"> {
2197 let IClass = 0b1001;
2198 let Inst{27-21} = 0b0010000;
2199 let Inst{20-16} = src;
2200 let Inst{13-12} = !if (!eq(mnemonic, "memd_locked"), 0b01, 0b00);
2202 let Inst{4-0} = dst;
2204 let hasNewValue = 1, accessSize = WordAccess, opNewValue = 0 in
2205 def L2_loadw_locked : T_load_locked <"memw_locked", IntRegs>;
2206 let accessSize = DoubleWordAccess in
2207 def L4_loadd_locked : T_load_locked <"memd_locked", DoubleRegs>;
2209 // S[24]_store[wd]_locked: Store word/double conditionally.
2210 let isSoloAX = 1, isPredicateLate = 1 in
2211 class T_store_locked <string mnemonic, RegisterClass RC>
2212 : ST0Inst <(outs PredRegs:$Pd), (ins IntRegs:$Rs, RC:$Rt),
2213 mnemonic#"($Rs, $Pd) = $Rt"> {
2218 let IClass = 0b1010;
2219 let Inst{27-23} = 0b00001;
2220 let Inst{22} = !if (!eq(mnemonic, "memw_locked"), 0b0, 0b1);
2222 let Inst{20-16} = Rs;
2223 let Inst{12-8} = Rt;
2227 let accessSize = WordAccess in
2228 def S2_storew_locked : T_store_locked <"memw_locked", IntRegs>;
2230 let accessSize = DoubleWordAccess in
2231 def S4_stored_locked : T_store_locked <"memd_locked", DoubleRegs>;
2233 //===----------------------------------------------------------------------===//
2234 // Bit-reversed loads with auto-increment register
2235 //===----------------------------------------------------------------------===//
2236 let hasSideEffects = 0 in
2237 class T_load_pbr<string mnemonic, RegisterClass RC,
2238 MemAccessSize addrSize, bits<4> majOp>
2240 <(outs RC:$dst, IntRegs:$_dst_),
2241 (ins IntRegs:$Rz, ModRegs:$Mu),
2242 "$dst = "#mnemonic#"($Rz ++ $Mu:brev)" ,
2243 [] , "$Rz = $_dst_" > {
2245 let accessSize = addrSize;
2251 let IClass = 0b1001;
2253 let Inst{27-25} = 0b111;
2254 let Inst{24-21} = majOp;
2255 let Inst{20-16} = Rz;
2259 let Inst{4-0} = dst;
2262 let hasNewValue =1, opNewValue = 0 in {
2263 def L2_loadrb_pbr : T_load_pbr <"memb", IntRegs, ByteAccess, 0b1000>;
2264 def L2_loadrub_pbr : T_load_pbr <"memub", IntRegs, ByteAccess, 0b1001>;
2265 def L2_loadrh_pbr : T_load_pbr <"memh", IntRegs, HalfWordAccess, 0b1010>;
2266 def L2_loadruh_pbr : T_load_pbr <"memuh", IntRegs, HalfWordAccess, 0b1011>;
2267 def L2_loadbsw2_pbr : T_load_pbr <"membh", IntRegs, HalfWordAccess, 0b0001>;
2268 def L2_loadbzw2_pbr : T_load_pbr <"memubh", IntRegs, HalfWordAccess, 0b0011>;
2269 def L2_loadri_pbr : T_load_pbr <"memw", IntRegs, WordAccess, 0b1100>;
2272 def L2_loadbzw4_pbr : T_load_pbr <"memubh", DoubleRegs, WordAccess, 0b0101>;
2273 def L2_loadbsw4_pbr : T_load_pbr <"membh", DoubleRegs, WordAccess, 0b0111>;
2274 def L2_loadrd_pbr : T_load_pbr <"memd", DoubleRegs, DoubleWordAccess, 0b1110>;
2276 def L2_loadalignb_pbr :T_load_pbr <"memb_fifo", DoubleRegs, ByteAccess, 0b0100>;
2277 def L2_loadalignh_pbr :T_load_pbr <"memh_fifo", DoubleRegs,
2278 HalfWordAccess, 0b0010>;
2280 //===----------------------------------------------------------------------===//
2281 // Bit-reversed loads - Pseudo
2283 // Please note that 'src2' doesn't appear in the AsmString because
2284 // it's same as 'dst'.
2285 //===----------------------------------------------------------------------===//
2286 let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0, isPseudo = 1 in
2287 class T_load_pbr_pseudo <string opc, RegisterClass RC>
2288 : LDInstPI<(outs IntRegs:$_dst_, RC:$dst),
2289 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2290 ".error \"$dst = "#opc#"($src1++$src3:brev)\"",
2291 [], "$src1 = $_dst_">;
2293 def L2_loadrb_pbr_pseudo : T_load_pbr_pseudo <"memb", IntRegs>;
2294 def L2_loadrub_pbr_pseudo : T_load_pbr_pseudo <"memub", IntRegs>;
2295 def L2_loadrh_pbr_pseudo : T_load_pbr_pseudo <"memh", IntRegs>;
2296 def L2_loadruh_pbr_pseudo : T_load_pbr_pseudo <"memuh", IntRegs>;
2297 def L2_loadri_pbr_pseudo : T_load_pbr_pseudo <"memw", IntRegs>;
2298 def L2_loadrd_pbr_pseudo : T_load_pbr_pseudo <"memd", DoubleRegs>;
2300 //===----------------------------------------------------------------------===//
2302 //===----------------------------------------------------------------------===//
2304 //===----------------------------------------------------------------------===//
2306 //===----------------------------------------------------------------------===//
2307 //===----------------------------------------------------------------------===//
2309 //===----------------------------------------------------------------------===//
2311 //===----------------------------------------------------------------------===//
2313 //===----------------------------------------------------------------------===//
2314 //===----------------------------------------------------------------------===//
2316 //===----------------------------------------------------------------------===//
2318 //===----------------------------------------------------------------------===//
2320 //===----------------------------------------------------------------------===//
2322 //===----------------------------------------------------------------------===//
2324 // MPYS / Multipy signed/unsigned halfwords
2325 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
2326 //===----------------------------------------------------------------------===//
2328 let hasNewValue = 1, opNewValue = 0 in
2329 class T_M2_mpy < bits<2> LHbits, bit isSat, bit isRnd,
2330 bit hasShift, bit isUnsigned>
2331 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
2332 "$Rd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
2333 #", $Rt."#!if(LHbits{0},"h)","l)")
2334 #!if(hasShift,":<<1","")
2335 #!if(isRnd,":rnd","")
2336 #!if(isSat,":sat",""),
2337 [], "", M_tc_3x_SLOT23 > {
2342 let IClass = 0b1110;
2344 let Inst{27-24} = 0b1100;
2345 let Inst{23} = hasShift;
2346 let Inst{22} = isUnsigned;
2347 let Inst{21} = isRnd;
2348 let Inst{7} = isSat;
2349 let Inst{6-5} = LHbits;
2351 let Inst{20-16} = Rs;
2352 let Inst{12-8} = Rt;
2355 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2356 def M2_mpy_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 0>;
2357 def M2_mpy_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 0>;
2358 def M2_mpy_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 0>;
2359 def M2_mpy_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 0>;
2360 def M2_mpy_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 0>;
2361 def M2_mpy_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 0>;
2362 def M2_mpy_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 0>;
2363 def M2_mpy_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 0>;
2365 //Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2366 def M2_mpyu_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 1>;
2367 def M2_mpyu_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 1>;
2368 def M2_mpyu_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 1>;
2369 def M2_mpyu_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 1>;
2370 def M2_mpyu_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 1>;
2371 def M2_mpyu_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 1>;
2372 def M2_mpyu_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 1>;
2373 def M2_mpyu_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 1>;
2375 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]:rnd
2376 def M2_mpy_rnd_ll_s1: T_M2_mpy <0b00, 0, 1, 1, 0>;
2377 def M2_mpy_rnd_ll_s0: T_M2_mpy <0b00, 0, 1, 0, 0>;
2378 def M2_mpy_rnd_lh_s1: T_M2_mpy <0b01, 0, 1, 1, 0>;
2379 def M2_mpy_rnd_lh_s0: T_M2_mpy <0b01, 0, 1, 0, 0>;
2380 def M2_mpy_rnd_hl_s1: T_M2_mpy <0b10, 0, 1, 1, 0>;
2381 def M2_mpy_rnd_hl_s0: T_M2_mpy <0b10, 0, 1, 0, 0>;
2382 def M2_mpy_rnd_hh_s1: T_M2_mpy <0b11, 0, 1, 1, 0>;
2383 def M2_mpy_rnd_hh_s0: T_M2_mpy <0b11, 0, 1, 0, 0>;
2385 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2386 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
2387 let Defs = [USR_OVF] in {
2388 def M2_mpy_sat_ll_s1: T_M2_mpy <0b00, 1, 0, 1, 0>;
2389 def M2_mpy_sat_ll_s0: T_M2_mpy <0b00, 1, 0, 0, 0>;
2390 def M2_mpy_sat_lh_s1: T_M2_mpy <0b01, 1, 0, 1, 0>;
2391 def M2_mpy_sat_lh_s0: T_M2_mpy <0b01, 1, 0, 0, 0>;
2392 def M2_mpy_sat_hl_s1: T_M2_mpy <0b10, 1, 0, 1, 0>;
2393 def M2_mpy_sat_hl_s0: T_M2_mpy <0b10, 1, 0, 0, 0>;
2394 def M2_mpy_sat_hh_s1: T_M2_mpy <0b11, 1, 0, 1, 0>;
2395 def M2_mpy_sat_hh_s0: T_M2_mpy <0b11, 1, 0, 0, 0>;
2397 def M2_mpy_sat_rnd_ll_s1: T_M2_mpy <0b00, 1, 1, 1, 0>;
2398 def M2_mpy_sat_rnd_ll_s0: T_M2_mpy <0b00, 1, 1, 0, 0>;
2399 def M2_mpy_sat_rnd_lh_s1: T_M2_mpy <0b01, 1, 1, 1, 0>;
2400 def M2_mpy_sat_rnd_lh_s0: T_M2_mpy <0b01, 1, 1, 0, 0>;
2401 def M2_mpy_sat_rnd_hl_s1: T_M2_mpy <0b10, 1, 1, 1, 0>;
2402 def M2_mpy_sat_rnd_hl_s0: T_M2_mpy <0b10, 1, 1, 0, 0>;
2403 def M2_mpy_sat_rnd_hh_s1: T_M2_mpy <0b11, 1, 1, 1, 0>;
2404 def M2_mpy_sat_rnd_hh_s0: T_M2_mpy <0b11, 1, 1, 0, 0>;
2407 //===----------------------------------------------------------------------===//
2409 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
2410 // result from the accumulator.
2411 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2412 //===----------------------------------------------------------------------===//
2414 let hasNewValue = 1, opNewValue = 0 in
2415 class T_M2_mpy_acc < bits<2> LHbits, bit isSat, bit isNac,
2416 bit hasShift, bit isUnsigned >
2417 : MInst_acc<(outs IntRegs:$Rx), (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2418 "$Rx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy")
2419 #"($Rs."#!if(LHbits{1},"h","l")
2420 #", $Rt."#!if(LHbits{0},"h)","l)")
2421 #!if(hasShift,":<<1","")
2422 #!if(isSat,":sat",""),
2423 [], "$dst2 = $Rx", M_tc_3x_SLOT23 > {
2428 let IClass = 0b1110;
2429 let Inst{27-24} = 0b1110;
2430 let Inst{23} = hasShift;
2431 let Inst{22} = isUnsigned;
2432 let Inst{21} = isNac;
2433 let Inst{7} = isSat;
2434 let Inst{6-5} = LHbits;
2436 let Inst{20-16} = Rs;
2437 let Inst{12-8} = Rt;
2440 //Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2441 def M2_mpy_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 0>;
2442 def M2_mpy_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 0>;
2443 def M2_mpy_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 0>;
2444 def M2_mpy_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 0>;
2445 def M2_mpy_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 0>;
2446 def M2_mpy_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 0>;
2447 def M2_mpy_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 0>;
2448 def M2_mpy_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 0>;
2450 //Rx += mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2451 def M2_mpyu_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 1>;
2452 def M2_mpyu_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 1>;
2453 def M2_mpyu_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 1>;
2454 def M2_mpyu_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 1>;
2455 def M2_mpyu_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 1>;
2456 def M2_mpyu_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 1>;
2457 def M2_mpyu_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 1>;
2458 def M2_mpyu_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 1>;
2460 //Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2461 def M2_mpy_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 0>;
2462 def M2_mpy_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 0>;
2463 def M2_mpy_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 0>;
2464 def M2_mpy_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 0>;
2465 def M2_mpy_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 0>;
2466 def M2_mpy_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 0>;
2467 def M2_mpy_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 0>;
2468 def M2_mpy_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 0>;
2470 //Rx -= mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2471 def M2_mpyu_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 1>;
2472 def M2_mpyu_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 1>;
2473 def M2_mpyu_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 1>;
2474 def M2_mpyu_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 1>;
2475 def M2_mpyu_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 1>;
2476 def M2_mpyu_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 1>;
2477 def M2_mpyu_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 1>;
2478 def M2_mpyu_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 1>;
2480 //Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat
2481 def M2_mpy_acc_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 0, 1, 0>;
2482 def M2_mpy_acc_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 0, 0, 0>;
2483 def M2_mpy_acc_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 0, 1, 0>;
2484 def M2_mpy_acc_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 0, 0, 0>;
2485 def M2_mpy_acc_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 0, 1, 0>;
2486 def M2_mpy_acc_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 0, 0, 0>;
2487 def M2_mpy_acc_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 0, 1, 0>;
2488 def M2_mpy_acc_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 0, 0, 0>;
2490 //Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat
2491 def M2_mpy_nac_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 1, 1, 0>;
2492 def M2_mpy_nac_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 1, 0, 0>;
2493 def M2_mpy_nac_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 1, 1, 0>;
2494 def M2_mpy_nac_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 1, 0, 0>;
2495 def M2_mpy_nac_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 1, 1, 0>;
2496 def M2_mpy_nac_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 1, 0, 0>;
2497 def M2_mpy_nac_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 1, 1, 0>;
2498 def M2_mpy_nac_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 1, 0, 0>;
2500 //===----------------------------------------------------------------------===//
2502 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
2503 // result from the 64-bit destination register.
2504 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2505 //===----------------------------------------------------------------------===//
2507 class T_M2_mpyd_acc < bits<2> LHbits, bit isNac, bit hasShift, bit isUnsigned>
2508 : MInst_acc<(outs DoubleRegs:$Rxx),
2509 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2510 "$Rxx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy")
2511 #"($Rs."#!if(LHbits{1},"h","l")
2512 #", $Rt."#!if(LHbits{0},"h)","l)")
2513 #!if(hasShift,":<<1",""),
2514 [], "$dst2 = $Rxx", M_tc_3x_SLOT23 > {
2519 let IClass = 0b1110;
2521 let Inst{27-24} = 0b0110;
2522 let Inst{23} = hasShift;
2523 let Inst{22} = isUnsigned;
2524 let Inst{21} = isNac;
2526 let Inst{6-5} = LHbits;
2527 let Inst{4-0} = Rxx;
2528 let Inst{20-16} = Rs;
2529 let Inst{12-8} = Rt;
2532 def M2_mpyd_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 0>;
2533 def M2_mpyd_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 0>;
2534 def M2_mpyd_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 0>;
2535 def M2_mpyd_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 0>;
2537 def M2_mpyd_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 0>;
2538 def M2_mpyd_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 0>;
2539 def M2_mpyd_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 0>;
2540 def M2_mpyd_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 0>;
2542 def M2_mpyd_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 0>;
2543 def M2_mpyd_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 0>;
2544 def M2_mpyd_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 0>;
2545 def M2_mpyd_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 0>;
2547 def M2_mpyd_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 0>;
2548 def M2_mpyd_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 0>;
2549 def M2_mpyd_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 0>;
2550 def M2_mpyd_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 0>;
2552 def M2_mpyud_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 1>;
2553 def M2_mpyud_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 1>;
2554 def M2_mpyud_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 1>;
2555 def M2_mpyud_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 1>;
2557 def M2_mpyud_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 1>;
2558 def M2_mpyud_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 1>;
2559 def M2_mpyud_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 1>;
2560 def M2_mpyud_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 1>;
2562 def M2_mpyud_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 1>;
2563 def M2_mpyud_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 1>;
2564 def M2_mpyud_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 1>;
2565 def M2_mpyud_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 1>;
2567 def M2_mpyud_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 1>;
2568 def M2_mpyud_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 1>;
2569 def M2_mpyud_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 1>;
2570 def M2_mpyud_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 1>;
2572 //===----------------------------------------------------------------------===//
2573 // Template Class -- Vector Multipy
2574 // Used for complex multiply real or imaginary, dual multiply and even halfwords
2575 //===----------------------------------------------------------------------===//
2576 class T_M2_vmpy < string opc, bits<3> MajOp, bits<3> MinOp, bit hasShift,
2577 bit isRnd, bit isSat >
2578 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
2579 "$Rdd = "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
2580 #!if(isRnd,":rnd","")
2581 #!if(isSat,":sat",""),
2587 let IClass = 0b1110;
2589 let Inst{27-24} = 0b1000;
2590 let Inst{23-21} = MajOp;
2591 let Inst{7-5} = MinOp;
2592 let Inst{4-0} = Rdd;
2593 let Inst{20-16} = Rss;
2594 let Inst{12-8} = Rtt;
2597 // Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat
2598 let Defs = [USR_OVF] in {
2599 def M2_vcmpy_s1_sat_i: T_M2_vmpy <"vcmpyi", 0b110, 0b110, 1, 0, 1>;
2600 def M2_vcmpy_s0_sat_i: T_M2_vmpy <"vcmpyi", 0b010, 0b110, 0, 0, 1>;
2602 // Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat
2603 def M2_vcmpy_s1_sat_r: T_M2_vmpy <"vcmpyr", 0b101, 0b110, 1, 0, 1>;
2604 def M2_vcmpy_s0_sat_r: T_M2_vmpy <"vcmpyr", 0b001, 0b110, 0, 0, 1>;
2606 // Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat
2607 def M2_vdmpys_s1: T_M2_vmpy <"vdmpy", 0b100, 0b100, 1, 0, 1>;
2608 def M2_vdmpys_s0: T_M2_vmpy <"vdmpy", 0b000, 0b100, 0, 0, 1>;
2610 // Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat
2611 def M2_vmpy2es_s1: T_M2_vmpy <"vmpyeh", 0b100, 0b110, 1, 0, 1>;
2612 def M2_vmpy2es_s0: T_M2_vmpy <"vmpyeh", 0b000, 0b110, 0, 0, 1>;
2614 //Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat
2615 def M2_mmpyh_s0: T_M2_vmpy <"vmpywoh", 0b000, 0b111, 0, 0, 1>;
2616 def M2_mmpyh_s1: T_M2_vmpy <"vmpywoh", 0b100, 0b111, 1, 0, 1>;
2617 def M2_mmpyh_rs0: T_M2_vmpy <"vmpywoh", 0b001, 0b111, 0, 1, 1>;
2618 def M2_mmpyh_rs1: T_M2_vmpy <"vmpywoh", 0b101, 0b111, 1, 1, 1>;
2620 //Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat
2621 def M2_mmpyl_s0: T_M2_vmpy <"vmpyweh", 0b000, 0b101, 0, 0, 1>;
2622 def M2_mmpyl_s1: T_M2_vmpy <"vmpyweh", 0b100, 0b101, 1, 0, 1>;
2623 def M2_mmpyl_rs0: T_M2_vmpy <"vmpyweh", 0b001, 0b101, 0, 1, 1>;
2624 def M2_mmpyl_rs1: T_M2_vmpy <"vmpyweh", 0b101, 0b101, 1, 1, 1>;
2626 //Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat
2627 def M2_mmpyuh_s0: T_M2_vmpy <"vmpywouh", 0b010, 0b111, 0, 0, 1>;
2628 def M2_mmpyuh_s1: T_M2_vmpy <"vmpywouh", 0b110, 0b111, 1, 0, 1>;
2629 def M2_mmpyuh_rs0: T_M2_vmpy <"vmpywouh", 0b011, 0b111, 0, 1, 1>;
2630 def M2_mmpyuh_rs1: T_M2_vmpy <"vmpywouh", 0b111, 0b111, 1, 1, 1>;
2632 //Rdd=vmpyweuh(Rss,Rtt)[:<<1][:rnd]:sat
2633 def M2_mmpyul_s0: T_M2_vmpy <"vmpyweuh", 0b010, 0b101, 0, 0, 1>;
2634 def M2_mmpyul_s1: T_M2_vmpy <"vmpyweuh", 0b110, 0b101, 1, 0, 1>;
2635 def M2_mmpyul_rs0: T_M2_vmpy <"vmpyweuh", 0b011, 0b101, 0, 1, 1>;
2636 def M2_mmpyul_rs1: T_M2_vmpy <"vmpyweuh", 0b111, 0b101, 1, 1, 1>;
2639 let hasNewValue = 1, opNewValue = 0 in
2640 class T_MType_mpy <string mnemonic, bits<4> RegTyBits, RegisterClass RC,
2641 bits<3> MajOp, bits<3> MinOp, bit isSat = 0, bit isRnd = 0,
2642 string op2Suffix = "", bit isRaw = 0, bit isHi = 0 >
2643 : MInst <(outs IntRegs:$dst), (ins RC:$src1, RC:$src2),
2645 #"($src1, $src2"#op2Suffix#")"
2646 #!if(MajOp{2}, ":<<1", "")
2647 #!if(isRnd, ":rnd", "")
2648 #!if(isSat, ":sat", "")
2649 #!if(isRaw, !if(isHi, ":raw:hi", ":raw:lo"), ""), [] > {
2654 let IClass = 0b1110;
2656 let Inst{27-24} = RegTyBits;
2657 let Inst{23-21} = MajOp;
2658 let Inst{20-16} = src1;
2660 let Inst{12-8} = src2;
2661 let Inst{7-5} = MinOp;
2662 let Inst{4-0} = dst;
2665 class T_MType_vrcmpy <string mnemonic, bits<3> MajOp, bits<3> MinOp, bit isHi>
2666 : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, 1, 1, "", 1, isHi>;
2668 class T_MType_dd <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2669 bit isSat = 0, bit isRnd = 0 >
2670 : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, isSat, isRnd>;
2672 class T_MType_rr1 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2673 bit isSat = 0, bit isRnd = 0 >
2674 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd>;
2676 class T_MType_rr2 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2677 bit isSat = 0, bit isRnd = 0, string op2str = "" >
2678 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd, op2str>;
2680 def M2_vradduh : T_MType_dd <"vradduh", 0b000, 0b001, 0, 0>;
2681 def M2_vdmpyrs_s0 : T_MType_dd <"vdmpy", 0b000, 0b000, 1, 1>;
2682 def M2_vdmpyrs_s1 : T_MType_dd <"vdmpy", 0b100, 0b000, 1, 1>;
2684 let CextOpcode = "mpyi", InputType = "reg" in
2685 def M2_mpyi : T_MType_rr1 <"mpyi", 0b000, 0b000>, ImmRegRel;
2687 def M2_mpy_up : T_MType_rr1 <"mpy", 0b000, 0b001>;
2688 def M2_mpyu_up : T_MType_rr1 <"mpyu", 0b010, 0b001>;
2690 def M2_dpmpyss_rnd_s0 : T_MType_rr1 <"mpy", 0b001, 0b001, 0, 1>;
2692 def M2_vmpy2s_s0pack : T_MType_rr1 <"vmpyh", 0b001, 0b111, 1, 1>;
2693 def M2_vmpy2s_s1pack : T_MType_rr1 <"vmpyh", 0b101, 0b111, 1, 1>;
2695 def M2_hmmpyh_rs1 : T_MType_rr2 <"mpy", 0b101, 0b100, 1, 1, ".h">;
2696 def M2_hmmpyl_rs1 : T_MType_rr2 <"mpy", 0b111, 0b100, 1, 1, ".l">;
2698 def M2_cmpyrs_s0 : T_MType_rr2 <"cmpy", 0b001, 0b110, 1, 1>;
2699 def M2_cmpyrs_s1 : T_MType_rr2 <"cmpy", 0b101, 0b110, 1, 1>;
2700 def M2_cmpyrsc_s0 : T_MType_rr2 <"cmpy", 0b011, 0b110, 1, 1, "*">;
2701 def M2_cmpyrsc_s1 : T_MType_rr2 <"cmpy", 0b111, 0b110, 1, 1, "*">;
2704 def M2_vraddh : T_MType_dd <"vraddh", 0b001, 0b111, 0>;
2705 def M2_mpysu_up : T_MType_rr1 <"mpysu", 0b011, 0b001, 0>;
2706 def M2_mpy_up_s1 : T_MType_rr1 <"mpy", 0b101, 0b010, 0>;
2707 def M2_mpy_up_s1_sat : T_MType_rr1 <"mpy", 0b111, 0b000, 1>;
2709 def M2_hmmpyh_s1 : T_MType_rr2 <"mpy", 0b101, 0b000, 1, 0, ".h">;
2710 def M2_hmmpyl_s1 : T_MType_rr2 <"mpy", 0b101, 0b001, 1, 0, ".l">;
2712 def: Pat<(i32 (mul I32:$src1, I32:$src2)), (M2_mpyi I32:$src1, I32:$src2)>;
2713 def: Pat<(i32 (mulhs I32:$src1, I32:$src2)), (M2_mpy_up I32:$src1, I32:$src2)>;
2714 def: Pat<(i32 (mulhu I32:$src1, I32:$src2)), (M2_mpyu_up I32:$src1, I32:$src2)>;
2716 let hasNewValue = 1, opNewValue = 0 in
2717 class T_MType_mpy_ri <bit isNeg, Operand ImmOp, list<dag> pattern>
2718 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, ImmOp:$u8),
2719 "$Rd ="#!if(isNeg, "- ", "+ ")#"mpyi($Rs, #$u8)" ,
2720 pattern, "", M_tc_3x_SLOT23> {
2725 let IClass = 0b1110;
2727 let Inst{27-24} = 0b0000;
2728 let Inst{23} = isNeg;
2731 let Inst{20-16} = Rs;
2732 let Inst{12-5} = u8;
2735 let isExtendable = 1, opExtentBits = 8, opExtendable = 2 in
2736 def M2_mpysip : T_MType_mpy_ri <0, u8Ext,
2737 [(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u32ImmPred:$u8))]>;
2739 def M2_mpysin : T_MType_mpy_ri <1, u8Imm,
2740 [(set (i32 IntRegs:$Rd), (ineg (mul IntRegs:$Rs,
2743 // Assember mapped to M2_mpyi
2744 let isAsmParserOnly = 1 in
2745 def M2_mpyui : MInst<(outs IntRegs:$dst),
2746 (ins IntRegs:$src1, IntRegs:$src2),
2747 "$dst = mpyui($src1, $src2)">;
2750 // s9 is NOT the same as m9 - but it works.. so far.
2751 // Assembler maps to either Rd=+mpyi(Rs,#u8) or Rd=-mpyi(Rs,#u8)
2752 // depending on the value of m9. See Arch Spec.
2753 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
2754 CextOpcode = "mpyi", InputType = "imm", hasNewValue = 1,
2755 isAsmParserOnly = 1 in
2756 def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
2757 "$dst = mpyi($src1, #$src2)",
2758 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
2759 s32ImmPred:$src2))]>, ImmRegRel;
2761 let hasNewValue = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 3,
2762 InputType = "imm" in
2763 class T_MType_acc_ri <string mnemonic, bits<3> MajOp, Operand ImmOp,
2764 list<dag> pattern = []>
2765 : MInst < (outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, ImmOp:$src3),
2766 "$dst "#mnemonic#"($src2, #$src3)",
2767 pattern, "$src1 = $dst", M_tc_2_SLOT23> {
2772 let IClass = 0b1110;
2774 let Inst{27-26} = 0b00;
2775 let Inst{25-23} = MajOp;
2776 let Inst{20-16} = src2;
2778 let Inst{12-5} = src3;
2779 let Inst{4-0} = dst;
2782 let InputType = "reg", hasNewValue = 1 in
2783 class T_MType_acc_rr <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2784 bit isSwap = 0, list<dag> pattern = [], bit hasNot = 0,
2785 bit isSat = 0, bit isShift = 0>
2786 : MInst < (outs IntRegs:$dst),
2787 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2788 "$dst "#mnemonic#"($src2, "#!if(hasNot, "~$src3)","$src3)")
2789 #!if(isShift, ":<<1", "")
2790 #!if(isSat, ":sat", ""),
2791 pattern, "$src1 = $dst", M_tc_2_SLOT23 > {
2796 let IClass = 0b1110;
2798 let Inst{27-24} = 0b1111;
2799 let Inst{23-21} = MajOp;
2800 let Inst{20-16} = !if(isSwap, src3, src2);
2802 let Inst{12-8} = !if(isSwap, src2, src3);
2803 let Inst{7-5} = MinOp;
2804 let Inst{4-0} = dst;
2807 let CextOpcode = "MPYI_acc", Itinerary = M_tc_3x_SLOT23 in {
2808 def M2_macsip : T_MType_acc_ri <"+= mpyi", 0b010, u8Ext,
2809 [(set (i32 IntRegs:$dst),
2810 (add (mul IntRegs:$src2, u32ImmPred:$src3),
2811 IntRegs:$src1))]>, ImmRegRel;
2813 def M2_maci : T_MType_acc_rr <"+= mpyi", 0b000, 0b000, 0,
2814 [(set (i32 IntRegs:$dst),
2815 (add (mul IntRegs:$src2, IntRegs:$src3),
2816 IntRegs:$src1))]>, ImmRegRel;
2819 let CextOpcode = "ADD_acc" in {
2820 let isExtentSigned = 1 in
2821 def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8Ext,
2822 [(set (i32 IntRegs:$dst),
2823 (add (add (i32 IntRegs:$src2), s32ImmPred:$src3),
2824 (i32 IntRegs:$src1)))]>, ImmRegRel;
2826 def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0,
2827 [(set (i32 IntRegs:$dst),
2828 (add (add (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
2829 (i32 IntRegs:$src1)))]>, ImmRegRel;
2832 let CextOpcode = "SUB_acc" in {
2833 let isExtentSigned = 1 in
2834 def M2_naccii : T_MType_acc_ri <"-= add", 0b101, s8Ext>, ImmRegRel;
2836 def M2_nacci : T_MType_acc_rr <"-= add", 0b100, 0b001, 0>, ImmRegRel;
2839 let Itinerary = M_tc_3x_SLOT23 in
2840 def M2_macsin : T_MType_acc_ri <"-= mpyi", 0b011, u8Ext>;
2842 def M2_xor_xacc : T_MType_acc_rr < "^= xor", 0b100, 0b011, 0>;
2843 def M2_subacc : T_MType_acc_rr <"+= sub", 0b000, 0b011, 1>;
2845 class T_MType_acc_pat1 <InstHexagon MI, SDNode firstOp, SDNode secOp,
2847 : Pat <(secOp IntRegs:$src1, (firstOp IntRegs:$src2, ImmPred:$src3)),
2848 (MI IntRegs:$src1, IntRegs:$src2, ImmPred:$src3)>;
2850 class T_MType_acc_pat2 <InstHexagon MI, SDNode firstOp, SDNode secOp>
2851 : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2, IntRegs:$src3))),
2852 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2854 def : T_MType_acc_pat2 <M2_xor_xacc, xor, xor>;
2855 def : T_MType_acc_pat1 <M2_macsin, mul, sub, u32ImmPred>;
2857 def : T_MType_acc_pat1 <M2_naccii, add, sub, s32ImmPred>;
2858 def : T_MType_acc_pat2 <M2_nacci, add, sub>;
2860 //===----------------------------------------------------------------------===//
2861 // Template Class -- XType Vector Instructions
2862 //===----------------------------------------------------------------------===//
2863 class T_XTYPE_Vect < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj >
2864 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
2865 "$Rdd = "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"),
2871 let IClass = 0b1110;
2873 let Inst{27-24} = 0b1000;
2874 let Inst{23-21} = MajOp;
2875 let Inst{7-5} = MinOp;
2876 let Inst{4-0} = Rdd;
2877 let Inst{20-16} = Rss;
2878 let Inst{12-8} = Rtt;
2881 class T_XTYPE_Vect_acc < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj >
2882 : MInst <(outs DoubleRegs:$Rdd),
2883 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2884 "$Rdd += "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"),
2885 [], "$dst2 = $Rdd",M_tc_3x_SLOT23 > {
2890 let IClass = 0b1110;
2892 let Inst{27-24} = 0b1010;
2893 let Inst{23-21} = MajOp;
2894 let Inst{7-5} = MinOp;
2895 let Inst{4-0} = Rdd;
2896 let Inst{20-16} = Rss;
2897 let Inst{12-8} = Rtt;
2900 class T_XTYPE_Vect_diff < bits<3> MajOp, string opc >
2901 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rtt, DoubleRegs:$Rss),
2902 "$Rdd = "#opc#"($Rtt, $Rss)",
2903 [], "",M_tc_2_SLOT23 > {
2908 let IClass = 0b1110;
2910 let Inst{27-24} = 0b1000;
2911 let Inst{23-21} = MajOp;
2912 let Inst{7-5} = 0b000;
2913 let Inst{4-0} = Rdd;
2914 let Inst{20-16} = Rss;
2915 let Inst{12-8} = Rtt;
2918 // Vector reduce add unsigned bytes: Rdd32=vrmpybu(Rss32,Rtt32)
2919 def A2_vraddub: T_XTYPE_Vect <"vraddub", 0b010, 0b001, 0>;
2920 def A2_vraddub_acc: T_XTYPE_Vect_acc <"vraddub", 0b010, 0b001, 0>;
2922 // Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt)
2923 def A2_vrsadub: T_XTYPE_Vect <"vrsadub", 0b010, 0b010, 0>;
2924 def A2_vrsadub_acc: T_XTYPE_Vect_acc <"vrsadub", 0b010, 0b010, 0>;
2926 // Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss)
2927 def M2_vabsdiffh: T_XTYPE_Vect_diff<0b011, "vabsdiffh">;
2929 // Vector absolute difference words: Rdd=vabsdiffw(Rtt,Rss)
2930 def M2_vabsdiffw: T_XTYPE_Vect_diff<0b001, "vabsdiffw">;
2932 // Vector reduce complex multiply real or imaginary:
2933 // Rdd[+]=vrcmpy[ir](Rss,Rtt[*])
2934 def M2_vrcmpyi_s0: T_XTYPE_Vect <"vrcmpyi", 0b000, 0b000, 0>;
2935 def M2_vrcmpyi_s0c: T_XTYPE_Vect <"vrcmpyi", 0b010, 0b000, 1>;
2936 def M2_vrcmaci_s0: T_XTYPE_Vect_acc <"vrcmpyi", 0b000, 0b000, 0>;
2937 def M2_vrcmaci_s0c: T_XTYPE_Vect_acc <"vrcmpyi", 0b010, 0b000, 1>;
2939 def M2_vrcmpyr_s0: T_XTYPE_Vect <"vrcmpyr", 0b000, 0b001, 0>;
2940 def M2_vrcmpyr_s0c: T_XTYPE_Vect <"vrcmpyr", 0b011, 0b001, 1>;
2941 def M2_vrcmacr_s0: T_XTYPE_Vect_acc <"vrcmpyr", 0b000, 0b001, 0>;
2942 def M2_vrcmacr_s0c: T_XTYPE_Vect_acc <"vrcmpyr", 0b011, 0b001, 1>;
2944 // Vector reduce halfwords:
2945 // Rdd[+]=vrmpyh(Rss,Rtt)
2946 def M2_vrmpy_s0: T_XTYPE_Vect <"vrmpyh", 0b000, 0b010, 0>;
2947 def M2_vrmac_s0: T_XTYPE_Vect_acc <"vrmpyh", 0b000, 0b010, 0>;
2949 //===----------------------------------------------------------------------===//
2950 // Template Class -- Vector Multipy with accumulation.
2951 // Used for complex multiply real or imaginary, dual multiply and even halfwords
2952 //===----------------------------------------------------------------------===//
2953 let Defs = [USR_OVF] in
2954 class T_M2_vmpy_acc_sat < string opc, bits<3> MajOp, bits<3> MinOp,
2955 bit hasShift, bit isRnd >
2956 : MInst <(outs DoubleRegs:$Rxx),
2957 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2958 "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
2959 #!if(isRnd,":rnd","")#":sat",
2960 [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > {
2965 let IClass = 0b1110;
2967 let Inst{27-24} = 0b1010;
2968 let Inst{23-21} = MajOp;
2969 let Inst{7-5} = MinOp;
2970 let Inst{4-0} = Rxx;
2971 let Inst{20-16} = Rss;
2972 let Inst{12-8} = Rtt;
2975 class T_M2_vmpy_acc < string opc, bits<3> MajOp, bits<3> MinOp,
2976 bit hasShift, bit isRnd >
2977 : MInst <(outs DoubleRegs:$Rxx),
2978 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2979 "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
2980 #!if(isRnd,":rnd",""),
2981 [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > {
2986 let IClass = 0b1110;
2988 let Inst{27-24} = 0b1010;
2989 let Inst{23-21} = MajOp;
2990 let Inst{7-5} = MinOp;
2991 let Inst{4-0} = Rxx;
2992 let Inst{20-16} = Rss;
2993 let Inst{12-8} = Rtt;
2996 // Vector multiply word by signed half with accumulation
2997 // Rxx+=vmpyw[eo]h(Rss,Rtt)[:<<1][:rnd]:sat
2998 def M2_mmacls_s1: T_M2_vmpy_acc_sat <"vmpyweh", 0b100, 0b101, 1, 0>;
2999 def M2_mmacls_s0: T_M2_vmpy_acc_sat <"vmpyweh", 0b000, 0b101, 0, 0>;
3000 def M2_mmacls_rs1: T_M2_vmpy_acc_sat <"vmpyweh", 0b101, 0b101, 1, 1>;
3001 def M2_mmacls_rs0: T_M2_vmpy_acc_sat <"vmpyweh", 0b001, 0b101, 0, 1>;
3003 def M2_mmachs_s1: T_M2_vmpy_acc_sat <"vmpywoh", 0b100, 0b111, 1, 0>;
3004 def M2_mmachs_s0: T_M2_vmpy_acc_sat <"vmpywoh", 0b000, 0b111, 0, 0>;
3005 def M2_mmachs_rs1: T_M2_vmpy_acc_sat <"vmpywoh", 0b101, 0b111, 1, 1>;
3006 def M2_mmachs_rs0: T_M2_vmpy_acc_sat <"vmpywoh", 0b001, 0b111, 0, 1>;
3008 // Vector multiply word by unsigned half with accumulation
3009 // Rxx+=vmpyw[eo]uh(Rss,Rtt)[:<<1][:rnd]:sat
3010 def M2_mmaculs_s1: T_M2_vmpy_acc_sat <"vmpyweuh", 0b110, 0b101, 1, 0>;
3011 def M2_mmaculs_s0: T_M2_vmpy_acc_sat <"vmpyweuh", 0b010, 0b101, 0, 0>;
3012 def M2_mmaculs_rs1: T_M2_vmpy_acc_sat <"vmpyweuh", 0b111, 0b101, 1, 1>;
3013 def M2_mmaculs_rs0: T_M2_vmpy_acc_sat <"vmpyweuh", 0b011, 0b101, 0, 1>;
3015 def M2_mmacuhs_s1: T_M2_vmpy_acc_sat <"vmpywouh", 0b110, 0b111, 1, 0>;
3016 def M2_mmacuhs_s0: T_M2_vmpy_acc_sat <"vmpywouh", 0b010, 0b111, 0, 0>;
3017 def M2_mmacuhs_rs1: T_M2_vmpy_acc_sat <"vmpywouh", 0b111, 0b111, 1, 1>;
3018 def M2_mmacuhs_rs0: T_M2_vmpy_acc_sat <"vmpywouh", 0b011, 0b111, 0, 1>;
3020 // Vector multiply even halfwords with accumulation
3021 // Rxx+=vmpyeh(Rss,Rtt)[:<<1][:sat]
3022 def M2_vmac2es: T_M2_vmpy_acc <"vmpyeh", 0b001, 0b010, 0, 0>;
3023 def M2_vmac2es_s1: T_M2_vmpy_acc_sat <"vmpyeh", 0b100, 0b110, 1, 0>;
3024 def M2_vmac2es_s0: T_M2_vmpy_acc_sat <"vmpyeh", 0b000, 0b110, 0, 0>;
3026 // Vector dual multiply with accumulation
3027 // Rxx+=vdmpy(Rss,Rtt)[:sat]
3028 def M2_vdmacs_s1: T_M2_vmpy_acc_sat <"vdmpy", 0b100, 0b100, 1, 0>;
3029 def M2_vdmacs_s0: T_M2_vmpy_acc_sat <"vdmpy", 0b000, 0b100, 0, 0>;
3031 // Vector complex multiply real or imaginary with accumulation
3032 // Rxx+=vcmpy[ir](Rss,Rtt):sat
3033 def M2_vcmac_s0_sat_r: T_M2_vmpy_acc_sat <"vcmpyr", 0b001, 0b100, 0, 0>;
3034 def M2_vcmac_s0_sat_i: T_M2_vmpy_acc_sat <"vcmpyi", 0b010, 0b100, 0, 0>;
3036 //===----------------------------------------------------------------------===//
3037 // Template Class -- Multiply signed/unsigned halfwords with and without
3038 // saturation and rounding
3039 //===----------------------------------------------------------------------===//
3040 class T_M2_mpyd < bits<2> LHbits, bit isRnd, bit hasShift, bit isUnsigned >
3041 : MInst < (outs DoubleRegs:$Rdd), (ins IntRegs:$Rs, IntRegs:$Rt),
3042 "$Rdd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
3043 #", $Rt."#!if(LHbits{0},"h)","l)")
3044 #!if(hasShift,":<<1","")
3045 #!if(isRnd,":rnd",""),
3051 let IClass = 0b1110;
3053 let Inst{27-24} = 0b0100;
3054 let Inst{23} = hasShift;
3055 let Inst{22} = isUnsigned;
3056 let Inst{21} = isRnd;
3057 let Inst{6-5} = LHbits;
3058 let Inst{4-0} = Rdd;
3059 let Inst{20-16} = Rs;
3060 let Inst{12-8} = Rt;
3063 def M2_mpyd_hh_s0: T_M2_mpyd<0b11, 0, 0, 0>;
3064 def M2_mpyd_hl_s0: T_M2_mpyd<0b10, 0, 0, 0>;
3065 def M2_mpyd_lh_s0: T_M2_mpyd<0b01, 0, 0, 0>;
3066 def M2_mpyd_ll_s0: T_M2_mpyd<0b00, 0, 0, 0>;
3068 def M2_mpyd_hh_s1: T_M2_mpyd<0b11, 0, 1, 0>;
3069 def M2_mpyd_hl_s1: T_M2_mpyd<0b10, 0, 1, 0>;
3070 def M2_mpyd_lh_s1: T_M2_mpyd<0b01, 0, 1, 0>;
3071 def M2_mpyd_ll_s1: T_M2_mpyd<0b00, 0, 1, 0>;
3073 def M2_mpyd_rnd_hh_s0: T_M2_mpyd<0b11, 1, 0, 0>;
3074 def M2_mpyd_rnd_hl_s0: T_M2_mpyd<0b10, 1, 0, 0>;
3075 def M2_mpyd_rnd_lh_s0: T_M2_mpyd<0b01, 1, 0, 0>;
3076 def M2_mpyd_rnd_ll_s0: T_M2_mpyd<0b00, 1, 0, 0>;
3078 def M2_mpyd_rnd_hh_s1: T_M2_mpyd<0b11, 1, 1, 0>;
3079 def M2_mpyd_rnd_hl_s1: T_M2_mpyd<0b10, 1, 1, 0>;
3080 def M2_mpyd_rnd_lh_s1: T_M2_mpyd<0b01, 1, 1, 0>;
3081 def M2_mpyd_rnd_ll_s1: T_M2_mpyd<0b00, 1, 1, 0>;
3083 //Rdd=mpyu(Rs.[HL],Rt.[HL])[:<<1]
3084 def M2_mpyud_hh_s0: T_M2_mpyd<0b11, 0, 0, 1>;
3085 def M2_mpyud_hl_s0: T_M2_mpyd<0b10, 0, 0, 1>;
3086 def M2_mpyud_lh_s0: T_M2_mpyd<0b01, 0, 0, 1>;
3087 def M2_mpyud_ll_s0: T_M2_mpyd<0b00, 0, 0, 1>;
3089 def M2_mpyud_hh_s1: T_M2_mpyd<0b11, 0, 1, 1>;
3090 def M2_mpyud_hl_s1: T_M2_mpyd<0b10, 0, 1, 1>;
3091 def M2_mpyud_lh_s1: T_M2_mpyd<0b01, 0, 1, 1>;
3092 def M2_mpyud_ll_s1: T_M2_mpyd<0b00, 0, 1, 1>;
3094 //===----------------------------------------------------------------------===//
3095 // Template Class for xtype mpy:
3098 // multiply 32X32 and use full result
3099 //===----------------------------------------------------------------------===//
3100 let hasSideEffects = 0 in
3101 class T_XTYPE_mpy64 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
3102 bit isSat, bit hasShift, bit isConj>
3103 : MInst <(outs DoubleRegs:$Rdd),
3104 (ins IntRegs:$Rs, IntRegs:$Rt),
3105 "$Rdd = "#mnemonic#"($Rs, $Rt"#!if(isConj,"*)",")")
3106 #!if(hasShift,":<<1","")
3107 #!if(isSat,":sat",""),
3113 let IClass = 0b1110;
3115 let Inst{27-24} = 0b0101;
3116 let Inst{23-21} = MajOp;
3117 let Inst{20-16} = Rs;
3118 let Inst{12-8} = Rt;
3119 let Inst{7-5} = MinOp;
3120 let Inst{4-0} = Rdd;
3123 //===----------------------------------------------------------------------===//
3124 // Template Class for xtype mpy with accumulation into 64-bit:
3127 // multiply 32X32 and use full result
3128 //===----------------------------------------------------------------------===//
3129 class T_XTYPE_mpy64_acc <string op1, string op2, bits<3> MajOp, bits<3> MinOp,
3130 bit isSat, bit hasShift, bit isConj>
3131 : MInst <(outs DoubleRegs:$Rxx),
3132 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
3133 "$Rxx "#op2#"= "#op1#"($Rs, $Rt"#!if(isConj,"*)",")")
3134 #!if(hasShift,":<<1","")
3135 #!if(isSat,":sat",""),
3137 [] , "$dst2 = $Rxx" > {
3142 let IClass = 0b1110;
3144 let Inst{27-24} = 0b0111;
3145 let Inst{23-21} = MajOp;
3146 let Inst{20-16} = Rs;
3147 let Inst{12-8} = Rt;
3148 let Inst{7-5} = MinOp;
3149 let Inst{4-0} = Rxx;
3152 // MPY - Multiply and use full result
3153 // Rdd = mpy[u](Rs,Rt)
3154 def M2_dpmpyss_s0 : T_XTYPE_mpy64 < "mpy", 0b000, 0b000, 0, 0, 0>;
3155 def M2_dpmpyuu_s0 : T_XTYPE_mpy64 < "mpyu", 0b010, 0b000, 0, 0, 0>;
3157 // Rxx[+-]= mpy[u](Rs,Rt)
3158 def M2_dpmpyss_acc_s0 : T_XTYPE_mpy64_acc < "mpy", "+", 0b000, 0b000, 0, 0, 0>;
3159 def M2_dpmpyss_nac_s0 : T_XTYPE_mpy64_acc < "mpy", "-", 0b001, 0b000, 0, 0, 0>;
3160 def M2_dpmpyuu_acc_s0 : T_XTYPE_mpy64_acc < "mpyu", "+", 0b010, 0b000, 0, 0, 0>;
3161 def M2_dpmpyuu_nac_s0 : T_XTYPE_mpy64_acc < "mpyu", "-", 0b011, 0b000, 0, 0, 0>;
3163 // Complex multiply real or imaginary
3164 // Rxx=cmpy[ir](Rs,Rt)
3165 def M2_cmpyi_s0 : T_XTYPE_mpy64 < "cmpyi", 0b000, 0b001, 0, 0, 0>;
3166 def M2_cmpyr_s0 : T_XTYPE_mpy64 < "cmpyr", 0b000, 0b010, 0, 0, 0>;
3168 // Rxx+=cmpy[ir](Rs,Rt)
3169 def M2_cmaci_s0 : T_XTYPE_mpy64_acc < "cmpyi", "+", 0b000, 0b001, 0, 0, 0>;
3170 def M2_cmacr_s0 : T_XTYPE_mpy64_acc < "cmpyr", "+", 0b000, 0b010, 0, 0, 0>;
3173 // Rdd=cmpy(Rs,Rt)[:<<]:sat
3174 def M2_cmpys_s0 : T_XTYPE_mpy64 < "cmpy", 0b000, 0b110, 1, 0, 0>;
3175 def M2_cmpys_s1 : T_XTYPE_mpy64 < "cmpy", 0b100, 0b110, 1, 1, 0>;
3177 // Rdd=cmpy(Rs,Rt*)[:<<]:sat
3178 def M2_cmpysc_s0 : T_XTYPE_mpy64 < "cmpy", 0b010, 0b110, 1, 0, 1>;
3179 def M2_cmpysc_s1 : T_XTYPE_mpy64 < "cmpy", 0b110, 0b110, 1, 1, 1>;
3181 // Rxx[-+]=cmpy(Rs,Rt)[:<<1]:sat
3182 def M2_cmacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b000, 0b110, 1, 0, 0>;
3183 def M2_cnacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b000, 0b111, 1, 0, 0>;
3184 def M2_cmacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b100, 0b110, 1, 1, 0>;
3185 def M2_cnacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b100, 0b111, 1, 1, 0>;
3187 // Rxx[-+]=cmpy(Rs,Rt*)[:<<1]:sat
3188 def M2_cmacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b010, 0b110, 1, 0, 1>;
3189 def M2_cnacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b010, 0b111, 1, 0, 1>;
3190 def M2_cmacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b110, 0b110, 1, 1, 1>;
3191 def M2_cnacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b110, 0b111, 1, 1, 1>;
3193 // Vector multiply halfwords
3194 // Rdd=vmpyh(Rs,Rt)[:<<]:sat
3195 //let Defs = [USR_OVF] in {
3196 def M2_vmpy2s_s1 : T_XTYPE_mpy64 < "vmpyh", 0b100, 0b101, 1, 1, 0>;
3197 def M2_vmpy2s_s0 : T_XTYPE_mpy64 < "vmpyh", 0b000, 0b101, 1, 0, 0>;
3200 // Rxx+=vmpyh(Rs,Rt)[:<<1][:sat]
3201 def M2_vmac2 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b001, 0b001, 0, 0, 0>;
3202 def M2_vmac2s_s1 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b100, 0b101, 1, 1, 0>;
3203 def M2_vmac2s_s0 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b000, 0b101, 1, 0, 0>;
3205 def: Pat<(i64 (mul (i64 (anyext (i32 IntRegs:$src1))),
3206 (i64 (anyext (i32 IntRegs:$src2))))),
3207 (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>;
3209 def: Pat<(i64 (mul (i64 (sext (i32 IntRegs:$src1))),
3210 (i64 (sext (i32 IntRegs:$src2))))),
3211 (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>;
3213 def: Pat<(i64 (mul (is_sext_i32:$src1),
3214 (is_sext_i32:$src2))),
3215 (M2_dpmpyss_s0 (LoReg DoubleRegs:$src1), (LoReg DoubleRegs:$src2))>;
3217 // Multiply and accumulate, use full result.
3218 // Rxx[+-]=mpy(Rs,Rt)
3220 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
3221 (mul (i64 (sext (i32 IntRegs:$src2))),
3222 (i64 (sext (i32 IntRegs:$src3)))))),
3223 (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3225 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
3226 (mul (i64 (sext (i32 IntRegs:$src2))),
3227 (i64 (sext (i32 IntRegs:$src3)))))),
3228 (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3230 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
3231 (mul (i64 (anyext (i32 IntRegs:$src2))),
3232 (i64 (anyext (i32 IntRegs:$src3)))))),
3233 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3235 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
3236 (mul (i64 (zext (i32 IntRegs:$src2))),
3237 (i64 (zext (i32 IntRegs:$src3)))))),
3238 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3240 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
3241 (mul (i64 (anyext (i32 IntRegs:$src2))),
3242 (i64 (anyext (i32 IntRegs:$src3)))))),
3243 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3245 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
3246 (mul (i64 (zext (i32 IntRegs:$src2))),
3247 (i64 (zext (i32 IntRegs:$src3)))))),
3248 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3250 //===----------------------------------------------------------------------===//
3252 //===----------------------------------------------------------------------===//
3254 //===----------------------------------------------------------------------===//
3256 //===----------------------------------------------------------------------===//
3257 //===----------------------------------------------------------------------===//
3259 //===----------------------------------------------------------------------===//
3261 //===----------------------------------------------------------------------===//
3263 //===----------------------------------------------------------------------===//
3264 //===----------------------------------------------------------------------===//
3266 //===----------------------------------------------------------------------===//
3268 //===----------------------------------------------------------------------===//
3270 //===----------------------------------------------------------------------===//
3271 //===----------------------------------------------------------------------===//
3273 //===----------------------------------------------------------------------===//
3275 //===----------------------------------------------------------------------===//
3277 //===----------------------------------------------------------------------===//
3279 // Store doubleword.
3280 //===----------------------------------------------------------------------===//
3281 // Template class for non-predicated post increment stores with immediate offset
3282 //===----------------------------------------------------------------------===//
3283 let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc in
3284 class T_store_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
3285 bits<4> MajOp, bit isHalf >
3286 : STInst <(outs IntRegs:$_dst_),
3287 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
3288 mnemonic#"($src1++#$offset) = $src2"#!if(isHalf, ".h", ""),
3289 [], "$src1 = $_dst_" >,
3296 string ImmOpStr = !cast<string>(ImmOp);
3297 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
3298 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
3299 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
3300 /* s4_0Imm */ offset{3-0})));
3301 // Store upper-half and store doubleword cannot be NV.
3302 let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, !if(isHalf,0,1));
3304 let IClass = 0b1010;
3306 let Inst{27-25} = 0b101;
3307 let Inst{24-21} = MajOp;
3308 let Inst{20-16} = src1;
3310 let Inst{12-8} = src2;
3312 let Inst{6-3} = offsetBits;
3316 //===----------------------------------------------------------------------===//
3317 // Template class for predicated post increment stores with immediate offset
3318 //===----------------------------------------------------------------------===//
3319 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
3320 class T_pstore_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
3321 bits<4> MajOp, bit isHalf, bit isPredNot, bit isPredNew>
3322 : STInst <(outs IntRegs:$_dst_),
3323 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
3324 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3325 ") ")#mnemonic#"($src2++#$offset) = $src3"#!if(isHalf, ".h", ""),
3326 [], "$src2 = $_dst_" >,
3334 string ImmOpStr = !cast<string>(ImmOp);
3335 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
3336 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
3337 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
3338 /* s4_0Imm */ offset{3-0})));
3340 // Store upper-half and store doubleword cannot be NV.
3341 let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, !if(isHalf,0,1));
3342 let isPredicatedNew = isPredNew;
3343 let isPredicatedFalse = isPredNot;
3345 let IClass = 0b1010;
3347 let Inst{27-25} = 0b101;
3348 let Inst{24-21} = MajOp;
3349 let Inst{20-16} = src2;
3351 let Inst{12-8} = src3;
3352 let Inst{7} = isPredNew;
3353 let Inst{6-3} = offsetBits;
3354 let Inst{2} = isPredNot;
3355 let Inst{1-0} = src1;
3358 multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
3359 Operand ImmOp, bits<4> MajOp, bit isHalf = 0 > {
3361 let BaseOpcode = "POST_"#BaseOp in {
3362 def S2_#NAME#_pi : T_store_pi <mnemonic, RC, ImmOp, MajOp, isHalf>;
3365 def S2_p#NAME#t_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 0, 0>;
3366 def S2_p#NAME#f_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 1, 0>;
3369 def S2_p#NAME#tnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp,
3371 def S2_p#NAME#fnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp,
3376 let accessSize = ByteAccess in
3377 defm storerb: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm, 0b1000>;
3379 let accessSize = HalfWordAccess in
3380 defm storerh: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm, 0b1010>;
3382 let accessSize = WordAccess in
3383 defm storeri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm, 0b1100>;
3385 let accessSize = DoubleWordAccess in
3386 defm storerd: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm, 0b1110>;
3388 let accessSize = HalfWordAccess, isNVStorable = 0 in
3389 defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>;
3391 class Storepi_pat<PatFrag Store, PatFrag Value, PatFrag Offset,
3393 : Pat<(Store Value:$src1, I32:$src2, Offset:$offset),
3394 (MI I32:$src2, imm:$offset, Value:$src1)>;
3396 def: Storepi_pat<post_truncsti8, I32, s4_0ImmPred, S2_storerb_pi>;
3397 def: Storepi_pat<post_truncsti16, I32, s4_1ImmPred, S2_storerh_pi>;
3398 def: Storepi_pat<post_store, I32, s4_2ImmPred, S2_storeri_pi>;
3399 def: Storepi_pat<post_store, I64, s4_3ImmPred, S2_storerd_pi>;
3401 //===----------------------------------------------------------------------===//
3402 // Template class for post increment stores with register offset.
3403 //===----------------------------------------------------------------------===//
3404 class T_store_pr <string mnemonic, RegisterClass RC, bits<3> MajOp,
3405 MemAccessSize AccessSz, bit isHalf = 0>
3406 : STInst <(outs IntRegs:$_dst_),
3407 (ins IntRegs:$src1, ModRegs:$src2, RC:$src3),
3408 mnemonic#"($src1++$src2) = $src3"#!if(isHalf, ".h", ""),
3409 [], "$src1 = $_dst_" > {
3413 let accessSize = AccessSz;
3415 // Store upper-half and store doubleword cannot be NV.
3416 let isNVStorable = !if(!eq(mnemonic,"memd"), 0, !if(isHalf,0,1));
3418 let IClass = 0b1010;
3420 let Inst{27-24} = 0b1101;
3421 let Inst{23-21} = MajOp;
3422 let Inst{20-16} = src1;
3423 let Inst{13} = src2;
3424 let Inst{12-8} = src3;
3428 def S2_storerb_pr : T_store_pr<"memb", IntRegs, 0b000, ByteAccess>;
3429 def S2_storerh_pr : T_store_pr<"memh", IntRegs, 0b010, HalfWordAccess>;
3430 def S2_storeri_pr : T_store_pr<"memw", IntRegs, 0b100, WordAccess>;
3431 def S2_storerd_pr : T_store_pr<"memd", DoubleRegs, 0b110, DoubleWordAccess>;
3432 def S2_storerf_pr : T_store_pr<"memh", IntRegs, 0b011, HalfWordAccess, 1>;
3434 let opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
3435 class T_store_io <string mnemonic, RegisterClass RC, Operand ImmOp,
3436 bits<3> MajOp, bit isH = 0>
3438 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
3439 mnemonic#"($src1+#$src2) = $src3"#!if(isH,".h","")>,
3440 AddrModeRel, ImmRegRel {
3442 bits<14> src2; // Actual address offset
3444 bits<11> offsetBits; // Represents offset encoding
3446 string ImmOpStr = !cast<string>(ImmOp);
3448 let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14,
3449 !if (!eq(ImmOpStr, "s11_2Ext"), 13,
3450 !if (!eq(ImmOpStr, "s11_1Ext"), 12,
3451 /* s11_0Ext */ 11)));
3452 let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), src2{13-3},
3453 !if (!eq(ImmOpStr, "s11_2Ext"), src2{12-2},
3454 !if (!eq(ImmOpStr, "s11_1Ext"), src2{11-1},
3455 /* s11_0Ext */ src2{10-0})));
3456 // Store upper-half and store doubleword cannot be NV.
3457 let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1));
3458 let IClass = 0b1010;
3461 let Inst{26-25} = offsetBits{10-9};
3463 let Inst{23-21} = MajOp;
3464 let Inst{20-16} = src1;
3465 let Inst{13} = offsetBits{8};
3466 let Inst{12-8} = src3;
3467 let Inst{7-0} = offsetBits{7-0};
3470 let opExtendable = 2, isPredicated = 1 in
3471 class T_pstore_io <string mnemonic, RegisterClass RC, Operand ImmOp,
3472 bits<3>MajOp, bit PredNot, bit isPredNew, bit isH = 0>
3474 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
3475 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3476 ") ")#mnemonic#"($src2+#$src3) = $src4"#!if(isH,".h",""),
3477 [],"",V2LDST_tc_st_SLOT01 >,
3478 AddrModeRel, ImmRegRel {
3481 bits<9> src3; // Actual address offset
3483 bits<6> offsetBits; // Represents offset encoding
3485 let isPredicatedNew = isPredNew;
3486 let isPredicatedFalse = PredNot;
3488 string ImmOpStr = !cast<string>(ImmOp);
3489 let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9,
3490 !if (!eq(ImmOpStr, "u6_2Ext"), 8,
3491 !if (!eq(ImmOpStr, "u6_1Ext"), 7,
3493 let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), src3{8-3},
3494 !if (!eq(ImmOpStr, "u6_2Ext"), src3{7-2},
3495 !if (!eq(ImmOpStr, "u6_1Ext"), src3{6-1},
3496 /* u6_0Ext */ src3{5-0})));
3497 // Store upper-half and store doubleword cannot be NV.
3498 let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1));
3500 let IClass = 0b0100;
3503 let Inst{26} = PredNot;
3504 let Inst{25} = isPredNew;
3506 let Inst{23-21} = MajOp;
3507 let Inst{20-16} = src2;
3508 let Inst{13} = offsetBits{5};
3509 let Inst{12-8} = src4;
3510 let Inst{7-3} = offsetBits{4-0};
3511 let Inst{1-0} = src1;
3514 let isExtendable = 1, hasSideEffects = 0 in
3515 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
3516 Operand ImmOp, Operand predImmOp, bits<3> MajOp, bit isH = 0> {
3517 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
3518 def S2_#NAME#_io : T_store_io <mnemonic, RC, ImmOp, MajOp, isH>;
3521 def S2_p#NAME#t_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 0, 0, isH>;
3522 def S2_p#NAME#f_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 1, 0, isH>;
3525 def S4_p#NAME#tnew_io : T_pstore_io <mnemonic, RC, predImmOp,
3527 def S4_p#NAME#fnew_io : T_pstore_io <mnemonic, RC, predImmOp,
3532 let addrMode = BaseImmOffset, InputType = "imm" in {
3533 let accessSize = ByteAccess in
3534 defm storerb: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext, u6_0Ext, 0b000>;
3536 let accessSize = HalfWordAccess, opExtentAlign = 1 in
3537 defm storerh: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext, u6_1Ext, 0b010>;
3539 let accessSize = WordAccess, opExtentAlign = 2 in
3540 defm storeri: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext, u6_2Ext, 0b100>;
3542 let accessSize = DoubleWordAccess, isNVStorable = 0, opExtentAlign = 3 in
3543 defm storerd: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
3546 let accessSize = HalfWordAccess, opExtentAlign = 1 in
3547 defm storerf: ST_Idxd < "memh", "STrif", IntRegs, s11_1Ext,
3551 // Patterns for generating stores, where the address takes different forms:
3553 // - frameindex + offset,
3555 // - simple (base address without offset).
3556 // These would usually be used together (via Storex_pat defined below), but
3557 // in some cases one may want to apply different properties (such as
3558 // AddedComplexity) to the individual patterns.
3559 class Storex_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
3560 : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>;
3561 class Storex_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
3563 : Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)),
3564 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>;
3565 class Storex_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
3567 : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
3568 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
3569 class Storex_simple_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
3570 : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)),
3571 (MI IntRegs:$Rs, 0, Value:$Rt)>;
3573 // Patterns for generating stores, where the address takes different forms,
3574 // and where the value being stored is transformed through the value modifier
3575 // ValueMod. The address forms are same as above.
3576 class Storexm_fi_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod,
3578 : Pat<(Store Value:$Rs, AddrFI:$fi),
3579 (MI AddrFI:$fi, 0, (ValueMod Value:$Rs))>;
3580 class Storexm_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
3581 PatFrag ValueMod, InstHexagon MI>
3582 : Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)),
3583 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>;
3584 class Storexm_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
3585 PatFrag ValueMod, InstHexagon MI>
3586 : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
3587 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>;
3588 class Storexm_simple_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod,
3590 : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)),
3591 (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>;
3593 multiclass Storex_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
3595 def: Storex_fi_pat <Store, Value, MI>;
3596 def: Storex_fi_add_pat <Store, Value, ImmPred, MI>;
3597 def: Storex_add_pat <Store, Value, ImmPred, MI>;
3600 multiclass Storexm_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
3601 PatFrag ValueMod, InstHexagon MI> {
3602 def: Storexm_fi_pat <Store, Value, ValueMod, MI>;
3603 def: Storexm_fi_add_pat <Store, Value, ImmPred, ValueMod, MI>;
3604 def: Storexm_add_pat <Store, Value, ImmPred, ValueMod, MI>;
3607 // Regular stores in the DAG have two operands: value and address.
3608 // Atomic stores also have two, but they are reversed: address, value.
3609 // To use atomic stores with the patterns, they need to have their operands
3610 // swapped. This relies on the knowledge that the F.Fragment uses names
3612 class SwapSt<PatFrag F>
3613 : PatFrag<(ops node:$val, node:$ptr), F.Fragment>;
3615 let AddedComplexity = 20 in {
3616 defm: Storex_pat<truncstorei8, I32, s32_0ImmPred, S2_storerb_io>;
3617 defm: Storex_pat<truncstorei16, I32, s31_1ImmPred, S2_storerh_io>;
3618 defm: Storex_pat<store, I32, s30_2ImmPred, S2_storeri_io>;
3619 defm: Storex_pat<store, I64, s29_3ImmPred, S2_storerd_io>;
3621 defm: Storex_pat<SwapSt<atomic_store_8>, I32, s32_0ImmPred, S2_storerb_io>;
3622 defm: Storex_pat<SwapSt<atomic_store_16>, I32, s31_1ImmPred, S2_storerh_io>;
3623 defm: Storex_pat<SwapSt<atomic_store_32>, I32, s30_2ImmPred, S2_storeri_io>;
3624 defm: Storex_pat<SwapSt<atomic_store_64>, I64, s29_3ImmPred, S2_storerd_io>;
3627 // Simple patterns should be tried with the least priority.
3628 def: Storex_simple_pat<truncstorei8, I32, S2_storerb_io>;
3629 def: Storex_simple_pat<truncstorei16, I32, S2_storerh_io>;
3630 def: Storex_simple_pat<store, I32, S2_storeri_io>;
3631 def: Storex_simple_pat<store, I64, S2_storerd_io>;
3633 def: Storex_simple_pat<SwapSt<atomic_store_8>, I32, S2_storerb_io>;
3634 def: Storex_simple_pat<SwapSt<atomic_store_16>, I32, S2_storerh_io>;
3635 def: Storex_simple_pat<SwapSt<atomic_store_32>, I32, S2_storeri_io>;
3636 def: Storex_simple_pat<SwapSt<atomic_store_64>, I64, S2_storerd_io>;
3638 let AddedComplexity = 20 in {
3639 defm: Storexm_pat<truncstorei8, I64, s32_0ImmPred, LoReg, S2_storerb_io>;
3640 defm: Storexm_pat<truncstorei16, I64, s31_1ImmPred, LoReg, S2_storerh_io>;
3641 defm: Storexm_pat<truncstorei32, I64, s30_2ImmPred, LoReg, S2_storeri_io>;
3644 def: Storexm_simple_pat<truncstorei8, I64, LoReg, S2_storerb_io>;
3645 def: Storexm_simple_pat<truncstorei16, I64, LoReg, S2_storerh_io>;
3646 def: Storexm_simple_pat<truncstorei32, I64, LoReg, S2_storeri_io>;
3649 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
3650 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
3651 def STriw_pred : STInst<(outs),
3652 (ins IntRegs:$addr, s11_2Ext:$off, PredRegs:$src1),
3653 ".error \"should not emit\"", []>;
3655 // S2_allocframe: Allocate stack frame.
3656 let Defs = [R29, R30], Uses = [R29, R31, R30],
3657 hasSideEffects = 0, accessSize = DoubleWordAccess in
3658 def S2_allocframe: ST0Inst <
3659 (outs), (ins u11_3Imm:$u11_3),
3660 "allocframe(#$u11_3)" > {
3663 let IClass = 0b1010;
3664 let Inst{27-16} = 0b000010011101;
3665 let Inst{13-11} = 0b000;
3666 let Inst{10-0} = u11_3{13-3};
3669 // S2_storer[bhwdf]_pci: Store byte/half/word/double.
3670 // S2_storer[bhwdf]_pci -> S2_storerbnew_pci
3672 class T_store_pci <string mnemonic, RegisterClass RC,
3673 Operand Imm, bits<4>MajOp,
3674 MemAccessSize AlignSize, string RegSrc = "Rt">
3675 : STInst <(outs IntRegs:$_dst_),
3676 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, RC:$Rt),
3677 #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $"#RegSrc#"",
3684 let accessSize = AlignSize;
3685 let isNVStorable = !if(!eq(mnemonic,"memd"), 0,
3686 !if(!eq(RegSrc,"Rt.h"), 0, 1));
3688 let IClass = 0b1010;
3689 let Inst{27-25} = 0b100;
3690 let Inst{24-21} = MajOp;
3691 let Inst{20-16} = Rz;
3693 let Inst{12-8} = Rt;
3696 !if (!eq(!cast<string>(AlignSize), "DoubleWordAccess"), offset{6-3},
3697 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
3698 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
3699 /* ByteAccess */ offset{3-0})));
3703 def S2_storerb_pci : T_store_pci<"memb", IntRegs, s4_0Imm, 0b1000,
3705 def S2_storerh_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1010,
3707 def S2_storerf_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1011,
3708 HalfWordAccess, "Rt.h">;
3709 def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100,
3711 def S2_storerd_pci : T_store_pci<"memd", DoubleRegs, s4_3Imm, 0b1110,
3714 let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 4 in
3715 class T_storenew_pci <string mnemonic, Operand Imm,
3716 bits<2>MajOp, MemAccessSize AlignSize>
3717 : NVInst < (outs IntRegs:$_dst_),
3718 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, IntRegs:$Nt),
3719 #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $Nt.new",
3727 let accessSize = AlignSize;
3729 let IClass = 0b1010;
3730 let Inst{27-21} = 0b1001101;
3731 let Inst{20-16} = Rz;
3733 let Inst{12-11} = MajOp;
3734 let Inst{10-8} = Nt;
3737 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
3738 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
3739 /* ByteAccess */ offset{3-0}));
3743 def S2_storerbnew_pci : T_storenew_pci <"memb", s4_0Imm, 0b00, ByteAccess>;
3744 def S2_storerhnew_pci : T_storenew_pci <"memh", s4_1Imm, 0b01, HalfWordAccess>;
3745 def S2_storerinew_pci : T_storenew_pci <"memw", s4_2Imm, 0b10, WordAccess>;
3747 //===----------------------------------------------------------------------===//
3748 // Circular stores - Pseudo
3750 // Please note that the input operand order in the pseudo instructions
3751 // doesn't match with the real instructions. Pseudo instructions operand
3752 // order should mimics the ordering in the intrinsics.
3753 //===----------------------------------------------------------------------===//
3754 let isCodeGenOnly = 1, mayStore = 1, hasSideEffects = 0, isPseudo = 1 in
3755 class T_store_pci_pseudo <string opc, RegisterClass RC>
3756 : STInstPI<(outs IntRegs:$_dst_),
3757 (ins IntRegs:$src1, RC:$src2, IntRegs:$src3, s4Imm:$src4),
3758 ".error \""#opc#"($src1++#$src4:circ($src3)) = $src2\"",
3759 [], "$_dst_ = $src1">;
3761 def S2_storerb_pci_pseudo : T_store_pci_pseudo <"memb", IntRegs>;
3762 def S2_storerh_pci_pseudo : T_store_pci_pseudo <"memh", IntRegs>;
3763 def S2_storerf_pci_pseudo : T_store_pci_pseudo <"memh", IntRegs>;
3764 def S2_storeri_pci_pseudo : T_store_pci_pseudo <"memw", IntRegs>;
3765 def S2_storerd_pci_pseudo : T_store_pci_pseudo <"memd", DoubleRegs>;
3767 //===----------------------------------------------------------------------===//
3768 // Circular stores with auto-increment register
3769 //===----------------------------------------------------------------------===//
3771 class T_store_pcr <string mnemonic, RegisterClass RC, bits<4>MajOp,
3772 MemAccessSize AlignSize, string RegSrc = "Rt">
3773 : STInst <(outs IntRegs:$_dst_),
3774 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$Rt),
3775 #mnemonic#"($Rz ++ I:circ($Mu)) = $"#RegSrc#"",
3782 let accessSize = AlignSize;
3783 let isNVStorable = !if(!eq(mnemonic,"memd"), 0,
3784 !if(!eq(RegSrc,"Rt.h"), 0, 1));
3786 let IClass = 0b1010;
3787 let Inst{27-25} = 0b100;
3788 let Inst{24-21} = MajOp;
3789 let Inst{20-16} = Rz;
3791 let Inst{12-8} = Rt;
3796 def S2_storerb_pcr : T_store_pcr<"memb", IntRegs, 0b1000, ByteAccess>;
3797 def S2_storerh_pcr : T_store_pcr<"memh", IntRegs, 0b1010, HalfWordAccess>;
3798 def S2_storeri_pcr : T_store_pcr<"memw", IntRegs, 0b1100, WordAccess>;
3799 def S2_storerd_pcr : T_store_pcr<"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
3800 def S2_storerf_pcr : T_store_pcr<"memh", IntRegs, 0b1011,
3801 HalfWordAccess, "Rt.h">;
3803 //===----------------------------------------------------------------------===//
3804 // Circular .new stores with auto-increment register
3805 //===----------------------------------------------------------------------===//
3806 let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
3807 class T_storenew_pcr <string mnemonic, bits<2>MajOp,
3808 MemAccessSize AlignSize>
3809 : NVInst <(outs IntRegs:$_dst_),
3810 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3811 #mnemonic#"($Rz ++ I:circ($Mu)) = $Nt.new" ,
3818 let accessSize = AlignSize;
3820 let IClass = 0b1010;
3821 let Inst{27-21} = 0b1001101;
3822 let Inst{20-16} = Rz;
3824 let Inst{12-11} = MajOp;
3825 let Inst{10-8} = Nt;
3830 def S2_storerbnew_pcr : T_storenew_pcr <"memb", 0b00, ByteAccess>;
3831 def S2_storerhnew_pcr : T_storenew_pcr <"memh", 0b01, HalfWordAccess>;
3832 def S2_storerinew_pcr : T_storenew_pcr <"memw", 0b10, WordAccess>;
3834 //===----------------------------------------------------------------------===//
3835 // Bit-reversed stores with auto-increment register
3836 //===----------------------------------------------------------------------===//
3837 let hasSideEffects = 0 in
3838 class T_store_pbr<string mnemonic, RegisterClass RC,
3839 MemAccessSize addrSize, bits<3> majOp,
3842 <(outs IntRegs:$_dst_),
3843 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$src),
3844 #mnemonic#"($Rz ++ $Mu:brev) = $src"#!if (!eq(isHalf, 1), ".h", ""),
3845 [], "$Rz = $_dst_" > {
3847 let accessSize = addrSize;
3853 let IClass = 0b1010;
3855 let Inst{27-24} = 0b1111;
3856 let Inst{23-21} = majOp;
3858 let Inst{20-16} = Rz;
3860 let Inst{12-8} = src;
3863 let isNVStorable = 1 in {
3864 let BaseOpcode = "S2_storerb_pbr" in
3865 def S2_storerb_pbr : T_store_pbr<"memb", IntRegs, ByteAccess,
3866 0b000>, NewValueRel;
3867 let BaseOpcode = "S2_storerh_pbr" in
3868 def S2_storerh_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess,
3869 0b010>, NewValueRel;
3870 let BaseOpcode = "S2_storeri_pbr" in
3871 def S2_storeri_pbr : T_store_pbr<"memw", IntRegs, WordAccess,
3872 0b100>, NewValueRel;
3875 def S2_storerf_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess, 0b011, 1>;
3876 def S2_storerd_pbr : T_store_pbr<"memd", DoubleRegs, DoubleWordAccess, 0b110>;
3878 //===----------------------------------------------------------------------===//
3879 // Bit-reversed .new stores with auto-increment register
3880 //===----------------------------------------------------------------------===//
3881 let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3,
3882 hasSideEffects = 0 in
3883 class T_storenew_pbr<string mnemonic, MemAccessSize addrSize, bits<2> majOp>
3884 : NVInst <(outs IntRegs:$_dst_),
3885 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3886 #mnemonic#"($Rz ++ $Mu:brev) = $Nt.new", [],
3887 "$Rz = $_dst_">, NewValueRel {
3888 let accessSize = addrSize;
3893 let IClass = 0b1010;
3895 let Inst{27-21} = 0b1111101;
3896 let Inst{12-11} = majOp;
3898 let Inst{20-16} = Rz;
3900 let Inst{10-8} = Nt;
3903 let BaseOpcode = "S2_storerb_pbr" in
3904 def S2_storerbnew_pbr : T_storenew_pbr<"memb", ByteAccess, 0b00>;
3906 let BaseOpcode = "S2_storerh_pbr" in
3907 def S2_storerhnew_pbr : T_storenew_pbr<"memh", HalfWordAccess, 0b01>;
3909 let BaseOpcode = "S2_storeri_pbr" in
3910 def S2_storerinew_pbr : T_storenew_pbr<"memw", WordAccess, 0b10>;
3912 //===----------------------------------------------------------------------===//
3913 // Bit-reversed stores - Pseudo
3915 // Please note that the input operand order in the pseudo instructions
3916 // doesn't match with the real instructions. Pseudo instructions operand
3917 // order should mimics the ordering in the intrinsics.
3918 //===----------------------------------------------------------------------===//
3919 let isCodeGenOnly = 1, mayStore = 1, hasSideEffects = 0, isPseudo = 1 in
3920 class T_store_pbr_pseudo <string opc, RegisterClass RC>
3921 : STInstPI<(outs IntRegs:$_dst_),
3922 (ins IntRegs:$src1, RC:$src2, IntRegs:$src3),
3923 ".error \""#opc#"($src1++$src3:brev) = $src2\"",
3924 [], "$_dst_ = $src1">;
3926 def S2_storerb_pbr_pseudo : T_store_pbr_pseudo <"memb", IntRegs>;
3927 def S2_storerh_pbr_pseudo : T_store_pbr_pseudo <"memh", IntRegs>;
3928 def S2_storeri_pbr_pseudo : T_store_pbr_pseudo <"memw", IntRegs>;
3929 def S2_storerf_pbr_pseudo : T_store_pbr_pseudo <"memh", IntRegs>;
3930 def S2_storerd_pbr_pseudo : T_store_pbr_pseudo <"memd", DoubleRegs>;
3932 //===----------------------------------------------------------------------===//
3934 //===----------------------------------------------------------------------===//
3936 //===----------------------------------------------------------------------===//
3937 // Template class for S_2op instructions.
3938 //===----------------------------------------------------------------------===//
3939 let hasSideEffects = 0 in
3940 class T_S2op_1 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
3941 RegisterClass RCIn, bits<2> MajOp, bits<3> MinOp, bit isSat>
3942 : SInst <(outs RCOut:$dst), (ins RCIn:$src),
3943 "$dst = "#mnemonic#"($src)"#!if(isSat, ":sat", ""),
3944 [], "", S_2op_tc_1_SLOT23 > {
3948 let IClass = 0b1000;
3950 let Inst{27-24} = RegTyBits;
3951 let Inst{23-22} = MajOp;
3953 let Inst{20-16} = src;
3954 let Inst{7-5} = MinOp;
3955 let Inst{4-0} = dst;
3958 class T_S2op_1_di <string mnemonic, bits<2> MajOp, bits<3> MinOp>
3959 : T_S2op_1 <mnemonic, 0b0100, DoubleRegs, IntRegs, MajOp, MinOp, 0>;
3961 let hasNewValue = 1 in
3962 class T_S2op_1_id <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
3963 : T_S2op_1 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, isSat>;
3965 let hasNewValue = 1 in
3966 class T_S2op_1_ii <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
3967 : T_S2op_1 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, isSat>;
3969 // Vector sign/zero extend
3970 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
3971 def S2_vsxtbh : T_S2op_1_di <"vsxtbh", 0b00, 0b000>;
3972 def S2_vsxthw : T_S2op_1_di <"vsxthw", 0b00, 0b100>;
3973 def S2_vzxtbh : T_S2op_1_di <"vzxtbh", 0b00, 0b010>;
3974 def S2_vzxthw : T_S2op_1_di <"vzxthw", 0b00, 0b110>;
3977 // Vector splat bytes/halfwords
3978 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
3979 def S2_vsplatrb : T_S2op_1_ii <"vsplatb", 0b01, 0b111>;
3980 def S2_vsplatrh : T_S2op_1_di <"vsplath", 0b01, 0b010>;
3983 // Sign extend word to doubleword
3984 def A2_sxtw : T_S2op_1_di <"sxtw", 0b01, 0b000>;
3986 def: Pat <(i64 (sext I32:$src)), (A2_sxtw I32:$src)>;
3988 // Vector saturate and pack
3989 let Defs = [USR_OVF] in {
3990 def S2_svsathb : T_S2op_1_ii <"vsathb", 0b10, 0b000>;
3991 def S2_svsathub : T_S2op_1_ii <"vsathub", 0b10, 0b010>;
3992 def S2_vsathb : T_S2op_1_id <"vsathb", 0b00, 0b110>;
3993 def S2_vsathub : T_S2op_1_id <"vsathub", 0b00, 0b000>;
3994 def S2_vsatwh : T_S2op_1_id <"vsatwh", 0b00, 0b010>;
3995 def S2_vsatwuh : T_S2op_1_id <"vsatwuh", 0b00, 0b100>;
3999 def S2_vtrunohb : T_S2op_1_id <"vtrunohb", 0b10, 0b000>;
4000 def S2_vtrunehb : T_S2op_1_id <"vtrunehb", 0b10, 0b010>;
4002 // Swizzle the bytes of a word
4003 def A2_swiz : T_S2op_1_ii <"swiz", 0b10, 0b111>;
4006 let Defs = [USR_OVF] in {
4007 def A2_sat : T_S2op_1_id <"sat", 0b11, 0b000>;
4008 def A2_satb : T_S2op_1_ii <"satb", 0b11, 0b111>;
4009 def A2_satub : T_S2op_1_ii <"satub", 0b11, 0b110>;
4010 def A2_sath : T_S2op_1_ii <"sath", 0b11, 0b100>;
4011 def A2_satuh : T_S2op_1_ii <"satuh", 0b11, 0b101>;
4012 def A2_roundsat : T_S2op_1_id <"round", 0b11, 0b001, 0b1>;
4015 let Itinerary = S_2op_tc_2_SLOT23 in {
4016 // Vector round and pack
4017 def S2_vrndpackwh : T_S2op_1_id <"vrndwh", 0b10, 0b100>;
4019 let Defs = [USR_OVF] in
4020 def S2_vrndpackwhs : T_S2op_1_id <"vrndwh", 0b10, 0b110, 1>;
4023 def S2_brev : T_S2op_1_ii <"brev", 0b01, 0b110>;
4025 // Absolute value word
4026 def A2_abs : T_S2op_1_ii <"abs", 0b10, 0b100>;
4028 let Defs = [USR_OVF] in
4029 def A2_abssat : T_S2op_1_ii <"abs", 0b10, 0b101, 1>;
4031 // Negate with saturation
4032 let Defs = [USR_OVF] in
4033 def A2_negsat : T_S2op_1_ii <"neg", 0b10, 0b110, 1>;
4036 def: Pat<(i32 (select (i1 (setlt (i32 IntRegs:$src), 0)),
4037 (i32 (sub 0, (i32 IntRegs:$src))),
4038 (i32 IntRegs:$src))),
4039 (A2_abs IntRegs:$src)>;
4041 let AddedComplexity = 50 in
4042 def: Pat<(i32 (xor (add (sra (i32 IntRegs:$src), (i32 31)),
4043 (i32 IntRegs:$src)),
4044 (sra (i32 IntRegs:$src), (i32 31)))),
4045 (A2_abs IntRegs:$src)>;
4047 class T_S2op_2 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
4048 RegisterClass RCIn, bits<3> MajOp, bits<3> MinOp,
4049 bit isSat, bit isRnd, list<dag> pattern = []>
4050 : SInst <(outs RCOut:$dst),
4051 (ins RCIn:$src, u5Imm:$u5),
4052 "$dst = "#mnemonic#"($src, #$u5)"#!if(isSat, ":sat", "")
4053 #!if(isRnd, ":rnd", ""),
4054 pattern, "", S_2op_tc_2_SLOT23> {
4059 let IClass = 0b1000;
4061 let Inst{27-24} = RegTyBits;
4062 let Inst{23-21} = MajOp;
4063 let Inst{20-16} = src;
4065 let Inst{12-8} = u5;
4066 let Inst{7-5} = MinOp;
4067 let Inst{4-0} = dst;
4070 class T_S2op_2_di <string mnemonic, bits<3> MajOp, bits<3> MinOp>
4071 : T_S2op_2 <mnemonic, 0b1000, DoubleRegs, IntRegs, MajOp, MinOp, 0, 0>;
4073 let hasNewValue = 1 in
4074 class T_S2op_2_id <string mnemonic, bits<3> MajOp, bits<3> MinOp>
4075 : T_S2op_2 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, 0, 0>;
4077 let hasNewValue = 1 in
4078 class T_S2op_2_ii <string mnemonic, bits<3> MajOp, bits<3> MinOp,
4079 bit isSat = 0, bit isRnd = 0, list<dag> pattern = []>
4080 : T_S2op_2 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp,
4081 isSat, isRnd, pattern>;
4083 class T_S2op_shift <string mnemonic, bits<3> MajOp, bits<3> MinOp, SDNode OpNd>
4084 : T_S2op_2_ii <mnemonic, MajOp, MinOp, 0, 0,
4085 [(set (i32 IntRegs:$dst), (OpNd (i32 IntRegs:$src),
4086 (u5ImmPred:$u5)))]>;
4088 // Vector arithmetic shift right by immediate with truncate and pack
4089 def S2_asr_i_svw_trun : T_S2op_2_id <"vasrw", 0b110, 0b010>;
4091 // Arithmetic/logical shift right/left by immediate
4092 let Itinerary = S_2op_tc_1_SLOT23 in {
4093 def S2_asr_i_r : T_S2op_shift <"asr", 0b000, 0b000, sra>;
4094 def S2_lsr_i_r : T_S2op_shift <"lsr", 0b000, 0b001, srl>;
4095 def S2_asl_i_r : T_S2op_shift <"asl", 0b000, 0b010, shl>;
4098 // Shift left by immediate with saturation
4099 let Defs = [USR_OVF] in
4100 def S2_asl_i_r_sat : T_S2op_2_ii <"asl", 0b010, 0b010, 1>;
4102 // Shift right with round
4103 def S2_asr_i_r_rnd : T_S2op_2_ii <"asr", 0b010, 0b000, 0, 1>;
4105 let isAsmParserOnly = 1 in
4106 def S2_asr_i_r_rnd_goodsyntax
4107 : SInst <(outs IntRegs:$dst), (ins IntRegs:$src, u5Imm:$u5),
4108 "$dst = asrrnd($src, #$u5)",
4109 [], "", S_2op_tc_1_SLOT23>;
4111 let isAsmParserOnly = 1 in
4112 def A2_not: ALU32_rr<(outs IntRegs:$dst),(ins IntRegs:$src),
4113 "$dst = not($src)">;
4115 def: Pat<(i32 (sra (i32 (add (i32 (sra I32:$src1, u5ImmPred:$src2)),
4118 (S2_asr_i_r_rnd IntRegs:$src1, u5ImmPred:$src2)>;
4120 class T_S2op_3<string opc, bits<2>MajOp, bits<3>minOp, bits<1> sat = 0>
4121 : SInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
4122 "$Rdd = "#opc#"($Rss)"#!if(!eq(sat, 1),":sat","")> {
4125 let IClass = 0b1000;
4126 let Inst{27-24} = 0;
4127 let Inst{23-22} = MajOp;
4128 let Inst{20-16} = Rss;
4129 let Inst{7-5} = minOp;
4130 let Inst{4-0} = Rdd;
4133 def A2_absp : T_S2op_3 <"abs", 0b10, 0b110>;
4134 def A2_negp : T_S2op_3 <"neg", 0b10, 0b101>;
4135 def A2_notp : T_S2op_3 <"not", 0b10, 0b100>;
4137 // Innterleave/deinterleave
4138 def S2_interleave : T_S2op_3 <"interleave", 0b11, 0b101>;
4139 def S2_deinterleave : T_S2op_3 <"deinterleave", 0b11, 0b100>;
4141 // Vector Complex conjugate
4142 def A2_vconj : T_S2op_3 <"vconj", 0b10, 0b111, 1>;
4144 // Vector saturate without pack
4145 def S2_vsathb_nopack : T_S2op_3 <"vsathb", 0b00, 0b111>;
4146 def S2_vsathub_nopack : T_S2op_3 <"vsathub", 0b00, 0b100>;
4147 def S2_vsatwh_nopack : T_S2op_3 <"vsatwh", 0b00, 0b110>;
4148 def S2_vsatwuh_nopack : T_S2op_3 <"vsatwuh", 0b00, 0b101>;
4150 // Vector absolute value halfwords with and without saturation
4151 // Rdd64=vabsh(Rss64)[:sat]
4152 def A2_vabsh : T_S2op_3 <"vabsh", 0b01, 0b100>;
4153 def A2_vabshsat : T_S2op_3 <"vabsh", 0b01, 0b101, 1>;
4155 // Vector absolute value words with and without saturation
4156 def A2_vabsw : T_S2op_3 <"vabsw", 0b01, 0b110>;
4157 def A2_vabswsat : T_S2op_3 <"vabsw", 0b01, 0b111, 1>;
4159 def : Pat<(not (i64 DoubleRegs:$src1)),
4160 (A2_notp DoubleRegs:$src1)>;
4162 //===----------------------------------------------------------------------===//
4164 //===----------------------------------------------------------------------===//
4167 let hasSideEffects = 0, hasNewValue = 1 in
4168 class T_COUNT_LEADING<string MnOp, bits<3> MajOp, bits<3> MinOp, bit Is32,
4170 : SInst<Out, Inp, "$Rd = "#MnOp#"($Rs)", [], "", S_2op_tc_1_SLOT23> {
4173 let IClass = 0b1000;
4175 let Inst{26} = Is32;
4176 let Inst{25-24} = 0b00;
4177 let Inst{23-21} = MajOp;
4178 let Inst{20-16} = Rs;
4179 let Inst{7-5} = MinOp;
4183 class T_COUNT_LEADING_32<string MnOp, bits<3> MajOp, bits<3> MinOp>
4184 : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b1,
4185 (outs IntRegs:$Rd), (ins IntRegs:$Rs)>;
4187 class T_COUNT_LEADING_64<string MnOp, bits<3> MajOp, bits<3> MinOp>
4188 : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b0,
4189 (outs IntRegs:$Rd), (ins DoubleRegs:$Rs)>;
4191 def S2_cl0 : T_COUNT_LEADING_32<"cl0", 0b000, 0b101>;
4192 def S2_cl1 : T_COUNT_LEADING_32<"cl1", 0b000, 0b110>;
4193 def S2_ct0 : T_COUNT_LEADING_32<"ct0", 0b010, 0b100>;
4194 def S2_ct1 : T_COUNT_LEADING_32<"ct1", 0b010, 0b101>;
4195 def S2_cl0p : T_COUNT_LEADING_64<"cl0", 0b010, 0b010>;
4196 def S2_cl1p : T_COUNT_LEADING_64<"cl1", 0b010, 0b100>;
4197 def S2_clb : T_COUNT_LEADING_32<"clb", 0b000, 0b100>;
4198 def S2_clbp : T_COUNT_LEADING_64<"clb", 0b010, 0b000>;
4199 def S2_clbnorm : T_COUNT_LEADING_32<"normamt", 0b000, 0b111>;
4201 // Count leading zeros.
4202 def: Pat<(i32 (ctlz I32:$Rs)), (S2_cl0 I32:$Rs)>;
4203 def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>;
4204 def: Pat<(i32 (ctlz_zero_undef I32:$Rs)), (S2_cl0 I32:$Rs)>;
4205 def: Pat<(i32 (trunc (ctlz_zero_undef I64:$Rss))), (S2_cl0p I64:$Rss)>;
4207 // Count trailing zeros: 32-bit.
4208 def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>;
4209 def: Pat<(i32 (cttz_zero_undef I32:$Rs)), (S2_ct0 I32:$Rs)>;
4211 // Count leading ones.
4212 def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>;
4213 def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>;
4214 def: Pat<(i32 (ctlz_zero_undef (not I32:$Rs))), (S2_cl1 I32:$Rs)>;
4215 def: Pat<(i32 (trunc (ctlz_zero_undef (not I64:$Rss)))), (S2_cl1p I64:$Rss)>;
4217 // Count trailing ones: 32-bit.
4218 def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>;
4219 def: Pat<(i32 (cttz_zero_undef (not I32:$Rs))), (S2_ct1 I32:$Rs)>;
4221 // The 64-bit counts leading/trailing are defined in HexagonInstrInfoV4.td.
4223 // Bit set/clear/toggle
4225 let hasSideEffects = 0, hasNewValue = 1 in
4226 class T_SCT_BIT_IMM<string MnOp, bits<3> MinOp>
4227 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u5Imm:$u5),
4228 "$Rd = "#MnOp#"($Rs, #$u5)", [], "", S_2op_tc_1_SLOT23> {
4232 let IClass = 0b1000;
4233 let Inst{27-21} = 0b1100110;
4234 let Inst{20-16} = Rs;
4236 let Inst{12-8} = u5;
4237 let Inst{7-5} = MinOp;
4241 let hasSideEffects = 0, hasNewValue = 1 in
4242 class T_SCT_BIT_REG<string MnOp, bits<2> MinOp>
4243 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
4244 "$Rd = "#MnOp#"($Rs, $Rt)", [], "", S_3op_tc_1_SLOT23> {
4248 let IClass = 0b1100;
4249 let Inst{27-22} = 0b011010;
4250 let Inst{20-16} = Rs;
4251 let Inst{12-8} = Rt;
4252 let Inst{7-6} = MinOp;
4256 def S2_clrbit_i : T_SCT_BIT_IMM<"clrbit", 0b001>;
4257 def S2_setbit_i : T_SCT_BIT_IMM<"setbit", 0b000>;
4258 def S2_togglebit_i : T_SCT_BIT_IMM<"togglebit", 0b010>;
4259 def S2_clrbit_r : T_SCT_BIT_REG<"clrbit", 0b01>;
4260 def S2_setbit_r : T_SCT_BIT_REG<"setbit", 0b00>;
4261 def S2_togglebit_r : T_SCT_BIT_REG<"togglebit", 0b10>;
4263 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, u5ImmPred:$u5)))),
4264 (S2_clrbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4265 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
4266 (S2_setbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4267 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
4268 (S2_togglebit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4269 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, (i32 IntRegs:$Rt))))),
4270 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4271 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
4272 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4273 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
4274 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>;
4278 let hasSideEffects = 0 in
4279 class T_TEST_BIT_IMM<string MnOp, bits<3> MajOp>
4280 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5Imm:$u5),
4281 "$Pd = "#MnOp#"($Rs, #$u5)",
4282 [], "", S_2op_tc_2early_SLOT23> {
4286 let IClass = 0b1000;
4287 let Inst{27-24} = 0b0101;
4288 let Inst{23-21} = MajOp;
4289 let Inst{20-16} = Rs;
4291 let Inst{12-8} = u5;
4295 let hasSideEffects = 0 in
4296 class T_TEST_BIT_REG<string MnOp, bit IsNeg>
4297 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
4298 "$Pd = "#MnOp#"($Rs, $Rt)",
4299 [], "", S_3op_tc_2early_SLOT23> {
4303 let IClass = 0b1100;
4304 let Inst{27-22} = 0b011100;
4305 let Inst{21} = IsNeg;
4306 let Inst{20-16} = Rs;
4307 let Inst{12-8} = Rt;
4311 def S2_tstbit_i : T_TEST_BIT_IMM<"tstbit", 0b000>;
4312 def S2_tstbit_r : T_TEST_BIT_REG<"tstbit", 0>;
4314 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
4315 def: Pat<(i1 (setne (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
4316 (S2_tstbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4317 def: Pat<(i1 (setne (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
4318 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4319 def: Pat<(i1 (trunc (i32 IntRegs:$Rs))),
4320 (S2_tstbit_i IntRegs:$Rs, 0)>;
4321 def: Pat<(i1 (trunc (i64 DoubleRegs:$Rs))),
4322 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>;
4325 let hasSideEffects = 0 in
4326 class T_TEST_BITS_IMM<string MnOp, bits<2> MajOp, bit IsNeg>
4327 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u6Imm:$u6),
4328 "$Pd = "#MnOp#"($Rs, #$u6)",
4329 [], "", S_2op_tc_2early_SLOT23> {
4333 let IClass = 0b1000;
4334 let Inst{27-24} = 0b0101;
4335 let Inst{23-22} = MajOp;
4336 let Inst{21} = IsNeg;
4337 let Inst{20-16} = Rs;
4338 let Inst{13-8} = u6;
4342 let hasSideEffects = 0 in
4343 class T_TEST_BITS_REG<string MnOp, bits<2> MajOp, bit IsNeg>
4344 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
4345 "$Pd = "#MnOp#"($Rs, $Rt)",
4346 [], "", S_3op_tc_2early_SLOT23> {
4350 let IClass = 0b1100;
4351 let Inst{27-24} = 0b0111;
4352 let Inst{23-22} = MajOp;
4353 let Inst{21} = IsNeg;
4354 let Inst{20-16} = Rs;
4355 let Inst{12-8} = Rt;
4359 def C2_bitsclri : T_TEST_BITS_IMM<"bitsclr", 0b10, 0>;
4360 def C2_bitsclr : T_TEST_BITS_REG<"bitsclr", 0b10, 0>;
4361 def C2_bitsset : T_TEST_BITS_REG<"bitsset", 0b01, 0>;
4363 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm.
4364 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), u6ImmPred:$u6), 0)),
4365 (C2_bitsclri IntRegs:$Rs, u6ImmPred:$u6)>;
4366 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), 0)),
4367 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>;
4370 let AddedComplexity = 10 in // Complexity greater than compare reg-reg.
4371 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), IntRegs:$Rt)),
4372 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>;
4374 //===----------------------------------------------------------------------===//
4376 //===----------------------------------------------------------------------===//
4378 //===----------------------------------------------------------------------===//
4380 //===----------------------------------------------------------------------===//
4381 //===----------------------------------------------------------------------===//
4383 //===----------------------------------------------------------------------===//
4385 //===----------------------------------------------------------------------===//
4387 //===----------------------------------------------------------------------===//
4389 def: Pat<(or (or (shl (or (shl (i32 (extloadi8 (add (i32 IntRegs:$b), 3))),
4391 (i32 (zextloadi8 (add (i32 IntRegs:$b), 2)))),
4393 (shl (i32 (zextloadi8 (add (i32 IntRegs:$b), 1))), (i32 8))),
4394 (zextloadi8 (i32 IntRegs:$b))),
4395 (A2_swiz (L2_loadri_io IntRegs:$b, 0))>;
4397 //===----------------------------------------------------------------------===//
4399 //===----------------------------------------------------------------------===//
4401 //===----------------------------------------------------------------------===//
4403 //===----------------------------------------------------------------------===//
4405 // Predicate transfer.
4406 let hasSideEffects = 0, hasNewValue = 1 in
4407 def C2_tfrpr : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps),
4408 "$Rd = $Ps", [], "", S_2op_tc_1_SLOT23> {
4412 let IClass = 0b1000;
4413 let Inst{27-24} = 0b1001;
4415 let Inst{17-16} = Ps;
4419 // Transfer general register to predicate.
4420 let hasSideEffects = 0 in
4421 def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs),
4422 "$Pd = $Rs", [], "", S_2op_tc_2early_SLOT23> {
4426 let IClass = 0b1000;
4427 let Inst{27-21} = 0b0101010;
4428 let Inst{20-16} = Rs;
4432 let hasSideEffects = 0, isCodeGenOnly = 1 in
4433 def C2_pxfer_map: SInst<(outs PredRegs:$dst), (ins PredRegs:$src),
4437 // Patterns for loads of i1:
4438 def: Pat<(i1 (load AddrFI:$fi)),
4439 (C2_tfrrp (L2_loadrub_io AddrFI:$fi, 0))>;
4440 def: Pat<(i1 (load (add (i32 IntRegs:$Rs), s32ImmPred:$Off))),
4441 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>;
4442 def: Pat<(i1 (load (i32 IntRegs:$Rs))),
4443 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>;
4445 def I1toI32: OutPatFrag<(ops node:$Rs),
4446 (C2_muxii (i1 $Rs), 1, 0)>;
4448 def I32toI1: OutPatFrag<(ops node:$Rs),
4449 (i1 (C2_tfrrp (i32 $Rs)))>;
4451 defm: Storexm_pat<store, I1, s32ImmPred, I1toI32, S2_storerb_io>;
4452 def: Storexm_simple_pat<store, I1, I1toI32, S2_storerb_io>;
4454 //===----------------------------------------------------------------------===//
4456 //===----------------------------------------------------------------------===//
4458 //===----------------------------------------------------------------------===//
4460 //===----------------------------------------------------------------------===//
4461 class S_2OpInstImm<string Mnemonic, bits<3>MajOp, bits<3>MinOp,
4462 Operand Imm, list<dag> pattern = [], bit isRnd = 0>
4463 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, Imm:$src2),
4464 "$dst = "#Mnemonic#"($src1, #$src2)"#!if(isRnd, ":rnd", ""),
4468 let IClass = 0b1000;
4469 let Inst{27-24} = 0;
4470 let Inst{23-21} = MajOp;
4471 let Inst{20-16} = src1;
4472 let Inst{7-5} = MinOp;
4473 let Inst{4-0} = dst;
4476 class S_2OpInstImmI6<string Mnemonic, SDNode OpNode, bits<3>MinOp>
4477 : S_2OpInstImm<Mnemonic, 0b000, MinOp, u6Imm,
4478 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1),
4479 u6ImmPred:$src2))]> {
4481 let Inst{13-8} = src2;
4484 // Shift by immediate.
4485 def S2_asr_i_p : S_2OpInstImmI6<"asr", sra, 0b000>;
4486 def S2_asl_i_p : S_2OpInstImmI6<"asl", shl, 0b010>;
4487 def S2_lsr_i_p : S_2OpInstImmI6<"lsr", srl, 0b001>;
4489 // Shift left by small amount and add.
4490 let AddedComplexity = 100, hasNewValue = 1, hasSideEffects = 0 in
4491 def S2_addasl_rrri: SInst <(outs IntRegs:$Rd),
4492 (ins IntRegs:$Rt, IntRegs:$Rs, u3Imm:$u3),
4493 "$Rd = addasl($Rt, $Rs, #$u3)" ,
4494 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rt),
4495 (shl (i32 IntRegs:$Rs), u3ImmPred:$u3)))],
4496 "", S_3op_tc_2_SLOT23> {
4502 let IClass = 0b1100;
4504 let Inst{27-21} = 0b0100000;
4505 let Inst{20-16} = Rs;
4507 let Inst{12-8} = Rt;
4512 //===----------------------------------------------------------------------===//
4514 //===----------------------------------------------------------------------===//
4516 //===----------------------------------------------------------------------===//
4518 //===----------------------------------------------------------------------===//
4519 //===----------------------------------------------------------------------===//
4521 //===----------------------------------------------------------------------===//
4523 //===----------------------------------------------------------------------===//
4525 //===----------------------------------------------------------------------===//
4526 //===----------------------------------------------------------------------===//
4528 //===----------------------------------------------------------------------===//
4530 //===----------------------------------------------------------------------===//
4532 //===----------------------------------------------------------------------===//
4534 //===----------------------------------------------------------------------===//
4536 //===----------------------------------------------------------------------===//
4537 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>;
4539 let hasSideEffects = 1, isSoloAX = 1 in
4540 def Y2_barrier : SYSInst<(outs), (ins),
4542 [(HexagonBARRIER)],"",ST_tc_st_SLOT0> {
4543 let Inst{31-28} = 0b1010;
4544 let Inst{27-21} = 0b1000000;
4547 //===----------------------------------------------------------------------===//
4549 //===----------------------------------------------------------------------===//
4551 // Generate frameindex addresses. The main reason for the offset operand is
4552 // that every instruction that is allowed to have frame index as an operand
4553 // will then have that operand followed by an immediate operand (the offset).
4554 // This simplifies the frame-index elimination code.
4556 let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
4557 isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in {
4558 def TFR_FI : ALU32_ri<(outs IntRegs:$Rd),
4559 (ins IntRegs:$fi, s32Imm:$off), "">;
4560 def TFR_FIA : ALU32_ri<(outs IntRegs:$Rd),
4561 (ins IntRegs:$Rs, IntRegs:$fi, s32Imm:$off), "">;
4564 //===----------------------------------------------------------------------===//
4566 //===----------------------------------------------------------------------===//
4568 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
4569 opExtendable = 0, hasSideEffects = 0 in
4570 class LOOP_iBase<string mnemonic, Operand brOp, bit mustExtend = 0>
4571 : CRInst<(outs), (ins brOp:$offset, u10Imm:$src2),
4572 #mnemonic#"($offset, #$src2)",
4573 [], "" , CR_tc_3x_SLOT3> {
4577 let IClass = 0b0110;
4579 let Inst{27-22} = 0b100100;
4580 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
4581 let Inst{20-16} = src2{9-5};
4582 let Inst{12-8} = offset{8-4};
4583 let Inst{7-5} = src2{4-2};
4584 let Inst{4-3} = offset{3-2};
4585 let Inst{1-0} = src2{1-0};
4588 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
4589 opExtendable = 0, hasSideEffects = 0 in
4590 class LOOP_rBase<string mnemonic, Operand brOp, bit mustExtend = 0>
4591 : CRInst<(outs), (ins brOp:$offset, IntRegs:$src2),
4592 #mnemonic#"($offset, $src2)",
4593 [], "" ,CR_tc_3x_SLOT3> {
4597 let IClass = 0b0110;
4599 let Inst{27-22} = 0b000000;
4600 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
4601 let Inst{20-16} = src2;
4602 let Inst{12-8} = offset{8-4};
4603 let Inst{4-3} = offset{3-2};
4606 multiclass LOOP_ri<string mnemonic> {
4607 def i : LOOP_iBase<mnemonic, brtarget>;
4608 def r : LOOP_rBase<mnemonic, brtarget>;
4610 let isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in {
4611 def iext: LOOP_iBase<mnemonic, brtargetExt, 1>;
4612 def rext: LOOP_rBase<mnemonic, brtargetExt, 1>;
4617 let Defs = [SA0, LC0, USR] in
4618 defm J2_loop0 : LOOP_ri<"loop0">;
4620 // Interestingly only loop0's appear to set usr.lpcfg
4621 let Defs = [SA1, LC1] in
4622 defm J2_loop1 : LOOP_ri<"loop1">;
4624 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
4625 Defs = [PC, LC0], Uses = [SA0, LC0] in {
4626 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
4631 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
4632 Defs = [PC, LC1], Uses = [SA1, LC1] in {
4633 def ENDLOOP1 : Endloop<(outs), (ins brtarget:$offset),
4638 // Pipelined loop instructions, sp[123]loop0
4639 let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0,
4640 isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2,
4641 opExtendable = 0, isPredicateLate = 1 in
4642 class SPLOOP_iBase<string SP, bits<2> op>
4643 : CRInst <(outs), (ins brtarget:$r7_2, u10Imm:$U10),
4644 "p3 = sp"#SP#"loop0($r7_2, #$U10)" > {
4648 let IClass = 0b0110;
4650 let Inst{22-21} = op;
4651 let Inst{27-23} = 0b10011;
4652 let Inst{20-16} = U10{9-5};
4653 let Inst{12-8} = r7_2{8-4};
4654 let Inst{7-5} = U10{4-2};
4655 let Inst{4-3} = r7_2{3-2};
4656 let Inst{1-0} = U10{1-0};
4659 let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0,
4660 isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2,
4661 opExtendable = 0, isPredicateLate = 1 in
4662 class SPLOOP_rBase<string SP, bits<2> op>
4663 : CRInst <(outs), (ins brtarget:$r7_2, IntRegs:$Rs),
4664 "p3 = sp"#SP#"loop0($r7_2, $Rs)" > {
4668 let IClass = 0b0110;
4670 let Inst{22-21} = op;
4671 let Inst{27-23} = 0b00001;
4672 let Inst{20-16} = Rs;
4673 let Inst{12-8} = r7_2{8-4};
4674 let Inst{4-3} = r7_2{3-2};
4677 multiclass SPLOOP_ri<string mnemonic, bits<2> op> {
4678 def i : SPLOOP_iBase<mnemonic, op>;
4679 def r : SPLOOP_rBase<mnemonic, op>;
4682 defm J2_ploop1s : SPLOOP_ri<"1", 0b01>;
4683 defm J2_ploop2s : SPLOOP_ri<"2", 0b10>;
4684 defm J2_ploop3s : SPLOOP_ri<"3", 0b11>;
4686 // if (Rs[!>=<]=#0) jump:[t/nt]
4687 let Defs = [PC], isPredicated = 1, isBranch = 1, hasSideEffects = 0,
4688 hasSideEffects = 0 in
4689 class J2_jump_0_Base<string compare, bit isTak, bits<2> op>
4690 : CRInst <(outs), (ins IntRegs:$Rs, brtarget:$r13_2),
4691 "if ($Rs"#compare#"#0) jump"#!if(isTak, ":t", ":nt")#" $r13_2" > {
4695 let IClass = 0b0110;
4697 let Inst{27-24} = 0b0001;
4698 let Inst{23-22} = op;
4699 let Inst{12} = isTak;
4700 let Inst{21} = r13_2{14};
4701 let Inst{20-16} = Rs;
4702 let Inst{11-1} = r13_2{12-2};
4703 let Inst{13} = r13_2{13};
4706 multiclass J2_jump_compare_0<string compare, bits<2> op> {
4707 def NAME : J2_jump_0_Base<compare, 0, op>;
4708 def NAME#pt : J2_jump_0_Base<compare, 1, op>;
4711 defm J2_jumprz : J2_jump_compare_0<"!=", 0b00>;
4712 defm J2_jumprgtez : J2_jump_compare_0<">=", 0b01>;
4713 defm J2_jumprnz : J2_jump_compare_0<"==", 0b10>;
4714 defm J2_jumprltez : J2_jump_compare_0<"<=", 0b11>;
4716 // Transfer to/from Control/GPR Guest/GPR
4717 let hasSideEffects = 0 in
4718 class TFR_CR_RS_base<RegisterClass CTRC, RegisterClass RC, bit isDouble>
4719 : CRInst <(outs CTRC:$dst), (ins RC:$src),
4720 "$dst = $src", [], "", CR_tc_3x_SLOT3> {
4724 let IClass = 0b0110;
4726 let Inst{27-25} = 0b001;
4727 let Inst{24} = isDouble;
4728 let Inst{23-21} = 0b001;
4729 let Inst{20-16} = src;
4730 let Inst{4-0} = dst;
4733 def A2_tfrrcr : TFR_CR_RS_base<CtrRegs, IntRegs, 0b0>;
4734 def A4_tfrpcp : TFR_CR_RS_base<CtrRegs64, DoubleRegs, 0b1>;
4735 def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>;
4736 def : InstAlias<"m1 = $Rs", (A2_tfrrcr C7, IntRegs:$Rs)>;
4738 let hasSideEffects = 0 in
4739 class TFR_RD_CR_base<RegisterClass RC, RegisterClass CTRC, bit isSingle>
4740 : CRInst <(outs RC:$dst), (ins CTRC:$src),
4741 "$dst = $src", [], "", CR_tc_3x_SLOT3> {
4745 let IClass = 0b0110;
4747 let Inst{27-26} = 0b10;
4748 let Inst{25} = isSingle;
4749 let Inst{24-21} = 0b0000;
4750 let Inst{20-16} = src;
4751 let Inst{4-0} = dst;
4754 let hasNewValue = 1, opNewValue = 0 in
4755 def A2_tfrcrr : TFR_RD_CR_base<IntRegs, CtrRegs, 1>;
4756 def A4_tfrcpp : TFR_RD_CR_base<DoubleRegs, CtrRegs64, 0>;
4757 def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>;
4758 def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>;
4760 // Y4_trace: Send value to etm trace.
4761 let isSoloAX = 1, hasSideEffects = 0 in
4762 def Y4_trace: CRInst <(outs), (ins IntRegs:$Rs),
4766 let IClass = 0b0110;
4767 let Inst{27-21} = 0b0010010;
4768 let Inst{20-16} = Rs;
4771 // Support for generating global address.
4772 // Taken from X86InstrInfo.td.
4773 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
4776 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
4777 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
4779 // HI/LO Instructions
4780 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
4781 hasNewValue = 1, opNewValue = 0 in
4782 class REG_IMMED<string RegHalf, string Op, bit Rs, bits<3> MajOp, bit MinOp>
4783 : ALU32_ri<(outs IntRegs:$dst),
4784 (ins i32imm:$imm_value),
4785 "$dst"#RegHalf#" = #"#Op#"($imm_value)", []> {
4788 let IClass = 0b0111;
4791 let Inst{26-24} = MajOp;
4792 let Inst{21} = MinOp;
4793 let Inst{20-16} = dst;
4794 let Inst{23-22} = !if (!eq(Op, "LO"), imm_value{15-14}, imm_value{31-30});
4795 let Inst{13-0} = !if (!eq(Op, "LO"), imm_value{13-0}, imm_value{29-16});
4798 let isAsmParserOnly = 1 in {
4799 def LO : REG_IMMED<".l", "LO", 0b0, 0b001, 0b1>;
4800 def LO_H : REG_IMMED<".l", "HI", 0b0, 0b001, 0b1>;
4801 def HI : REG_IMMED<".h", "HI", 0b0, 0b010, 0b1>;
4802 def HI_L : REG_IMMED<".h", "LO", 0b0, 0b010, 0b1>;
4805 let isMoveImm = 1, isCodeGenOnly = 1 in
4806 def LO_PIC : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4807 "$dst.l = #LO($label@GOTREL)",
4810 let isMoveImm = 1, isCodeGenOnly = 1 in
4811 def HI_PIC : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4812 "$dst.h = #HI($label@GOTREL)",
4815 let isReMaterializable = 1, isMoveImm = 1,
4816 isCodeGenOnly = 1, hasSideEffects = 0 in
4817 def HI_GOT : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4818 "$dst.h = #HI($global@GOT)",
4821 let isReMaterializable = 1, isMoveImm = 1,
4822 isCodeGenOnly = 1, hasSideEffects = 0 in
4823 def LO_GOT : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4824 "$dst.l = #LO($global@GOT)",
4827 let isReMaterializable = 1, isMoveImm = 1,
4828 isCodeGenOnly = 1, hasSideEffects = 0 in
4829 def HI_GOTREL : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4830 "$dst.h = #HI($global@GOTREL)",
4833 let isReMaterializable = 1, isMoveImm = 1,
4834 isCodeGenOnly = 1, hasSideEffects = 0 in
4835 def LO_GOTREL : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4836 "$dst.l = #LO($global@GOTREL)",
4839 // This pattern is incorrect. When we add small data, we should change
4840 // this pattern to use memw(#foo).
4841 // This is for sdata.
4842 let isMoveImm = 1, isAsmParserOnly = 1 in
4843 def CONST32 : CONSTLDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
4844 "$dst = CONST32(#$global)",
4845 [(set (i32 IntRegs:$dst),
4846 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
4848 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
4849 def CONST32_Int_Real : CONSTLDInst<(outs IntRegs:$dst), (ins i32imm:$global),
4850 "$dst = CONST32(#$global)",
4851 [(set (i32 IntRegs:$dst), imm:$global) ]>;
4853 // Map TLS addressses to a CONST32 instruction
4854 def: Pat<(HexagonCONST32 tglobaltlsaddr:$addr), (A2_tfrsi s16Ext:$addr)>;
4855 def: Pat<(HexagonCONST32 bbl:$label), (A2_tfrsi s16Ext:$label)>;
4857 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
4858 def CONST64_Int_Real : CONSTLDInst<(outs DoubleRegs:$dst), (ins i64imm:$global),
4859 "$dst = CONST64(#$global)",
4860 [(set (i64 DoubleRegs:$dst), imm:$global)]>;
4862 let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
4863 isCodeGenOnly = 1 in
4864 def TFR_PdTrue : SInst<(outs PredRegs:$dst), (ins), "",
4865 [(set (i1 PredRegs:$dst), 1)]>;
4867 let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
4868 isCodeGenOnly = 1 in
4869 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins), "$dst = xor($dst, $dst)",
4870 [(set (i1 PredRegs:$dst), 0)]>;
4872 // Pseudo instructions.
4873 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
4874 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
4875 SDTCisVT<1, i32> ]>;
4877 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
4878 [SDNPHasChain, SDNPOutGlue]>;
4879 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
4880 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
4882 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
4884 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
4885 // Optional Flag and Variable Arguments.
4886 // Its 1 Operand has pointer type.
4887 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
4888 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
4890 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
4891 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
4892 ".error \"should not emit\" ",
4893 [(callseq_start timm:$amt)]>;
4895 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
4896 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
4897 ".error \"should not emit\" ",
4898 [(callseq_end timm:$amt1, timm:$amt2)]>;
4900 // Call subroutine indirectly.
4901 let Defs = VolatileV3.Regs in
4902 def J2_callr : JUMPR_MISC_CALLR<0, 1>;
4904 // Indirect tail-call.
4905 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
4906 isTerminator = 1, isCodeGenOnly = 1 in
4907 def TCRETURNr : T_JMPr;
4909 // Direct tail-calls.
4910 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
4911 isTerminator = 1, isCodeGenOnly = 1 in
4912 def TCRETURNi : JInst<(outs), (ins calltarget:$dst), "", []>;
4915 def: Pat<(HexagonTCRet tglobaladdr:$dst),
4916 (TCRETURNi tglobaladdr:$dst)>;
4917 def: Pat<(HexagonTCRet texternalsym:$dst),
4918 (TCRETURNi texternalsym:$dst)>;
4919 def: Pat<(HexagonTCRet (i32 IntRegs:$dst)),
4920 (TCRETURNr IntRegs:$dst)>;
4922 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
4923 def: Pat<(and (i32 IntRegs:$src1), 65535),
4924 (A2_zxth IntRegs:$src1)>;
4926 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
4927 def: Pat<(and (i32 IntRegs:$src1), 255),
4928 (A2_zxtb IntRegs:$src1)>;
4930 // Map Add(p1, true) to p1 = not(p1).
4931 // Add(p1, false) should never be produced,
4932 // if it does, it got to be mapped to NOOP.
4933 def: Pat<(add (i1 PredRegs:$src1), -1),
4934 (C2_not PredRegs:$src1)>;
4936 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
4937 def: Pat<(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s32ImmPred:$src3),
4938 (C2_muxii PredRegs:$src1, s32ImmPred:$src3, s8ImmPred:$src2)>;
4940 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
4941 // => r0 = C2_muxir(p0, r1, #i)
4942 def: Pat<(select (not (i1 PredRegs:$src1)), s32ImmPred:$src2,
4943 (i32 IntRegs:$src3)),
4944 (C2_muxir PredRegs:$src1, IntRegs:$src3, s32ImmPred:$src2)>;
4946 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
4947 // => r0 = C2_muxri (p0, #i, r1)
4948 def: Pat<(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s32ImmPred:$src3),
4949 (C2_muxri PredRegs:$src1, s32ImmPred:$src3, IntRegs:$src2)>;
4951 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
4952 def: Pat<(brcond (not (i1 PredRegs:$src1)), bb:$offset),
4953 (J2_jumpf PredRegs:$src1, bb:$offset)>;
4955 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = A2_sxtw(Rss.lo).
4956 def: Pat<(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
4957 (A2_sxtw (LoReg DoubleRegs:$src1))>;
4959 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = A2_sxtw(A2_sxth(Rss.lo)).
4960 def: Pat<(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
4961 (A2_sxtw (A2_sxth (LoReg DoubleRegs:$src1)))>;
4963 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = A2_sxtw(A2_sxtb(Rss.lo)).
4964 def: Pat<(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
4965 (A2_sxtw (A2_sxtb (LoReg DoubleRegs:$src1)))>;
4967 // We want to prevent emitting pnot's as much as possible.
4968 // Map brcond with an unsupported setcc to a J2_jumpf.
4969 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4971 (J2_jumpf (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
4974 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
4976 (J2_jumpf (C2_cmpeqi (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
4978 def: Pat<(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
4979 (J2_jumpf PredRegs:$src1, bb:$offset)>;
4981 def: Pat<(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
4982 (J2_jumpt PredRegs:$src1, bb:$offset)>;
4984 // cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1)
4985 def: Pat<(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)), bb:$offset),
4986 (J2_jumpf (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s8ImmPred:$src2)),
4989 // Map from a 64-bit select to an emulated 64-bit mux.
4990 // Hexagon does not support 64-bit MUXes; so emulate with combines.
4991 def: Pat<(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
4992 (i64 DoubleRegs:$src3)),
4993 (A2_combinew (C2_mux PredRegs:$src1, (HiReg DoubleRegs:$src2),
4994 (HiReg DoubleRegs:$src3)),
4995 (C2_mux PredRegs:$src1, (LoReg DoubleRegs:$src2),
4996 (LoReg DoubleRegs:$src3)))>;
4998 // Map from a 1-bit select to logical ops.
4999 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
5000 def: Pat<(select (i1 PredRegs:$src1), (i1 PredRegs:$src2), (i1 PredRegs:$src3)),
5001 (C2_or (C2_and PredRegs:$src1, PredRegs:$src2),
5002 (C2_and (C2_not PredRegs:$src1), PredRegs:$src3))>;
5004 // Map for truncating from 64 immediates to 32 bit immediates.
5005 def: Pat<(i32 (trunc (i64 DoubleRegs:$src))),
5006 (LoReg DoubleRegs:$src)>;
5008 // Map for truncating from i64 immediates to i1 bit immediates.
5009 def: Pat<(i1 (trunc (i64 DoubleRegs:$src))),
5010 (C2_tfrrp (LoReg DoubleRegs:$src))>;
5012 // rs <= rt -> !(rs > rt).
5013 let AddedComplexity = 30 in
5014 def: Pat<(i1 (setle (i32 IntRegs:$src1), s32ImmPred:$src2)),
5015 (C2_not (C2_cmpgti IntRegs:$src1, s32ImmPred:$src2))>;
5017 // rs <= rt -> !(rs > rt).
5018 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
5019 (i1 (C2_not (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
5021 // Rss <= Rtt -> !(Rss > Rtt).
5022 def: Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
5023 (C2_not (C2_cmpgtp DoubleRegs:$src1, DoubleRegs:$src2))>;
5025 // Map cmpne -> cmpeq.
5026 // Hexagon_TODO: We should improve on this.
5027 // rs != rt -> !(rs == rt).
5028 let AddedComplexity = 30 in
5029 def: Pat<(i1 (setne (i32 IntRegs:$src1), s32ImmPred:$src2)),
5030 (C2_not (C2_cmpeqi IntRegs:$src1, s32ImmPred:$src2))>;
5032 // Convert setne back to xor for hexagon since we compute w/ pred registers.
5033 def: Pat<(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
5034 (C2_xor PredRegs:$src1, PredRegs:$src2)>;
5036 // Map cmpne(Rss) -> !cmpew(Rss).
5037 // rs != rt -> !(rs == rt).
5038 def: Pat<(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
5039 (C2_not (C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2))>;
5041 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
5042 // rs >= rt -> !(rt > rs).
5043 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
5044 (i1 (C2_not (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
5046 // cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
5047 let AddedComplexity = 30 in
5048 def: Pat<(i1 (setge (i32 IntRegs:$src1), s32ImmPred:$src2)),
5049 (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s32ImmPred:$src2))>;
5051 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
5052 // rss >= rtt -> !(rtt > rss).
5053 def: Pat<(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
5054 (C2_not (C2_cmpgtp DoubleRegs:$src2, DoubleRegs:$src1))>;
5056 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
5057 // !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
5058 // rs < rt -> !(rs >= rt).
5059 let AddedComplexity = 30 in
5060 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32ImmPred:$src2)),
5061 (C2_not (C2_cmpgti IntRegs:$src1,
5062 (DEC_CONST_SIGNED s32ImmPred:$src2)))>;
5064 // Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs)
5065 def: Pat<(i1 (setuge (i32 IntRegs:$src1), 0)),
5066 (C2_cmpeq IntRegs:$src1, IntRegs:$src1)>;
5068 // Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1)
5069 def: Pat<(i1 (setuge (i32 IntRegs:$src1), u32ImmPred:$src2)),
5070 (C2_cmpgtui IntRegs:$src1, (DEC_CONST_UNSIGNED u32ImmPred:$src2))>;
5072 // Generate cmpgtu(Rs, #u9)
5073 def: Pat<(i1 (setugt (i32 IntRegs:$src1), u32ImmPred:$src2)),
5074 (C2_cmpgtui IntRegs:$src1, u32ImmPred:$src2)>;
5076 // Map from Rs >= Rt -> !(Rt > Rs).
5077 // rs >= rt -> !(rt > rs).
5078 def: Pat<(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
5079 (C2_not (C2_cmpgtup DoubleRegs:$src2, DoubleRegs:$src1))>;
5081 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
5082 // Map from (Rs <= Rt) -> !(Rs > Rt).
5083 def: Pat<(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
5084 (C2_not (C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2))>;
5088 def: Pat<(i32 (sext (i1 PredRegs:$src1))),
5089 (C2_muxii PredRegs:$src1, -1, 0)>;
5092 def: Pat<(i64 (sext (i1 PredRegs:$src1))),
5093 (A2_combinew (A2_tfrsi -1), (C2_muxii PredRegs:$src1, -1, 0))>;
5097 def: Pat<(i32 (zext (i1 PredRegs:$src1))),
5098 (C2_muxii PredRegs:$src1, 1, 0)>;
5100 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
5101 def: Pat<(i32 (anyext (i1 PredRegs:$src1))),
5102 (C2_muxii PredRegs:$src1, 1, 0)>;
5104 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
5105 def: Pat<(i64 (anyext (i1 PredRegs:$src1))),
5106 (A2_sxtw (C2_muxii PredRegs:$src1, 1, 0))>;
5108 // Multiply 64-bit unsigned and use upper result.
5109 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
5115 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $src1), (LoReg $src2)), 32),
5118 (A2_combinew (A2_tfrsi 0),
5119 (LoReg (M2_dpmpyuu_s0 (LoReg $src1), (HiReg $src2))))),
5123 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $src1), (HiReg $src2)), 32)
5126 // Hexagon specific ISD nodes.
5127 def SDTHexagonALLOCA : SDTypeProfile<1, 2,
5128 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
5129 def HexagonALLOCA : SDNode<"HexagonISD::ALLOCA", SDTHexagonALLOCA,
5132 // The reason for the custom inserter is to record all ALLOCA instructions
5133 // in MachineFunctionInfo.
5134 let Defs = [R29], isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 1,
5135 usesCustomInserter = 1 in
5136 def ALLOCA: ALU32Inst<(outs IntRegs:$Rd),
5137 (ins IntRegs:$Rs, u32Imm:$A), "",
5138 [(set (i32 IntRegs:$Rd),
5139 (HexagonALLOCA (i32 IntRegs:$Rs), (i32 imm:$A)))]>;
5141 let isCodeGenOnly = 1, isPseudo = 1, Uses = [R30], hasSideEffects = 0 in
5142 def ALIGNA : ALU32Inst<(outs IntRegs:$Rd), (ins u32Imm:$A), "", []>;
5144 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
5145 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
5146 let isCodeGenOnly = 1 in
5147 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
5149 [(set (i32 IntRegs:$dst),
5150 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
5152 let AddedComplexity = 100 in
5153 def: Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
5154 (i32 IntRegs:$src1)>;
5156 def HexagonJT: SDNode<"HexagonISD::JT", SDTIntUnaryOp>;
5157 def HexagonCP: SDNode<"HexagonISD::CP", SDTIntUnaryOp>;
5159 def: Pat<(HexagonJT tjumptable:$dst), (A2_tfrsi s16Ext:$dst)>;
5160 def: Pat<(HexagonCP tconstpool:$dst), (A2_tfrsi s16Ext:$dst)>;
5164 //===----------------------------------------------------------------------===//
5166 // Shift by immediate/register and accumulate/logical
5167 //===----------------------------------------------------------------------===//
5169 // Rx[+-&|]=asr(Rs,#u5)
5170 // Rx[+-&|^]=lsr(Rs,#u5)
5171 // Rx[+-&|^]=asl(Rs,#u5)
5173 let hasNewValue = 1, opNewValue = 0 in
5174 class T_shift_imm_acc_r <string opc1, string opc2, SDNode OpNode1,
5175 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
5176 : SInst_acc<(outs IntRegs:$Rx),
5177 (ins IntRegs:$src1, IntRegs:$Rs, u5Imm:$u5),
5178 "$Rx "#opc2#opc1#"($Rs, #$u5)",
5179 [(set (i32 IntRegs:$Rx),
5180 (OpNode2 (i32 IntRegs:$src1),
5181 (OpNode1 (i32 IntRegs:$Rs), u5ImmPred:$u5)))],
5182 "$src1 = $Rx", S_2op_tc_2_SLOT23> {
5187 let IClass = 0b1000;
5189 let Inst{27-24} = 0b1110;
5190 let Inst{23-22} = majOp{2-1};
5192 let Inst{7} = majOp{0};
5193 let Inst{6-5} = minOp;
5195 let Inst{20-16} = Rs;
5196 let Inst{12-8} = u5;
5199 // Rx[+-&|]=asr(Rs,Rt)
5200 // Rx[+-&|^]=lsr(Rs,Rt)
5201 // Rx[+-&|^]=asl(Rs,Rt)
5203 let hasNewValue = 1, opNewValue = 0 in
5204 class T_shift_reg_acc_r <string opc1, string opc2, SDNode OpNode1,
5205 SDNode OpNode2, bits<2> majOp, bits<2> minOp>
5206 : SInst_acc<(outs IntRegs:$Rx),
5207 (ins IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt),
5208 "$Rx "#opc2#opc1#"($Rs, $Rt)",
5209 [(set (i32 IntRegs:$Rx),
5210 (OpNode2 (i32 IntRegs:$src1),
5211 (OpNode1 (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))],
5212 "$src1 = $Rx", S_3op_tc_2_SLOT23 > {
5217 let IClass = 0b1100;
5219 let Inst{27-24} = 0b1100;
5220 let Inst{23-22} = majOp;
5221 let Inst{7-6} = minOp;
5223 let Inst{20-16} = Rs;
5224 let Inst{12-8} = Rt;
5227 // Rxx[+-&|]=asr(Rss,#u6)
5228 // Rxx[+-&|^]=lsr(Rss,#u6)
5229 // Rxx[+-&|^]=asl(Rss,#u6)
5231 class T_shift_imm_acc_p <string opc1, string opc2, SDNode OpNode1,
5232 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
5233 : SInst_acc<(outs DoubleRegs:$Rxx),
5234 (ins DoubleRegs:$src1, DoubleRegs:$Rss, u6Imm:$u6),
5235 "$Rxx "#opc2#opc1#"($Rss, #$u6)",
5236 [(set (i64 DoubleRegs:$Rxx),
5237 (OpNode2 (i64 DoubleRegs:$src1),
5238 (OpNode1 (i64 DoubleRegs:$Rss), u6ImmPred:$u6)))],
5239 "$src1 = $Rxx", S_2op_tc_2_SLOT23> {
5244 let IClass = 0b1000;
5246 let Inst{27-24} = 0b0010;
5247 let Inst{23-22} = majOp{2-1};
5248 let Inst{7} = majOp{0};
5249 let Inst{6-5} = minOp;
5250 let Inst{4-0} = Rxx;
5251 let Inst{20-16} = Rss;
5252 let Inst{13-8} = u6;
5256 // Rxx[+-&|]=asr(Rss,Rt)
5257 // Rxx[+-&|^]=lsr(Rss,Rt)
5258 // Rxx[+-&|^]=asl(Rss,Rt)
5259 // Rxx[+-&|^]=lsl(Rss,Rt)
5261 class T_shift_reg_acc_p <string opc1, string opc2, SDNode OpNode1,
5262 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
5263 : SInst_acc<(outs DoubleRegs:$Rxx),
5264 (ins DoubleRegs:$src1, DoubleRegs:$Rss, IntRegs:$Rt),
5265 "$Rxx "#opc2#opc1#"($Rss, $Rt)",
5266 [(set (i64 DoubleRegs:$Rxx),
5267 (OpNode2 (i64 DoubleRegs:$src1),
5268 (OpNode1 (i64 DoubleRegs:$Rss), (i32 IntRegs:$Rt))))],
5269 "$src1 = $Rxx", S_3op_tc_2_SLOT23> {
5274 let IClass = 0b1100;
5276 let Inst{27-24} = 0b1011;
5277 let Inst{23-21} = majOp;
5278 let Inst{20-16} = Rss;
5279 let Inst{12-8} = Rt;
5280 let Inst{7-6} = minOp;
5281 let Inst{4-0} = Rxx;
5284 //===----------------------------------------------------------------------===//
5285 // Multi-class for the shift instructions with logical/arithmetic operators.
5286 //===----------------------------------------------------------------------===//
5288 multiclass xtype_imm_base<string OpcStr1, string OpcStr2, SDNode OpNode1,
5289 SDNode OpNode2, bits<3> majOp, bits<2> minOp > {
5290 def _i_r#NAME : T_shift_imm_acc_r< OpcStr1, OpcStr2, OpNode1,
5291 OpNode2, majOp, minOp >;
5292 def _i_p#NAME : T_shift_imm_acc_p< OpcStr1, OpcStr2, OpNode1,
5293 OpNode2, majOp, minOp >;
5296 multiclass xtype_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
5297 let AddedComplexity = 100 in
5298 defm _acc : xtype_imm_base< opc1, "+= ", OpNode, add, 0b001, minOp>;
5300 defm _nac : xtype_imm_base< opc1, "-= ", OpNode, sub, 0b000, minOp>;
5301 defm _and : xtype_imm_base< opc1, "&= ", OpNode, and, 0b010, minOp>;
5302 defm _or : xtype_imm_base< opc1, "|= ", OpNode, or, 0b011, minOp>;
5305 multiclass xtype_xor_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
5306 let AddedComplexity = 100 in
5307 defm _xacc : xtype_imm_base< opc1, "^= ", OpNode, xor, 0b100, minOp>;
5310 defm S2_asr : xtype_imm_acc<"asr", sra, 0b00>;
5312 defm S2_lsr : xtype_imm_acc<"lsr", srl, 0b01>,
5313 xtype_xor_imm_acc<"lsr", srl, 0b01>;
5315 defm S2_asl : xtype_imm_acc<"asl", shl, 0b10>,
5316 xtype_xor_imm_acc<"asl", shl, 0b10>;
5318 multiclass xtype_reg_acc_r<string opc1, SDNode OpNode, bits<2>minOp> {
5319 let AddedComplexity = 100 in
5320 def _acc : T_shift_reg_acc_r <opc1, "+= ", OpNode, add, 0b11, minOp>;
5322 def _nac : T_shift_reg_acc_r <opc1, "-= ", OpNode, sub, 0b10, minOp>;
5323 def _and : T_shift_reg_acc_r <opc1, "&= ", OpNode, and, 0b01, minOp>;
5324 def _or : T_shift_reg_acc_r <opc1, "|= ", OpNode, or, 0b00, minOp>;
5327 multiclass xtype_reg_acc_p<string opc1, SDNode OpNode, bits<2>minOp> {
5328 let AddedComplexity = 100 in
5329 def _acc : T_shift_reg_acc_p <opc1, "+= ", OpNode, add, 0b110, minOp>;
5331 def _nac : T_shift_reg_acc_p <opc1, "-= ", OpNode, sub, 0b100, minOp>;
5332 def _and : T_shift_reg_acc_p <opc1, "&= ", OpNode, and, 0b010, minOp>;
5333 def _or : T_shift_reg_acc_p <opc1, "|= ", OpNode, or, 0b000, minOp>;
5334 def _xor : T_shift_reg_acc_p <opc1, "^= ", OpNode, xor, 0b011, minOp>;
5337 multiclass xtype_reg_acc<string OpcStr, SDNode OpNode, bits<2> minOp > {
5338 defm _r_r : xtype_reg_acc_r <OpcStr, OpNode, minOp>;
5339 defm _r_p : xtype_reg_acc_p <OpcStr, OpNode, minOp>;
5342 defm S2_asl : xtype_reg_acc<"asl", shl, 0b10>;
5343 defm S2_asr : xtype_reg_acc<"asr", sra, 0b00>;
5344 defm S2_lsr : xtype_reg_acc<"lsr", srl, 0b01>;
5345 defm S2_lsl : xtype_reg_acc<"lsl", shl, 0b11>;
5347 //===----------------------------------------------------------------------===//
5348 let hasSideEffects = 0 in
5349 class T_S3op_1 <string mnemonic, RegisterClass RC, bits<2> MajOp, bits<3> MinOp,
5350 bit SwapOps, bit isSat = 0, bit isRnd = 0, bit hasShift = 0>
5351 : SInst <(outs RC:$dst),
5352 (ins DoubleRegs:$src1, DoubleRegs:$src2),
5353 "$dst = "#mnemonic#"($src1, $src2)"#!if(isRnd, ":rnd", "")
5354 #!if(hasShift,":>>1","")
5355 #!if(isSat, ":sat", ""),
5356 [], "", S_3op_tc_2_SLOT23 > {
5361 let IClass = 0b1100;
5363 let Inst{27-24} = 0b0001;
5364 let Inst{23-22} = MajOp;
5365 let Inst{20-16} = !if (SwapOps, src2, src1);
5366 let Inst{12-8} = !if (SwapOps, src1, src2);
5367 let Inst{7-5} = MinOp;
5368 let Inst{4-0} = dst;
5371 class T_S3op_64 <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit SwapOps,
5372 bit isSat = 0, bit isRnd = 0, bit hasShift = 0 >
5373 : T_S3op_1 <mnemonic, DoubleRegs, MajOp, MinOp, SwapOps,
5374 isSat, isRnd, hasShift>;
5376 let Itinerary = S_3op_tc_1_SLOT23 in {
5377 def S2_shuffeb : T_S3op_64 < "shuffeb", 0b00, 0b010, 0>;
5378 def S2_shuffeh : T_S3op_64 < "shuffeh", 0b00, 0b110, 0>;
5379 def S2_shuffob : T_S3op_64 < "shuffob", 0b00, 0b100, 1>;
5380 def S2_shuffoh : T_S3op_64 < "shuffoh", 0b10, 0b000, 1>;
5382 def S2_vtrunewh : T_S3op_64 < "vtrunewh", 0b10, 0b010, 0>;
5383 def S2_vtrunowh : T_S3op_64 < "vtrunowh", 0b10, 0b100, 0>;
5386 def S2_lfsp : T_S3op_64 < "lfs", 0b10, 0b110, 0>;
5388 let hasSideEffects = 0 in
5389 class T_S3op_2 <string mnemonic, bits<3> MajOp, bit SwapOps>
5390 : SInst < (outs DoubleRegs:$Rdd),
5391 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
5392 "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu)",
5393 [], "", S_3op_tc_1_SLOT23 > {
5399 let IClass = 0b1100;
5401 let Inst{27-24} = 0b0010;
5402 let Inst{23-21} = MajOp;
5403 let Inst{20-16} = !if (SwapOps, Rtt, Rss);
5404 let Inst{12-8} = !if (SwapOps, Rss, Rtt);
5406 let Inst{4-0} = Rdd;
5409 def S2_valignrb : T_S3op_2 < "valignb", 0b000, 1>;
5410 def S2_vsplicerb : T_S3op_2 < "vspliceb", 0b100, 0>;
5412 //===----------------------------------------------------------------------===//
5413 // Template class used by vector shift, vector rotate, vector neg,
5414 // 32-bit shift, 64-bit shifts, etc.
5415 //===----------------------------------------------------------------------===//
5417 let hasSideEffects = 0 in
5418 class T_S3op_3 <string mnemonic, RegisterClass RC, bits<2> MajOp,
5419 bits<2> MinOp, bit isSat = 0, list<dag> pattern = [] >
5420 : SInst <(outs RC:$dst),
5421 (ins RC:$src1, IntRegs:$src2),
5422 "$dst = "#mnemonic#"($src1, $src2)"#!if(isSat, ":sat", ""),
5423 pattern, "", S_3op_tc_1_SLOT23> {
5428 let IClass = 0b1100;
5430 let Inst{27-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b0110, 0b0011);
5431 let Inst{23-22} = MajOp;
5432 let Inst{20-16} = src1;
5433 let Inst{12-8} = src2;
5434 let Inst{7-6} = MinOp;
5435 let Inst{4-0} = dst;
5438 let hasNewValue = 1 in
5439 class T_S3op_shift32 <string mnemonic, SDNode OpNode, bits<2> MinOp>
5440 : T_S3op_3 <mnemonic, IntRegs, 0b01, MinOp, 0,
5441 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
5442 (i32 IntRegs:$src2)))]>;
5444 let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in
5445 class T_S3op_shift32_Sat <string mnemonic, bits<2> MinOp>
5446 : T_S3op_3 <mnemonic, IntRegs, 0b00, MinOp, 1, []>;
5449 class T_S3op_shift64 <string mnemonic, SDNode OpNode, bits<2> MinOp>
5450 : T_S3op_3 <mnemonic, DoubleRegs, 0b10, MinOp, 0,
5451 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1),
5452 (i32 IntRegs:$src2)))]>;
5455 class T_S3op_shiftVect <string mnemonic, bits<2> MajOp, bits<2> MinOp>
5456 : T_S3op_3 <mnemonic, DoubleRegs, MajOp, MinOp, 0, []>;
5459 // Shift by register
5460 // Rdd=[asr|lsr|asl|lsl](Rss,Rt)
5462 def S2_asr_r_p : T_S3op_shift64 < "asr", sra, 0b00>;
5463 def S2_lsr_r_p : T_S3op_shift64 < "lsr", srl, 0b01>;
5464 def S2_asl_r_p : T_S3op_shift64 < "asl", shl, 0b10>;
5465 def S2_lsl_r_p : T_S3op_shift64 < "lsl", shl, 0b11>;
5467 // Rd=[asr|lsr|asl|lsl](Rs,Rt)
5469 def S2_asr_r_r : T_S3op_shift32<"asr", sra, 0b00>;
5470 def S2_lsr_r_r : T_S3op_shift32<"lsr", srl, 0b01>;
5471 def S2_asl_r_r : T_S3op_shift32<"asl", shl, 0b10>;
5472 def S2_lsl_r_r : T_S3op_shift32<"lsl", shl, 0b11>;
5474 // Shift by register with saturation
5475 // Rd=asr(Rs,Rt):sat
5476 // Rd=asl(Rs,Rt):sat
5478 let Defs = [USR_OVF] in {
5479 def S2_asr_r_r_sat : T_S3op_shift32_Sat<"asr", 0b00>;
5480 def S2_asl_r_r_sat : T_S3op_shift32_Sat<"asl", 0b10>;
5483 let hasNewValue = 1, hasSideEffects = 0 in
5484 class T_S3op_8 <string opc, bits<3> MinOp, bit isSat, bit isRnd, bit hasShift, bit hasSplat = 0>
5485 : SInst < (outs IntRegs:$Rd),
5486 (ins DoubleRegs:$Rss, IntRegs:$Rt),
5487 "$Rd = "#opc#"($Rss, $Rt"#!if(hasSplat, "*", "")#")"
5488 #!if(hasShift, ":<<1", "")
5489 #!if(isRnd, ":rnd", "")
5490 #!if(isSat, ":sat", ""),
5491 [], "", S_3op_tc_1_SLOT23 > {
5496 let IClass = 0b1100;
5498 let Inst{27-24} = 0b0101;
5499 let Inst{20-16} = Rss;
5500 let Inst{12-8} = Rt;
5501 let Inst{7-5} = MinOp;
5505 def S2_asr_r_svw_trun : T_S3op_8<"vasrw", 0b010, 0, 0, 0>;
5507 let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in
5508 def S2_vcrotate : T_S3op_shiftVect < "vcrotate", 0b11, 0b00>;
5510 let hasSideEffects = 0 in
5511 class T_S3op_7 <string mnemonic, bit MajOp >
5512 : SInst <(outs DoubleRegs:$Rdd),
5513 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, u3Imm:$u3),
5514 "$Rdd = "#mnemonic#"($Rss, $Rtt, #$u3)" ,
5515 [], "", S_3op_tc_1_SLOT23 > {
5521 let IClass = 0b1100;
5523 let Inst{27-24} = 0b0000;
5524 let Inst{23} = MajOp;
5525 let Inst{20-16} = !if(MajOp, Rss, Rtt);
5526 let Inst{12-8} = !if(MajOp, Rtt, Rss);
5528 let Inst{4-0} = Rdd;
5531 def S2_valignib : T_S3op_7 < "valignb", 0>;
5532 def S2_vspliceib : T_S3op_7 < "vspliceb", 1>;
5534 //===----------------------------------------------------------------------===//
5535 // Template class for 'insert bitfield' instructions
5536 //===----------------------------------------------------------------------===//
5537 let hasSideEffects = 0 in
5538 class T_S3op_insert <string mnemonic, RegisterClass RC>
5539 : SInst <(outs RC:$dst),
5540 (ins RC:$src1, RC:$src2, DoubleRegs:$src3),
5541 "$dst = "#mnemonic#"($src2, $src3)" ,
5542 [], "$src1 = $dst", S_3op_tc_1_SLOT23 > {
5547 let IClass = 0b1100;
5549 let Inst{27-26} = 0b10;
5550 let Inst{25-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b00, 0b10);
5552 let Inst{20-16} = src2;
5553 let Inst{12-8} = src3;
5554 let Inst{4-0} = dst;
5557 let hasSideEffects = 0 in
5558 class T_S2op_insert <bits<4> RegTyBits, RegisterClass RC, Operand ImmOp>
5559 : SInst <(outs RC:$dst), (ins RC:$dst2, RC:$src1, ImmOp:$src2, ImmOp:$src3),
5560 "$dst = insert($src1, #$src2, #$src3)",
5561 [], "$dst2 = $dst", S_2op_tc_2_SLOT23> {
5568 string ImmOpStr = !cast<string>(ImmOp);
5570 let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5}, 0);
5571 let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0);
5573 let IClass = 0b1000;
5575 let Inst{27-24} = RegTyBits;
5576 let Inst{23} = bit23;
5577 let Inst{22-21} = src3{4-3};
5578 let Inst{20-16} = src1;
5579 let Inst{13} = bit13;
5580 let Inst{12-8} = src2{4-0};
5581 let Inst{7-5} = src3{2-0};
5582 let Inst{4-0} = dst;
5585 // Rx=insert(Rs,Rtt)
5586 // Rx=insert(Rs,#u5,#U5)
5587 let hasNewValue = 1 in {
5588 def S2_insert_rp : T_S3op_insert <"insert", IntRegs>;
5589 def S2_insert : T_S2op_insert <0b1111, IntRegs, u5Imm>;
5592 // Rxx=insert(Rss,Rtt)
5593 // Rxx=insert(Rss,#u6,#U6)
5594 def S2_insertp_rp : T_S3op_insert<"insert", DoubleRegs>;
5595 def S2_insertp : T_S2op_insert <0b0011, DoubleRegs, u6Imm>;
5598 def SDTHexagonINSERT:
5599 SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
5600 SDTCisInt<0>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>;
5601 def SDTHexagonINSERTRP:
5602 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
5603 SDTCisInt<0>, SDTCisVT<3, i64>]>;
5605 def HexagonINSERT : SDNode<"HexagonISD::INSERT", SDTHexagonINSERT>;
5606 def HexagonINSERTRP : SDNode<"HexagonISD::INSERTRP", SDTHexagonINSERTRP>;
5608 def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, u5ImmPred:$u1, u5ImmPred:$u2),
5609 (S2_insert I32:$Rs, I32:$Rt, u5ImmPred:$u1, u5ImmPred:$u2)>;
5610 def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, u6ImmPred:$u1, u6ImmPred:$u2),
5611 (S2_insertp I64:$Rs, I64:$Rt, u6ImmPred:$u1, u6ImmPred:$u2)>;
5612 def: Pat<(HexagonINSERTRP I32:$Rs, I32:$Rt, I64:$Ru),
5613 (S2_insert_rp I32:$Rs, I32:$Rt, I64:$Ru)>;
5614 def: Pat<(HexagonINSERTRP I64:$Rs, I64:$Rt, I64:$Ru),
5615 (S2_insertp_rp I64:$Rs, I64:$Rt, I64:$Ru)>;
5617 let AddedComplexity = 100 in
5618 def: Pat<(or (or (shl (HexagonINSERT (i32 (zextloadi8 (add I32:$b, 2))),
5619 (i32 (extloadi8 (add I32:$b, 3))),
5622 (shl (i32 (zextloadi8 (add I32:$b, 1))), (i32 8))),
5623 (zextloadi8 I32:$b)),
5624 (A2_swiz (L2_loadri_io I32:$b, 0))>;
5627 //===----------------------------------------------------------------------===//
5628 // Template class for 'extract bitfield' instructions
5629 //===----------------------------------------------------------------------===//
5630 let hasNewValue = 1, hasSideEffects = 0 in
5631 class T_S3op_extract <string mnemonic, bits<2> MinOp>
5632 : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
5633 "$Rd = "#mnemonic#"($Rs, $Rtt)",
5634 [], "", S_3op_tc_2_SLOT23 > {
5639 let IClass = 0b1100;
5641 let Inst{27-22} = 0b100100;
5642 let Inst{20-16} = Rs;
5643 let Inst{12-8} = Rtt;
5644 let Inst{7-6} = MinOp;
5648 let hasSideEffects = 0 in
5649 class T_S2op_extract <string mnemonic, bits<4> RegTyBits,
5650 RegisterClass RC, Operand ImmOp>
5651 : SInst <(outs RC:$dst), (ins RC:$src1, ImmOp:$src2, ImmOp:$src3),
5652 "$dst = "#mnemonic#"($src1, #$src2, #$src3)",
5653 [], "", S_2op_tc_2_SLOT23> {
5660 string ImmOpStr = !cast<string>(ImmOp);
5662 let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5},
5663 !if (!eq(mnemonic, "extractu"), 0, 1));
5665 let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0);
5667 let IClass = 0b1000;
5669 let Inst{27-24} = RegTyBits;
5670 let Inst{23} = bit23;
5671 let Inst{22-21} = src3{4-3};
5672 let Inst{20-16} = src1;
5673 let Inst{13} = bit13;
5674 let Inst{12-8} = src2{4-0};
5675 let Inst{7-5} = src3{2-0};
5676 let Inst{4-0} = dst;
5681 // Rdd=extractu(Rss,Rtt)
5682 // Rdd=extractu(Rss,#u6,#U6)
5683 def S2_extractup_rp : T_S3op_64 < "extractu", 0b00, 0b000, 0>;
5684 def S2_extractup : T_S2op_extract <"extractu", 0b0001, DoubleRegs, u6Imm>;
5686 // Rd=extractu(Rs,Rtt)
5687 // Rd=extractu(Rs,#u5,#U5)
5688 let hasNewValue = 1 in {
5689 def S2_extractu_rp : T_S3op_extract<"extractu", 0b00>;
5690 def S2_extractu : T_S2op_extract <"extractu", 0b1101, IntRegs, u5Imm>;
5693 def SDTHexagonEXTRACTU:
5694 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<1>,
5695 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
5696 def SDTHexagonEXTRACTURP:
5697 SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<1>,
5700 def HexagonEXTRACTU : SDNode<"HexagonISD::EXTRACTU", SDTHexagonEXTRACTU>;
5701 def HexagonEXTRACTURP : SDNode<"HexagonISD::EXTRACTURP", SDTHexagonEXTRACTURP>;
5703 def: Pat<(HexagonEXTRACTU I32:$src1, u5ImmPred:$src2, u5ImmPred:$src3),
5704 (S2_extractu I32:$src1, u5ImmPred:$src2, u5ImmPred:$src3)>;
5705 def: Pat<(HexagonEXTRACTU I64:$src1, u6ImmPred:$src2, u6ImmPred:$src3),
5706 (S2_extractup I64:$src1, u6ImmPred:$src2, u6ImmPred:$src3)>;
5707 def: Pat<(HexagonEXTRACTURP I32:$src1, I64:$src2),
5708 (S2_extractu_rp I32:$src1, I64:$src2)>;
5709 def: Pat<(HexagonEXTRACTURP I64:$src1, I64:$src2),
5710 (S2_extractup_rp I64:$src1, I64:$src2)>;
5712 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
5713 def: Pat<(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
5714 (M2_mpysin IntRegs:$src1, u8ImmPred:$src2)>;
5716 //===----------------------------------------------------------------------===//
5717 // :raw for of tableindx[bdhw] insns
5718 //===----------------------------------------------------------------------===//
5720 let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
5721 class tableidxRaw<string OpStr, bits<2>MinOp>
5722 : SInst <(outs IntRegs:$Rx),
5723 (ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, s6Imm:$S6),
5724 "$Rx = "#OpStr#"($Rs, #$u4, #$S6):raw",
5725 [], "$Rx = $_dst_" > {
5731 let IClass = 0b1000;
5733 let Inst{27-24} = 0b0111;
5734 let Inst{23-22} = MinOp;
5735 let Inst{21} = u4{3};
5736 let Inst{20-16} = Rs;
5737 let Inst{13-8} = S6;
5738 let Inst{7-5} = u4{2-0};
5742 def S2_tableidxb : tableidxRaw<"tableidxb", 0b00>;
5743 def S2_tableidxh : tableidxRaw<"tableidxh", 0b01>;
5744 def S2_tableidxw : tableidxRaw<"tableidxw", 0b10>;
5745 def S2_tableidxd : tableidxRaw<"tableidxd", 0b11>;
5747 //===----------------------------------------------------------------------===//
5748 // Template class for 'table index' instructions which are assembler mapped
5749 // to their :raw format.
5750 //===----------------------------------------------------------------------===//
5752 class tableidx_goodsyntax <string mnemonic>
5753 : SInst <(outs IntRegs:$Rx),
5754 (ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, u5Imm:$u5),
5755 "$Rx = "#mnemonic#"($Rs, #$u4, #$u5)",
5756 [], "$Rx = $_dst_" >;
5758 def S2_tableidxb_goodsyntax : tableidx_goodsyntax<"tableidxb">;
5759 def S2_tableidxh_goodsyntax : tableidx_goodsyntax<"tableidxh">;
5760 def S2_tableidxw_goodsyntax : tableidx_goodsyntax<"tableidxw">;
5761 def S2_tableidxd_goodsyntax : tableidx_goodsyntax<"tableidxd">;
5763 //===----------------------------------------------------------------------===//
5764 // V3 Instructions +
5765 //===----------------------------------------------------------------------===//
5767 include "HexagonInstrInfoV3.td"
5769 //===----------------------------------------------------------------------===//
5770 // V3 Instructions -
5771 //===----------------------------------------------------------------------===//
5773 //===----------------------------------------------------------------------===//
5774 // V4 Instructions +
5775 //===----------------------------------------------------------------------===//
5777 include "HexagonInstrInfoV4.td"
5779 //===----------------------------------------------------------------------===//
5780 // V4 Instructions -
5781 //===----------------------------------------------------------------------===//
5783 //===----------------------------------------------------------------------===//
5784 // V5 Instructions +
5785 //===----------------------------------------------------------------------===//
5787 include "HexagonInstrInfoV5.td"
5789 //===----------------------------------------------------------------------===//
5790 // V5 Instructions -
5791 //===----------------------------------------------------------------------===//
5793 //===----------------------------------------------------------------------===//
5794 // V60 Instructions +
5795 //===----------------------------------------------------------------------===//
5797 include "HexagonInstrInfoV60.td"
5799 //===----------------------------------------------------------------------===//
5800 // V60 Instructions -
5801 //===----------------------------------------------------------------------===//
5803 //===----------------------------------------------------------------------===//
5804 // ALU32/64/Vector +
5805 //===----------------------------------------------------------------------===///
5807 include "HexagonInstrInfoVector.td"
5809 include "HexagonInstrAlias.td"
5810 include "HexagonSystemInst.td"