1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
17 // Multi-class for logical operators.
18 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
19 def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
20 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
21 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),
23 def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
24 !strconcat("$dst = ", !strconcat(OpcStr, "(#$b, $c)")),
25 [(set (i32 IntRegs:$dst), (OpNode s10Imm:$b,
29 // Multi-class for compare ops.
30 let isCompare = 1 in {
31 multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
32 def rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
33 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
34 [(set (i1 PredRegs:$dst),
35 (OpNode (i64 DoubleRegs:$b), (i64 DoubleRegs:$c)))]>;
37 multiclass CMP32_rr<string OpcStr, PatFrag OpNode> {
38 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
39 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
40 [(set (i1 PredRegs:$dst),
41 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
44 multiclass CMP32_rr_ri_s10<string OpcStr, string CextOp, PatFrag OpNode> {
45 let CextOpcode = CextOp in {
46 let InputType = "reg" in
47 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
48 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
49 [(set (i1 PredRegs:$dst),
50 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
52 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1,
53 opExtentBits = 10, InputType = "imm" in
54 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Ext:$c),
55 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
56 [(set (i1 PredRegs:$dst),
57 (OpNode (i32 IntRegs:$b), s10ExtPred:$c))]>;
61 multiclass CMP32_rr_ri_u9<string OpcStr, string CextOp, PatFrag OpNode> {
62 let CextOpcode = CextOp in {
63 let InputType = "reg" in
64 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
65 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
66 [(set (i1 PredRegs:$dst),
67 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
69 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0,
70 opExtentBits = 9, InputType = "imm" in
71 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Ext:$c),
72 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
73 [(set (i1 PredRegs:$dst),
74 (OpNode (i32 IntRegs:$b), u9ExtPred:$c))]>;
78 multiclass CMP32_ri_u8<string OpcStr, PatFrag OpNode> {
79 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in
80 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u8Ext:$c),
81 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
82 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
86 multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
87 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
88 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Ext:$c),
89 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
90 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
95 //===----------------------------------------------------------------------===//
96 // ALU32/ALU (Instructions with register-register form)
97 //===----------------------------------------------------------------------===//
98 multiclass ALU32_Pbase<string mnemonic, bit isNot,
101 let PNewValue = #!if(isPredNew, "new", "") in
102 def #NAME# : ALU32_rr<(outs IntRegs:$dst),
103 (ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
104 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
105 ") $dst = ")#mnemonic#"($src2, $src3)",
109 multiclass ALU32_Pred<string mnemonic, bit PredNot> {
110 let PredSense = #!if(PredNot, "false", "true") in {
111 defm _c#NAME# : ALU32_Pbase<mnemonic, PredNot, 0>;
113 defm _cdn#NAME# : ALU32_Pbase<mnemonic, PredNot, 1>;
117 let InputType = "reg" in
118 multiclass ALU32_base<string mnemonic, string CextOp, SDNode OpNode> {
119 let CextOpcode = CextOp, BaseOpcode = CextOp#_rr in {
120 let isPredicable = 1 in
121 def #NAME# : ALU32_rr<(outs IntRegs:$dst),
122 (ins IntRegs:$src1, IntRegs:$src2),
123 "$dst = "#mnemonic#"($src1, $src2)",
124 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
125 (i32 IntRegs:$src2)))]>;
127 let neverHasSideEffects = 1, isPredicated = 1 in {
128 defm Pt : ALU32_Pred<mnemonic, 0>;
129 defm NotPt : ALU32_Pred<mnemonic, 1>;
134 let isCommutable = 1 in {
135 defm ADD_rr : ALU32_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
136 defm AND_rr : ALU32_base<"and", "AND", and>, ImmRegRel, PredNewRel;
137 defm XOR_rr : ALU32_base<"xor", "XOR", xor>, ImmRegRel, PredNewRel;
138 defm OR_rr : ALU32_base<"or", "OR", or>, ImmRegRel, PredNewRel;
141 defm SUB_rr : ALU32_base<"sub", "SUB", sub>, ImmRegRel, PredNewRel;
143 //===----------------------------------------------------------------------===//
144 // ALU32/ALU (ADD with register-immediate form)
145 //===----------------------------------------------------------------------===//
146 multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
147 let PNewValue = #!if(isPredNew, "new", "") in
148 def #NAME# : ALU32_ri<(outs IntRegs:$dst),
149 (ins PredRegs:$src1, IntRegs:$src2, s8Ext: $src3),
150 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
151 ") $dst = ")#mnemonic#"($src2, #$src3)",
155 multiclass ALU32ri_Pred<string mnemonic, bit PredNot> {
156 let PredSense = #!if(PredNot, "false", "true") in {
157 defm _c#NAME# : ALU32ri_Pbase<mnemonic, PredNot, 0>;
159 defm _cdn#NAME# : ALU32ri_Pbase<mnemonic, PredNot, 1>;
163 let isExtendable = 1, InputType = "imm" in
164 multiclass ALU32ri_base<string mnemonic, string CextOp, SDNode OpNode> {
165 let CextOpcode = CextOp, BaseOpcode = CextOp#_ri in {
166 let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
168 def #NAME# : ALU32_ri<(outs IntRegs:$dst),
169 (ins IntRegs:$src1, s16Ext:$src2),
170 "$dst = "#mnemonic#"($src1, #$src2)",
171 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
172 (s16ExtPred:$src2)))]>;
174 let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
175 neverHasSideEffects = 1, isPredicated = 1 in {
176 defm Pt : ALU32ri_Pred<mnemonic, 0>;
177 defm NotPt : ALU32ri_Pred<mnemonic, 1>;
182 defm ADD_ri : ALU32ri_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
184 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
185 CextOpcode = "OR", InputType = "imm" in
186 def OR_ri : ALU32_ri<(outs IntRegs:$dst),
187 (ins IntRegs:$src1, s10Ext:$src2),
188 "$dst = or($src1, #$src2)",
189 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
190 s10ExtPred:$src2))]>, ImmRegRel;
192 def NOT_rr : ALU32_rr<(outs IntRegs:$dst),
195 [(set (i32 IntRegs:$dst), (not (i32 IntRegs:$src1)))]>;
197 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
198 InputType = "imm", CextOpcode = "AND" in
199 def AND_ri : ALU32_ri<(outs IntRegs:$dst),
200 (ins IntRegs:$src1, s10Ext:$src2),
201 "$dst = and($src1, #$src2)",
202 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
203 s10ExtPred:$src2))]>, ImmRegRel;
205 def NEG : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
207 [(set (i32 IntRegs:$dst), (ineg (i32 IntRegs:$src1)))]>;
209 let neverHasSideEffects = 1 in
210 def NOP : ALU32_rr<(outs), (ins),
214 // Rd32=sub(#s10,Rs32)
215 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
216 CextOpcode = "SUB", InputType = "imm" in
217 def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
218 (ins s10Ext:$src1, IntRegs:$src2),
219 "$dst = sub(#$src1, $src2)",
220 [(set IntRegs:$dst, (sub s10ExtPred:$src1, IntRegs:$src2))]>,
224 multiclass TFR_Pred<bit PredNot> {
225 let PredSense = #!if(PredNot, "false", "true") in {
226 def _c#NAME# : ALU32_rr<(outs IntRegs:$dst),
227 (ins PredRegs:$src1, IntRegs:$src2),
228 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
231 let PNewValue = "new" in
232 def _cdn#NAME# : ALU32_rr<(outs IntRegs:$dst),
233 (ins PredRegs:$src1, IntRegs:$src2),
234 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
239 let InputType = "reg", neverHasSideEffects = 1 in
240 multiclass TFR_base<string CextOp> {
241 let CextOpcode = CextOp, BaseOpcode = CextOp in {
242 let isPredicable = 1 in
243 def #NAME# : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
247 let isPredicated = 1 in {
248 defm Pt : TFR_Pred<0>;
249 defm NotPt : TFR_Pred<1>;
254 multiclass TFR64_Pred<bit PredNot> {
255 let PredSense = #!if(PredNot, "false", "true") in {
256 def _c#NAME# : ALU32_rr<(outs DoubleRegs:$dst),
257 (ins PredRegs:$src1, DoubleRegs:$src2),
258 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
261 let PNewValue = "new" in
262 def _cdn#NAME# : ALU32_rr<(outs DoubleRegs:$dst),
263 (ins PredRegs:$src1, DoubleRegs:$src2),
264 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
269 let InputType = "reg", neverHasSideEffects = 1 in
270 multiclass TFR64_base<string CextOp> {
271 let CextOpcode = CextOp, BaseOpcode = CextOp in {
272 let isPredicable = 1 in
273 def #NAME# : ALU32_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
277 let isPredicated = 1 in {
278 defm Pt : TFR64_Pred<0>;
279 defm NotPt : TFR64_Pred<1>;
285 multiclass TFRI_Pred<bit PredNot> {
286 let PredSense = #!if(PredNot, "false", "true") in {
287 def _c#NAME# : ALU32_ri<(outs IntRegs:$dst),
288 (ins PredRegs:$src1, s12Ext:$src2),
289 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = #$src2",
293 let PNewValue = "new" in
294 def _cdn#NAME# : ALU32_rr<(outs IntRegs:$dst),
295 (ins PredRegs:$src1, s12Ext:$src2),
296 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = #$src2",
301 let InputType = "imm", isExtendable = 1, isExtentSigned = 1 in
302 multiclass TFRI_base<string CextOp> {
303 let CextOpcode = CextOp, BaseOpcode = CextOp#I in {
304 let opExtendable = 1, opExtentBits = 16, isMoveImm = 1, isPredicable = 1,
305 isReMaterializable = 1 in
306 def #NAME# : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
308 [(set (i32 IntRegs:$dst), s16ExtPred:$src1)]>;
310 let opExtendable = 2, opExtentBits = 12, neverHasSideEffects = 1,
311 isPredicated = 1 in {
312 defm Pt : TFRI_Pred<0>;
313 defm NotPt : TFRI_Pred<1>;
318 defm TFRI : TFRI_base<"TFR">, ImmRegRel, PredNewRel;
319 defm TFR : TFR_base<"TFR">, ImmRegRel, PredNewRel;
320 defm TFR64 : TFR64_base<"TFR64">, ImmRegRel, PredNewRel;
322 // Transfer control register.
323 let neverHasSideEffects = 1 in
324 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
327 //===----------------------------------------------------------------------===//
329 //===----------------------------------------------------------------------===//
332 //===----------------------------------------------------------------------===//
334 //===----------------------------------------------------------------------===//
338 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
339 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
341 def HexagonWrapperCombineII :
342 SDNode<"HexagonISD::WrapperCombineII", SDTHexagonI64I32I32>;
343 def HexagonWrapperCombineRR :
344 SDNode<"HexagonISD::WrapperCombineRR", SDTHexagonI64I32I32>;
346 // Combines the two integer registers SRC1 and SRC2 into a double register.
347 let isPredicable = 1 in
348 def COMBINE_rr : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1,
350 "$dst = combine($src1, $src2)",
351 [(set (i64 DoubleRegs:$dst),
352 (i64 (HexagonWrapperCombineRR (i32 IntRegs:$src1),
353 (i32 IntRegs:$src2))))]>;
355 // Rd=combine(Rt.[HL], Rs.[HL])
356 class COMBINE_halves<string A, string B>: ALU32_rr<(outs IntRegs:$dst),
359 "$dst = combine($src1."# A #", $src2."# B #")", []>;
361 let isPredicable = 1 in {
362 def COMBINE_hh : COMBINE_halves<"H", "H">;
363 def COMBINE_hl : COMBINE_halves<"H", "L">;
364 def COMBINE_lh : COMBINE_halves<"L", "H">;
365 def COMBINE_ll : COMBINE_halves<"L", "L">;
368 def : Pat<(i32 (trunc (i64 (srl (i64 DoubleRegs:$a), (i32 16))))),
369 (COMBINE_lh (EXTRACT_SUBREG (i64 DoubleRegs:$a), subreg_hireg),
370 (EXTRACT_SUBREG (i64 DoubleRegs:$a), subreg_loreg))>;
372 // Combines the two immediates SRC1 and SRC2 into a double register.
373 class COMBINE_imm<Operand imm1, Operand imm2, PatLeaf pat1, PatLeaf pat2> :
374 ALU32_ii<(outs DoubleRegs:$dst), (ins imm1:$src1, imm2:$src2),
375 "$dst = combine(#$src1, #$src2)",
376 [(set (i64 DoubleRegs:$dst),
377 (i64 (HexagonWrapperCombineII (i32 pat1:$src1), (i32 pat2:$src2))))]>;
379 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8 in
380 def COMBINE_Ii : COMBINE_imm<s8Ext, s8Imm, s8ExtPred, s8ImmPred>;
383 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
386 "$dst = vmux($src1, $src2, $src3)",
389 let CextOpcode = "MUX", InputType = "reg" in
390 def MUX_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
391 IntRegs:$src2, IntRegs:$src3),
392 "$dst = mux($src1, $src2, $src3)",
393 [(set (i32 IntRegs:$dst),
394 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
395 (i32 IntRegs:$src3))))]>, ImmRegRel;
397 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
398 CextOpcode = "MUX", InputType = "imm" in
399 def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
401 "$dst = mux($src1, #$src2, $src3)",
402 [(set (i32 IntRegs:$dst),
403 (i32 (select (i1 PredRegs:$src1), s8ExtPred:$src2,
404 (i32 IntRegs:$src3))))]>, ImmRegRel;
406 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
407 CextOpcode = "MUX", InputType = "imm" in
408 def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
410 "$dst = mux($src1, $src2, #$src3)",
411 [(set (i32 IntRegs:$dst),
412 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
413 s8ExtPred:$src3)))]>, ImmRegRel;
415 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
416 def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
418 "$dst = mux($src1, #$src2, #$src3)",
419 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
421 s8ImmPred:$src3)))]>;
424 let isPredicable = 1 in
425 def ASLH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
426 "$dst = aslh($src1)",
427 [(set (i32 IntRegs:$dst), (shl 16, (i32 IntRegs:$src1)))]>;
429 let isPredicable = 1 in
430 def ASRH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
431 "$dst = asrh($src1)",
432 [(set (i32 IntRegs:$dst), (sra 16, (i32 IntRegs:$src1)))]>;
435 let isPredicable = 1 in
436 def SXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
437 "$dst = sxtb($src1)",
438 [(set (i32 IntRegs:$dst), (sext_inreg (i32 IntRegs:$src1), i8))]>;
440 let isPredicable = 1 in
441 def SXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
442 "$dst = sxth($src1)",
443 [(set (i32 IntRegs:$dst), (sext_inreg (i32 IntRegs:$src1), i16))]>;
446 let isPredicable = 1, neverHasSideEffects = 1 in
447 def ZXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
448 "$dst = zxtb($src1)",
451 let isPredicable = 1, neverHasSideEffects = 1 in
452 def ZXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
453 "$dst = zxth($src1)",
455 //===----------------------------------------------------------------------===//
457 //===----------------------------------------------------------------------===//
460 //===----------------------------------------------------------------------===//
462 //===----------------------------------------------------------------------===//
464 // Conditional combine.
465 let neverHasSideEffects = 1, isPredicated = 1 in
466 def COMBINE_rr_cPt : ALU32_rr<(outs DoubleRegs:$dst),
467 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
468 "if ($src1) $dst = combine($src2, $src3)",
471 let neverHasSideEffects = 1, isPredicated = 1 in
472 def COMBINE_rr_cNotPt : ALU32_rr<(outs DoubleRegs:$dst),
473 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
474 "if (!$src1) $dst = combine($src2, $src3)",
477 let neverHasSideEffects = 1, isPredicated = 1 in
478 def COMBINE_rr_cdnPt : ALU32_rr<(outs DoubleRegs:$dst),
479 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
480 "if ($src1.new) $dst = combine($src2, $src3)",
483 let neverHasSideEffects = 1, isPredicated = 1 in
484 def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst),
485 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
486 "if (!$src1.new) $dst = combine($src2, $src3)",
490 defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", "CMPGTU", setugt>, ImmRegRel;
491 defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", "CMPGT", setgt>, ImmRegRel;
492 defm CMPLT : CMP32_rr<"cmp.lt", setlt>;
493 defm CMPLTU : CMP32_rr<"cmp.ltu", setult>;
494 defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", "CMPEQ", seteq>, ImmRegRel;
495 defm CMPGE : CMP32_ri_s8<"cmp.ge", setge>;
496 defm CMPGEU : CMP32_ri_u8<"cmp.geu", setuge>;
498 def CTLZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
500 [(set (i32 IntRegs:$dst), (ctlz (i32 IntRegs:$src1)))]>;
502 def CTTZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
504 [(set (i32 IntRegs:$dst), (cttz (i32 IntRegs:$src1)))]>;
506 def CTLZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
508 [(set (i32 IntRegs:$dst), (i32 (trunc (ctlz (i64 DoubleRegs:$src1)))))]>;
510 def CTTZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
512 [(set (i32 IntRegs:$dst), (i32 (trunc (cttz (i64 DoubleRegs:$src1)))))]>;
514 def TSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
515 "$dst = tstbit($src1, $src2)",
516 [(set (i1 PredRegs:$dst),
517 (setne (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>;
519 def TSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
520 "$dst = tstbit($src1, $src2)",
521 [(set (i1 PredRegs:$dst),
522 (setne (and (shl 1, (u5ImmPred:$src2)), (i32 IntRegs:$src1)), 0))]>;
524 //===----------------------------------------------------------------------===//
526 //===----------------------------------------------------------------------===//
529 //===----------------------------------------------------------------------===//
531 //===----------------------------------------------------------------------===//
533 def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
535 "$dst = add($src1, $src2)",
536 [(set (i64 DoubleRegs:$dst), (add (i64 DoubleRegs:$src1),
537 (i64 DoubleRegs:$src2)))]>;
542 defm CMPEHexagon4 : CMP64_rr<"cmp.eq", seteq>;
543 defm CMPGT64 : CMP64_rr<"cmp.gt", setgt>;
544 defm CMPGTU64 : CMP64_rr<"cmp.gtu", setugt>;
546 // Logical operations.
547 def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
549 "$dst = and($src1, $src2)",
550 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
551 (i64 DoubleRegs:$src2)))]>;
553 def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
555 "$dst = or($src1, $src2)",
556 [(set (i64 DoubleRegs:$dst), (or (i64 DoubleRegs:$src1),
557 (i64 DoubleRegs:$src2)))]>;
559 def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
561 "$dst = xor($src1, $src2)",
562 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
563 (i64 DoubleRegs:$src2)))]>;
566 def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
567 "$dst = max($src2, $src1)",
568 [(set (i32 IntRegs:$dst),
569 (i32 (select (i1 (setlt (i32 IntRegs:$src2),
570 (i32 IntRegs:$src1))),
571 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
573 def MAXUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
574 "$dst = maxu($src2, $src1)",
575 [(set (i32 IntRegs:$dst),
576 (i32 (select (i1 (setult (i32 IntRegs:$src2),
577 (i32 IntRegs:$src1))),
578 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
580 def MAXd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
582 "$dst = max($src2, $src1)",
583 [(set (i64 DoubleRegs:$dst),
584 (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
585 (i64 DoubleRegs:$src1))),
586 (i64 DoubleRegs:$src1),
587 (i64 DoubleRegs:$src2))))]>;
589 def MAXUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
591 "$dst = maxu($src2, $src1)",
592 [(set (i64 DoubleRegs:$dst),
593 (i64 (select (i1 (setult (i64 DoubleRegs:$src2),
594 (i64 DoubleRegs:$src1))),
595 (i64 DoubleRegs:$src1),
596 (i64 DoubleRegs:$src2))))]>;
599 def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
600 "$dst = min($src2, $src1)",
601 [(set (i32 IntRegs:$dst),
602 (i32 (select (i1 (setgt (i32 IntRegs:$src2),
603 (i32 IntRegs:$src1))),
604 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
606 def MINUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
607 "$dst = minu($src2, $src1)",
608 [(set (i32 IntRegs:$dst),
609 (i32 (select (i1 (setugt (i32 IntRegs:$src2),
610 (i32 IntRegs:$src1))),
611 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
613 def MINd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
615 "$dst = min($src2, $src1)",
616 [(set (i64 DoubleRegs:$dst),
617 (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
618 (i64 DoubleRegs:$src1))),
619 (i64 DoubleRegs:$src1),
620 (i64 DoubleRegs:$src2))))]>;
622 def MINUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
624 "$dst = minu($src2, $src1)",
625 [(set (i64 DoubleRegs:$dst),
626 (i64 (select (i1 (setugt (i64 DoubleRegs:$src2),
627 (i64 DoubleRegs:$src1))),
628 (i64 DoubleRegs:$src1),
629 (i64 DoubleRegs:$src2))))]>;
632 def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
634 "$dst = sub($src1, $src2)",
635 [(set (i64 DoubleRegs:$dst), (sub (i64 DoubleRegs:$src1),
636 (i64 DoubleRegs:$src2)))]>;
638 // Subtract halfword.
640 //===----------------------------------------------------------------------===//
642 //===----------------------------------------------------------------------===//
644 //===----------------------------------------------------------------------===//
646 //===----------------------------------------------------------------------===//
648 //===----------------------------------------------------------------------===//
650 //===----------------------------------------------------------------------===//
652 //===----------------------------------------------------------------------===//
654 //===----------------------------------------------------------------------===//
656 //===----------------------------------------------------------------------===//
658 //===----------------------------------------------------------------------===//
660 //===----------------------------------------------------------------------===//
662 //===----------------------------------------------------------------------===//
663 // Logical reductions on predicates.
665 // Looping instructions.
667 // Pipelined looping instructions.
669 // Logical operations on predicates.
670 def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
671 "$dst = and($src1, $src2)",
672 [(set (i1 PredRegs:$dst), (and (i1 PredRegs:$src1),
673 (i1 PredRegs:$src2)))]>;
675 let neverHasSideEffects = 1 in
676 def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
678 "$dst = and($src1, !$src2)",
681 def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
682 "$dst = any8($src1)",
685 def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
686 "$dst = all8($src1)",
689 def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
691 "$dst = vitpack($src1, $src2)",
694 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
697 "$dst = valignb($src1, $src2, $src3)",
700 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
703 "$dst = vspliceb($src1, $src2, $src3)",
706 def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
707 "$dst = mask($src1)",
710 def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
712 [(set (i1 PredRegs:$dst), (not (i1 PredRegs:$src1)))]>;
714 def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
715 "$dst = or($src1, $src2)",
716 [(set (i1 PredRegs:$dst), (or (i1 PredRegs:$src1),
717 (i1 PredRegs:$src2)))]>;
719 def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
720 "$dst = xor($src1, $src2)",
721 [(set (i1 PredRegs:$dst), (xor (i1 PredRegs:$src1),
722 (i1 PredRegs:$src2)))]>;
725 // User control register transfer.
726 //===----------------------------------------------------------------------===//
728 //===----------------------------------------------------------------------===//
731 //===----------------------------------------------------------------------===//
733 //===----------------------------------------------------------------------===//
735 let isBranch = 1, isTerminator=1, isBarrier = 1, isPredicable = 1 in {
736 def JMP : JInst< (outs),
737 (ins brtarget:$offset),
743 let isBranch = 1, isTerminator=1, Defs = [PC],
744 isPredicated = 1 in {
745 def JMP_c : JInst< (outs),
746 (ins PredRegs:$src, brtarget:$offset),
747 "if ($src) jump $offset",
748 [(brcond (i1 PredRegs:$src), bb:$offset)]>;
752 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
753 isPredicated = 1 in {
754 def JMP_cNot : JInst< (outs),
755 (ins PredRegs:$src, brtarget:$offset),
756 "if (!$src) jump $offset",
760 let isTerminator = 1, isBranch = 1, neverHasSideEffects = 1, Defs = [PC],
761 isPredicated = 1 in {
762 def BRCOND : JInst < (outs), (ins PredRegs:$pred, brtarget:$dst),
763 "if ($pred) jump $dst",
767 // Jump to address conditioned on new predicate.
769 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
770 isPredicated = 1 in {
771 def JMP_cdnPt : JInst< (outs),
772 (ins PredRegs:$src, brtarget:$offset),
773 "if ($src.new) jump:t $offset",
778 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
779 isPredicated = 1 in {
780 def JMP_cdnNotPt : JInst< (outs),
781 (ins PredRegs:$src, brtarget:$offset),
782 "if (!$src.new) jump:t $offset",
787 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
788 isPredicated = 1 in {
789 def JMP_cdnPnt : JInst< (outs),
790 (ins PredRegs:$src, brtarget:$offset),
791 "if ($src.new) jump:nt $offset",
796 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
797 isPredicated = 1 in {
798 def JMP_cdnNotPnt : JInst< (outs),
799 (ins PredRegs:$src, brtarget:$offset),
800 "if (!$src.new) jump:nt $offset",
803 //===----------------------------------------------------------------------===//
805 //===----------------------------------------------------------------------===//
807 //===----------------------------------------------------------------------===//
809 //===----------------------------------------------------------------------===//
810 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
811 [SDNPHasChain, SDNPOptInGlue]>;
813 // Jump to address from register.
814 let isPredicable =1, isReturn = 1, isTerminator = 1, isBarrier = 1,
815 Defs = [PC], Uses = [R31] in {
816 def JMPR: JRInst<(outs), (ins),
821 // Jump to address from register.
822 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
823 Defs = [PC], Uses = [R31] in {
824 def JMPR_cPt: JRInst<(outs), (ins PredRegs:$src1),
825 "if ($src1) jumpr r31",
829 // Jump to address from register.
830 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
831 Defs = [PC], Uses = [R31] in {
832 def JMPR_cNotPt: JRInst<(outs), (ins PredRegs:$src1),
833 "if (!$src1) jumpr r31",
837 //===----------------------------------------------------------------------===//
839 //===----------------------------------------------------------------------===//
841 //===----------------------------------------------------------------------===//
843 //===----------------------------------------------------------------------===//
845 // Load -- MEMri operand
846 multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
847 bit isNot, bit isPredNew> {
848 let PNewValue = #!if(isPredNew, "new", "") in
849 def #NAME# : LDInst2<(outs RC:$dst),
850 (ins PredRegs:$src1, MEMri:$addr),
851 #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
852 ") ")#"$dst = "#mnemonic#"($addr)",
856 multiclass LD_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
857 let PredSense = #!if(PredNot, "false", "true") in {
858 defm _c#NAME# : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
860 defm _cdn#NAME# : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
864 let isExtendable = 1, neverHasSideEffects = 1 in
865 multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
866 bits<5> ImmBits, bits<5> PredImmBits> {
868 let CextOpcode = CextOp, BaseOpcode = CextOp in {
869 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
871 def #NAME# : LDInst2<(outs RC:$dst), (ins MEMri:$addr),
872 "$dst = "#mnemonic#"($addr)",
875 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
876 isPredicated = 1 in {
877 defm Pt : LD_MEMri_Pred<mnemonic, RC, 0 >;
878 defm NotPt : LD_MEMri_Pred<mnemonic, RC, 1 >;
883 let addrMode = BaseImmOffset, isMEMri = "true" in {
884 defm LDrib: LD_MEMri < "memb", "LDrib", IntRegs, 11, 6>, AddrModeRel;
885 defm LDriub: LD_MEMri < "memub" , "LDriub", IntRegs, 11, 6>, AddrModeRel;
886 defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
887 defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel;
888 defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;
889 defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;
892 def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
893 (LDrib ADDRriS11_0:$addr) >;
895 def : Pat < (i32 (zextloadi8 ADDRriS11_0:$addr)),
896 (LDriub ADDRriS11_0:$addr) >;
898 def : Pat < (i32 (sextloadi16 ADDRriS11_1:$addr)),
899 (LDrih ADDRriS11_1:$addr) >;
901 def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)),
902 (LDriuh ADDRriS11_1:$addr) >;
904 def : Pat < (i32 (load ADDRriS11_2:$addr)),
905 (LDriw ADDRriS11_2:$addr) >;
907 def : Pat < (i64 (load ADDRriS11_3:$addr)),
908 (LDrid ADDRriS11_3:$addr) >;
911 // Load - Base with Immediate offset addressing mode
912 multiclass LD_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
913 bit isNot, bit isPredNew> {
914 let PNewValue = #!if(isPredNew, "new", "") in
915 def #NAME# : LDInst2<(outs RC:$dst),
916 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
917 #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
918 ") ")#"$dst = "#mnemonic#"($src2+#$src3)",
922 multiclass LD_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
924 let PredSense = #!if(PredNot, "false", "true") in {
925 defm _c#NAME# : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
927 defm _cdn#NAME# : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
931 let isExtendable = 1, neverHasSideEffects = 1 in
932 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
933 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
934 bits<5> PredImmBits> {
936 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
937 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
938 isPredicable = 1, AddedComplexity = 20 in
939 def #NAME# : LDInst2<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
940 "$dst = "#mnemonic#"($src1+#$offset)",
943 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
944 isPredicated = 1 in {
945 defm Pt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 0 >;
946 defm NotPt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 1 >;
951 let addrMode = BaseImmOffset in {
952 defm LDrib_indexed: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext,
954 defm LDriub_indexed: LD_Idxd <"memub" , "LDriub", IntRegs, s11_0Ext, u6_0Ext,
956 defm LDrih_indexed: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
958 defm LDriuh_indexed: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext,
960 defm LDriw_indexed: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
962 defm LDrid_indexed: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,
966 let AddedComplexity = 20 in {
967 def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
968 (LDrib_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
970 def : Pat < (i32 (zextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
971 (LDriub_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
973 def : Pat < (i32 (sextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
974 (LDrih_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
976 def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
977 (LDriuh_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
979 def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
980 (LDriw_indexed IntRegs:$src1, s11_2ExtPred:$offset) >;
982 def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
983 (LDrid_indexed IntRegs:$src1, s11_3ExtPred:$offset) >;
986 let neverHasSideEffects = 1 in
987 def LDrid_GP : LDInst2<(outs DoubleRegs:$dst),
988 (ins globaladdress:$global, u16Imm:$offset),
989 "$dst = memd(#$global+$offset)",
993 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
994 def LDd_GP : LDInst2<(outs DoubleRegs:$dst),
995 (ins globaladdress:$global),
996 "$dst = memd(#$global)",
1000 //===----------------------------------------------------------------------===//
1001 // Post increment load
1002 // Make sure that in post increment load, the first operand is always the post
1003 // increment operand.
1004 //===----------------------------------------------------------------------===//
1006 multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1007 bit isNot, bit isPredNew> {
1008 let PNewValue = #!if(isPredNew, "new", "") in
1009 def #NAME# : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1010 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1011 #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1012 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1017 multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,
1018 Operand ImmOp, bit PredNot> {
1019 let PredSense = #!if(PredNot, "false", "true") in {
1020 defm _c#NAME# : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1022 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1023 defm _cdn#NAME#_V4 : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1027 multiclass LD_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1030 let BaseOpcode = "POST_"#BaseOp in {
1031 let isPredicable = 1 in
1032 def #NAME# : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1033 (ins IntRegs:$src1, ImmOp:$offset),
1034 "$dst = "#mnemonic#"($src1++#$offset)",
1038 let isPredicated = 1 in {
1039 defm Pt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1040 defm NotPt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1045 let hasCtrlDep = 1, neverHasSideEffects = 1 in {
1046 defm POST_LDrib : LD_PostInc<"memb", "LDrib", IntRegs, s4_0Imm>,
1048 defm POST_LDriub : LD_PostInc<"memub", "LDriub", IntRegs, s4_0Imm>,
1050 defm POST_LDrih : LD_PostInc<"memh", "LDrih", IntRegs, s4_1Imm>,
1052 defm POST_LDriuh : LD_PostInc<"memuh", "LDriuh", IntRegs, s4_1Imm>,
1054 defm POST_LDriw : LD_PostInc<"memw", "LDriw", IntRegs, s4_2Imm>,
1056 defm POST_LDrid : LD_PostInc<"memd", "LDrid", DoubleRegs, s4_3Imm>,
1060 def : Pat< (i32 (extloadi1 ADDRriS11_0:$addr)),
1061 (i32 (LDrib ADDRriS11_0:$addr)) >;
1063 // Load byte any-extend.
1064 def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
1065 (i32 (LDrib ADDRriS11_0:$addr)) >;
1067 // Indexed load byte any-extend.
1068 let AddedComplexity = 20 in
1069 def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1070 (i32 (LDrib_indexed IntRegs:$src1, s11_0ImmPred:$offset)) >;
1072 let neverHasSideEffects = 1 in
1073 def LDrib_GP : LDInst2<(outs IntRegs:$dst),
1074 (ins globaladdress:$global, u16Imm:$offset),
1075 "$dst = memb(#$global+$offset)",
1079 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1080 def LDb_GP : LDInst2<(outs IntRegs:$dst),
1081 (ins globaladdress:$global),
1082 "$dst = memb(#$global)",
1086 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1087 def LDub_GP : LDInst2<(outs IntRegs:$dst),
1088 (ins globaladdress:$global),
1089 "$dst = memub(#$global)",
1093 def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
1094 (i32 (LDrih ADDRriS11_1:$addr))>;
1096 let AddedComplexity = 20 in
1097 def : Pat < (i32 (extloadi16 (add IntRegs:$src1, s11_1ImmPred:$offset))),
1098 (i32 (LDrih_indexed IntRegs:$src1, s11_1ImmPred:$offset)) >;
1100 let neverHasSideEffects = 1 in
1101 def LDrih_GP : LDInst2<(outs IntRegs:$dst),
1102 (ins globaladdress:$global, u16Imm:$offset),
1103 "$dst = memh(#$global+$offset)",
1107 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1108 def LDh_GP : LDInst2<(outs IntRegs:$dst),
1109 (ins globaladdress:$global),
1110 "$dst = memh(#$global)",
1114 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1115 def LDuh_GP : LDInst2<(outs IntRegs:$dst),
1116 (ins globaladdress:$global),
1117 "$dst = memuh(#$global)",
1121 let AddedComplexity = 10 in
1122 def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
1123 (i32 (LDriub ADDRriS11_0:$addr))>;
1125 let AddedComplexity = 20 in
1126 def : Pat < (i32 (zextloadi1 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1127 (i32 (LDriub_indexed IntRegs:$src1, s11_0ImmPred:$offset))>;
1129 let neverHasSideEffects = 1 in
1130 def LDriub_GP : LDInst2<(outs IntRegs:$dst),
1131 (ins globaladdress:$global, u16Imm:$offset),
1132 "$dst = memub(#$global+$offset)",
1136 // Load unsigned halfword.
1137 let neverHasSideEffects = 1 in
1138 def LDriuh_GP : LDInst2<(outs IntRegs:$dst),
1139 (ins globaladdress:$global, u16Imm:$offset),
1140 "$dst = memuh(#$global+$offset)",
1145 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
1146 isPseudo = 1, Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1147 def LDriw_pred : LDInst2<(outs PredRegs:$dst),
1149 "Error; should not emit",
1153 let neverHasSideEffects = 1 in
1154 def LDriw_GP : LDInst2<(outs IntRegs:$dst),
1155 (ins globaladdress:$global, u16Imm:$offset),
1156 "$dst = memw(#$global+$offset)",
1160 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1161 def LDw_GP : LDInst2<(outs IntRegs:$dst),
1162 (ins globaladdress:$global),
1163 "$dst = memw(#$global)",
1167 // Deallocate stack frame.
1168 let Defs = [R29, R30, R31], Uses = [R29], neverHasSideEffects = 1 in {
1169 def DEALLOCFRAME : LDInst2<(outs), (ins),
1174 // Load and unpack bytes to halfwords.
1175 //===----------------------------------------------------------------------===//
1177 //===----------------------------------------------------------------------===//
1179 //===----------------------------------------------------------------------===//
1181 //===----------------------------------------------------------------------===//
1182 //===----------------------------------------------------------------------===//
1184 //===----------------------------------------------------------------------===//
1186 //===----------------------------------------------------------------------===//
1188 //===----------------------------------------------------------------------===//
1189 //===----------------------------------------------------------------------===//
1191 //===----------------------------------------------------------------------===//
1193 //===----------------------------------------------------------------------===//
1195 //===----------------------------------------------------------------------===//
1196 // Multiply and use lower result.
1198 def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1199 "$dst =+ mpyi($src1, #$src2)",
1200 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1201 u8ImmPred:$src2))]>;
1204 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, n8Imm:$src2),
1205 "$dst =- mpyi($src1, #$src2)",
1206 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1207 n8ImmPred:$src2))]>;
1210 // s9 is NOT the same as m9 - but it works.. so far.
1211 // Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
1212 // depending on the value of m9. See Arch Spec.
1213 def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Imm:$src2),
1214 "$dst = mpyi($src1, #$src2)",
1215 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1216 s9ImmPred:$src2))]>;
1219 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1220 "$dst = mpyi($src1, $src2)",
1221 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1222 (i32 IntRegs:$src2)))]>;
1225 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
1226 (ins IntRegs:$src1, IntRegs:$src2, u8Imm:$src3),
1227 "$dst += mpyi($src2, #$src3)",
1228 [(set (i32 IntRegs:$dst),
1229 (add (mul (i32 IntRegs:$src2), u8ImmPred:$src3),
1230 (i32 IntRegs:$src1)))],
1234 def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
1235 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1236 "$dst += mpyi($src2, $src3)",
1237 [(set (i32 IntRegs:$dst),
1238 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1239 (i32 IntRegs:$src1)))],
1243 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
1244 (ins IntRegs:$src1, IntRegs:$src2, u8Imm:$src3),
1245 "$dst -= mpyi($src2, #$src3)",
1246 [(set (i32 IntRegs:$dst),
1247 (sub (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1248 u8ImmPred:$src3)))],
1251 // Multiply and use upper result.
1252 // Rd=mpy(Rs,Rt.H):<<1:rnd:sat
1253 // Rd=mpy(Rs,Rt.L):<<1:rnd:sat
1255 def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1256 "$dst = mpy($src1, $src2)",
1257 [(set (i32 IntRegs:$dst), (mulhs (i32 IntRegs:$src1),
1258 (i32 IntRegs:$src2)))]>;
1260 // Rd=mpy(Rs,Rt):rnd
1262 def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1263 "$dst = mpyu($src1, $src2)",
1264 [(set (i32 IntRegs:$dst), (mulhu (i32 IntRegs:$src1),
1265 (i32 IntRegs:$src2)))]>;
1267 // Multiply and use full result.
1269 def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1270 "$dst = mpyu($src1, $src2)",
1271 [(set (i64 DoubleRegs:$dst),
1272 (mul (i64 (anyext (i32 IntRegs:$src1))),
1273 (i64 (anyext (i32 IntRegs:$src2)))))]>;
1276 def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1277 "$dst = mpy($src1, $src2)",
1278 [(set (i64 DoubleRegs:$dst),
1279 (mul (i64 (sext (i32 IntRegs:$src1))),
1280 (i64 (sext (i32 IntRegs:$src2)))))]>;
1282 // Multiply and accumulate, use full result.
1283 // Rxx[+-]=mpy(Rs,Rt)
1285 def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
1286 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1287 "$dst += mpy($src2, $src3)",
1288 [(set (i64 DoubleRegs:$dst),
1289 (add (mul (i64 (sext (i32 IntRegs:$src2))),
1290 (i64 (sext (i32 IntRegs:$src3)))),
1291 (i64 DoubleRegs:$src1)))],
1295 def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
1296 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1297 "$dst -= mpy($src2, $src3)",
1298 [(set (i64 DoubleRegs:$dst),
1299 (sub (i64 DoubleRegs:$src1),
1300 (mul (i64 (sext (i32 IntRegs:$src2))),
1301 (i64 (sext (i32 IntRegs:$src3))))))],
1304 // Rxx[+-]=mpyu(Rs,Rt)
1306 def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1307 IntRegs:$src2, IntRegs:$src3),
1308 "$dst += mpyu($src2, $src3)",
1309 [(set (i64 DoubleRegs:$dst),
1310 (add (mul (i64 (anyext (i32 IntRegs:$src2))),
1311 (i64 (anyext (i32 IntRegs:$src3)))),
1312 (i64 DoubleRegs:$src1)))], "$src1 = $dst">;
1315 def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
1316 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1317 "$dst += mpyu($src2, $src3)",
1318 [(set (i64 DoubleRegs:$dst),
1319 (sub (i64 DoubleRegs:$src1),
1320 (mul (i64 (anyext (i32 IntRegs:$src2))),
1321 (i64 (anyext (i32 IntRegs:$src3))))))],
1325 def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1326 IntRegs:$src2, IntRegs:$src3),
1327 "$dst += add($src2, $src3)",
1328 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1329 (i32 IntRegs:$src3)),
1330 (i32 IntRegs:$src1)))],
1333 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1334 IntRegs:$src2, s8Imm:$src3),
1335 "$dst += add($src2, #$src3)",
1336 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1338 (i32 IntRegs:$src1)))],
1341 def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1342 IntRegs:$src2, IntRegs:$src3),
1343 "$dst -= add($src2, $src3)",
1344 [(set (i32 IntRegs:$dst),
1345 (sub (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1346 (i32 IntRegs:$src3))))],
1349 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1350 IntRegs:$src2, s8Imm:$src3),
1351 "$dst -= add($src2, #$src3)",
1352 [(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
1353 (add (i32 IntRegs:$src2),
1354 s8ImmPred:$src3)))],
1357 //===----------------------------------------------------------------------===//
1359 //===----------------------------------------------------------------------===//
1361 //===----------------------------------------------------------------------===//
1363 //===----------------------------------------------------------------------===//
1364 //===----------------------------------------------------------------------===//
1366 //===----------------------------------------------------------------------===//
1368 //===----------------------------------------------------------------------===//
1370 //===----------------------------------------------------------------------===//
1371 //===----------------------------------------------------------------------===//
1373 //===----------------------------------------------------------------------===//
1375 //===----------------------------------------------------------------------===//
1377 //===----------------------------------------------------------------------===//
1378 //===----------------------------------------------------------------------===//
1380 //===----------------------------------------------------------------------===//
1382 //===----------------------------------------------------------------------===//
1384 //===----------------------------------------------------------------------===//
1386 /// Assumptions::: ****** DO NOT IGNORE ********
1387 /// 1. Make sure that in post increment store, the zero'th operand is always the
1388 /// post increment operand.
1389 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
1392 // Store doubleword.
1394 let neverHasSideEffects = 1 in
1395 def STrid_GP : STInst2<(outs),
1396 (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),
1397 "memd(#$global+$offset) = $src",
1401 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1402 def STd_GP : STInst2<(outs),
1403 (ins globaladdress:$global, DoubleRegs:$src),
1404 "memd(#$global) = $src",
1408 let hasCtrlDep = 1, isPredicable = 1 in
1409 def POST_STdri : STInstPI<(outs IntRegs:$dst),
1410 (ins DoubleRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1411 "memd($src2++#$offset) = $src1",
1413 (post_store (i64 DoubleRegs:$src1), (i32 IntRegs:$src2),
1414 s4_3ImmPred:$offset))],
1417 // if ([!]Pv) memd(Rx++#s4:3)=Rtt
1418 // if (Pv) memd(Rx++#s4:3)=Rtt
1419 let AddedComplexity = 10, neverHasSideEffects = 1,
1421 def POST_STdri_cPt : STInst2PI<(outs IntRegs:$dst),
1422 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1424 "if ($src1) memd($src3++#$offset) = $src2",
1428 // if (!Pv) memd(Rx++#s4:3)=Rtt
1429 let AddedComplexity = 10, neverHasSideEffects = 1, isPredicated = 1,
1431 def POST_STdri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1432 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1434 "if (!$src1) memd($src3++#$offset) = $src2",
1438 //===----------------------------------------------------------------------===//
1439 // multiclass for the store instructions with MEMri operand.
1440 //===----------------------------------------------------------------------===//
1441 multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot,
1443 let PNewValue = #!if(isPredNew, "new", "") in
1444 def #NAME# : STInst2<(outs),
1445 (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
1446 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1447 ") ")#mnemonic#"($addr) = $src2",
1451 multiclass ST_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1452 let PredSense = #!if(PredNot, "false", "true") in {
1453 defm _c#NAME# : ST_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
1456 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1457 defm _cdn#NAME#_V4 : ST_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
1461 let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1462 multiclass ST_MEMri<string mnemonic, string CextOp, RegisterClass RC,
1463 bits<5> ImmBits, bits<5> PredImmBits> {
1465 let CextOpcode = CextOp, BaseOpcode = CextOp in {
1466 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1468 def #NAME# : STInst2<(outs),
1469 (ins MEMri:$addr, RC:$src),
1470 #mnemonic#"($addr) = $src",
1473 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
1474 isPredicated = 1 in {
1475 defm Pt : ST_MEMri_Pred<mnemonic, RC, 0>;
1476 defm NotPt : ST_MEMri_Pred<mnemonic, RC, 1>;
1481 let addrMode = BaseImmOffset, isMEMri = "true" in {
1482 defm STrib: ST_MEMri < "memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
1483 defm STrih: ST_MEMri < "memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
1484 defm STriw: ST_MEMri < "memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
1486 let isNVStorable = 0 in
1487 defm STrid: ST_MEMri < "memd", "STrid", DoubleRegs, 14, 9>, AddrModeRel;
1490 def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
1491 (STrib ADDRriS11_0:$addr, (i32 IntRegs:$src1))>;
1493 def : Pat<(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr),
1494 (STrih ADDRriS11_1:$addr, (i32 IntRegs:$src1))>;
1496 def : Pat<(store (i32 IntRegs:$src1), ADDRriS11_2:$addr),
1497 (STriw ADDRriS11_2:$addr, (i32 IntRegs:$src1))>;
1499 def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
1500 (STrid ADDRriS11_3:$addr, (i64 DoubleRegs:$src1))>;
1503 //===----------------------------------------------------------------------===//
1504 // multiclass for the store instructions with base+immediate offset
1506 //===----------------------------------------------------------------------===//
1507 multiclass ST_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
1508 bit isNot, bit isPredNew> {
1509 let PNewValue = #!if(isPredNew, "new", "") in
1510 def #NAME# : STInst2<(outs),
1511 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
1512 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1513 ") ")#mnemonic#"($src2+#$src3) = $src4",
1517 multiclass ST_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
1519 let PredSense = #!if(PredNot, "false", "true"), isPredicated = 1 in {
1520 defm _c#NAME# : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
1523 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1524 defm _cdn#NAME#_V4 : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
1528 let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1529 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1530 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
1531 bits<5> PredImmBits> {
1533 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1534 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1536 def #NAME# : STInst2<(outs),
1537 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1538 #mnemonic#"($src1+#$src2) = $src3",
1541 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits in {
1542 defm Pt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 0>;
1543 defm NotPt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 1>;
1548 let addrMode = BaseImmOffset, InputType = "reg" in {
1549 defm STrib_indexed: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext,
1550 u6_0Ext, 11, 6>, AddrModeRel, ImmRegRel;
1551 defm STrih_indexed: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext,
1552 u6_1Ext, 12, 7>, AddrModeRel, ImmRegRel;
1553 defm STriw_indexed: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext,
1554 u6_2Ext, 13, 8>, AddrModeRel, ImmRegRel;
1555 let isNVStorable = 0 in
1556 defm STrid_indexed: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
1557 u6_3Ext, 14, 9>, AddrModeRel;
1560 let AddedComplexity = 10 in {
1561 def : Pat<(truncstorei8 (i32 IntRegs:$src1), (add IntRegs:$src2,
1562 s11_0ExtPred:$offset)),
1563 (STrib_indexed IntRegs:$src2, s11_0ImmPred:$offset,
1564 (i32 IntRegs:$src1))>;
1566 def : Pat<(truncstorei16 (i32 IntRegs:$src1), (add IntRegs:$src2,
1567 s11_1ExtPred:$offset)),
1568 (STrih_indexed IntRegs:$src2, s11_1ImmPred:$offset,
1569 (i32 IntRegs:$src1))>;
1571 def : Pat<(store (i32 IntRegs:$src1), (add IntRegs:$src2,
1572 s11_2ExtPred:$offset)),
1573 (STriw_indexed IntRegs:$src2, s11_2ImmPred:$offset,
1574 (i32 IntRegs:$src1))>;
1576 def : Pat<(store (i64 DoubleRegs:$src1), (add IntRegs:$src2,
1577 s11_3ExtPred:$offset)),
1578 (STrid_indexed IntRegs:$src2, s11_3ImmPred:$offset,
1579 (i64 DoubleRegs:$src1))>;
1582 // memb(gp+#u16:0)=Rt
1583 let neverHasSideEffects = 1 in
1584 def STrib_GP : STInst2<(outs),
1585 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1586 "memb(#$global+$offset) = $src",
1591 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1592 def STb_GP : STInst2<(outs),
1593 (ins globaladdress:$global, IntRegs:$src),
1594 "memb(#$global) = $src",
1598 // memb(Rx++#s4:0)=Rt
1599 let hasCtrlDep = 1, isPredicable = 1 in
1600 def POST_STbri : STInstPI<(outs IntRegs:$dst), (ins IntRegs:$src1,
1603 "memb($src2++#$offset) = $src1",
1605 (post_truncsti8 (i32 IntRegs:$src1), (i32 IntRegs:$src2),
1606 s4_0ImmPred:$offset))],
1609 // if ([!]Pv) memb(Rx++#s4:0)=Rt
1610 // if (Pv) memb(Rx++#s4:0)=Rt
1611 let hasCtrlDep = 1, isPredicated = 1 in
1612 def POST_STbri_cPt : STInst2PI<(outs IntRegs:$dst),
1613 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1614 "if ($src1) memb($src3++#$offset) = $src2",
1617 // if (!Pv) memb(Rx++#s4:0)=Rt
1618 let hasCtrlDep = 1, isPredicated = 1 in
1619 def POST_STbri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1620 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1621 "if (!$src1) memb($src3++#$offset) = $src2",
1624 let neverHasSideEffects = 1 in
1625 def STrih_GP : STInst2<(outs),
1626 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1627 "memh(#$global+$offset) = $src",
1631 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1632 def STh_GP : STInst2<(outs),
1633 (ins globaladdress:$global, IntRegs:$src),
1634 "memh(#$global) = $src",
1638 // memh(Rx++#s4:1)=Rt.H
1639 // memh(Rx++#s4:1)=Rt
1640 let hasCtrlDep = 1, isPredicable = 1 in
1641 def POST_SThri : STInstPI<(outs IntRegs:$dst),
1642 (ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1643 "memh($src2++#$offset) = $src1",
1645 (post_truncsti16 (i32 IntRegs:$src1), (i32 IntRegs:$src2),
1646 s4_1ImmPred:$offset))],
1649 // if ([!]Pv) memh(Rx++#s4:1)=Rt
1650 // if (Pv) memh(Rx++#s4:1)=Rt
1651 let hasCtrlDep = 1, isPredicated = 1 in
1652 def POST_SThri_cPt : STInst2PI<(outs IntRegs:$dst),
1653 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1654 "if ($src1) memh($src3++#$offset) = $src2",
1657 // if (!Pv) memh(Rx++#s4:1)=Rt
1658 let hasCtrlDep = 1, isPredicated = 1 in
1659 def POST_SThri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1660 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1661 "if (!$src1) memh($src3++#$offset) = $src2",
1667 let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1668 def STriw_pred : STInst2<(outs),
1669 (ins MEMri:$addr, PredRegs:$src1),
1670 "Error; should not emit",
1673 let neverHasSideEffects = 1 in
1674 def STriw_GP : STInst2<(outs),
1675 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1676 "memw(#$global+$offset) = $src",
1680 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1681 def STw_GP : STInst2<(outs),
1682 (ins globaladdress:$global, IntRegs:$src),
1683 "memw(#$global) = $src",
1687 let hasCtrlDep = 1, isPredicable = 1 in
1688 def POST_STwri : STInstPI<(outs IntRegs:$dst),
1689 (ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1690 "memw($src2++#$offset) = $src1",
1692 (post_store (i32 IntRegs:$src1), (i32 IntRegs:$src2),
1693 s4_2ImmPred:$offset))],
1696 // if ([!]Pv) memw(Rx++#s4:2)=Rt
1697 // if (Pv) memw(Rx++#s4:2)=Rt
1698 let hasCtrlDep = 1, isPredicated = 1 in
1699 def POST_STwri_cPt : STInst2PI<(outs IntRegs:$dst),
1700 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
1701 "if ($src1) memw($src3++#$offset) = $src2",
1704 // if (!Pv) memw(Rx++#s4:2)=Rt
1705 let hasCtrlDep = 1, isPredicated = 1 in
1706 def POST_STwri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1707 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
1708 "if (!$src1) memw($src3++#$offset) = $src2",
1713 // Allocate stack frame.
1714 let Defs = [R29, R30], Uses = [R31, R30], neverHasSideEffects = 1 in {
1715 def ALLOCFRAME : STInst2<(outs),
1717 "allocframe(#$amt)",
1720 //===----------------------------------------------------------------------===//
1722 //===----------------------------------------------------------------------===//
1724 //===----------------------------------------------------------------------===//
1726 //===----------------------------------------------------------------------===//
1728 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
1729 "$dst = not($src1)",
1730 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
1733 // Sign extend word to doubleword.
1734 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
1735 "$dst = sxtw($src1)",
1736 [(set (i64 DoubleRegs:$dst), (sext (i32 IntRegs:$src1)))]>;
1737 //===----------------------------------------------------------------------===//
1739 //===----------------------------------------------------------------------===//
1741 //===----------------------------------------------------------------------===//
1743 //===----------------------------------------------------------------------===//
1745 def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1746 "$dst = clrbit($src1, #$src2)",
1747 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
1749 (shl 1, u5ImmPred:$src2))))]>;
1751 def CLRBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1752 "$dst = clrbit($src1, #$src2)",
1755 // Map from r0 = and(r1, 2147483647) to r0 = clrbit(r1, #31).
1756 def : Pat <(and (i32 IntRegs:$src1), 2147483647),
1757 (CLRBIT_31 (i32 IntRegs:$src1), 31)>;
1760 def SETBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1761 "$dst = setbit($src1, #$src2)",
1762 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
1763 (shl 1, u5ImmPred:$src2)))]>;
1765 // Map from r0 = or(r1, -2147483648) to r0 = setbit(r1, #31).
1766 def SETBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1767 "$dst = setbit($src1, #$src2)",
1770 def : Pat <(or (i32 IntRegs:$src1), -2147483648),
1771 (SETBIT_31 (i32 IntRegs:$src1), 31)>;
1774 def TOGBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1775 "$dst = setbit($src1, #$src2)",
1776 [(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
1777 (shl 1, u5ImmPred:$src2)))]>;
1779 // Map from r0 = xor(r1, -2147483648) to r0 = togglebit(r1, #31).
1780 def TOGBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1781 "$dst = togglebit($src1, #$src2)",
1784 def : Pat <(xor (i32 IntRegs:$src1), -2147483648),
1785 (TOGBIT_31 (i32 IntRegs:$src1), 31)>;
1787 // Predicate transfer.
1788 let neverHasSideEffects = 1 in
1789 def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
1790 "$dst = $src1 /* Should almost never emit this. */",
1793 def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1),
1794 "$dst = $src1 /* Should almost never emit this. */",
1795 [(set (i1 PredRegs:$dst), (trunc (i32 IntRegs:$src1)))]>;
1796 //===----------------------------------------------------------------------===//
1798 //===----------------------------------------------------------------------===//
1800 //===----------------------------------------------------------------------===//
1802 //===----------------------------------------------------------------------===//
1803 // Shift by immediate.
1804 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1805 "$dst = asr($src1, #$src2)",
1806 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1807 u5ImmPred:$src2))]>;
1809 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1810 "$dst = asr($src1, #$src2)",
1811 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1812 u6ImmPred:$src2))]>;
1814 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1815 "$dst = asl($src1, #$src2)",
1816 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1817 u5ImmPred:$src2))]>;
1819 def ASLd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1820 "$dst = asl($src1, #$src2)",
1821 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1822 u6ImmPred:$src2))]>;
1824 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1825 "$dst = lsr($src1, #$src2)",
1826 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1827 u5ImmPred:$src2))]>;
1829 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1830 "$dst = lsr($src1, #$src2)",
1831 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1832 u6ImmPred:$src2))]>;
1834 // Shift by immediate and add.
1835 let AddedComplexity = 100 in
1836 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
1838 "$dst = addasl($src1, $src2, #$src3)",
1839 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
1840 (shl (i32 IntRegs:$src2),
1841 u3ImmPred:$src3)))]>;
1843 // Shift by register.
1844 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1845 "$dst = asl($src1, $src2)",
1846 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1847 (i32 IntRegs:$src2)))]>;
1849 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1850 "$dst = asr($src1, $src2)",
1851 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1852 (i32 IntRegs:$src2)))]>;
1854 def LSL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1855 "$dst = lsl($src1, $src2)",
1856 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1857 (i32 IntRegs:$src2)))]>;
1859 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1860 "$dst = lsr($src1, $src2)",
1861 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1862 (i32 IntRegs:$src2)))]>;
1864 def ASLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1865 "$dst = asl($src1, $src2)",
1866 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1867 (i32 IntRegs:$src2)))]>;
1869 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1870 "$dst = lsl($src1, $src2)",
1871 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1872 (i32 IntRegs:$src2)))]>;
1874 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1876 "$dst = asr($src1, $src2)",
1877 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1878 (i32 IntRegs:$src2)))]>;
1880 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1882 "$dst = lsr($src1, $src2)",
1883 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1884 (i32 IntRegs:$src2)))]>;
1886 //===----------------------------------------------------------------------===//
1888 //===----------------------------------------------------------------------===//
1890 //===----------------------------------------------------------------------===//
1892 //===----------------------------------------------------------------------===//
1893 //===----------------------------------------------------------------------===//
1895 //===----------------------------------------------------------------------===//
1897 //===----------------------------------------------------------------------===//
1899 //===----------------------------------------------------------------------===//
1900 //===----------------------------------------------------------------------===//
1902 //===----------------------------------------------------------------------===//
1904 //===----------------------------------------------------------------------===//
1906 //===----------------------------------------------------------------------===//
1908 //===----------------------------------------------------------------------===//
1910 //===----------------------------------------------------------------------===//
1911 def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
1912 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
1915 let hasSideEffects = 1, isHexagonSolo = 1 in
1916 def BARRIER : SYSInst<(outs), (ins),
1918 [(HexagonBARRIER)]>;
1920 //===----------------------------------------------------------------------===//
1922 //===----------------------------------------------------------------------===//
1924 // TFRI64 - assembly mapped.
1925 let isReMaterializable = 1 in
1926 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
1928 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
1930 // Pseudo instruction to encode a set of conditional transfers.
1931 // This instruction is used instead of a mux and trades-off codesize
1932 // for performance. We conduct this transformation optimistically in
1933 // the hope that these instructions get promoted to dot-new transfers.
1934 let AddedComplexity = 100, isPredicated = 1 in
1935 def TFR_condset_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
1938 "Error; should not emit",
1939 [(set (i32 IntRegs:$dst),
1940 (i32 (select (i1 PredRegs:$src1),
1941 (i32 IntRegs:$src2),
1942 (i32 IntRegs:$src3))))]>;
1943 let AddedComplexity = 100, isPredicated = 1 in
1944 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
1945 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
1946 "Error; should not emit",
1947 [(set (i32 IntRegs:$dst),
1948 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
1949 s12ImmPred:$src3)))]>;
1951 let AddedComplexity = 100, isPredicated = 1 in
1952 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
1953 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
1954 "Error; should not emit",
1955 [(set (i32 IntRegs:$dst),
1956 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
1957 (i32 IntRegs:$src3))))]>;
1959 let AddedComplexity = 100, isPredicated = 1 in
1960 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
1961 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
1962 "Error; should not emit",
1963 [(set (i32 IntRegs:$dst),
1964 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
1965 s12ImmPred:$src3)))]>;
1967 // Generate frameindex addresses.
1968 let isReMaterializable = 1 in
1969 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
1970 "$dst = add($src1)",
1971 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
1976 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
1977 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
1978 "loop0($offset, #$src2)",
1982 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
1983 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
1984 "loop0($offset, $src2)",
1988 let isBranch = 1, isTerminator = 1, neverHasSideEffects = 1,
1989 Defs = [PC, LC0], Uses = [SA0, LC0] in {
1990 def ENDLOOP0 : Marker<(outs), (ins brtarget:$offset),
1995 // Support for generating global address.
1996 // Taken from X86InstrInfo.td.
1997 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [
2001 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
2002 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
2004 // HI/LO Instructions
2005 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2006 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
2007 "$dst.l = #LO($global)",
2010 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2011 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
2012 "$dst.h = #HI($global)",
2015 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2016 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2017 "$dst.l = #LO($imm_value)",
2021 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2022 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2023 "$dst.h = #HI($imm_value)",
2026 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2027 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2028 "$dst.l = #LO($jt)",
2031 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2032 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2033 "$dst.h = #HI($jt)",
2037 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2038 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2039 "$dst.l = #LO($label)",
2042 let isReMaterializable = 1, isMoveImm = 1 , neverHasSideEffects = 1 in
2043 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2044 "$dst.h = #HI($label)",
2047 // This pattern is incorrect. When we add small data, we should change
2048 // this pattern to use memw(#foo).
2049 // This is for sdata.
2050 let isMoveImm = 1 in
2051 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2052 "$dst = CONST32(#$global)",
2053 [(set (i32 IntRegs:$dst),
2054 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
2056 // This is for non-sdata.
2057 let isReMaterializable = 1, isMoveImm = 1 in
2058 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2059 "$dst = CONST32(#$global)",
2060 [(set (i32 IntRegs:$dst),
2061 (HexagonCONST32 tglobaladdr:$global))]>;
2063 let isReMaterializable = 1, isMoveImm = 1 in
2064 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2065 "$dst = CONST32(#$jt)",
2066 [(set (i32 IntRegs:$dst),
2067 (HexagonCONST32 tjumptable:$jt))]>;
2069 let isReMaterializable = 1, isMoveImm = 1 in
2070 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2071 "$dst = CONST32(#$global)",
2072 [(set (i32 IntRegs:$dst),
2073 (HexagonCONST32_GP tglobaladdr:$global))]>;
2075 let isReMaterializable = 1, isMoveImm = 1 in
2076 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
2077 "$dst = CONST32(#$global)",
2078 [(set (i32 IntRegs:$dst), imm:$global) ]>;
2080 let isReMaterializable = 1, isMoveImm = 1 in
2081 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
2082 "$dst = CONST32($label)",
2083 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
2085 let isReMaterializable = 1, isMoveImm = 1 in
2086 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
2087 "$dst = CONST64(#$global)",
2088 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
2090 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
2091 "$dst = xor($dst, $dst)",
2092 [(set (i1 PredRegs:$dst), 0)]>;
2094 def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2095 "$dst = mpy($src1, $src2)",
2096 [(set (i32 IntRegs:$dst),
2097 (trunc (i64 (srl (i64 (mul (i64 (sext (i32 IntRegs:$src1))),
2098 (i64 (sext (i32 IntRegs:$src2))))),
2101 // Pseudo instructions.
2102 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
2104 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
2105 SDTCisVT<1, i32> ]>;
2107 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
2108 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2110 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
2111 [SDNPHasChain, SDNPOutGlue]>;
2113 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2115 def call : SDNode<"HexagonISD::CALL", SDT_SPCall,
2116 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
2118 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
2119 // Optional Flag and Variable Arguments.
2120 // Its 1 Operand has pointer type.
2121 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
2122 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
2124 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
2125 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
2126 "Should never be emitted",
2127 [(callseq_start timm:$amt)]>;
2130 let Defs = [R29, R30, R31], Uses = [R29] in {
2131 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2132 "Should never be emitted",
2133 [(callseq_end timm:$amt1, timm:$amt2)]>;
2136 let isCall = 1, neverHasSideEffects = 1,
2137 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2138 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2139 def CALL : JInst<(outs), (ins calltarget:$dst),
2143 // Call subroutine from register.
2144 let isCall = 1, neverHasSideEffects = 1,
2145 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2146 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2147 def CALLR : JRInst<(outs), (ins IntRegs:$dst),
2153 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2154 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst),
2155 "jump $dst // TAILCALL", []>;
2157 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2158 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst),
2159 "jump $dst // TAILCALL", []>;
2162 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2163 def TCRETURNR : JInst<(outs), (ins IntRegs:$dst),
2164 "jumpr $dst // TAILCALL", []>;
2166 // Map call instruction.
2167 def : Pat<(call (i32 IntRegs:$dst)),
2168 (CALLR (i32 IntRegs:$dst))>, Requires<[HasV2TOnly]>;
2169 def : Pat<(call tglobaladdr:$dst),
2170 (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
2171 def : Pat<(call texternalsym:$dst),
2172 (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>;
2174 def : Pat<(HexagonTCRet tglobaladdr:$dst),
2175 (TCRETURNtg tglobaladdr:$dst)>;
2176 def : Pat<(HexagonTCRet texternalsym:$dst),
2177 (TCRETURNtext texternalsym:$dst)>;
2178 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
2179 (TCRETURNR (i32 IntRegs:$dst))>;
2181 // Atomic load and store support
2182 // 8 bit atomic load
2183 def : Pat<(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
2184 (i32 (LDub_GP tglobaladdr:$global))>,
2187 def : Pat<(atomic_load_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2188 u16ImmPred:$offset)),
2189 (i32 (LDriub_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2192 def : Pat<(atomic_load_8 ADDRriS11_0:$src1),
2193 (i32 (LDriub ADDRriS11_0:$src1))>;
2195 def : Pat<(atomic_load_8 (add (i32 IntRegs:$src1), s11_0ImmPred:$offset)),
2196 (i32 (LDriub_indexed (i32 IntRegs:$src1), s11_0ImmPred:$offset))>;
2200 // 16 bit atomic load
2201 def : Pat<(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
2202 (i32 (LDuh_GP tglobaladdr:$global))>,
2205 def : Pat<(atomic_load_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2206 u16ImmPred:$offset)),
2207 (i32 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2210 def : Pat<(atomic_load_16 ADDRriS11_1:$src1),
2211 (i32 (LDriuh ADDRriS11_1:$src1))>;
2213 def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)),
2214 (i32 (LDriuh_indexed (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
2218 // 32 bit atomic load
2219 def : Pat<(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
2220 (i32 (LDw_GP tglobaladdr:$global))>,
2223 def : Pat<(atomic_load_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2224 u16ImmPred:$offset)),
2225 (i32 (LDriw_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2228 def : Pat<(atomic_load_32 ADDRriS11_2:$src1),
2229 (i32 (LDriw ADDRriS11_2:$src1))>;
2231 def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),
2232 (i32 (LDriw_indexed (i32 IntRegs:$src1), s11_2ImmPred:$offset))>;
2235 // 64 bit atomic load
2236 def : Pat<(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
2237 (i64 (LDd_GP tglobaladdr:$global))>,
2240 def : Pat<(atomic_load_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2241 u16ImmPred:$offset)),
2242 (i64 (LDrid_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2245 def : Pat<(atomic_load_64 ADDRriS11_3:$src1),
2246 (i64 (LDrid ADDRriS11_3:$src1))>;
2248 def : Pat<(atomic_load_64 (add (i32 IntRegs:$src1), s11_3ImmPred:$offset)),
2249 (i64 (LDrid_indexed (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
2252 // 64 bit atomic store
2253 def : Pat<(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
2254 (i64 DoubleRegs:$src1)),
2255 (STd_GP tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2258 def : Pat<(atomic_store_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2259 u16ImmPred:$offset),
2260 (i64 DoubleRegs:$src1)),
2261 (STrid_GP tglobaladdr:$global, u16ImmPred:$offset,
2262 (i64 DoubleRegs:$src1))>, Requires<[NoV4T]>;
2264 // 8 bit atomic store
2265 def : Pat<(atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
2266 (i32 IntRegs:$src1)),
2267 (STb_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2270 def : Pat<(atomic_store_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2271 u16ImmPred:$offset),
2272 (i32 IntRegs:$src1)),
2273 (STrib_GP tglobaladdr:$global, u16ImmPred:$offset,
2274 (i32 IntRegs:$src1))>, Requires<[NoV4T]>;
2276 def : Pat<(atomic_store_8 ADDRriS11_0:$src2, (i32 IntRegs:$src1)),
2277 (STrib ADDRriS11_0:$src2, (i32 IntRegs:$src1))>;
2279 def : Pat<(atomic_store_8 (add (i32 IntRegs:$src2), s11_0ImmPred:$offset),
2280 (i32 IntRegs:$src1)),
2281 (STrib_indexed (i32 IntRegs:$src2), s11_0ImmPred:$offset,
2282 (i32 IntRegs:$src1))>;
2285 // 16 bit atomic store
2286 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
2287 (i32 IntRegs:$src1)),
2288 (STh_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2291 def : Pat<(atomic_store_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2292 u16ImmPred:$offset),
2293 (i32 IntRegs:$src1)),
2294 (STrih_GP tglobaladdr:$global, u16ImmPred:$offset,
2295 (i32 IntRegs:$src1))>, Requires<[NoV4T]>;
2297 def : Pat<(atomic_store_16 ADDRriS11_1:$src2, (i32 IntRegs:$src1)),
2298 (STrih ADDRriS11_1:$src2, (i32 IntRegs:$src1))>;
2300 def : Pat<(atomic_store_16 (i32 IntRegs:$src1),
2301 (add (i32 IntRegs:$src2), s11_1ImmPred:$offset)),
2302 (STrih_indexed (i32 IntRegs:$src2), s11_1ImmPred:$offset,
2303 (i32 IntRegs:$src1))>;
2306 // 32 bit atomic store
2307 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
2308 (i32 IntRegs:$src1)),
2309 (STw_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2312 def : Pat<(atomic_store_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2313 u16ImmPred:$offset),
2314 (i32 IntRegs:$src1)),
2315 (STriw_GP tglobaladdr:$global, u16ImmPred:$offset,
2316 (i32 IntRegs:$src1))>,
2319 def : Pat<(atomic_store_32 ADDRriS11_2:$src2, (i32 IntRegs:$src1)),
2320 (STriw ADDRriS11_2:$src2, (i32 IntRegs:$src1))>;
2322 def : Pat<(atomic_store_32 (add (i32 IntRegs:$src2), s11_2ImmPred:$offset),
2323 (i32 IntRegs:$src1)),
2324 (STriw_indexed (i32 IntRegs:$src2), s11_2ImmPred:$offset,
2325 (i32 IntRegs:$src1))>;
2330 def : Pat<(atomic_store_64 ADDRriS11_3:$src2, (i64 DoubleRegs:$src1)),
2331 (STrid ADDRriS11_3:$src2, (i64 DoubleRegs:$src1))>;
2333 def : Pat<(atomic_store_64 (add (i32 IntRegs:$src2), s11_3ImmPred:$offset),
2334 (i64 DoubleRegs:$src1)),
2335 (STrid_indexed (i32 IntRegs:$src2), s11_3ImmPred:$offset,
2336 (i64 DoubleRegs:$src1))>;
2338 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
2339 def : Pat <(and (i32 IntRegs:$src1), 65535),
2340 (ZXTH (i32 IntRegs:$src1))>;
2342 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
2343 def : Pat <(and (i32 IntRegs:$src1), 255),
2344 (ZXTB (i32 IntRegs:$src1))>;
2346 // Map Add(p1, true) to p1 = not(p1).
2347 // Add(p1, false) should never be produced,
2348 // if it does, it got to be mapped to NOOP.
2349 def : Pat <(add (i1 PredRegs:$src1), -1),
2350 (NOT_p (i1 PredRegs:$src1))>;
2352 // Map from p0 = setlt(r0, r1) r2 = mux(p0, r3, r4) =>
2353 // p0 = cmp.lt(r0, r1), r0 = mux(p0, r2, r1).
2354 def : Pat <(select (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2355 (i32 IntRegs:$src3),
2356 (i32 IntRegs:$src4)),
2357 (i32 (TFR_condset_rr (CMPLTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2358 (i32 IntRegs:$src4), (i32 IntRegs:$src3)))>,
2359 Requires<[HasV2TOnly]>;
2361 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
2362 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
2363 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
2366 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
2367 // => r0 = TFR_condset_ri(p0, r1, #i)
2368 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
2369 (i32 IntRegs:$src3)),
2370 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
2371 s12ImmPred:$src2))>;
2373 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
2374 // => r0 = TFR_condset_ir(p0, #i, r1)
2375 def : Pat <(select (not PredRegs:$src1), IntRegs:$src2, s12ImmPred:$src3),
2376 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
2377 (i32 IntRegs:$src2)))>;
2379 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
2380 def : Pat <(brcond (not PredRegs:$src1), bb:$offset),
2381 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
2383 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
2384 def : Pat <(and PredRegs:$src1, (not PredRegs:$src2)),
2385 (i1 (AND_pnotp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2387 // Map from store(globaladdress + x) -> memd(#foo + x).
2388 let AddedComplexity = 100 in
2389 def : Pat <(store (i64 DoubleRegs:$src1),
2390 (add (HexagonCONST32_GP tglobaladdr:$global),
2391 u16ImmPred:$offset)),
2392 (STrid_GP tglobaladdr:$global, u16ImmPred:$offset,
2393 (i64 DoubleRegs:$src1))>, Requires<[NoV4T]>;
2395 // Map from store(globaladdress) -> memd(#foo).
2396 let AddedComplexity = 100 in
2397 def : Pat <(store (i64 DoubleRegs:$src1),
2398 (HexagonCONST32_GP tglobaladdr:$global)),
2399 (STd_GP tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2402 // Map from store(globaladdress + x) -> memw(#foo + x).
2403 let AddedComplexity = 100 in
2404 def : Pat <(store (i32 IntRegs:$src1),
2405 (add (HexagonCONST32_GP tglobaladdr:$global),
2406 u16ImmPred:$offset)),
2407 (STriw_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2410 // Map from store(globaladdress) -> memw(#foo + 0).
2411 let AddedComplexity = 100 in
2412 def : Pat <(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2413 (STriw_GP tglobaladdr:$global, 0, (i32 IntRegs:$src1))>;
2415 // Map from store(globaladdress) -> memw(#foo).
2416 let AddedComplexity = 100 in
2417 def : Pat <(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2418 (STriw_GP tglobaladdr:$global, 0, (i32 IntRegs:$src1))>,
2421 // Map from store(globaladdress + x) -> memh(#foo + x).
2422 let AddedComplexity = 100 in
2423 def : Pat <(truncstorei16 (i32 IntRegs:$src1),
2424 (add (HexagonCONST32_GP tglobaladdr:$global),
2425 u16ImmPred:$offset)),
2426 (STrih_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2429 // Map from store(globaladdress) -> memh(#foo).
2430 let AddedComplexity = 100 in
2431 def : Pat <(truncstorei16 (i32 IntRegs:$src1),
2432 (HexagonCONST32_GP tglobaladdr:$global)),
2433 (STh_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2436 // Map from store(globaladdress + x) -> memb(#foo + x).
2437 let AddedComplexity = 100 in
2438 def : Pat <(truncstorei8 (i32 IntRegs:$src1),
2439 (add (HexagonCONST32_GP tglobaladdr:$global),
2440 u16ImmPred:$offset)),
2441 (STrib_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2444 // Map from store(globaladdress) -> memb(#foo).
2445 let AddedComplexity = 100 in
2446 def : Pat <(truncstorei8 (i32 IntRegs:$src1),
2447 (HexagonCONST32_GP tglobaladdr:$global)),
2448 (STb_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2451 // Map from load(globaladdress + x) -> memw(#foo + x).
2452 let AddedComplexity = 100 in
2453 def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global),
2454 u16ImmPred:$offset))),
2455 (i32 (LDriw_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2458 // Map from load(globaladdress) -> memw(#foo).
2459 let AddedComplexity = 100 in
2460 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
2461 (i32 (LDw_GP tglobaladdr:$global))>,
2464 // Map from load(globaladdress + x) -> memd(#foo + x).
2465 let AddedComplexity = 100 in
2466 def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),
2467 u16ImmPred:$offset))),
2468 (i64 (LDrid_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2471 // Map from load(globaladdress) -> memw(#foo + 0).
2472 let AddedComplexity = 100 in
2473 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
2474 (i64 (LDd_GP tglobaladdr:$global))>,
2477 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd.
2478 let AddedComplexity = 100 in
2479 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
2480 (i1 (TFR_PdRs (i32 (LDb_GP tglobaladdr:$global))))>,
2483 // Map from load(globaladdress + x) -> memh(#foo + x).
2484 let AddedComplexity = 100 in
2485 def : Pat <(i32 (extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2486 u16ImmPred:$offset))),
2487 (i32 (LDrih_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2490 // Map from load(globaladdress + x) -> memh(#foo + x).
2491 let AddedComplexity = 100 in
2492 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2493 (i32 (LDrih_GP tglobaladdr:$global, 0))>,
2496 // Map from load(globaladdress + x) -> memuh(#foo + x).
2497 let AddedComplexity = 100 in
2498 def : Pat <(i32 (zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2499 u16ImmPred:$offset))),
2500 (i32 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2503 // Map from load(globaladdress) -> memuh(#foo).
2504 let AddedComplexity = 100 in
2505 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2506 (i32 (LDriuh_GP tglobaladdr:$global, 0))>,
2509 // Map from load(globaladdress) -> memh(#foo).
2510 let AddedComplexity = 100 in
2511 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2512 (i32 (LDh_GP tglobaladdr:$global))>,
2515 // Map from load(globaladdress) -> memuh(#foo).
2516 let AddedComplexity = 100 in
2517 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2518 (i32 (LDuh_GP tglobaladdr:$global))>,
2521 // Map from load(globaladdress + x) -> memb(#foo + x).
2522 let AddedComplexity = 100 in
2523 def : Pat <(i32 (extloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2524 u16ImmPred:$offset))),
2525 (i32 (LDrib_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2528 // Map from load(globaladdress + x) -> memb(#foo + x).
2529 let AddedComplexity = 100 in
2530 def : Pat <(i32 (sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2531 u16ImmPred:$offset))),
2532 (i32 (LDrib_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2535 // Map from load(globaladdress + x) -> memub(#foo + x).
2536 let AddedComplexity = 100 in
2537 def : Pat <(i32 (zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2538 u16ImmPred:$offset))),
2539 (i32 (LDriub_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2542 // Map from load(globaladdress) -> memb(#foo).
2543 let AddedComplexity = 100 in
2544 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2545 (i32 (LDb_GP tglobaladdr:$global))>,
2548 // Map from load(globaladdress) -> memb(#foo).
2549 let AddedComplexity = 100 in
2550 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2551 (i32 (LDb_GP tglobaladdr:$global))>,
2554 // Map from load(globaladdress) -> memub(#foo).
2555 let AddedComplexity = 100 in
2556 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2557 (i32 (LDub_GP tglobaladdr:$global))>,
2560 // When the Interprocedural Global Variable optimizer realizes that a
2561 // certain global variable takes only two constant values, it shrinks the
2562 // global to a boolean. Catch those loads here in the following 3 patterns.
2563 let AddedComplexity = 100 in
2564 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2565 (i32 (LDb_GP tglobaladdr:$global))>,
2568 let AddedComplexity = 100 in
2569 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2570 (i32 (LDb_GP tglobaladdr:$global))>,
2573 let AddedComplexity = 100 in
2574 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2575 (i32 (LDub_GP tglobaladdr:$global))>,
2578 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
2579 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
2580 (i32 (AND_rr (i32 (LDrib ADDRriS11_0:$addr)), (TFRI 0x1)))>;
2582 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
2583 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
2584 (i64 (SXTW (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
2586 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
2587 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
2588 (i64 (SXTW (i32 (SXTH (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2589 subreg_loreg))))))>;
2591 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
2592 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
2593 (i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2594 subreg_loreg))))))>;
2596 // We want to prevent emitting pnot's as much as possible.
2597 // Map brcond with an unsupported setcc to a JMP_cNot.
2598 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2600 (JMP_cNot (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2603 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
2605 (JMP_cNot (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
2607 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
2608 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
2610 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
2611 (JMP_c (i1 PredRegs:$src1), bb:$offset)>;
2613 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
2615 (JMP_cNot (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2), bb:$offset)>;
2617 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2619 (JMP_c (CMPLTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)), bb:$offset)>;
2621 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2623 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
2626 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2628 (JMP_cNot (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2631 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2633 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2636 // Map from a 64-bit select to an emulated 64-bit mux.
2637 // Hexagon does not support 64-bit MUXes; so emulate with combines.
2638 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
2639 (i64 DoubleRegs:$src3)),
2640 (i64 (COMBINE_rr (i32 (MUX_rr (i1 PredRegs:$src1),
2641 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2643 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2645 (i32 (MUX_rr (i1 PredRegs:$src1),
2646 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2648 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2649 subreg_loreg))))))>;
2651 // Map from a 1-bit select to logical ops.
2652 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
2653 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
2654 (i1 PredRegs:$src3)),
2655 (OR_pp (AND_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
2656 (AND_pp (NOT_p (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
2658 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
2659 def : Pat<(i1 (load ADDRriS11_2:$addr)),
2660 (i1 (TFR_PdRs (i32 (LDrib ADDRriS11_2:$addr))))>;
2662 // Map for truncating from 64 immediates to 32 bit immediates.
2663 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
2664 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
2666 // Map for truncating from i64 immediates to i1 bit immediates.
2667 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
2668 (i1 (TFR_PdRs (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2671 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
2672 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2673 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2676 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
2677 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2678 (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2680 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
2681 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2682 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2685 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
2686 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2687 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2690 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
2691 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2692 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2694 let AddedComplexity = 100 in
2695 // Map from i1 = constant<-1>; memw(CONST32(#foo)) = i1 -> r0 = 1;
2697 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
2698 (STb_GP tglobaladdr:$global, (TFRI 1))>,
2701 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
2702 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2703 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2705 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
2706 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
2707 (STrib ADDRriS11_2:$addr, (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0)) )>;
2709 // Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs).
2710 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
2711 // Better way to do this?
2712 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
2713 (i64 (SXTW (i32 IntRegs:$src1)))>;
2715 // Map cmple -> cmpgt.
2716 // rs <= rt -> !(rs > rt).
2717 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ImmPred:$src2)),
2718 (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), s10ImmPred:$src2)))>;
2720 // rs <= rt -> !(rs > rt).
2721 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2722 (i1 (NOT_p (CMPGTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2724 // Rss <= Rtt -> !(Rss > Rtt).
2725 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2726 (i1 (NOT_p (CMPGT64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2728 // Map cmpne -> cmpeq.
2729 // Hexagon_TODO: We should improve on this.
2730 // rs != rt -> !(rs == rt).
2731 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
2732 (i1 (NOT_p(i1 (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2))))>;
2734 // Map cmpne(Rs) -> !cmpeqe(Rs).
2735 // rs != rt -> !(rs == rt).
2736 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2737 (i1 (NOT_p (i1 (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
2739 // Convert setne back to xor for hexagon since we compute w/ pred registers.
2740 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
2741 (i1 (XOR_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2743 // Map cmpne(Rss) -> !cmpew(Rss).
2744 // rs != rt -> !(rs == rt).
2745 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2746 (i1 (NOT_p (i1 (CMPEHexagon4rr (i64 DoubleRegs:$src1),
2747 (i64 DoubleRegs:$src2)))))>;
2749 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
2750 // rs >= rt -> !(rt > rs).
2751 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2752 (i1 (NOT_p (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
2754 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ImmPred:$src2)),
2755 (i1 (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2))>;
2757 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
2758 // rss >= rtt -> !(rtt > rss).
2759 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2760 (i1 (NOT_p (i1 (CMPGT64rr (i64 DoubleRegs:$src2),
2761 (i64 DoubleRegs:$src1)))))>;
2763 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
2764 // rs < rt -> !(rs >= rt).
2765 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
2766 (i1 (NOT_p (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2)))>;
2768 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
2769 // rs < rt -> rt > rs.
2770 // We can let assembler map it, or we can do in the compiler itself.
2771 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2772 (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2774 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
2775 // rss < rtt -> (rtt > rss).
2776 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2777 (i1 (CMPGT64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2779 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
2780 // rs < rt -> rt > rs.
2781 // We can let assembler map it, or we can do in the compiler itself.
2782 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2783 (i1 (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2785 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
2786 // rs < rt -> rt > rs.
2787 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2788 (i1 (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2790 // Generate cmpgeu(Rs, #u8)
2791 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ImmPred:$src2)),
2792 (i1 (CMPGEUri (i32 IntRegs:$src1), u8ImmPred:$src2))>;
2794 // Generate cmpgtu(Rs, #u9)
2795 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ImmPred:$src2)),
2796 (i1 (CMPGTUri (i32 IntRegs:$src1), u9ImmPred:$src2))>;
2798 // Map from Rs >= Rt -> !(Rt > Rs).
2799 // rs >= rt -> !(rt > rs).
2800 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2801 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
2803 // Map from Rs >= Rt -> !(Rt > Rs).
2804 // rs >= rt -> !(rt > rs).
2805 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2806 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
2808 // Map from cmpleu(Rs, Rs) -> !cmpgtu(Rs, Rs).
2809 // Map from (Rs <= Rt) -> !(Rs > Rt).
2810 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2811 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2813 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
2814 // Map from (Rs <= Rt) -> !(Rs > Rt).
2815 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2816 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2820 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
2821 (i32 (MUX_ii (i1 PredRegs:$src1), -1, 0))>;
2824 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
2825 (i64 (COMBINE_rr (TFRI -1), (MUX_ii (i1 PredRegs:$src1), -1, 0)))>;
2827 // Convert sign-extended load back to load and sign extend.
2829 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
2830 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2832 // Convert any-extended load back to load and sign extend.
2834 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
2835 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2837 // Convert sign-extended load back to load and sign extend.
2839 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
2840 (i64 (SXTW (LDrih ADDRriS11_1:$src1)))>;
2842 // Convert sign-extended load back to load and sign extend.
2844 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
2845 (i64 (SXTW (LDriw ADDRriS11_2:$src1)))>;
2850 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2851 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2854 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
2855 (i64 (COMBINE_rr (TFRI 0), (MUX_ii (i1 PredRegs:$src1), 1, 0)))>;
2858 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
2859 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>;
2862 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
2863 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>;
2866 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
2867 (i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>;
2870 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
2871 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>;
2873 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
2874 (i32 (LDriw ADDRriS11_0:$src1))>;
2876 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2877 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2878 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2880 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2881 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
2882 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2884 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
2885 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
2886 (i64 (SXTW (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))))>;
2889 // Any extended 64-bit load.
2890 // anyext i32 -> i64
2891 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
2892 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>;
2894 // anyext i16 -> i64.
2895 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
2896 (i64 (COMBINE_rr (TFRI 0), (LDrih ADDRriS11_2:$src1)))>;
2898 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
2899 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
2900 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>;
2902 // Multiply 64-bit unsigned and use upper result.
2903 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2918 (COMBINE_rr (TFRI 0),
2924 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2926 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2927 subreg_loreg)))), 32)),
2929 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2930 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2931 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2932 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2933 32)), subreg_loreg)))),
2934 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2935 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2937 // Multiply 64-bit signed and use upper result.
2938 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2942 (COMBINE_rr (TFRI 0),
2952 (COMBINE_rr (TFRI 0),
2958 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2960 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2961 subreg_loreg)))), 32)),
2963 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2964 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2965 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2966 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2967 32)), subreg_loreg)))),
2968 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2969 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2971 // Hexagon specific ISD nodes.
2972 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
2973 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
2974 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
2975 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
2976 SDTHexagonADJDYNALLOC>;
2977 // Needed to tag these instructions for stack layout.
2978 let usesCustomInserter = 1 in
2979 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
2981 "$dst = add($src1, #$src2)",
2982 [(set (i32 IntRegs:$dst),
2983 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
2984 s16ImmPred:$src2))]>;
2986 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
2987 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
2988 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
2990 [(set (i32 IntRegs:$dst),
2991 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
2993 let AddedComplexity = 100 in
2994 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
2995 (COPY (i32 IntRegs:$src1))>;
2997 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2998 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
3000 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
3001 def BR_JT : JRInst<(outs), (ins IntRegs:$src),
3003 [(HexagonBR_JT (i32 IntRegs:$src))]>;
3005 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
3007 def : Pat<(HexagonWrapperJT tjumptable:$dst),
3008 (i32 (CONST32_set_jt tjumptable:$dst))>;
3012 // Multi-class for logical operators :
3013 // Shift by immediate/register and accumulate/logical
3014 multiclass xtype_imm<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
3015 def _ri : SInst_acc<(outs IntRegs:$dst),
3016 (ins IntRegs:$src1, IntRegs:$src2, u5Imm:$src3),
3017 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
3018 [(set (i32 IntRegs:$dst),
3019 (OpNode2 (i32 IntRegs:$src1),
3020 (OpNode1 (i32 IntRegs:$src2),
3021 u5ImmPred:$src3)))],
3024 def d_ri : SInst_acc<(outs DoubleRegs:$dst),
3025 (ins DoubleRegs:$src1, DoubleRegs:$src2, u6Imm:$src3),
3026 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
3027 [(set (i64 DoubleRegs:$dst), (OpNode2 (i64 DoubleRegs:$src1),
3028 (OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
3032 // Multi-class for logical operators :
3033 // Shift by register and accumulate/logical (32/64 bits)
3034 multiclass xtype_reg<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
3035 def _rr : SInst_acc<(outs IntRegs:$dst),
3036 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
3037 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
3038 [(set (i32 IntRegs:$dst),
3039 (OpNode2 (i32 IntRegs:$src1),
3040 (OpNode1 (i32 IntRegs:$src2),
3041 (i32 IntRegs:$src3))))],
3044 def d_rr : SInst_acc<(outs DoubleRegs:$dst),
3045 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3046 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
3047 [(set (i64 DoubleRegs:$dst),
3048 (OpNode2 (i64 DoubleRegs:$src1),
3049 (OpNode1 (i64 DoubleRegs:$src2),
3050 (i32 IntRegs:$src3))))],
3055 multiclass basic_xtype_imm<string OpcStr, SDNode OpNode> {
3056 let AddedComplexity = 100 in
3057 defm _ADD : xtype_imm< !strconcat("+= ", OpcStr), OpNode, add>;
3058 defm _SUB : xtype_imm< !strconcat("-= ", OpcStr), OpNode, sub>;
3059 defm _AND : xtype_imm< !strconcat("&= ", OpcStr), OpNode, and>;
3060 defm _OR : xtype_imm< !strconcat("|= ", OpcStr), OpNode, or>;
3063 multiclass basic_xtype_reg<string OpcStr, SDNode OpNode> {
3064 let AddedComplexity = 100 in
3065 defm _ADD : xtype_reg< !strconcat("+= ", OpcStr), OpNode, add>;
3066 defm _SUB : xtype_reg< !strconcat("-= ", OpcStr), OpNode, sub>;
3067 defm _AND : xtype_reg< !strconcat("&= ", OpcStr), OpNode, and>;
3068 defm _OR : xtype_reg< !strconcat("|= ", OpcStr), OpNode, or>;
3071 multiclass xtype_xor_imm<string OpcStr, SDNode OpNode> {
3072 let AddedComplexity = 100 in
3073 defm _XOR : xtype_imm< !strconcat("^= ", OpcStr), OpNode, xor>;
3076 defm ASL : basic_xtype_imm<"asl", shl>, basic_xtype_reg<"asl", shl>,
3077 xtype_xor_imm<"asl", shl>;
3079 defm LSR : basic_xtype_imm<"lsr", srl>, basic_xtype_reg<"lsr", srl>,
3080 xtype_xor_imm<"lsr", srl>;
3082 defm ASR : basic_xtype_imm<"asr", sra>, basic_xtype_reg<"asr", sra>;
3083 defm LSL : basic_xtype_reg<"lsl", shl>;
3085 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
3086 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
3087 (i32 (MPYI_rin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
3089 //===----------------------------------------------------------------------===//
3090 // V3 Instructions +
3091 //===----------------------------------------------------------------------===//
3093 include "HexagonInstrInfoV3.td"
3095 //===----------------------------------------------------------------------===//
3096 // V3 Instructions -
3097 //===----------------------------------------------------------------------===//
3099 //===----------------------------------------------------------------------===//
3100 // V4 Instructions +
3101 //===----------------------------------------------------------------------===//
3103 include "HexagonInstrInfoV4.td"
3105 //===----------------------------------------------------------------------===//
3106 // V4 Instructions -
3107 //===----------------------------------------------------------------------===//
3109 //===----------------------------------------------------------------------===//
3110 // V5 Instructions +
3111 //===----------------------------------------------------------------------===//
3113 include "HexagonInstrInfoV5.td"
3115 //===----------------------------------------------------------------------===//
3116 // V5 Instructions -
3117 //===----------------------------------------------------------------------===//