1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonImmediates.td"
17 //===----------------------------------------------------------------------===//
18 // Hexagon Instruction Predicate Definitions.
19 //===----------------------------------------------------------------------===//
20 def HasV2T : Predicate<"Subtarget.hasV2TOps()">;
21 def HasV2TOnly : Predicate<"Subtarget.hasV2TOpsOnly()">;
22 def NoV2T : Predicate<"!Subtarget.hasV2TOps()">;
23 def HasV3T : Predicate<"Subtarget.hasV3TOps()">;
24 def HasV3TOnly : Predicate<"Subtarget.hasV3TOpsOnly()">;
25 def NoV3T : Predicate<"!Subtarget.hasV3TOps()">;
26 def HasV4T : Predicate<"Subtarget.hasV4TOps()">;
27 def NoV4T : Predicate<"!Subtarget.hasV4TOps()">;
28 def HasV5T : Predicate<"Subtarget.hasV5TOps()">;
29 def NoV5T : Predicate<"!Subtarget.hasV5TOps()">;
30 def UseMEMOP : Predicate<"Subtarget.useMemOps()">;
31 def IEEERndNearV5T : Predicate<"Subtarget.modeIEEERndNear()">;
34 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
35 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>;
36 def ADDRriS11_0 : ComplexPattern<i32, 2, "SelectADDRriS11_0", [frameindex], []>;
37 def ADDRriS11_1 : ComplexPattern<i32, 2, "SelectADDRriS11_1", [frameindex], []>;
38 def ADDRriS11_2 : ComplexPattern<i32, 2, "SelectADDRriS11_2", [frameindex], []>;
39 def ADDRriS11_3 : ComplexPattern<i32, 2, "SelectADDRriS11_3", [frameindex], []>;
40 def ADDRriU6_0 : ComplexPattern<i32, 2, "SelectADDRriU6_0", [frameindex], []>;
41 def ADDRriU6_1 : ComplexPattern<i32, 2, "SelectADDRriU6_1", [frameindex], []>;
42 def ADDRriU6_2 : ComplexPattern<i32, 2, "SelectADDRriU6_2", [frameindex], []>;
45 def MEMrr : Operand<i32> {
46 let PrintMethod = "printMEMrrOperand";
47 let MIOperandInfo = (ops IntRegs, IntRegs);
51 def MEMri : Operand<i32> {
52 let PrintMethod = "printMEMriOperand";
53 let MIOperandInfo = (ops IntRegs, IntRegs);
56 def MEMri_s11_2 : Operand<i32>,
57 ComplexPattern<i32, 2, "SelectMEMriS11_2", []> {
58 let PrintMethod = "printMEMriOperand";
59 let MIOperandInfo = (ops IntRegs, s11Imm);
62 def FrameIndex : Operand<i32> {
63 let PrintMethod = "printFrameIndexOperand";
64 let MIOperandInfo = (ops IntRegs, s11Imm);
67 let PrintMethod = "printGlobalOperand" in
68 def globaladdress : Operand<i32>;
70 let PrintMethod = "printJumpTable" in
71 def jumptablebase : Operand<i32>;
73 def brtarget : Operand<OtherVT>;
74 def calltarget : Operand<i32>;
76 def bblabel : Operand<i32>;
77 def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf , [], "BasicBlockSDNode">;
79 def symbolHi32 : Operand<i32> {
80 let PrintMethod = "printSymbolHi";
82 def symbolLo32 : Operand<i32> {
83 let PrintMethod = "printSymbolLo";
86 // Multi-class for logical operators.
87 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
88 def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
89 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
90 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),
92 def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
93 !strconcat("$dst = ", !strconcat(OpcStr, "(#$b, $c)")),
94 [(set (i32 IntRegs:$dst), (OpNode s10Imm:$b,
98 // Multi-class for compare ops.
99 let isCompare = 1 in {
100 multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
101 def rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
102 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
103 [(set (i1 PredRegs:$dst),
104 (OpNode (i64 DoubleRegs:$b), (i64 DoubleRegs:$c)))]>;
106 multiclass CMP32_rr<string OpcStr, PatFrag OpNode> {
107 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
108 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
109 [(set (i1 PredRegs:$dst),
110 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
113 multiclass CMP32_rr_ri_s10<string OpcStr, PatFrag OpNode> {
114 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
115 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
116 [(set (i1 PredRegs:$dst),
117 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
118 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Imm:$c),
119 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
120 [(set (i1 PredRegs:$dst),
121 (OpNode (i32 IntRegs:$b), s10ImmPred:$c))]>;
124 multiclass CMP32_rr_ri_u9<string OpcStr, PatFrag OpNode> {
125 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
126 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
127 [(set (i1 PredRegs:$dst),
128 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
129 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Imm:$c),
130 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
131 [(set (i1 PredRegs:$dst),
132 (OpNode (i32 IntRegs:$b), u9ImmPred:$c))]>;
135 multiclass CMP32_ri_u8<string OpcStr, PatFrag OpNode> {
136 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u8Imm:$c),
137 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
138 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
142 multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
143 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Imm:$c),
144 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
145 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
150 //===----------------------------------------------------------------------===//
152 //===----------------------------------------------------------------------===//
154 let isCommutable = 1, isPredicable = 1 in
155 def ADD_rr : ALU32_rr<(outs IntRegs:$dst),
156 (ins IntRegs:$src1, IntRegs:$src2),
157 "$dst = add($src1, $src2)",
158 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
159 (i32 IntRegs:$src2)))]>;
161 let isPredicable = 1 in
162 def ADD_ri : ALU32_ri<(outs IntRegs:$dst),
163 (ins IntRegs:$src1, s16Imm:$src2),
164 "$dst = add($src1, #$src2)",
165 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
166 s16ImmPred:$src2))]>;
168 // Logical operations.
169 let isPredicable = 1 in
170 def XOR_rr : ALU32_rr<(outs IntRegs:$dst),
171 (ins IntRegs:$src1, IntRegs:$src2),
172 "$dst = xor($src1, $src2)",
173 [(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
174 (i32 IntRegs:$src2)))]>;
176 let isCommutable = 1, isPredicable = 1 in
177 def AND_rr : ALU32_rr<(outs IntRegs:$dst),
178 (ins IntRegs:$src1, IntRegs:$src2),
179 "$dst = and($src1, $src2)",
180 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
181 (i32 IntRegs:$src2)))]>;
183 def OR_ri : ALU32_ri<(outs IntRegs:$dst),
184 (ins IntRegs:$src1, s10Imm:$src2),
185 "$dst = or($src1, #$src2)",
186 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
187 s10ImmPred:$src2))]>;
189 def NOT_rr : ALU32_rr<(outs IntRegs:$dst),
192 [(set (i32 IntRegs:$dst), (not (i32 IntRegs:$src1)))]>;
194 def AND_ri : ALU32_ri<(outs IntRegs:$dst),
195 (ins IntRegs:$src1, s10Imm:$src2),
196 "$dst = and($src1, #$src2)",
197 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
198 s10ImmPred:$src2))]>;
200 let isCommutable = 1, isPredicable = 1 in
201 def OR_rr : ALU32_rr<(outs IntRegs:$dst),
202 (ins IntRegs:$src1, IntRegs:$src2),
203 "$dst = or($src1, $src2)",
204 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
205 (i32 IntRegs:$src2)))]>;
208 def NEG : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
210 [(set (i32 IntRegs:$dst), (ineg (i32 IntRegs:$src1)))]>;
212 let neverHasSideEffects = 1 in
213 def NOP : ALU32_rr<(outs), (ins),
218 let isPredicable = 1 in
219 def SUB_rr : ALU32_rr<(outs IntRegs:$dst),
220 (ins IntRegs:$src1, IntRegs:$src2),
221 "$dst = sub($src1, $src2)",
222 [(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
223 (i32 IntRegs:$src2)))]>;
225 // Rd32=sub(#s10,Rs32)
226 def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
227 (ins s10Imm:$src1, IntRegs:$src2),
228 "$dst = sub(#$src1, $src2)",
229 [(set IntRegs:$dst, (sub s10ImmPred:$src1, IntRegs:$src2))]>;
231 // Transfer immediate.
232 let isMoveImm = 1, isReMaterializable = 1, isPredicable = 1 in
233 def TFRI : ALU32_ri<(outs IntRegs:$dst), (ins s16Imm:$src1),
235 [(set (i32 IntRegs:$dst), s16ImmPred:$src1)]>;
237 // Transfer register.
238 let neverHasSideEffects = 1, isPredicable = 1 in
239 def TFR : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1),
243 let neverHasSideEffects = 1, isPredicable = 1 in
244 def TFR64 : ALU32_ri<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
248 // Transfer control register.
249 let neverHasSideEffects = 1 in
250 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
253 //===----------------------------------------------------------------------===//
255 //===----------------------------------------------------------------------===//
258 //===----------------------------------------------------------------------===//
260 //===----------------------------------------------------------------------===//
263 let isPredicable = 1, neverHasSideEffects = 1 in
264 def COMBINE_rr : ALU32_rr<(outs DoubleRegs:$dst),
265 (ins IntRegs:$src1, IntRegs:$src2),
266 "$dst = combine($src1, $src2)",
269 let neverHasSideEffects = 1 in
270 def COMBINE_ii : ALU32_ii<(outs DoubleRegs:$dst),
271 (ins s8Imm:$src1, s8Imm:$src2),
272 "$dst = combine(#$src1, #$src2)",
276 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
279 "$dst = vmux($src1, $src2, $src3)",
282 def MUX_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
283 IntRegs:$src2, IntRegs:$src3),
284 "$dst = mux($src1, $src2, $src3)",
285 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
287 (i32 IntRegs:$src3))))]>;
289 def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Imm:$src2,
291 "$dst = mux($src1, #$src2, $src3)",
292 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
294 (i32 IntRegs:$src3))))]>;
296 def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
298 "$dst = mux($src1, $src2, #$src3)",
299 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
301 s8ImmPred:$src3)))]>;
303 def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Imm:$src2,
305 "$dst = mux($src1, #$src2, #$src3)",
306 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
308 s8ImmPred:$src3)))]>;
311 let isPredicable = 1 in
312 def ASLH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
313 "$dst = aslh($src1)",
314 [(set (i32 IntRegs:$dst), (shl 16, (i32 IntRegs:$src1)))]>;
316 let isPredicable = 1 in
317 def ASRH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
318 "$dst = asrh($src1)",
319 [(set (i32 IntRegs:$dst), (sra 16, (i32 IntRegs:$src1)))]>;
322 let isPredicable = 1 in
323 def SXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
324 "$dst = sxtb($src1)",
325 [(set (i32 IntRegs:$dst), (sext_inreg (i32 IntRegs:$src1), i8))]>;
327 let isPredicable = 1 in
328 def SXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
329 "$dst = sxth($src1)",
330 [(set (i32 IntRegs:$dst), (sext_inreg (i32 IntRegs:$src1), i16))]>;
333 let isPredicable = 1, neverHasSideEffects = 1 in
334 def ZXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
335 "$dst = zxtb($src1)",
338 let isPredicable = 1, neverHasSideEffects = 1 in
339 def ZXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
340 "$dst = zxth($src1)",
342 //===----------------------------------------------------------------------===//
344 //===----------------------------------------------------------------------===//
347 //===----------------------------------------------------------------------===//
349 //===----------------------------------------------------------------------===//
352 let neverHasSideEffects = 1, isPredicated = 1 in
353 def ADD_ri_cPt : ALU32_ri<(outs IntRegs:$dst),
354 (ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
355 "if ($src1) $dst = add($src2, #$src3)",
358 let neverHasSideEffects = 1, isPredicated = 1 in
359 def ADD_ri_cNotPt : ALU32_ri<(outs IntRegs:$dst),
360 (ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
361 "if (!$src1) $dst = add($src2, #$src3)",
364 let neverHasSideEffects = 1, isPredicated = 1 in
365 def ADD_ri_cdnPt : ALU32_ri<(outs IntRegs:$dst),
366 (ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
367 "if ($src1.new) $dst = add($src2, #$src3)",
370 let neverHasSideEffects = 1, isPredicated = 1 in
371 def ADD_ri_cdnNotPt : ALU32_ri<(outs IntRegs:$dst),
372 (ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
373 "if (!$src1.new) $dst = add($src2, #$src3)",
376 let neverHasSideEffects = 1, isPredicated = 1 in
377 def ADD_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
378 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
379 "if ($src1) $dst = add($src2, $src3)",
382 let neverHasSideEffects = 1, isPredicated = 1 in
383 def ADD_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
384 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
385 "if (!$src1) $dst = add($src2, $src3)",
388 let neverHasSideEffects = 1, isPredicated = 1 in
389 def ADD_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
390 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
391 "if ($src1.new) $dst = add($src2, $src3)",
394 let neverHasSideEffects = 1, isPredicated = 1 in
395 def ADD_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
396 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
397 "if (!$src1.new) $dst = add($src2, $src3)",
401 // Conditional combine.
403 let neverHasSideEffects = 1, isPredicated = 1 in
404 def COMBINE_rr_cPt : ALU32_rr<(outs DoubleRegs:$dst),
405 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
406 "if ($src1) $dst = combine($src2, $src3)",
409 let neverHasSideEffects = 1, isPredicated = 1 in
410 def COMBINE_rr_cNotPt : ALU32_rr<(outs DoubleRegs:$dst),
411 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
412 "if (!$src1) $dst = combine($src2, $src3)",
415 let neverHasSideEffects = 1, isPredicated = 1 in
416 def COMBINE_rr_cdnPt : ALU32_rr<(outs DoubleRegs:$dst),
417 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
418 "if ($src1.new) $dst = combine($src2, $src3)",
421 let neverHasSideEffects = 1, isPredicated = 1 in
422 def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst),
423 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
424 "if (!$src1.new) $dst = combine($src2, $src3)",
427 // Conditional logical operations.
429 let isPredicated = 1 in
430 def XOR_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
431 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
432 "if ($src1) $dst = xor($src2, $src3)",
435 let isPredicated = 1 in
436 def XOR_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
437 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
438 "if (!$src1) $dst = xor($src2, $src3)",
441 let isPredicated = 1 in
442 def XOR_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
443 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
444 "if ($src1.new) $dst = xor($src2, $src3)",
447 let isPredicated = 1 in
448 def XOR_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
449 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
450 "if (!$src1.new) $dst = xor($src2, $src3)",
453 let isPredicated = 1 in
454 def AND_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
455 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
456 "if ($src1) $dst = and($src2, $src3)",
459 let isPredicated = 1 in
460 def AND_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
461 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
462 "if (!$src1) $dst = and($src2, $src3)",
465 let isPredicated = 1 in
466 def AND_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
467 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
468 "if ($src1.new) $dst = and($src2, $src3)",
471 let isPredicated = 1 in
472 def AND_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
473 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
474 "if (!$src1.new) $dst = and($src2, $src3)",
477 let isPredicated = 1 in
478 def OR_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
479 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
480 "if ($src1) $dst = or($src2, $src3)",
483 let isPredicated = 1 in
484 def OR_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
485 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
486 "if (!$src1) $dst = or($src2, $src3)",
489 let isPredicated = 1 in
490 def OR_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
491 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
492 "if ($src1.new) $dst = or($src2, $src3)",
495 let isPredicated = 1 in
496 def OR_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
497 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
498 "if (!$src1.new) $dst = or($src2, $src3)",
502 // Conditional subtract.
504 let isPredicated = 1 in
505 def SUB_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
506 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
507 "if ($src1) $dst = sub($src2, $src3)",
510 let isPredicated = 1 in
511 def SUB_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
512 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
513 "if (!$src1) $dst = sub($src2, $src3)",
516 let isPredicated = 1 in
517 def SUB_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
518 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
519 "if ($src1.new) $dst = sub($src2, $src3)",
522 let isPredicated = 1 in
523 def SUB_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
524 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
525 "if (!$src1.new) $dst = sub($src2, $src3)",
529 // Conditional transfer.
530 let neverHasSideEffects = 1, isPredicated = 1 in
531 def TFR_cPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2),
532 "if ($src1) $dst = $src2",
535 let neverHasSideEffects = 1, isPredicated = 1 in
536 def TFR_cNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
538 "if (!$src1) $dst = $src2",
541 let neverHasSideEffects = 1, isPredicated = 1 in
542 def TFR64_cPt : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
544 "if ($src1) $dst = $src2",
547 let neverHasSideEffects = 1, isPredicated = 1 in
548 def TFR64_cNotPt : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
550 "if (!$src1) $dst = $src2",
553 let neverHasSideEffects = 1, isPredicated = 1 in
554 def TFRI_cPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, s12Imm:$src2),
555 "if ($src1) $dst = #$src2",
558 let neverHasSideEffects = 1, isPredicated = 1 in
559 def TFRI_cNotPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
561 "if (!$src1) $dst = #$src2",
564 let neverHasSideEffects = 1, isPredicated = 1 in
565 def TFR_cdnPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
567 "if ($src1.new) $dst = $src2",
570 let neverHasSideEffects = 1, isPredicated = 1 in
571 def TFR_cdnNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
573 "if (!$src1.new) $dst = $src2",
576 let neverHasSideEffects = 1, isPredicated = 1 in
577 def TFRI_cdnPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
579 "if ($src1.new) $dst = #$src2",
582 let neverHasSideEffects = 1, isPredicated = 1 in
583 def TFRI_cdnNotPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
585 "if (!$src1.new) $dst = #$src2",
589 defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", setugt>;
590 defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", setgt>;
591 defm CMPLT : CMP32_rr<"cmp.lt", setlt>;
592 defm CMPLTU : CMP32_rr<"cmp.ltu", setult>;
593 defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", seteq>;
594 defm CMPGE : CMP32_ri_s8<"cmp.ge", setge>;
595 defm CMPGEU : CMP32_ri_u8<"cmp.geu", setuge>;
596 //===----------------------------------------------------------------------===//
598 //===----------------------------------------------------------------------===//
601 //===----------------------------------------------------------------------===//
603 //===----------------------------------------------------------------------===//
605 def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
607 "$dst = add($src1, $src2)",
608 [(set (i64 DoubleRegs:$dst), (add (i64 DoubleRegs:$src1),
609 (i64 DoubleRegs:$src2)))]>;
614 defm CMPEHexagon4 : CMP64_rr<"cmp.eq", seteq>;
615 defm CMPGT64 : CMP64_rr<"cmp.gt", setgt>;
616 defm CMPGTU64 : CMP64_rr<"cmp.gtu", setugt>;
618 // Logical operations.
619 def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
621 "$dst = and($src1, $src2)",
622 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
623 (i64 DoubleRegs:$src2)))]>;
625 def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
627 "$dst = or($src1, $src2)",
628 [(set (i64 DoubleRegs:$dst), (or (i64 DoubleRegs:$src1),
629 (i64 DoubleRegs:$src2)))]>;
631 def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
633 "$dst = xor($src1, $src2)",
634 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
635 (i64 DoubleRegs:$src2)))]>;
638 def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
639 "$dst = max($src2, $src1)",
640 [(set (i32 IntRegs:$dst),
641 (i32 (select (i1 (setlt (i32 IntRegs:$src2),
642 (i32 IntRegs:$src1))),
643 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
645 def MAXUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
646 "$dst = maxu($src2, $src1)",
647 [(set (i32 IntRegs:$dst),
648 (i32 (select (i1 (setult (i32 IntRegs:$src2),
649 (i32 IntRegs:$src1))),
650 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
652 def MAXd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
654 "$dst = max($src2, $src1)",
655 [(set (i64 DoubleRegs:$dst),
656 (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
657 (i64 DoubleRegs:$src1))),
658 (i64 DoubleRegs:$src1),
659 (i64 DoubleRegs:$src2))))]>;
661 def MAXUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
663 "$dst = maxu($src2, $src1)",
664 [(set (i64 DoubleRegs:$dst),
665 (i64 (select (i1 (setult (i64 DoubleRegs:$src2),
666 (i64 DoubleRegs:$src1))),
667 (i64 DoubleRegs:$src1),
668 (i64 DoubleRegs:$src2))))]>;
671 def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
672 "$dst = min($src2, $src1)",
673 [(set (i32 IntRegs:$dst),
674 (i32 (select (i1 (setgt (i32 IntRegs:$src2),
675 (i32 IntRegs:$src1))),
676 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
678 def MINUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
679 "$dst = minu($src2, $src1)",
680 [(set (i32 IntRegs:$dst),
681 (i32 (select (i1 (setugt (i32 IntRegs:$src2),
682 (i32 IntRegs:$src1))),
683 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
685 def MINd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
687 "$dst = min($src2, $src1)",
688 [(set (i64 DoubleRegs:$dst),
689 (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
690 (i64 DoubleRegs:$src1))),
691 (i64 DoubleRegs:$src1),
692 (i64 DoubleRegs:$src2))))]>;
694 def MINUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
696 "$dst = minu($src2, $src1)",
697 [(set (i64 DoubleRegs:$dst),
698 (i64 (select (i1 (setugt (i64 DoubleRegs:$src2),
699 (i64 DoubleRegs:$src1))),
700 (i64 DoubleRegs:$src1),
701 (i64 DoubleRegs:$src2))))]>;
704 def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
706 "$dst = sub($src1, $src2)",
707 [(set (i64 DoubleRegs:$dst), (sub (i64 DoubleRegs:$src1),
708 (i64 DoubleRegs:$src2)))]>;
710 // Subtract halfword.
712 // Transfer register.
713 let neverHasSideEffects = 1 in
714 def TFR_64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
717 //===----------------------------------------------------------------------===//
719 //===----------------------------------------------------------------------===//
721 //===----------------------------------------------------------------------===//
723 //===----------------------------------------------------------------------===//
725 //===----------------------------------------------------------------------===//
727 //===----------------------------------------------------------------------===//
729 //===----------------------------------------------------------------------===//
731 //===----------------------------------------------------------------------===//
733 //===----------------------------------------------------------------------===//
735 //===----------------------------------------------------------------------===//
737 //===----------------------------------------------------------------------===//
739 //===----------------------------------------------------------------------===//
740 // Logical reductions on predicates.
742 // Looping instructions.
744 // Pipelined looping instructions.
746 // Logical operations on predicates.
747 def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
748 "$dst = and($src1, $src2)",
749 [(set (i1 PredRegs:$dst), (and (i1 PredRegs:$src1),
750 (i1 PredRegs:$src2)))]>;
752 let neverHasSideEffects = 1 in
753 def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
755 "$dst = and($src1, !$src2)",
758 def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
759 "$dst = any8($src1)",
762 def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
763 "$dst = all8($src1)",
766 def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
768 "$dst = vitpack($src1, $src2)",
771 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
774 "$dst = valignb($src1, $src2, $src3)",
777 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
780 "$dst = vspliceb($src1, $src2, $src3)",
783 def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
784 "$dst = mask($src1)",
787 def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
789 [(set (i1 PredRegs:$dst), (not (i1 PredRegs:$src1)))]>;
791 def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
792 "$dst = or($src1, $src2)",
793 [(set (i1 PredRegs:$dst), (or (i1 PredRegs:$src1),
794 (i1 PredRegs:$src2)))]>;
796 def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
797 "$dst = xor($src1, $src2)",
798 [(set (i1 PredRegs:$dst), (xor (i1 PredRegs:$src1),
799 (i1 PredRegs:$src2)))]>;
802 // User control register transfer.
803 //===----------------------------------------------------------------------===//
805 //===----------------------------------------------------------------------===//
808 //===----------------------------------------------------------------------===//
810 //===----------------------------------------------------------------------===//
812 let isBranch = 1, isTerminator=1, isBarrier = 1, isPredicable = 1 in {
813 def JMP : JInst< (outs),
814 (ins brtarget:$offset),
820 let isBranch = 1, isTerminator=1, Defs = [PC],
821 isPredicated = 1 in {
822 def JMP_c : JInst< (outs),
823 (ins PredRegs:$src, brtarget:$offset),
824 "if ($src) jump $offset",
825 [(brcond (i1 PredRegs:$src), bb:$offset)]>;
829 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
830 isPredicated = 1 in {
831 def JMP_cNot : JInst< (outs),
832 (ins PredRegs:$src, brtarget:$offset),
833 "if (!$src) jump $offset",
837 let isTerminator = 1, isBranch = 1, neverHasSideEffects = 1, Defs = [PC],
838 isPredicated = 1 in {
839 def BRCOND : JInst < (outs), (ins PredRegs:$pred, brtarget:$dst),
840 "if ($pred) jump $dst",
844 // Jump to address conditioned on new predicate.
846 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
847 isPredicated = 1 in {
848 def JMP_cdnPt : JInst< (outs),
849 (ins PredRegs:$src, brtarget:$offset),
850 "if ($src.new) jump:t $offset",
855 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
856 isPredicated = 1 in {
857 def JMP_cdnNotPt : JInst< (outs),
858 (ins PredRegs:$src, brtarget:$offset),
859 "if (!$src.new) jump:t $offset",
864 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
865 isPredicated = 1 in {
866 def JMP_cdnPnt : JInst< (outs),
867 (ins PredRegs:$src, brtarget:$offset),
868 "if ($src.new) jump:nt $offset",
873 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
874 isPredicated = 1 in {
875 def JMP_cdnNotPnt : JInst< (outs),
876 (ins PredRegs:$src, brtarget:$offset),
877 "if (!$src.new) jump:nt $offset",
880 //===----------------------------------------------------------------------===//
882 //===----------------------------------------------------------------------===//
884 //===----------------------------------------------------------------------===//
886 //===----------------------------------------------------------------------===//
887 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
888 [SDNPHasChain, SDNPOptInGlue]>;
890 // Jump to address from register.
891 let isPredicable =1, isReturn = 1, isTerminator = 1, isBarrier = 1,
892 Defs = [PC], Uses = [R31] in {
893 def JMPR: JRInst<(outs), (ins),
898 // Jump to address from register.
899 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
900 Defs = [PC], Uses = [R31] in {
901 def JMPR_cPt: JRInst<(outs), (ins PredRegs:$src1),
902 "if ($src1) jumpr r31",
906 // Jump to address from register.
907 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
908 Defs = [PC], Uses = [R31] in {
909 def JMPR_cNotPt: JRInst<(outs), (ins PredRegs:$src1),
910 "if (!$src1) jumpr r31",
914 //===----------------------------------------------------------------------===//
916 //===----------------------------------------------------------------------===//
918 //===----------------------------------------------------------------------===//
920 //===----------------------------------------------------------------------===//
922 /// Make sure that in post increment load, the first operand is always the post
923 /// increment operand.
926 let isPredicable = 1 in
927 def LDrid : LDInst<(outs DoubleRegs:$dst),
929 "$dst = memd($addr)",
930 [(set (i64 DoubleRegs:$dst), (i64 (load ADDRriS11_3:$addr)))]>;
932 let isPredicable = 1, AddedComplexity = 20 in
933 def LDrid_indexed : LDInst<(outs DoubleRegs:$dst),
934 (ins IntRegs:$src1, s11_3Imm:$offset),
935 "$dst = memd($src1+#$offset)",
936 [(set (i64 DoubleRegs:$dst),
937 (i64 (load (add (i32 IntRegs:$src1),
938 s11_3ImmPred:$offset))))]>;
940 let neverHasSideEffects = 1 in
941 def LDrid_GP : LDInst2<(outs DoubleRegs:$dst),
942 (ins globaladdress:$global, u16Imm:$offset),
943 "$dst = memd(#$global+$offset)",
947 let neverHasSideEffects = 1 in
948 def LDd_GP : LDInst2<(outs DoubleRegs:$dst),
949 (ins globaladdress:$global),
950 "$dst = memd(#$global)",
954 let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
955 def POST_LDrid : LDInst2PI<(outs DoubleRegs:$dst, IntRegs:$dst2),
956 (ins IntRegs:$src1, s4Imm:$offset),
957 "$dst = memd($src1++#$offset)",
961 // Load doubleword conditionally.
962 let neverHasSideEffects = 1, isPredicated = 1 in
963 def LDrid_cPt : LDInst2<(outs DoubleRegs:$dst),
964 (ins PredRegs:$src1, MEMri:$addr),
965 "if ($src1) $dst = memd($addr)",
969 let neverHasSideEffects = 1, isPredicated = 1 in
970 def LDrid_cNotPt : LDInst2<(outs DoubleRegs:$dst),
971 (ins PredRegs:$src1, MEMri:$addr),
972 "if (!$src1) $dst = memd($addr)",
975 let neverHasSideEffects = 1, isPredicated = 1 in
976 def LDrid_indexed_cPt : LDInst2<(outs DoubleRegs:$dst),
977 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
978 "if ($src1) $dst = memd($src2+#$src3)",
981 let neverHasSideEffects = 1, isPredicated = 1 in
982 def LDrid_indexed_cNotPt : LDInst2<(outs DoubleRegs:$dst),
983 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
984 "if (!$src1) $dst = memd($src2+#$src3)",
987 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
988 def POST_LDrid_cPt : LDInst2PI<(outs DoubleRegs:$dst1, IntRegs:$dst2),
989 (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),
990 "if ($src1) $dst1 = memd($src2++#$src3)",
994 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
995 def POST_LDrid_cNotPt : LDInst2PI<(outs DoubleRegs:$dst1, IntRegs:$dst2),
996 (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),
997 "if (!$src1) $dst1 = memd($src2++#$src3)",
1001 let neverHasSideEffects = 1, isPredicated = 1 in
1002 def LDrid_cdnPt : LDInst2<(outs DoubleRegs:$dst),
1003 (ins PredRegs:$src1, MEMri:$addr),
1004 "if ($src1.new) $dst = memd($addr)",
1007 let neverHasSideEffects = 1, isPredicated = 1 in
1008 def LDrid_cdnNotPt : LDInst2<(outs DoubleRegs:$dst),
1009 (ins PredRegs:$src1, MEMri:$addr),
1010 "if (!$src1.new) $dst = memd($addr)",
1013 let neverHasSideEffects = 1, isPredicated = 1 in
1014 def LDrid_indexed_cdnPt : LDInst2<(outs DoubleRegs:$dst),
1015 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
1016 "if ($src1.new) $dst = memd($src2+#$src3)",
1019 let neverHasSideEffects = 1, isPredicated = 1 in
1020 def LDrid_indexed_cdnNotPt : LDInst2<(outs DoubleRegs:$dst),
1021 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
1022 "if (!$src1.new) $dst = memd($src2+#$src3)",
1027 let isPredicable = 1 in
1028 def LDrib : LDInst<(outs IntRegs:$dst),
1030 "$dst = memb($addr)",
1031 [(set (i32 IntRegs:$dst), (i32 (sextloadi8 ADDRriS11_0:$addr)))]>;
1033 // Load byte any-extend.
1034 def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
1035 (i32 (LDrib ADDRriS11_0:$addr)) >;
1037 // Indexed load byte.
1038 let isPredicable = 1, AddedComplexity = 20 in
1039 def LDrib_indexed : LDInst<(outs IntRegs:$dst),
1040 (ins IntRegs:$src1, s11_0Imm:$offset),
1041 "$dst = memb($src1+#$offset)",
1042 [(set (i32 IntRegs:$dst),
1043 (i32 (sextloadi8 (add (i32 IntRegs:$src1),
1044 s11_0ImmPred:$offset))))]>;
1046 // Indexed load byte any-extend.
1047 let AddedComplexity = 20 in
1048 def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1049 (i32 (LDrib_indexed IntRegs:$src1, s11_0ImmPred:$offset)) >;
1051 let neverHasSideEffects = 1 in
1052 def LDrib_GP : LDInst2<(outs IntRegs:$dst),
1053 (ins globaladdress:$global, u16Imm:$offset),
1054 "$dst = memb(#$global+$offset)",
1058 let neverHasSideEffects = 1 in
1059 def LDb_GP : LDInst2<(outs IntRegs:$dst),
1060 (ins globaladdress:$global),
1061 "$dst = memb(#$global)",
1065 let neverHasSideEffects = 1 in
1066 def LDub_GP : LDInst2<(outs IntRegs:$dst),
1067 (ins globaladdress:$global),
1068 "$dst = memub(#$global)",
1072 let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1073 def POST_LDrib : LDInst2PI<(outs IntRegs:$dst, IntRegs:$dst2),
1074 (ins IntRegs:$src1, s4Imm:$offset),
1075 "$dst = memb($src1++#$offset)",
1079 // Load byte conditionally.
1080 let neverHasSideEffects = 1, isPredicated = 1 in
1081 def LDrib_cPt : LDInst2<(outs IntRegs:$dst),
1082 (ins PredRegs:$src1, MEMri:$addr),
1083 "if ($src1) $dst = memb($addr)",
1086 let neverHasSideEffects = 1, isPredicated = 1 in
1087 def LDrib_cNotPt : LDInst2<(outs IntRegs:$dst),
1088 (ins PredRegs:$src1, MEMri:$addr),
1089 "if (!$src1) $dst = memb($addr)",
1092 let neverHasSideEffects = 1, isPredicated = 1 in
1093 def LDrib_indexed_cPt : LDInst2<(outs IntRegs:$dst),
1094 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1095 "if ($src1) $dst = memb($src2+#$src3)",
1098 let neverHasSideEffects = 1, isPredicated = 1 in
1099 def LDrib_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
1100 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1101 "if (!$src1) $dst = memb($src2+#$src3)",
1104 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1105 def POST_LDrib_cPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1106 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1107 "if ($src1) $dst1 = memb($src2++#$src3)",
1111 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1112 def POST_LDrib_cNotPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1113 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1114 "if (!$src1) $dst1 = memb($src2++#$src3)",
1118 let neverHasSideEffects = 1, isPredicated = 1 in
1119 def LDrib_cdnPt : LDInst2<(outs IntRegs:$dst),
1120 (ins PredRegs:$src1, MEMri:$addr),
1121 "if ($src1.new) $dst = memb($addr)",
1124 let neverHasSideEffects = 1, isPredicated = 1 in
1125 def LDrib_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1126 (ins PredRegs:$src1, MEMri:$addr),
1127 "if (!$src1.new) $dst = memb($addr)",
1130 let neverHasSideEffects = 1, isPredicated = 1 in
1131 def LDrib_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
1132 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1133 "if ($src1.new) $dst = memb($src2+#$src3)",
1136 let neverHasSideEffects = 1, isPredicated = 1 in
1137 def LDrib_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1138 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1139 "if (!$src1.new) $dst = memb($src2+#$src3)",
1144 let isPredicable = 1 in
1145 def LDrih : LDInst<(outs IntRegs:$dst),
1147 "$dst = memh($addr)",
1148 [(set (i32 IntRegs:$dst), (i32 (sextloadi16 ADDRriS11_1:$addr)))]>;
1150 let isPredicable = 1, AddedComplexity = 20 in
1151 def LDrih_indexed : LDInst<(outs IntRegs:$dst),
1152 (ins IntRegs:$src1, s11_1Imm:$offset),
1153 "$dst = memh($src1+#$offset)",
1154 [(set (i32 IntRegs:$dst),
1155 (i32 (sextloadi16 (add (i32 IntRegs:$src1),
1156 s11_1ImmPred:$offset))))]>;
1158 def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
1159 (i32 (LDrih ADDRriS11_1:$addr))>;
1161 let AddedComplexity = 20 in
1162 def : Pat < (i32 (extloadi16 (add IntRegs:$src1, s11_1ImmPred:$offset))),
1163 (i32 (LDrih_indexed IntRegs:$src1, s11_1ImmPred:$offset)) >;
1165 let neverHasSideEffects = 1 in
1166 def LDrih_GP : LDInst2<(outs IntRegs:$dst),
1167 (ins globaladdress:$global, u16Imm:$offset),
1168 "$dst = memh(#$global+$offset)",
1172 let neverHasSideEffects = 1 in
1173 def LDh_GP : LDInst2<(outs IntRegs:$dst),
1174 (ins globaladdress:$global),
1175 "$dst = memh(#$global)",
1179 let neverHasSideEffects = 1 in
1180 def LDuh_GP : LDInst2<(outs IntRegs:$dst),
1181 (ins globaladdress:$global),
1182 "$dst = memuh(#$global)",
1186 let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1187 def POST_LDrih : LDInst2PI<(outs IntRegs:$dst, IntRegs:$dst2),
1188 (ins IntRegs:$src1, s4Imm:$offset),
1189 "$dst = memh($src1++#$offset)",
1193 // Load halfword conditionally.
1194 let neverHasSideEffects = 1, isPredicated = 1 in
1195 def LDrih_cPt : LDInst2<(outs IntRegs:$dst),
1196 (ins PredRegs:$src1, MEMri:$addr),
1197 "if ($src1) $dst = memh($addr)",
1200 let neverHasSideEffects = 1, isPredicated = 1 in
1201 def LDrih_cNotPt : LDInst2<(outs IntRegs:$dst),
1202 (ins PredRegs:$src1, MEMri:$addr),
1203 "if (!$src1) $dst = memh($addr)",
1206 let neverHasSideEffects = 1, isPredicated = 1 in
1207 def LDrih_indexed_cPt : LDInst2<(outs IntRegs:$dst),
1208 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1209 "if ($src1) $dst = memh($src2+#$src3)",
1212 let neverHasSideEffects = 1, isPredicated = 1 in
1213 def LDrih_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
1214 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1215 "if (!$src1) $dst = memh($src2+#$src3)",
1218 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1219 def POST_LDrih_cPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1220 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1221 "if ($src1) $dst1 = memh($src2++#$src3)",
1225 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1226 def POST_LDrih_cNotPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1227 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1228 "if (!$src1) $dst1 = memh($src2++#$src3)",
1232 let neverHasSideEffects = 1, isPredicated = 1 in
1233 def LDrih_cdnPt : LDInst2<(outs IntRegs:$dst),
1234 (ins PredRegs:$src1, MEMri:$addr),
1235 "if ($src1.new) $dst = memh($addr)",
1238 let neverHasSideEffects = 1, isPredicated = 1 in
1239 def LDrih_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1240 (ins PredRegs:$src1, MEMri:$addr),
1241 "if (!$src1.new) $dst = memh($addr)",
1244 let neverHasSideEffects = 1, isPredicated = 1 in
1245 def LDrih_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
1246 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1247 "if ($src1.new) $dst = memh($src2+#$src3)",
1250 let neverHasSideEffects = 1, isPredicated = 1 in
1251 def LDrih_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1252 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1253 "if (!$src1.new) $dst = memh($src2+#$src3)",
1256 // Load unsigned byte.
1257 let isPredicable = 1 in
1258 def LDriub : LDInst<(outs IntRegs:$dst),
1260 "$dst = memub($addr)",
1261 [(set (i32 IntRegs:$dst), (i32 (zextloadi8 ADDRriS11_0:$addr)))]>;
1263 def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
1264 (i32 (LDriub ADDRriS11_0:$addr))>;
1266 let isPredicable = 1, AddedComplexity = 20 in
1267 def LDriub_indexed : LDInst<(outs IntRegs:$dst),
1268 (ins IntRegs:$src1, s11_0Imm:$offset),
1269 "$dst = memub($src1+#$offset)",
1270 [(set (i32 IntRegs:$dst),
1271 (i32 (zextloadi8 (add (i32 IntRegs:$src1),
1272 s11_0ImmPred:$offset))))]>;
1274 let AddedComplexity = 20 in
1275 def : Pat < (i32 (zextloadi1 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1276 (i32 (LDriub_indexed IntRegs:$src1, s11_0ImmPred:$offset))>;
1278 let neverHasSideEffects = 1 in
1279 def LDriub_GP : LDInst2<(outs IntRegs:$dst),
1280 (ins globaladdress:$global, u16Imm:$offset),
1281 "$dst = memub(#$global+$offset)",
1285 let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1286 def POST_LDriub : LDInst2PI<(outs IntRegs:$dst, IntRegs:$dst2),
1287 (ins IntRegs:$src1, s4Imm:$offset),
1288 "$dst = memub($src1++#$offset)",
1292 // Load unsigned byte conditionally.
1293 let neverHasSideEffects = 1, isPredicated = 1 in
1294 def LDriub_cPt : LDInst2<(outs IntRegs:$dst),
1295 (ins PredRegs:$src1, MEMri:$addr),
1296 "if ($src1) $dst = memub($addr)",
1299 let neverHasSideEffects = 1, isPredicated = 1 in
1300 def LDriub_cNotPt : LDInst2<(outs IntRegs:$dst),
1301 (ins PredRegs:$src1, MEMri:$addr),
1302 "if (!$src1) $dst = memub($addr)",
1305 let neverHasSideEffects = 1, isPredicated = 1 in
1306 def LDriub_indexed_cPt : LDInst2<(outs IntRegs:$dst),
1307 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1308 "if ($src1) $dst = memub($src2+#$src3)",
1311 let neverHasSideEffects = 1, isPredicated = 1 in
1312 def LDriub_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
1313 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1314 "if (!$src1) $dst = memub($src2+#$src3)",
1317 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1318 def POST_LDriub_cPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1319 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1320 "if ($src1) $dst1 = memub($src2++#$src3)",
1324 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1325 def POST_LDriub_cNotPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1326 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1327 "if (!$src1) $dst1 = memub($src2++#$src3)",
1331 let neverHasSideEffects = 1, isPredicated = 1 in
1332 def LDriub_cdnPt : LDInst2<(outs IntRegs:$dst),
1333 (ins PredRegs:$src1, MEMri:$addr),
1334 "if ($src1.new) $dst = memub($addr)",
1337 let neverHasSideEffects = 1, isPredicated = 1 in
1338 def LDriub_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1339 (ins PredRegs:$src1, MEMri:$addr),
1340 "if (!$src1.new) $dst = memub($addr)",
1343 let neverHasSideEffects = 1, isPredicated = 1 in
1344 def LDriub_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
1345 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1346 "if ($src1.new) $dst = memub($src2+#$src3)",
1349 let neverHasSideEffects = 1, isPredicated = 1 in
1350 def LDriub_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1351 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1352 "if (!$src1.new) $dst = memub($src2+#$src3)",
1355 // Load unsigned halfword.
1356 let isPredicable = 1 in
1357 def LDriuh : LDInst<(outs IntRegs:$dst),
1359 "$dst = memuh($addr)",
1360 [(set (i32 IntRegs:$dst), (i32 (zextloadi16 ADDRriS11_1:$addr)))]>;
1362 // Indexed load unsigned halfword.
1363 let isPredicable = 1, AddedComplexity = 20 in
1364 def LDriuh_indexed : LDInst<(outs IntRegs:$dst),
1365 (ins IntRegs:$src1, s11_1Imm:$offset),
1366 "$dst = memuh($src1+#$offset)",
1367 [(set (i32 IntRegs:$dst),
1368 (i32 (zextloadi16 (add (i32 IntRegs:$src1),
1369 s11_1ImmPred:$offset))))]>;
1371 let neverHasSideEffects = 1 in
1372 def LDriuh_GP : LDInst2<(outs IntRegs:$dst),
1373 (ins globaladdress:$global, u16Imm:$offset),
1374 "$dst = memuh(#$global+$offset)",
1378 let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1379 def POST_LDriuh : LDInst2PI<(outs IntRegs:$dst, IntRegs:$dst2),
1380 (ins IntRegs:$src1, s4Imm:$offset),
1381 "$dst = memuh($src1++#$offset)",
1385 // Load unsigned halfword conditionally.
1386 let neverHasSideEffects = 1, isPredicated = 1 in
1387 def LDriuh_cPt : LDInst2<(outs IntRegs:$dst),
1388 (ins PredRegs:$src1, MEMri:$addr),
1389 "if ($src1) $dst = memuh($addr)",
1392 let neverHasSideEffects = 1, isPredicated = 1 in
1393 def LDriuh_cNotPt : LDInst2<(outs IntRegs:$dst),
1394 (ins PredRegs:$src1, MEMri:$addr),
1395 "if (!$src1) $dst = memuh($addr)",
1398 let neverHasSideEffects = 1, isPredicated = 1 in
1399 def LDriuh_indexed_cPt : LDInst2<(outs IntRegs:$dst),
1400 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1401 "if ($src1) $dst = memuh($src2+#$src3)",
1404 let neverHasSideEffects = 1, isPredicated = 1 in
1405 def LDriuh_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
1406 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1407 "if (!$src1) $dst = memuh($src2+#$src3)",
1410 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1411 def POST_LDriuh_cPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1412 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1413 "if ($src1) $dst1 = memuh($src2++#$src3)",
1417 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1418 def POST_LDriuh_cNotPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1419 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1420 "if (!$src1) $dst1 = memuh($src2++#$src3)",
1424 let neverHasSideEffects = 1, isPredicated = 1 in
1425 def LDriuh_cdnPt : LDInst2<(outs IntRegs:$dst),
1426 (ins PredRegs:$src1, MEMri:$addr),
1427 "if ($src1.new) $dst = memuh($addr)",
1430 let neverHasSideEffects = 1, isPredicated = 1 in
1431 def LDriuh_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1432 (ins PredRegs:$src1, MEMri:$addr),
1433 "if (!$src1.new) $dst = memuh($addr)",
1436 let neverHasSideEffects = 1, isPredicated = 1 in
1437 def LDriuh_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
1438 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1439 "if ($src1.new) $dst = memuh($src2+#$src3)",
1442 let neverHasSideEffects = 1, isPredicated = 1 in
1443 def LDriuh_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1444 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1445 "if (!$src1.new) $dst = memuh($src2+#$src3)",
1450 let isPredicable = 1 in
1451 def LDriw : LDInst<(outs IntRegs:$dst),
1452 (ins MEMri:$addr), "$dst = memw($addr)",
1453 [(set IntRegs:$dst, (i32 (load ADDRriS11_2:$addr)))]>;
1456 let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1457 def LDriw_pred : LDInst<(outs PredRegs:$dst),
1459 "Error; should not emit",
1463 let isPredicable = 1, AddedComplexity = 20 in
1464 def LDriw_indexed : LDInst<(outs IntRegs:$dst),
1465 (ins IntRegs:$src1, s11_2Imm:$offset),
1466 "$dst = memw($src1+#$offset)",
1467 [(set IntRegs:$dst, (i32 (load (add IntRegs:$src1,
1468 s11_2ImmPred:$offset))))]>;
1470 let neverHasSideEffects = 1 in
1471 def LDriw_GP : LDInst2<(outs IntRegs:$dst),
1472 (ins globaladdress:$global, u16Imm:$offset),
1473 "$dst = memw(#$global+$offset)",
1477 let neverHasSideEffects = 1 in
1478 def LDw_GP : LDInst2<(outs IntRegs:$dst),
1479 (ins globaladdress:$global),
1480 "$dst = memw(#$global)",
1484 let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1485 def POST_LDriw : LDInst2PI<(outs IntRegs:$dst, IntRegs:$dst2),
1486 (ins IntRegs:$src1, s4Imm:$offset),
1487 "$dst = memw($src1++#$offset)",
1491 // Load word conditionally.
1493 let neverHasSideEffects = 1, isPredicated = 1 in
1494 def LDriw_cPt : LDInst2<(outs IntRegs:$dst),
1495 (ins PredRegs:$src1, MEMri:$addr),
1496 "if ($src1) $dst = memw($addr)",
1499 let neverHasSideEffects = 1, isPredicated = 1 in
1500 def LDriw_cNotPt : LDInst2<(outs IntRegs:$dst),
1501 (ins PredRegs:$src1, MEMri:$addr),
1502 "if (!$src1) $dst = memw($addr)",
1505 let neverHasSideEffects = 1, isPredicated = 1 in
1506 def LDriw_indexed_cPt : LDInst2<(outs IntRegs:$dst),
1507 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1508 "if ($src1) $dst = memw($src2+#$src3)",
1511 let neverHasSideEffects = 1, isPredicated = 1 in
1512 def LDriw_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
1513 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1514 "if (!$src1) $dst = memw($src2+#$src3)",
1517 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1518 def POST_LDriw_cPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1519 (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3),
1520 "if ($src1) $dst1 = memw($src2++#$src3)",
1524 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1525 def POST_LDriw_cNotPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1526 (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3),
1527 "if (!$src1) $dst1 = memw($src2++#$src3)",
1531 let neverHasSideEffects = 1, isPredicated = 1 in
1532 def LDriw_cdnPt : LDInst2<(outs IntRegs:$dst),
1533 (ins PredRegs:$src1, MEMri:$addr),
1534 "if ($src1.new) $dst = memw($addr)",
1537 let neverHasSideEffects = 1, isPredicated = 1 in
1538 def LDriw_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1539 (ins PredRegs:$src1, MEMri:$addr),
1540 "if (!$src1.new) $dst = memw($addr)",
1543 let neverHasSideEffects = 1, isPredicated = 1 in
1544 def LDriw_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
1545 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1546 "if ($src1.new) $dst = memw($src2+#$src3)",
1549 let neverHasSideEffects = 1, isPredicated = 1 in
1550 def LDriw_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1551 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1552 "if (!$src1.new) $dst = memw($src2+#$src3)",
1555 // Deallocate stack frame.
1556 let Defs = [R29, R30, R31], Uses = [R29], neverHasSideEffects = 1 in {
1557 def DEALLOCFRAME : LDInst2<(outs), (ins i32imm:$amt1),
1562 // Load and unpack bytes to halfwords.
1563 //===----------------------------------------------------------------------===//
1565 //===----------------------------------------------------------------------===//
1567 //===----------------------------------------------------------------------===//
1569 //===----------------------------------------------------------------------===//
1570 //===----------------------------------------------------------------------===//
1572 //===----------------------------------------------------------------------===//
1574 //===----------------------------------------------------------------------===//
1576 //===----------------------------------------------------------------------===//
1577 //===----------------------------------------------------------------------===//
1579 //===----------------------------------------------------------------------===//
1581 //===----------------------------------------------------------------------===//
1583 //===----------------------------------------------------------------------===//
1584 // Multiply and use lower result.
1586 def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1587 "$dst =+ mpyi($src1, #$src2)",
1588 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1589 u8ImmPred:$src2))]>;
1592 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, n8Imm:$src2),
1593 "$dst =- mpyi($src1, #$src2)",
1594 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1595 n8ImmPred:$src2))]>;
1598 // s9 is NOT the same as m9 - but it works.. so far.
1599 // Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
1600 // depending on the value of m9. See Arch Spec.
1601 def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Imm:$src2),
1602 "$dst = mpyi($src1, #$src2)",
1603 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1604 s9ImmPred:$src2))]>;
1607 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1608 "$dst = mpyi($src1, $src2)",
1609 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1610 (i32 IntRegs:$src2)))]>;
1613 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
1614 (ins IntRegs:$src1, IntRegs:$src2, u8Imm:$src3),
1615 "$dst += mpyi($src2, #$src3)",
1616 [(set (i32 IntRegs:$dst),
1617 (add (mul (i32 IntRegs:$src2), u8ImmPred:$src3),
1618 (i32 IntRegs:$src1)))],
1622 def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
1623 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1624 "$dst += mpyi($src2, $src3)",
1625 [(set (i32 IntRegs:$dst),
1626 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1627 (i32 IntRegs:$src1)))],
1631 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
1632 (ins IntRegs:$src1, IntRegs:$src2, u8Imm:$src3),
1633 "$dst -= mpyi($src2, #$src3)",
1634 [(set (i32 IntRegs:$dst),
1635 (sub (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1636 u8ImmPred:$src3)))],
1639 // Multiply and use upper result.
1640 // Rd=mpy(Rs,Rt.H):<<1:rnd:sat
1641 // Rd=mpy(Rs,Rt.L):<<1:rnd:sat
1643 def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1644 "$dst = mpy($src1, $src2)",
1645 [(set (i32 IntRegs:$dst), (mulhs (i32 IntRegs:$src1),
1646 (i32 IntRegs:$src2)))]>;
1648 // Rd=mpy(Rs,Rt):rnd
1650 def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1651 "$dst = mpyu($src1, $src2)",
1652 [(set (i32 IntRegs:$dst), (mulhu (i32 IntRegs:$src1),
1653 (i32 IntRegs:$src2)))]>;
1655 // Multiply and use full result.
1657 def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1658 "$dst = mpyu($src1, $src2)",
1659 [(set (i64 DoubleRegs:$dst),
1660 (mul (i64 (anyext (i32 IntRegs:$src1))),
1661 (i64 (anyext (i32 IntRegs:$src2)))))]>;
1664 def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1665 "$dst = mpy($src1, $src2)",
1666 [(set (i64 DoubleRegs:$dst),
1667 (mul (i64 (sext (i32 IntRegs:$src1))),
1668 (i64 (sext (i32 IntRegs:$src2)))))]>;
1670 // Multiply and accumulate, use full result.
1671 // Rxx[+-]=mpy(Rs,Rt)
1673 def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
1674 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1675 "$dst += mpy($src2, $src3)",
1676 [(set (i64 DoubleRegs:$dst),
1677 (add (mul (i64 (sext (i32 IntRegs:$src2))),
1678 (i64 (sext (i32 IntRegs:$src3)))),
1679 (i64 DoubleRegs:$src1)))],
1683 def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
1684 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1685 "$dst -= mpy($src2, $src3)",
1686 [(set (i64 DoubleRegs:$dst),
1687 (sub (i64 DoubleRegs:$src1),
1688 (mul (i64 (sext (i32 IntRegs:$src2))),
1689 (i64 (sext (i32 IntRegs:$src3))))))],
1692 // Rxx[+-]=mpyu(Rs,Rt)
1694 def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1695 IntRegs:$src2, IntRegs:$src3),
1696 "$dst += mpyu($src2, $src3)",
1697 [(set (i64 DoubleRegs:$dst),
1698 (add (mul (i64 (anyext (i32 IntRegs:$src2))),
1699 (i64 (anyext (i32 IntRegs:$src3)))),
1700 (i64 DoubleRegs:$src1)))], "$src1 = $dst">;
1703 def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
1704 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1705 "$dst += mpyu($src2, $src3)",
1706 [(set (i64 DoubleRegs:$dst),
1707 (sub (i64 DoubleRegs:$src1),
1708 (mul (i64 (anyext (i32 IntRegs:$src2))),
1709 (i64 (anyext (i32 IntRegs:$src3))))))],
1713 def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1714 IntRegs:$src2, IntRegs:$src3),
1715 "$dst += add($src2, $src3)",
1716 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1717 (i32 IntRegs:$src3)),
1718 (i32 IntRegs:$src1)))],
1721 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1722 IntRegs:$src2, s8Imm:$src3),
1723 "$dst += add($src2, #$src3)",
1724 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1726 (i32 IntRegs:$src1)))],
1729 def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1730 IntRegs:$src2, IntRegs:$src3),
1731 "$dst -= add($src2, $src3)",
1732 [(set (i32 IntRegs:$dst),
1733 (sub (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1734 (i32 IntRegs:$src3))))],
1737 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1738 IntRegs:$src2, s8Imm:$src3),
1739 "$dst -= add($src2, #$src3)",
1740 [(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
1741 (add (i32 IntRegs:$src2),
1742 s8ImmPred:$src3)))],
1745 //===----------------------------------------------------------------------===//
1747 //===----------------------------------------------------------------------===//
1749 //===----------------------------------------------------------------------===//
1751 //===----------------------------------------------------------------------===//
1752 //===----------------------------------------------------------------------===//
1754 //===----------------------------------------------------------------------===//
1756 //===----------------------------------------------------------------------===//
1758 //===----------------------------------------------------------------------===//
1759 //===----------------------------------------------------------------------===//
1761 //===----------------------------------------------------------------------===//
1763 //===----------------------------------------------------------------------===//
1765 //===----------------------------------------------------------------------===//
1766 //===----------------------------------------------------------------------===//
1768 //===----------------------------------------------------------------------===//
1770 //===----------------------------------------------------------------------===//
1772 //===----------------------------------------------------------------------===//
1774 /// Assumptions::: ****** DO NOT IGNORE ********
1775 /// 1. Make sure that in post increment store, the zero'th operand is always the
1776 /// post increment operand.
1777 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
1780 // Store doubleword.
1781 let isPredicable = 1 in
1782 def STrid : STInst<(outs),
1783 (ins MEMri:$addr, DoubleRegs:$src1),
1784 "memd($addr) = $src1",
1785 [(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr)]>;
1787 // Indexed store double word.
1788 let AddedComplexity = 10, isPredicable = 1 in
1789 def STrid_indexed : STInst<(outs),
1790 (ins IntRegs:$src1, s11_3Imm:$src2, DoubleRegs:$src3),
1791 "memd($src1+#$src2) = $src3",
1792 [(store (i64 DoubleRegs:$src3),
1793 (add (i32 IntRegs:$src1), s11_3ImmPred:$src2))]>;
1795 let neverHasSideEffects = 1 in
1796 def STrid_GP : STInst2<(outs),
1797 (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),
1798 "memd(#$global+$offset) = $src",
1802 let neverHasSideEffects = 1 in
1803 def STd_GP : STInst2<(outs),
1804 (ins globaladdress:$global, DoubleRegs:$src),
1805 "memd(#$global) = $src",
1809 let hasCtrlDep = 1, isPredicable = 1 in
1810 def POST_STdri : STInstPI<(outs IntRegs:$dst),
1811 (ins DoubleRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1812 "memd($src2++#$offset) = $src1",
1814 (post_store (i64 DoubleRegs:$src1), (i32 IntRegs:$src2),
1815 s4_3ImmPred:$offset))],
1818 // Store doubleword conditionally.
1819 // if ([!]Pv) memd(Rs+#u6:3)=Rtt
1820 // if (Pv) memd(Rs+#u6:3)=Rtt
1821 let AddedComplexity = 10, neverHasSideEffects = 1,
1823 def STrid_cPt : STInst2<(outs),
1824 (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
1825 "if ($src1) memd($addr) = $src2",
1828 // if (!Pv) memd(Rs+#u6:3)=Rtt
1829 let AddedComplexity = 10, neverHasSideEffects = 1,
1831 def STrid_cNotPt : STInst2<(outs),
1832 (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
1833 "if (!$src1) memd($addr) = $src2",
1836 // if (Pv) memd(Rs+#u6:3)=Rtt
1837 let AddedComplexity = 10, neverHasSideEffects = 1,
1839 def STrid_indexed_cPt : STInst2<(outs),
1840 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
1842 "if ($src1) memd($src2+#$src3) = $src4",
1845 // if (!Pv) memd(Rs+#u6:3)=Rtt
1846 let AddedComplexity = 10, neverHasSideEffects = 1,
1848 def STrid_indexed_cNotPt : STInst2<(outs),
1849 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
1851 "if (!$src1) memd($src2+#$src3) = $src4",
1854 // if ([!]Pv) memd(Rx++#s4:3)=Rtt
1855 // if (Pv) memd(Rx++#s4:3)=Rtt
1856 let AddedComplexity = 10, neverHasSideEffects = 1,
1858 def POST_STdri_cPt : STInst2PI<(outs IntRegs:$dst),
1859 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1861 "if ($src1) memd($src3++#$offset) = $src2",
1865 // if (!Pv) memd(Rx++#s4:3)=Rtt
1866 let AddedComplexity = 10, neverHasSideEffects = 1, isPredicated = 1,
1868 def POST_STdri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1869 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1871 "if (!$src1) memd($src3++#$offset) = $src2",
1877 // memb(Rs+#s11:0)=Rt
1878 let isPredicable = 1 in
1879 def STrib : STInst<(outs),
1880 (ins MEMri:$addr, IntRegs:$src1),
1881 "memb($addr) = $src1",
1882 [(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr)]>;
1884 let AddedComplexity = 10, isPredicable = 1 in
1885 def STrib_indexed : STInst<(outs),
1886 (ins IntRegs:$src1, s11_0Imm:$src2, IntRegs:$src3),
1887 "memb($src1+#$src2) = $src3",
1888 [(truncstorei8 (i32 IntRegs:$src3), (add (i32 IntRegs:$src1),
1889 s11_0ImmPred:$src2))]>;
1891 // memb(gp+#u16:0)=Rt
1892 let neverHasSideEffects = 1 in
1893 def STrib_GP : STInst2<(outs),
1894 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1895 "memb(#$global+$offset) = $src",
1900 let neverHasSideEffects = 1 in
1901 def STb_GP : STInst2<(outs),
1902 (ins globaladdress:$global, IntRegs:$src),
1903 "memb(#$global) = $src",
1907 // memb(Rx++#s4:0)=Rt
1908 let hasCtrlDep = 1, isPredicable = 1 in
1909 def POST_STbri : STInstPI<(outs IntRegs:$dst), (ins IntRegs:$src1,
1912 "memb($src2++#$offset) = $src1",
1914 (post_truncsti8 (i32 IntRegs:$src1), (i32 IntRegs:$src2),
1915 s4_0ImmPred:$offset))],
1918 // Store byte conditionally.
1919 // if ([!]Pv) memb(Rs+#u6:0)=Rt
1920 // if (Pv) memb(Rs+#u6:0)=Rt
1921 let neverHasSideEffects = 1, isPredicated = 1 in
1922 def STrib_cPt : STInst2<(outs),
1923 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1924 "if ($src1) memb($addr) = $src2",
1927 // if (!Pv) memb(Rs+#u6:0)=Rt
1928 let neverHasSideEffects = 1, isPredicated = 1 in
1929 def STrib_cNotPt : STInst2<(outs),
1930 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1931 "if (!$src1) memb($addr) = $src2",
1934 // if (Pv) memb(Rs+#u6:0)=Rt
1935 let neverHasSideEffects = 1, isPredicated = 1 in
1936 def STrib_indexed_cPt : STInst2<(outs),
1937 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1938 "if ($src1) memb($src2+#$src3) = $src4",
1941 // if (!Pv) memb(Rs+#u6:0)=Rt
1942 let neverHasSideEffects = 1, isPredicated = 1 in
1943 def STrib_indexed_cNotPt : STInst2<(outs),
1944 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1945 "if (!$src1) memb($src2+#$src3) = $src4",
1948 // if ([!]Pv) memb(Rx++#s4:0)=Rt
1949 // if (Pv) memb(Rx++#s4:0)=Rt
1950 let hasCtrlDep = 1, isPredicated = 1 in
1951 def POST_STbri_cPt : STInst2PI<(outs IntRegs:$dst),
1952 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1953 "if ($src1) memb($src3++#$offset) = $src2",
1956 // if (!Pv) memb(Rx++#s4:0)=Rt
1957 let hasCtrlDep = 1, isPredicated = 1 in
1958 def POST_STbri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1959 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1960 "if (!$src1) memb($src3++#$offset) = $src2",
1965 // memh(Rs+#s11:1)=Rt
1966 let isPredicable = 1 in
1967 def STrih : STInst<(outs),
1968 (ins MEMri:$addr, IntRegs:$src1),
1969 "memh($addr) = $src1",
1970 [(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr)]>;
1973 let AddedComplexity = 10, isPredicable = 1 in
1974 def STrih_indexed : STInst<(outs),
1975 (ins IntRegs:$src1, s11_1Imm:$src2, IntRegs:$src3),
1976 "memh($src1+#$src2) = $src3",
1977 [(truncstorei16 (i32 IntRegs:$src3), (add (i32 IntRegs:$src1),
1978 s11_1ImmPred:$src2))]>;
1980 let neverHasSideEffects = 1 in
1981 def STrih_GP : STInst2<(outs),
1982 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1983 "memh(#$global+$offset) = $src",
1987 let neverHasSideEffects = 1 in
1988 def STh_GP : STInst2<(outs),
1989 (ins globaladdress:$global, IntRegs:$src),
1990 "memh(#$global) = $src",
1994 // memh(Rx++#s4:1)=Rt.H
1995 // memh(Rx++#s4:1)=Rt
1996 let hasCtrlDep = 1, isPredicable = 1 in
1997 def POST_SThri : STInstPI<(outs IntRegs:$dst),
1998 (ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1999 "memh($src2++#$offset) = $src1",
2001 (post_truncsti16 (i32 IntRegs:$src1), (i32 IntRegs:$src2),
2002 s4_1ImmPred:$offset))],
2005 // Store halfword conditionally.
2006 // if ([!]Pv) memh(Rs+#u6:1)=Rt
2007 // if (Pv) memh(Rs+#u6:1)=Rt
2008 let neverHasSideEffects = 1, isPredicated = 1 in
2009 def STrih_cPt : STInst2<(outs),
2010 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2011 "if ($src1) memh($addr) = $src2",
2014 // if (!Pv) memh(Rs+#u6:1)=Rt
2015 let neverHasSideEffects = 1, isPredicated = 1 in
2016 def STrih_cNotPt : STInst2<(outs),
2017 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2018 "if (!$src1) memh($addr) = $src2",
2021 // if (Pv) memh(Rs+#u6:1)=Rt
2022 let neverHasSideEffects = 1, isPredicated = 1 in
2023 def STrih_indexed_cPt : STInst2<(outs),
2024 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
2025 "if ($src1) memh($src2+#$src3) = $src4",
2028 // if (!Pv) memh(Rs+#u6:1)=Rt
2029 let neverHasSideEffects = 1, isPredicated = 1 in
2030 def STrih_indexed_cNotPt : STInst2<(outs),
2031 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
2032 "if (!$src1) memh($src2+#$src3) = $src4",
2035 // if ([!]Pv) memh(Rx++#s4:1)=Rt
2036 // if (Pv) memh(Rx++#s4:1)=Rt
2037 let hasCtrlDep = 1, isPredicated = 1 in
2038 def POST_SThri_cPt : STInst2PI<(outs IntRegs:$dst),
2039 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2040 "if ($src1) memh($src3++#$offset) = $src2",
2043 // if (!Pv) memh(Rx++#s4:1)=Rt
2044 let hasCtrlDep = 1, isPredicated = 1 in
2045 def POST_SThri_cNotPt : STInst2PI<(outs IntRegs:$dst),
2046 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2047 "if (!$src1) memh($src3++#$offset) = $src2",
2053 let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
2054 def STriw_pred : STInst2<(outs),
2055 (ins MEMri:$addr, PredRegs:$src1),
2056 "Error; should not emit",
2059 // memw(Rs+#s11:2)=Rt
2060 let isPredicable = 1 in
2061 def STriw : STInst<(outs),
2062 (ins MEMri:$addr, IntRegs:$src1),
2063 "memw($addr) = $src1",
2064 [(store (i32 IntRegs:$src1), ADDRriS11_2:$addr)]>;
2066 let AddedComplexity = 10, isPredicable = 1 in
2067 def STriw_indexed : STInst<(outs),
2068 (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
2069 "memw($src1+#$src2) = $src3",
2070 [(store (i32 IntRegs:$src3),
2071 (add (i32 IntRegs:$src1), s11_2ImmPred:$src2))]>;
2073 let neverHasSideEffects = 1 in
2074 def STriw_GP : STInst2<(outs),
2075 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2076 "memw(#$global+$offset) = $src",
2080 let neverHasSideEffects = 1 in
2081 def STw_GP : STInst2<(outs),
2082 (ins globaladdress:$global, IntRegs:$src),
2083 "memw(#$global) = $src",
2087 let hasCtrlDep = 1, isPredicable = 1 in
2088 def POST_STwri : STInstPI<(outs IntRegs:$dst),
2089 (ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
2090 "memw($src2++#$offset) = $src1",
2092 (post_store (i32 IntRegs:$src1), (i32 IntRegs:$src2),
2093 s4_2ImmPred:$offset))],
2096 // Store word conditionally.
2097 // if ([!]Pv) memw(Rs+#u6:2)=Rt
2098 // if (Pv) memw(Rs+#u6:2)=Rt
2099 let neverHasSideEffects = 1, isPredicated = 1 in
2100 def STriw_cPt : STInst2<(outs),
2101 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2102 "if ($src1) memw($addr) = $src2",
2105 // if (!Pv) memw(Rs+#u6:2)=Rt
2106 let neverHasSideEffects = 1, isPredicated = 1 in
2107 def STriw_cNotPt : STInst2<(outs),
2108 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2109 "if (!$src1) memw($addr) = $src2",
2112 // if (Pv) memw(Rs+#u6:2)=Rt
2113 let neverHasSideEffects = 1, isPredicated = 1 in
2114 def STriw_indexed_cPt : STInst2<(outs),
2115 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2116 "if ($src1) memw($src2+#$src3) = $src4",
2119 // if (!Pv) memw(Rs+#u6:2)=Rt
2120 let neverHasSideEffects = 1, isPredicated = 1 in
2121 def STriw_indexed_cNotPt : STInst2<(outs),
2122 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2123 "if (!$src1) memw($src2+#$src3) = $src4",
2126 // if ([!]Pv) memw(Rx++#s4:2)=Rt
2127 // if (Pv) memw(Rx++#s4:2)=Rt
2128 let hasCtrlDep = 1, isPredicated = 1 in
2129 def POST_STwri_cPt : STInst2PI<(outs IntRegs:$dst),
2130 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2131 "if ($src1) memw($src3++#$offset) = $src2",
2134 // if (!Pv) memw(Rx++#s4:2)=Rt
2135 let hasCtrlDep = 1, isPredicated = 1 in
2136 def POST_STwri_cNotPt : STInst2PI<(outs IntRegs:$dst),
2137 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2138 "if (!$src1) memw($src3++#$offset) = $src2",
2143 // Allocate stack frame.
2144 let Defs = [R29, R30], Uses = [R31, R30], neverHasSideEffects = 1 in {
2145 def ALLOCFRAME : STInst2<(outs),
2147 "allocframe(#$amt)",
2150 //===----------------------------------------------------------------------===//
2152 //===----------------------------------------------------------------------===//
2154 //===----------------------------------------------------------------------===//
2156 //===----------------------------------------------------------------------===//
2158 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
2159 "$dst = not($src1)",
2160 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
2163 // Sign extend word to doubleword.
2164 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
2165 "$dst = sxtw($src1)",
2166 [(set (i64 DoubleRegs:$dst), (sext (i32 IntRegs:$src1)))]>;
2167 //===----------------------------------------------------------------------===//
2169 //===----------------------------------------------------------------------===//
2171 //===----------------------------------------------------------------------===//
2173 //===----------------------------------------------------------------------===//
2175 def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2176 "$dst = clrbit($src1, #$src2)",
2177 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
2179 (shl 1, u5ImmPred:$src2))))]>;
2181 def CLRBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2182 "$dst = clrbit($src1, #$src2)",
2185 // Map from r0 = and(r1, 2147483647) to r0 = clrbit(r1, #31).
2186 def : Pat <(and (i32 IntRegs:$src1), 2147483647),
2187 (CLRBIT_31 (i32 IntRegs:$src1), 31)>;
2190 def SETBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2191 "$dst = setbit($src1, #$src2)",
2192 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
2193 (shl 1, u5ImmPred:$src2)))]>;
2195 // Map from r0 = or(r1, -2147483648) to r0 = setbit(r1, #31).
2196 def SETBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2197 "$dst = setbit($src1, #$src2)",
2200 def : Pat <(or (i32 IntRegs:$src1), -2147483648),
2201 (SETBIT_31 (i32 IntRegs:$src1), 31)>;
2204 def TOGBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2205 "$dst = setbit($src1, #$src2)",
2206 [(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
2207 (shl 1, u5ImmPred:$src2)))]>;
2209 // Map from r0 = xor(r1, -2147483648) to r0 = togglebit(r1, #31).
2210 def TOGBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2211 "$dst = togglebit($src1, #$src2)",
2214 def : Pat <(xor (i32 IntRegs:$src1), -2147483648),
2215 (TOGBIT_31 (i32 IntRegs:$src1), 31)>;
2217 // Predicate transfer.
2218 let neverHasSideEffects = 1 in
2219 def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
2220 "$dst = $src1 /* Should almost never emit this. */",
2223 def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1),
2224 "$dst = $src1 /* Should almost never emit this. */",
2225 [(set (i1 PredRegs:$dst), (trunc (i32 IntRegs:$src1)))]>;
2226 //===----------------------------------------------------------------------===//
2228 //===----------------------------------------------------------------------===//
2230 //===----------------------------------------------------------------------===//
2232 //===----------------------------------------------------------------------===//
2233 // Shift by immediate.
2234 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2235 "$dst = asr($src1, #$src2)",
2236 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
2237 u5ImmPred:$src2))]>;
2239 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2240 "$dst = asr($src1, #$src2)",
2241 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
2242 u6ImmPred:$src2))]>;
2244 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2245 "$dst = asl($src1, #$src2)",
2246 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
2247 u5ImmPred:$src2))]>;
2249 def ASLd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2250 "$dst = asl($src1, #$src2)",
2251 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
2252 u6ImmPred:$src2))]>;
2254 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2255 "$dst = lsr($src1, #$src2)",
2256 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
2257 u5ImmPred:$src2))]>;
2259 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2260 "$dst = lsr($src1, #$src2)",
2261 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
2262 u6ImmPred:$src2))]>;
2264 // Shift by immediate and add.
2265 let AddedComplexity = 100 in
2266 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
2268 "$dst = addasl($src1, $src2, #$src3)",
2269 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
2270 (shl (i32 IntRegs:$src2),
2271 u3ImmPred:$src3)))]>;
2273 // Shift by register.
2274 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2275 "$dst = asl($src1, $src2)",
2276 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
2277 (i32 IntRegs:$src2)))]>;
2279 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2280 "$dst = asr($src1, $src2)",
2281 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
2282 (i32 IntRegs:$src2)))]>;
2284 def LSL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2285 "$dst = lsl($src1, $src2)",
2286 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
2287 (i32 IntRegs:$src2)))]>;
2289 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2290 "$dst = lsr($src1, $src2)",
2291 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
2292 (i32 IntRegs:$src2)))]>;
2294 def ASLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2295 "$dst = asl($src1, $src2)",
2296 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
2297 (i32 IntRegs:$src2)))]>;
2299 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2300 "$dst = lsl($src1, $src2)",
2301 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
2302 (i32 IntRegs:$src2)))]>;
2304 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2306 "$dst = asr($src1, $src2)",
2307 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
2308 (i32 IntRegs:$src2)))]>;
2310 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2312 "$dst = lsr($src1, $src2)",
2313 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
2314 (i32 IntRegs:$src2)))]>;
2316 //===----------------------------------------------------------------------===//
2318 //===----------------------------------------------------------------------===//
2320 //===----------------------------------------------------------------------===//
2322 //===----------------------------------------------------------------------===//
2323 //===----------------------------------------------------------------------===//
2325 //===----------------------------------------------------------------------===//
2327 //===----------------------------------------------------------------------===//
2329 //===----------------------------------------------------------------------===//
2330 //===----------------------------------------------------------------------===//
2332 //===----------------------------------------------------------------------===//
2334 //===----------------------------------------------------------------------===//
2336 //===----------------------------------------------------------------------===//
2338 //===----------------------------------------------------------------------===//
2340 //===----------------------------------------------------------------------===//
2341 def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
2342 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
2345 let hasSideEffects = 1, isHexagonSolo = 1 in
2346 def BARRIER : SYSInst<(outs), (ins),
2348 [(HexagonBARRIER)]>;
2350 //===----------------------------------------------------------------------===//
2352 //===----------------------------------------------------------------------===//
2354 // TFRI64 - assembly mapped.
2355 let isReMaterializable = 1 in
2356 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
2358 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
2360 // Pseudo instruction to encode a set of conditional transfers.
2361 // This instruction is used instead of a mux and trades-off codesize
2362 // for performance. We conduct this transformation optimistically in
2363 // the hope that these instructions get promoted to dot-new transfers.
2364 let AddedComplexity = 100, isPredicated = 1 in
2365 def TFR_condset_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
2368 "Error; should not emit",
2369 [(set (i32 IntRegs:$dst),
2370 (i32 (select (i1 PredRegs:$src1),
2371 (i32 IntRegs:$src2),
2372 (i32 IntRegs:$src3))))]>;
2373 let AddedComplexity = 100, isPredicated = 1 in
2374 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
2375 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
2376 "Error; should not emit",
2377 [(set (i32 IntRegs:$dst),
2378 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
2379 s12ImmPred:$src3)))]>;
2381 let AddedComplexity = 100, isPredicated = 1 in
2382 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
2383 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
2384 "Error; should not emit",
2385 [(set (i32 IntRegs:$dst),
2386 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
2387 (i32 IntRegs:$src3))))]>;
2389 let AddedComplexity = 100, isPredicated = 1 in
2390 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
2391 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
2392 "Error; should not emit",
2393 [(set (i32 IntRegs:$dst),
2394 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
2395 s12ImmPred:$src3)))]>;
2397 // Generate frameindex addresses.
2398 let isReMaterializable = 1 in
2399 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
2400 "$dst = add($src1)",
2401 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
2406 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
2407 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
2408 "loop0($offset, #$src2)",
2412 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
2413 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
2414 "loop0($offset, $src2)",
2418 let isBranch = 1, isTerminator = 1, neverHasSideEffects = 1,
2419 Defs = [PC, LC0], Uses = [SA0, LC0] in {
2420 def ENDLOOP0 : Marker<(outs), (ins brtarget:$offset),
2425 // Support for generating global address.
2426 // Taken from X86InstrInfo.td.
2427 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [
2431 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
2432 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
2434 // HI/LO Instructions
2435 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2436 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
2437 "$dst.l = #LO($global)",
2440 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2441 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
2442 "$dst.h = #HI($global)",
2445 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2446 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2447 "$dst.l = #LO($imm_value)",
2451 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2452 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2453 "$dst.h = #HI($imm_value)",
2456 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2457 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2458 "$dst.l = #LO($jt)",
2461 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2462 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2463 "$dst.h = #HI($jt)",
2467 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2468 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2469 "$dst.l = #LO($label)",
2472 let isReMaterializable = 1, isMoveImm = 1 , neverHasSideEffects = 1 in
2473 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2474 "$dst.h = #HI($label)",
2477 // This pattern is incorrect. When we add small data, we should change
2478 // this pattern to use memw(#foo).
2479 // This is for sdata.
2480 let isMoveImm = 1 in
2481 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2482 "$dst = CONST32(#$global)",
2483 [(set (i32 IntRegs:$dst),
2484 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
2486 // This is for non-sdata.
2487 let isReMaterializable = 1, isMoveImm = 1 in
2488 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2489 "$dst = CONST32(#$global)",
2490 [(set (i32 IntRegs:$dst),
2491 (HexagonCONST32 tglobaladdr:$global))]>;
2493 let isReMaterializable = 1, isMoveImm = 1 in
2494 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2495 "$dst = CONST32(#$jt)",
2496 [(set (i32 IntRegs:$dst),
2497 (HexagonCONST32 tjumptable:$jt))]>;
2499 let isReMaterializable = 1, isMoveImm = 1 in
2500 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2501 "$dst = CONST32(#$global)",
2502 [(set (i32 IntRegs:$dst),
2503 (HexagonCONST32_GP tglobaladdr:$global))]>;
2505 let isReMaterializable = 1, isMoveImm = 1 in
2506 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
2507 "$dst = CONST32(#$global)",
2508 [(set (i32 IntRegs:$dst), imm:$global) ]>;
2510 let isReMaterializable = 1, isMoveImm = 1 in
2511 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
2512 "$dst = CONST32($label)",
2513 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
2515 let isReMaterializable = 1, isMoveImm = 1 in
2516 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
2517 "$dst = CONST64(#$global)",
2518 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
2520 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
2521 "$dst = xor($dst, $dst)",
2522 [(set (i1 PredRegs:$dst), 0)]>;
2524 def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2525 "$dst = mpy($src1, $src2)",
2526 [(set (i32 IntRegs:$dst),
2527 (trunc (i64 (srl (i64 (mul (i64 (sext (i32 IntRegs:$src1))),
2528 (i64 (sext (i32 IntRegs:$src2))))),
2531 // Pseudo instructions.
2532 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
2534 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
2535 SDTCisVT<1, i32> ]>;
2537 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
2538 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2540 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
2541 [SDNPHasChain, SDNPOutGlue]>;
2543 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2545 def call : SDNode<"HexagonISD::CALL", SDT_SPCall,
2546 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
2548 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
2549 // Optional Flag and Variable Arguments.
2550 // Its 1 Operand has pointer type.
2551 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
2552 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
2554 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
2555 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
2556 "Should never be emitted",
2557 [(callseq_start timm:$amt)]>;
2560 let Defs = [R29, R30, R31], Uses = [R29] in {
2561 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2562 "Should never be emitted",
2563 [(callseq_end timm:$amt1, timm:$amt2)]>;
2566 let isCall = 1, neverHasSideEffects = 1,
2567 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2568 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2569 def CALL : JInst<(outs), (ins calltarget:$dst),
2573 // Call subroutine from register.
2574 let isCall = 1, neverHasSideEffects = 1,
2575 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2576 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2577 def CALLR : JRInst<(outs), (ins IntRegs:$dst),
2583 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2584 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst),
2585 "jump $dst // TAILCALL", []>;
2587 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2588 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst),
2589 "jump $dst // TAILCALL", []>;
2592 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2593 def TCRETURNR : JInst<(outs), (ins IntRegs:$dst),
2594 "jumpr $dst // TAILCALL", []>;
2596 // Map call instruction.
2597 def : Pat<(call (i32 IntRegs:$dst)),
2598 (CALLR (i32 IntRegs:$dst))>, Requires<[HasV2TOnly]>;
2599 def : Pat<(call tglobaladdr:$dst),
2600 (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
2601 def : Pat<(call texternalsym:$dst),
2602 (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>;
2604 def : Pat<(HexagonTCRet tglobaladdr:$dst),
2605 (TCRETURNtg tglobaladdr:$dst)>;
2606 def : Pat<(HexagonTCRet texternalsym:$dst),
2607 (TCRETURNtext texternalsym:$dst)>;
2608 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
2609 (TCRETURNR (i32 IntRegs:$dst))>;
2611 // Atomic load and store support
2612 // 8 bit atomic load
2613 def : Pat<(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
2614 (i32 (LDub_GP tglobaladdr:$global))>,
2617 def : Pat<(atomic_load_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2618 u16ImmPred:$offset)),
2619 (i32 (LDriub_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2622 def : Pat<(atomic_load_8 ADDRriS11_0:$src1),
2623 (i32 (LDriub ADDRriS11_0:$src1))>;
2625 def : Pat<(atomic_load_8 (add (i32 IntRegs:$src1), s11_0ImmPred:$offset)),
2626 (i32 (LDriub_indexed (i32 IntRegs:$src1), s11_0ImmPred:$offset))>;
2630 // 16 bit atomic load
2631 def : Pat<(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
2632 (i32 (LDuh_GP tglobaladdr:$global))>,
2635 def : Pat<(atomic_load_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2636 u16ImmPred:$offset)),
2637 (i32 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2640 def : Pat<(atomic_load_16 ADDRriS11_1:$src1),
2641 (i32 (LDriuh ADDRriS11_1:$src1))>;
2643 def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)),
2644 (i32 (LDriuh_indexed (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
2648 // 32 bit atomic load
2649 def : Pat<(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
2650 (i32 (LDw_GP tglobaladdr:$global))>,
2653 def : Pat<(atomic_load_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2654 u16ImmPred:$offset)),
2655 (i32 (LDriw_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2658 def : Pat<(atomic_load_32 ADDRriS11_2:$src1),
2659 (i32 (LDriw ADDRriS11_2:$src1))>;
2661 def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),
2662 (i32 (LDriw_indexed (i32 IntRegs:$src1), s11_2ImmPred:$offset))>;
2665 // 64 bit atomic load
2666 def : Pat<(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
2667 (i64 (LDd_GP tglobaladdr:$global))>,
2670 def : Pat<(atomic_load_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2671 u16ImmPred:$offset)),
2672 (i64 (LDrid_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2675 def : Pat<(atomic_load_64 ADDRriS11_3:$src1),
2676 (i64 (LDrid ADDRriS11_3:$src1))>;
2678 def : Pat<(atomic_load_64 (add (i32 IntRegs:$src1), s11_3ImmPred:$offset)),
2679 (i64 (LDrid_indexed (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
2682 // 64 bit atomic store
2683 def : Pat<(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
2684 (i64 DoubleRegs:$src1)),
2685 (STd_GP tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2688 def : Pat<(atomic_store_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2689 u16ImmPred:$offset),
2690 (i64 DoubleRegs:$src1)),
2691 (STrid_GP tglobaladdr:$global, u16ImmPred:$offset,
2692 (i64 DoubleRegs:$src1))>, Requires<[NoV4T]>;
2694 // 8 bit atomic store
2695 def : Pat<(atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
2696 (i32 IntRegs:$src1)),
2697 (STb_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2700 def : Pat<(atomic_store_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2701 u16ImmPred:$offset),
2702 (i32 IntRegs:$src1)),
2703 (STrib_GP tglobaladdr:$global, u16ImmPred:$offset,
2704 (i32 IntRegs:$src1))>, Requires<[NoV4T]>;
2706 def : Pat<(atomic_store_8 ADDRriS11_0:$src2, (i32 IntRegs:$src1)),
2707 (STrib ADDRriS11_0:$src2, (i32 IntRegs:$src1))>;
2709 def : Pat<(atomic_store_8 (add (i32 IntRegs:$src2), s11_0ImmPred:$offset),
2710 (i32 IntRegs:$src1)),
2711 (STrib_indexed (i32 IntRegs:$src2), s11_0ImmPred:$offset,
2712 (i32 IntRegs:$src1))>;
2715 // 16 bit atomic store
2716 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
2717 (i32 IntRegs:$src1)),
2718 (STh_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2721 def : Pat<(atomic_store_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2722 u16ImmPred:$offset),
2723 (i32 IntRegs:$src1)),
2724 (STrih_GP tglobaladdr:$global, u16ImmPred:$offset,
2725 (i32 IntRegs:$src1))>, Requires<[NoV4T]>;
2727 def : Pat<(atomic_store_16 ADDRriS11_1:$src2, (i32 IntRegs:$src1)),
2728 (STrih ADDRriS11_1:$src2, (i32 IntRegs:$src1))>;
2730 def : Pat<(atomic_store_16 (i32 IntRegs:$src1),
2731 (add (i32 IntRegs:$src2), s11_1ImmPred:$offset)),
2732 (STrih_indexed (i32 IntRegs:$src2), s11_1ImmPred:$offset,
2733 (i32 IntRegs:$src1))>;
2736 // 32 bit atomic store
2737 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
2738 (i32 IntRegs:$src1)),
2739 (STw_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2742 def : Pat<(atomic_store_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2743 u16ImmPred:$offset),
2744 (i32 IntRegs:$src1)),
2745 (STriw_GP tglobaladdr:$global, u16ImmPred:$offset,
2746 (i32 IntRegs:$src1))>,
2749 def : Pat<(atomic_store_32 ADDRriS11_2:$src2, (i32 IntRegs:$src1)),
2750 (STriw ADDRriS11_2:$src2, (i32 IntRegs:$src1))>;
2752 def : Pat<(atomic_store_32 (add (i32 IntRegs:$src2), s11_2ImmPred:$offset),
2753 (i32 IntRegs:$src1)),
2754 (STriw_indexed (i32 IntRegs:$src2), s11_2ImmPred:$offset,
2755 (i32 IntRegs:$src1))>;
2760 def : Pat<(atomic_store_64 ADDRriS11_3:$src2, (i64 DoubleRegs:$src1)),
2761 (STrid ADDRriS11_3:$src2, (i64 DoubleRegs:$src1))>;
2763 def : Pat<(atomic_store_64 (add (i32 IntRegs:$src2), s11_3ImmPred:$offset),
2764 (i64 DoubleRegs:$src1)),
2765 (STrid_indexed (i32 IntRegs:$src2), s11_3ImmPred:$offset,
2766 (i64 DoubleRegs:$src1))>;
2768 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
2769 def : Pat <(and (i32 IntRegs:$src1), 65535),
2770 (ZXTH (i32 IntRegs:$src1))>;
2772 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
2773 def : Pat <(and (i32 IntRegs:$src1), 255),
2774 (ZXTB (i32 IntRegs:$src1))>;
2776 // Map Add(p1, true) to p1 = not(p1).
2777 // Add(p1, false) should never be produced,
2778 // if it does, it got to be mapped to NOOP.
2779 def : Pat <(add (i1 PredRegs:$src1), -1),
2780 (NOT_p (i1 PredRegs:$src1))>;
2782 // Map from p0 = setlt(r0, r1) r2 = mux(p0, r3, r4) =>
2783 // p0 = cmp.lt(r0, r1), r0 = mux(p0, r2, r1).
2784 def : Pat <(select (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2785 (i32 IntRegs:$src3),
2786 (i32 IntRegs:$src4)),
2787 (i32 (TFR_condset_rr (CMPLTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2788 (i32 IntRegs:$src4), (i32 IntRegs:$src3)))>,
2789 Requires<[HasV2TOnly]>;
2791 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
2792 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
2793 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
2796 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
2797 // => r0 = TFR_condset_ri(p0, r1, #i)
2798 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
2799 (i32 IntRegs:$src3)),
2800 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
2801 s12ImmPred:$src2))>;
2803 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
2804 // => r0 = TFR_condset_ir(p0, #i, r1)
2805 def : Pat <(select (not PredRegs:$src1), IntRegs:$src2, s12ImmPred:$src3),
2806 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
2807 (i32 IntRegs:$src2)))>;
2809 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
2810 def : Pat <(brcond (not PredRegs:$src1), bb:$offset),
2811 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
2813 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
2814 def : Pat <(and PredRegs:$src1, (not PredRegs:$src2)),
2815 (i1 (AND_pnotp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2817 // Map from store(globaladdress + x) -> memd(#foo + x).
2818 let AddedComplexity = 100 in
2819 def : Pat <(store (i64 DoubleRegs:$src1),
2820 (add (HexagonCONST32_GP tglobaladdr:$global),
2821 u16ImmPred:$offset)),
2822 (STrid_GP tglobaladdr:$global, u16ImmPred:$offset,
2823 (i64 DoubleRegs:$src1))>, Requires<[NoV4T]>;
2825 // Map from store(globaladdress) -> memd(#foo).
2826 let AddedComplexity = 100 in
2827 def : Pat <(store (i64 DoubleRegs:$src1),
2828 (HexagonCONST32_GP tglobaladdr:$global)),
2829 (STd_GP tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2832 // Map from store(globaladdress + x) -> memw(#foo + x).
2833 let AddedComplexity = 100 in
2834 def : Pat <(store (i32 IntRegs:$src1),
2835 (add (HexagonCONST32_GP tglobaladdr:$global),
2836 u16ImmPred:$offset)),
2837 (STriw_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2840 // Map from store(globaladdress) -> memw(#foo + 0).
2841 let AddedComplexity = 100 in
2842 def : Pat <(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2843 (STriw_GP tglobaladdr:$global, 0, (i32 IntRegs:$src1))>;
2845 // Map from store(globaladdress) -> memw(#foo).
2846 let AddedComplexity = 100 in
2847 def : Pat <(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2848 (STriw_GP tglobaladdr:$global, 0, (i32 IntRegs:$src1))>,
2851 // Map from store(globaladdress + x) -> memh(#foo + x).
2852 let AddedComplexity = 100 in
2853 def : Pat <(truncstorei16 (i32 IntRegs:$src1),
2854 (add (HexagonCONST32_GP tglobaladdr:$global),
2855 u16ImmPred:$offset)),
2856 (STrih_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2859 // Map from store(globaladdress) -> memh(#foo).
2860 let AddedComplexity = 100 in
2861 def : Pat <(truncstorei16 (i32 IntRegs:$src1),
2862 (HexagonCONST32_GP tglobaladdr:$global)),
2863 (STh_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2866 // Map from store(globaladdress + x) -> memb(#foo + x).
2867 let AddedComplexity = 100 in
2868 def : Pat <(truncstorei8 (i32 IntRegs:$src1),
2869 (add (HexagonCONST32_GP tglobaladdr:$global),
2870 u16ImmPred:$offset)),
2871 (STrib_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2874 // Map from store(globaladdress) -> memb(#foo).
2875 let AddedComplexity = 100 in
2876 def : Pat <(truncstorei8 (i32 IntRegs:$src1),
2877 (HexagonCONST32_GP tglobaladdr:$global)),
2878 (STb_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2881 // Map from load(globaladdress + x) -> memw(#foo + x).
2882 let AddedComplexity = 100 in
2883 def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global),
2884 u16ImmPred:$offset))),
2885 (i32 (LDriw_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2888 // Map from load(globaladdress) -> memw(#foo).
2889 let AddedComplexity = 100 in
2890 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
2891 (i32 (LDw_GP tglobaladdr:$global))>,
2894 // Map from load(globaladdress + x) -> memd(#foo + x).
2895 let AddedComplexity = 100 in
2896 def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),
2897 u16ImmPred:$offset))),
2898 (i64 (LDrid_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2901 // Map from load(globaladdress) -> memw(#foo + 0).
2902 let AddedComplexity = 100 in
2903 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
2904 (i64 (LDd_GP tglobaladdr:$global))>,
2907 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd.
2908 let AddedComplexity = 100 in
2909 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
2910 (i1 (TFR_PdRs (i32 (LDb_GP tglobaladdr:$global))))>,
2913 // Map from load(globaladdress + x) -> memh(#foo + x).
2914 let AddedComplexity = 100 in
2915 def : Pat <(i32 (extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2916 u16ImmPred:$offset))),
2917 (i32 (LDrih_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2920 // Map from load(globaladdress + x) -> memh(#foo + x).
2921 let AddedComplexity = 100 in
2922 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2923 (i32 (LDrih_GP tglobaladdr:$global, 0))>,
2926 // Map from load(globaladdress + x) -> memuh(#foo + x).
2927 let AddedComplexity = 100 in
2928 def : Pat <(i32 (zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2929 u16ImmPred:$offset))),
2930 (i32 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2933 // Map from load(globaladdress) -> memuh(#foo).
2934 let AddedComplexity = 100 in
2935 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2936 (i32 (LDriuh_GP tglobaladdr:$global, 0))>,
2939 // Map from load(globaladdress) -> memh(#foo).
2940 let AddedComplexity = 100 in
2941 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2942 (i32 (LDh_GP tglobaladdr:$global))>,
2945 // Map from load(globaladdress) -> memuh(#foo).
2946 let AddedComplexity = 100 in
2947 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2948 (i32 (LDuh_GP tglobaladdr:$global))>,
2951 // Map from load(globaladdress + x) -> memb(#foo + x).
2952 let AddedComplexity = 100 in
2953 def : Pat <(i32 (extloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2954 u16ImmPred:$offset))),
2955 (i32 (LDrib_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2958 // Map from load(globaladdress + x) -> memb(#foo + x).
2959 let AddedComplexity = 100 in
2960 def : Pat <(i32 (sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2961 u16ImmPred:$offset))),
2962 (i32 (LDrib_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2965 // Map from load(globaladdress + x) -> memub(#foo + x).
2966 let AddedComplexity = 100 in
2967 def : Pat <(i32 (zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2968 u16ImmPred:$offset))),
2969 (i32 (LDriub_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2972 // Map from load(globaladdress) -> memb(#foo).
2973 let AddedComplexity = 100 in
2974 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2975 (i32 (LDb_GP tglobaladdr:$global))>,
2978 // Map from load(globaladdress) -> memb(#foo).
2979 let AddedComplexity = 100 in
2980 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2981 (i32 (LDb_GP tglobaladdr:$global))>,
2984 // Map from load(globaladdress) -> memub(#foo).
2985 let AddedComplexity = 100 in
2986 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2987 (i32 (LDub_GP tglobaladdr:$global))>,
2990 // When the Interprocedural Global Variable optimizer realizes that a
2991 // certain global variable takes only two constant values, it shrinks the
2992 // global to a boolean. Catch those loads here in the following 3 patterns.
2993 let AddedComplexity = 100 in
2994 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2995 (i32 (LDb_GP tglobaladdr:$global))>,
2998 let AddedComplexity = 100 in
2999 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3000 (i32 (LDb_GP tglobaladdr:$global))>,
3003 let AddedComplexity = 100 in
3004 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3005 (i32 (LDub_GP tglobaladdr:$global))>,
3008 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
3009 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
3010 (i32 (AND_rr (i32 (LDrib ADDRriS11_0:$addr)), (TFRI 0x1)))>;
3012 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
3013 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
3014 (i64 (SXTW (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
3016 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
3017 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
3018 (i64 (SXTW (i32 (SXTH (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
3019 subreg_loreg))))))>;
3021 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
3022 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
3023 (i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
3024 subreg_loreg))))))>;
3026 // We want to prevent emitting pnot's as much as possible.
3027 // Map brcond with an unsupported setcc to a JMP_cNot.
3028 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3030 (JMP_cNot (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
3033 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
3035 (JMP_cNot (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
3037 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
3038 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
3040 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
3041 (JMP_c (i1 PredRegs:$src1), bb:$offset)>;
3043 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
3045 (JMP_cNot (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2), bb:$offset)>;
3047 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3049 (JMP_c (CMPLTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)), bb:$offset)>;
3051 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3053 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
3056 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3058 (JMP_cNot (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
3061 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3063 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
3066 // Map from a 64-bit select to an emulated 64-bit mux.
3067 // Hexagon does not support 64-bit MUXes; so emulate with combines.
3068 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
3069 (i64 DoubleRegs:$src3)),
3070 (i64 (COMBINE_rr (i32 (MUX_rr (i1 PredRegs:$src1),
3071 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
3073 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
3075 (i32 (MUX_rr (i1 PredRegs:$src1),
3076 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
3078 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
3079 subreg_loreg))))))>;
3081 // Map from a 1-bit select to logical ops.
3082 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
3083 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
3084 (i1 PredRegs:$src3)),
3085 (OR_pp (AND_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
3086 (AND_pp (NOT_p (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
3088 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
3089 def : Pat<(i1 (load ADDRriS11_2:$addr)),
3090 (i1 (TFR_PdRs (i32 (LDrib ADDRriS11_2:$addr))))>;
3092 // Map for truncating from 64 immediates to 32 bit immediates.
3093 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
3094 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
3096 // Map for truncating from i64 immediates to i1 bit immediates.
3097 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
3098 (i1 (TFR_PdRs (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
3101 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
3102 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
3103 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
3106 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
3107 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
3108 (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
3110 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
3111 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
3112 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
3115 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
3116 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
3117 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
3120 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
3121 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
3122 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
3124 let AddedComplexity = 100 in
3125 // Map from i1 = constant<-1>; memw(CONST32(#foo)) = i1 -> r0 = 1;
3127 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
3128 (STb_GP tglobaladdr:$global, (TFRI 1))>,
3131 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
3132 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
3133 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
3135 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
3136 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
3137 (STrib ADDRriS11_2:$addr, (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0)) )>;
3139 // Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs).
3140 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
3141 // Better way to do this?
3142 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
3143 (i64 (SXTW (i32 IntRegs:$src1)))>;
3145 // Map cmple -> cmpgt.
3146 // rs <= rt -> !(rs > rt).
3147 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ImmPred:$src2)),
3148 (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), s10ImmPred:$src2)))>;
3150 // rs <= rt -> !(rs > rt).
3151 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3152 (i1 (NOT_p (CMPGTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
3154 // Rss <= Rtt -> !(Rss > Rtt).
3155 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3156 (i1 (NOT_p (CMPGT64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
3158 // Map cmpne -> cmpeq.
3159 // Hexagon_TODO: We should improve on this.
3160 // rs != rt -> !(rs == rt).
3161 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
3162 (i1 (NOT_p(i1 (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2))))>;
3164 // Map cmpne(Rs) -> !cmpeqe(Rs).
3165 // rs != rt -> !(rs == rt).
3166 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3167 (i1 (NOT_p (i1 (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
3169 // Convert setne back to xor for hexagon since we compute w/ pred registers.
3170 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
3171 (i1 (XOR_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
3173 // Map cmpne(Rss) -> !cmpew(Rss).
3174 // rs != rt -> !(rs == rt).
3175 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3176 (i1 (NOT_p (i1 (CMPEHexagon4rr (i64 DoubleRegs:$src1),
3177 (i64 DoubleRegs:$src2)))))>;
3179 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
3180 // rs >= rt -> !(rt > rs).
3181 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3182 (i1 (NOT_p (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
3184 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ImmPred:$src2)),
3185 (i1 (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2))>;
3187 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
3188 // rss >= rtt -> !(rtt > rss).
3189 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3190 (i1 (NOT_p (i1 (CMPGT64rr (i64 DoubleRegs:$src2),
3191 (i64 DoubleRegs:$src1)))))>;
3193 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
3194 // rs < rt -> !(rs >= rt).
3195 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
3196 (i1 (NOT_p (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2)))>;
3198 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
3199 // rs < rt -> rt > rs.
3200 // We can let assembler map it, or we can do in the compiler itself.
3201 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3202 (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
3204 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
3205 // rss < rtt -> (rtt > rss).
3206 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3207 (i1 (CMPGT64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
3209 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
3210 // rs < rt -> rt > rs.
3211 // We can let assembler map it, or we can do in the compiler itself.
3212 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3213 (i1 (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
3215 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
3216 // rs < rt -> rt > rs.
3217 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3218 (i1 (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
3220 // Generate cmpgeu(Rs, #u8)
3221 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ImmPred:$src2)),
3222 (i1 (CMPGEUri (i32 IntRegs:$src1), u8ImmPred:$src2))>;
3224 // Generate cmpgtu(Rs, #u9)
3225 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ImmPred:$src2)),
3226 (i1 (CMPGTUri (i32 IntRegs:$src1), u9ImmPred:$src2))>;
3228 // Map from Rs >= Rt -> !(Rt > Rs).
3229 // rs >= rt -> !(rt > rs).
3230 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3231 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
3233 // Map from Rs >= Rt -> !(Rt > Rs).
3234 // rs >= rt -> !(rt > rs).
3235 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3236 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
3238 // Map from cmpleu(Rs, Rs) -> !cmpgtu(Rs, Rs).
3239 // Map from (Rs <= Rt) -> !(Rs > Rt).
3240 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3241 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
3243 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
3244 // Map from (Rs <= Rt) -> !(Rs > Rt).
3245 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3246 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
3250 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
3251 (i32 (MUX_ii (i1 PredRegs:$src1), -1, 0))>;
3254 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
3255 (i64 (COMBINE_rr (TFRI -1), (MUX_ii (i1 PredRegs:$src1), -1, 0)))>;
3257 // Convert sign-extended load back to load and sign extend.
3259 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
3260 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
3262 // Convert any-extended load back to load and sign extend.
3264 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
3265 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
3267 // Convert sign-extended load back to load and sign extend.
3269 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
3270 (i64 (SXTW (LDrih ADDRriS11_1:$src1)))>;
3272 // Convert sign-extended load back to load and sign extend.
3274 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
3275 (i64 (SXTW (LDriw ADDRriS11_2:$src1)))>;
3280 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
3281 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
3284 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
3285 (i64 (COMBINE_rr (TFRI 0), (MUX_ii (i1 PredRegs:$src1), 1, 0)))>;
3288 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
3289 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>;
3292 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
3293 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>;
3296 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
3297 (i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>;
3300 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
3301 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>;
3303 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
3304 (i32 (LDriw ADDRriS11_0:$src1))>;
3306 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
3307 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
3308 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
3310 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
3311 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
3312 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
3314 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
3315 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
3316 (i64 (SXTW (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))))>;
3319 // Any extended 64-bit load.
3320 // anyext i32 -> i64
3321 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
3322 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>;
3324 // anyext i16 -> i64.
3325 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
3326 (i64 (COMBINE_rr (TFRI 0), (LDrih ADDRriS11_2:$src1)))>;
3328 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
3329 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
3330 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>;
3332 // Multiply 64-bit unsigned and use upper result.
3333 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
3348 (COMBINE_rr (TFRI 0),
3354 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
3356 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
3357 subreg_loreg)))), 32)),
3359 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3360 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
3361 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
3362 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
3363 32)), subreg_loreg)))),
3364 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3365 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
3367 // Multiply 64-bit signed and use upper result.
3368 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
3372 (COMBINE_rr (TFRI 0),
3382 (COMBINE_rr (TFRI 0),
3388 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
3390 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
3391 subreg_loreg)))), 32)),
3393 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3394 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
3395 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
3396 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
3397 32)), subreg_loreg)))),
3398 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3399 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
3401 // Hexagon specific ISD nodes.
3402 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
3403 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
3404 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
3405 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
3406 SDTHexagonADJDYNALLOC>;
3407 // Needed to tag these instructions for stack layout.
3408 let usesCustomInserter = 1 in
3409 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
3411 "$dst = add($src1, #$src2)",
3412 [(set (i32 IntRegs:$dst),
3413 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
3414 s16ImmPred:$src2))]>;
3416 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
3417 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
3418 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
3420 [(set (i32 IntRegs:$dst),
3421 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
3423 let AddedComplexity = 100 in
3424 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
3425 (COPY (i32 IntRegs:$src1))>;
3427 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
3428 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
3430 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
3431 def BR_JT : JRInst<(outs), (ins IntRegs:$src),
3433 [(HexagonBR_JT (i32 IntRegs:$src))]>;
3435 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
3437 def : Pat<(HexagonWrapperJT tjumptable:$dst),
3438 (i32 (CONST32_set_jt tjumptable:$dst))>;
3442 // Multi-class for logical operators :
3443 // Shift by immediate/register and accumulate/logical
3444 multiclass xtype_imm<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
3445 def _ri : SInst_acc<(outs IntRegs:$dst),
3446 (ins IntRegs:$src1, IntRegs:$src2, u5Imm:$src3),
3447 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
3448 [(set (i32 IntRegs:$dst),
3449 (OpNode2 (i32 IntRegs:$src1),
3450 (OpNode1 (i32 IntRegs:$src2),
3451 u5ImmPred:$src3)))],
3454 def d_ri : SInst_acc<(outs DoubleRegs:$dst),
3455 (ins DoubleRegs:$src1, DoubleRegs:$src2, u6Imm:$src3),
3456 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
3457 [(set (i64 DoubleRegs:$dst), (OpNode2 (i64 DoubleRegs:$src1),
3458 (OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
3462 // Multi-class for logical operators :
3463 // Shift by register and accumulate/logical (32/64 bits)
3464 multiclass xtype_reg<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
3465 def _rr : SInst_acc<(outs IntRegs:$dst),
3466 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
3467 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
3468 [(set (i32 IntRegs:$dst),
3469 (OpNode2 (i32 IntRegs:$src1),
3470 (OpNode1 (i32 IntRegs:$src2),
3471 (i32 IntRegs:$src3))))],
3474 def d_rr : SInst_acc<(outs DoubleRegs:$dst),
3475 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3476 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
3477 [(set (i64 DoubleRegs:$dst),
3478 (OpNode2 (i64 DoubleRegs:$src1),
3479 (OpNode1 (i64 DoubleRegs:$src2),
3480 (i32 IntRegs:$src3))))],
3485 multiclass basic_xtype_imm<string OpcStr, SDNode OpNode> {
3486 let AddedComplexity = 100 in
3487 defm _ADD : xtype_imm< !strconcat("+= ", OpcStr), OpNode, add>;
3488 defm _SUB : xtype_imm< !strconcat("-= ", OpcStr), OpNode, sub>;
3489 defm _AND : xtype_imm< !strconcat("&= ", OpcStr), OpNode, and>;
3490 defm _OR : xtype_imm< !strconcat("|= ", OpcStr), OpNode, or>;
3493 multiclass basic_xtype_reg<string OpcStr, SDNode OpNode> {
3494 let AddedComplexity = 100 in
3495 defm _ADD : xtype_reg< !strconcat("+= ", OpcStr), OpNode, add>;
3496 defm _SUB : xtype_reg< !strconcat("-= ", OpcStr), OpNode, sub>;
3497 defm _AND : xtype_reg< !strconcat("&= ", OpcStr), OpNode, and>;
3498 defm _OR : xtype_reg< !strconcat("|= ", OpcStr), OpNode, or>;
3501 multiclass xtype_xor_imm<string OpcStr, SDNode OpNode> {
3502 let AddedComplexity = 100 in
3503 defm _XOR : xtype_imm< !strconcat("^= ", OpcStr), OpNode, xor>;
3506 defm ASL : basic_xtype_imm<"asl", shl>, basic_xtype_reg<"asl", shl>,
3507 xtype_xor_imm<"asl", shl>;
3509 defm LSR : basic_xtype_imm<"lsr", srl>, basic_xtype_reg<"lsr", srl>,
3510 xtype_xor_imm<"lsr", srl>;
3512 defm ASR : basic_xtype_imm<"asr", sra>, basic_xtype_reg<"asr", sra>;
3513 defm LSL : basic_xtype_reg<"lsl", shl>;
3515 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
3516 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
3517 (i32 (MPYI_rin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
3519 //===----------------------------------------------------------------------===//
3520 // V3 Instructions +
3521 //===----------------------------------------------------------------------===//
3523 include "HexagonInstrInfoV3.td"
3525 //===----------------------------------------------------------------------===//
3526 // V3 Instructions -
3527 //===----------------------------------------------------------------------===//
3529 //===----------------------------------------------------------------------===//
3530 // V4 Instructions +
3531 //===----------------------------------------------------------------------===//
3533 include "HexagonInstrInfoV4.td"
3535 //===----------------------------------------------------------------------===//
3536 // V4 Instructions -
3537 //===----------------------------------------------------------------------===//
3539 //===----------------------------------------------------------------------===//
3540 // V5 Instructions +
3541 //===----------------------------------------------------------------------===//
3543 include "HexagonInstrInfoV5.td"
3545 //===----------------------------------------------------------------------===//
3546 // V5 Instructions -
3547 //===----------------------------------------------------------------------===//