1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
17 //===----------------------------------------------------------------------===//
19 // Multi-class for logical operators.
20 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
21 def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
22 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
23 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),
25 def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
26 !strconcat("$dst = ", !strconcat(OpcStr, "(#$b, $c)")),
27 [(set (i32 IntRegs:$dst), (OpNode s10Imm:$b,
31 // Multi-class for compare ops.
32 let isCompare = 1 in {
33 multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
34 def rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
35 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
36 [(set (i1 PredRegs:$dst),
37 (OpNode (i64 DoubleRegs:$b), (i64 DoubleRegs:$c)))]>;
40 multiclass CMP32_rr_ri_s10<string OpcStr, string CextOp, PatFrag OpNode> {
41 let CextOpcode = CextOp in {
42 let InputType = "reg" in
43 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
44 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
45 [(set (i1 PredRegs:$dst),
46 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
48 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1,
49 opExtentBits = 10, InputType = "imm" in
50 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Ext:$c),
51 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
52 [(set (i1 PredRegs:$dst),
53 (OpNode (i32 IntRegs:$b), s10ExtPred:$c))]>;
57 multiclass CMP32_rr_ri_u9<string OpcStr, string CextOp, PatFrag OpNode> {
58 let CextOpcode = CextOp in {
59 let InputType = "reg" in
60 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
61 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
62 [(set (i1 PredRegs:$dst),
63 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
65 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0,
66 opExtentBits = 9, InputType = "imm" in
67 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Ext:$c),
68 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
69 [(set (i1 PredRegs:$dst),
70 (OpNode (i32 IntRegs:$b), u9ExtPred:$c))]>;
74 multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
75 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
76 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Ext:$c),
77 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
78 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
83 //===----------------------------------------------------------------------===//
84 // ALU32/ALU (Instructions with register-register form)
85 //===----------------------------------------------------------------------===//
86 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
87 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
89 def HexagonWrapperCombineII :
90 SDNode<"HexagonISD::WrapperCombineII", SDTHexagonI64I32I32>;
92 def HexagonWrapperCombineRR :
93 SDNode<"HexagonISD::WrapperCombineRR", SDTHexagonI64I32I32>;
95 multiclass ALU32_Pbase<string mnemonic, RegisterClass RC, bit isNot,
97 let isPredicatedNew = isPredNew in
98 def NAME : ALU32_rr<(outs RC:$dst),
99 (ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
100 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
101 ") $dst = ")#mnemonic#"($src2, $src3)",
105 multiclass ALU32_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
106 let isPredicatedFalse = PredNot in {
107 defm _c#NAME : ALU32_Pbase<mnemonic, RC, PredNot, 0>;
109 defm _cdn#NAME : ALU32_Pbase<mnemonic, RC, PredNot, 1>;
113 let InputType = "reg" in
114 multiclass ALU32_base<string mnemonic, string CextOp, SDNode OpNode> {
115 let CextOpcode = CextOp, BaseOpcode = CextOp#_rr in {
116 let isPredicable = 1 in
117 def NAME : ALU32_rr<(outs IntRegs:$dst),
118 (ins IntRegs:$src1, IntRegs:$src2),
119 "$dst = "#mnemonic#"($src1, $src2)",
120 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
121 (i32 IntRegs:$src2)))]>;
123 let neverHasSideEffects = 1, isPredicated = 1 in {
124 defm Pt : ALU32_Pred<mnemonic, IntRegs, 0>;
125 defm NotPt : ALU32_Pred<mnemonic, IntRegs, 1>;
130 let isCommutable = 1 in {
131 defm ADD_rr : ALU32_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
132 defm AND_rr : ALU32_base<"and", "AND", and>, ImmRegRel, PredNewRel;
133 defm XOR_rr : ALU32_base<"xor", "XOR", xor>, ImmRegRel, PredNewRel;
134 defm OR_rr : ALU32_base<"or", "OR", or>, ImmRegRel, PredNewRel;
137 defm SUB_rr : ALU32_base<"sub", "SUB", sub>, ImmRegRel, PredNewRel;
139 // Combines the two integer registers SRC1 and SRC2 into a double register.
140 let isPredicable = 1 in
141 class T_Combine : ALU32_rr<(outs DoubleRegs:$dst),
142 (ins IntRegs:$src1, IntRegs:$src2),
143 "$dst = combine($src1, $src2)",
144 [(set (i64 DoubleRegs:$dst),
145 (i64 (HexagonWrapperCombineRR (i32 IntRegs:$src1),
146 (i32 IntRegs:$src2))))]>;
148 multiclass Combine_base {
149 let BaseOpcode = "combine" in {
150 def NAME : T_Combine;
151 let neverHasSideEffects = 1, isPredicated = 1 in {
152 defm Pt : ALU32_Pred<"combine", DoubleRegs, 0>;
153 defm NotPt : ALU32_Pred<"combine", DoubleRegs, 1>;
158 defm COMBINE_rr : Combine_base, PredNewRel;
160 // Combines the two immediates SRC1 and SRC2 into a double register.
161 class COMBINE_imm<Operand imm1, Operand imm2, PatLeaf pat1, PatLeaf pat2> :
162 ALU32_ii<(outs DoubleRegs:$dst), (ins imm1:$src1, imm2:$src2),
163 "$dst = combine(#$src1, #$src2)",
164 [(set (i64 DoubleRegs:$dst),
165 (i64 (HexagonWrapperCombineII (i32 pat1:$src1), (i32 pat2:$src2))))]>;
167 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8 in
168 def COMBINE_Ii : COMBINE_imm<s8Ext, s8Imm, s8ExtPred, s8ImmPred>;
170 //===----------------------------------------------------------------------===//
171 // ALU32/ALU (ADD with register-immediate form)
172 //===----------------------------------------------------------------------===//
173 multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
174 let isPredicatedNew = isPredNew in
175 def NAME : ALU32_ri<(outs IntRegs:$dst),
176 (ins PredRegs:$src1, IntRegs:$src2, s8Ext: $src3),
177 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
178 ") $dst = ")#mnemonic#"($src2, #$src3)",
182 multiclass ALU32ri_Pred<string mnemonic, bit PredNot> {
183 let isPredicatedFalse = PredNot in {
184 defm _c#NAME : ALU32ri_Pbase<mnemonic, PredNot, 0>;
186 defm _cdn#NAME : ALU32ri_Pbase<mnemonic, PredNot, 1>;
190 let isExtendable = 1, InputType = "imm" in
191 multiclass ALU32ri_base<string mnemonic, string CextOp, SDNode OpNode> {
192 let CextOpcode = CextOp, BaseOpcode = CextOp#_ri in {
193 let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
195 def NAME : ALU32_ri<(outs IntRegs:$dst),
196 (ins IntRegs:$src1, s16Ext:$src2),
197 "$dst = "#mnemonic#"($src1, #$src2)",
198 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
199 (s16ExtPred:$src2)))]>;
201 let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
202 neverHasSideEffects = 1, isPredicated = 1 in {
203 defm Pt : ALU32ri_Pred<mnemonic, 0>;
204 defm NotPt : ALU32ri_Pred<mnemonic, 1>;
209 defm ADD_ri : ALU32ri_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
211 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
212 CextOpcode = "OR", InputType = "imm" in
213 def OR_ri : ALU32_ri<(outs IntRegs:$dst),
214 (ins IntRegs:$src1, s10Ext:$src2),
215 "$dst = or($src1, #$src2)",
216 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
217 s10ExtPred:$src2))]>, ImmRegRel;
219 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
220 InputType = "imm", CextOpcode = "AND" in
221 def AND_ri : ALU32_ri<(outs IntRegs:$dst),
222 (ins IntRegs:$src1, s10Ext:$src2),
223 "$dst = and($src1, #$src2)",
224 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
225 s10ExtPred:$src2))]>, ImmRegRel;
228 let neverHasSideEffects = 1 in
229 def NOP : ALU32_rr<(outs), (ins),
233 // Rd32=sub(#s10,Rs32)
234 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
235 CextOpcode = "SUB", InputType = "imm" in
236 def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
237 (ins s10Ext:$src1, IntRegs:$src2),
238 "$dst = sub(#$src1, $src2)",
239 [(set IntRegs:$dst, (sub s10ExtPred:$src1, IntRegs:$src2))]>,
242 // Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
243 def : Pat<(not (i32 IntRegs:$src1)),
244 (SUB_ri -1, (i32 IntRegs:$src1))>;
246 // Rd = neg(Rs) gets mapped to Rd=sub(#0, Rs).
247 // Pattern definition for 'neg' was not necessary.
249 multiclass TFR_Pred<bit PredNot> {
250 let isPredicatedFalse = PredNot in {
251 def _c#NAME : ALU32_rr<(outs IntRegs:$dst),
252 (ins PredRegs:$src1, IntRegs:$src2),
253 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
256 let isPredicatedNew = 1 in
257 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
258 (ins PredRegs:$src1, IntRegs:$src2),
259 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
264 let InputType = "reg", neverHasSideEffects = 1 in
265 multiclass TFR_base<string CextOp> {
266 let CextOpcode = CextOp, BaseOpcode = CextOp in {
267 let isPredicable = 1 in
268 def NAME : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
272 let isPredicated = 1 in {
273 defm Pt : TFR_Pred<0>;
274 defm NotPt : TFR_Pred<1>;
279 class T_TFR64_Pred<bit PredNot, bit isPredNew>
280 : ALU32_rr<(outs DoubleRegs:$dst),
281 (ins PredRegs:$src1, DoubleRegs:$src2),
282 !if(PredNot, "if (!$src1", "if ($src1")#
283 !if(isPredNew, ".new) ", ") ")#"$dst = $src2", []>
290 let Inst{27-24} = 0b1101;
291 let Inst{13} = isPredNew;
292 let Inst{7} = PredNot;
294 let Inst{6-5} = src1;
295 let Inst{20-17} = src2{4-1};
297 let Inst{12-9} = src2{4-1};
301 multiclass TFR64_Pred<bit PredNot> {
302 let isPredicatedFalse = PredNot in {
303 def _c#NAME : T_TFR64_Pred<PredNot, 0>;
305 let isPredicatedNew = 1 in
306 def _cdn#NAME : T_TFR64_Pred<PredNot, 1>; // Predicate new
310 let neverHasSideEffects = 1 in
311 multiclass TFR64_base<string BaseName> {
312 let BaseOpcode = BaseName in {
313 let isPredicable = 1 in
314 def NAME : ALU32Inst <(outs DoubleRegs:$dst),
315 (ins DoubleRegs:$src1),
321 let Inst{27-23} = 0b01010;
323 let Inst{20-17} = src1{4-1};
325 let Inst{12-9} = src1{4-1};
329 let isPredicated = 1 in {
330 defm Pt : TFR64_Pred<0>;
331 defm NotPt : TFR64_Pred<1>;
336 multiclass TFRI_Pred<bit PredNot> {
337 let isMoveImm = 1, isPredicatedFalse = PredNot in {
338 def _c#NAME : ALU32_ri<(outs IntRegs:$dst),
339 (ins PredRegs:$src1, s12Ext:$src2),
340 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = #$src2",
344 let isPredicatedNew = 1 in
345 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
346 (ins PredRegs:$src1, s12Ext:$src2),
347 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = #$src2",
352 let InputType = "imm", isExtendable = 1, isExtentSigned = 1 in
353 multiclass TFRI_base<string CextOp> {
354 let CextOpcode = CextOp, BaseOpcode = CextOp#I in {
355 let isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16,
356 isMoveImm = 1, isPredicable = 1, isReMaterializable = 1 in
357 def NAME : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
359 [(set (i32 IntRegs:$dst), s16ExtPred:$src1)]>;
361 let opExtendable = 2, opExtentBits = 12, neverHasSideEffects = 1,
362 isPredicated = 1 in {
363 defm Pt : TFRI_Pred<0>;
364 defm NotPt : TFRI_Pred<1>;
369 defm TFRI : TFRI_base<"TFR">, ImmRegRel, PredNewRel;
370 defm TFR : TFR_base<"TFR">, ImmRegRel, PredNewRel;
371 defm TFR64 : TFR64_base<"TFR64">, PredNewRel;
373 // Transfer control register.
374 let neverHasSideEffects = 1 in
375 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
378 //===----------------------------------------------------------------------===//
380 //===----------------------------------------------------------------------===//
383 //===----------------------------------------------------------------------===//
385 //===----------------------------------------------------------------------===//
387 let neverHasSideEffects = 1 in
388 def COMBINE_ii : ALU32_ii<(outs DoubleRegs:$dst),
389 (ins s8Imm:$src1, s8Imm:$src2),
390 "$dst = combine(#$src1, #$src2)",
394 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
397 "$dst = vmux($src1, $src2, $src3)",
400 let CextOpcode = "MUX", InputType = "reg" in
401 def MUX_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
402 IntRegs:$src2, IntRegs:$src3),
403 "$dst = mux($src1, $src2, $src3)",
404 [(set (i32 IntRegs:$dst),
405 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
406 (i32 IntRegs:$src3))))]>, ImmRegRel;
408 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
409 CextOpcode = "MUX", InputType = "imm" in
410 def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
412 "$dst = mux($src1, #$src2, $src3)",
413 [(set (i32 IntRegs:$dst),
414 (i32 (select (i1 PredRegs:$src1), s8ExtPred:$src2,
415 (i32 IntRegs:$src3))))]>, ImmRegRel;
417 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
418 CextOpcode = "MUX", InputType = "imm" in
419 def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
421 "$dst = mux($src1, $src2, #$src3)",
422 [(set (i32 IntRegs:$dst),
423 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
424 s8ExtPred:$src3)))]>, ImmRegRel;
426 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
427 def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
429 "$dst = mux($src1, #$src2, #$src3)",
430 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
432 s8ImmPred:$src3)))]>;
434 // ALU32 - aslh, asrh, sxtb, sxth, zxtb, zxth
435 multiclass ALU32_2op_Pbase<string mnemonic, bit isNot, bit isPredNew> {
436 let isPredicatedNew = isPredNew in
437 def NAME : ALU32Inst<(outs IntRegs:$dst),
438 (ins PredRegs:$src1, IntRegs:$src2),
439 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
440 ") $dst = ")#mnemonic#"($src2)">,
444 multiclass ALU32_2op_Pred<string mnemonic, bit PredNot> {
445 let isPredicatedFalse = PredNot in {
446 defm _c#NAME : ALU32_2op_Pbase<mnemonic, PredNot, 0>;
448 defm _cdn#NAME : ALU32_2op_Pbase<mnemonic, PredNot, 1>;
452 multiclass ALU32_2op_base<string mnemonic> {
453 let BaseOpcode = mnemonic in {
454 let isPredicable = 1, neverHasSideEffects = 1 in
455 def NAME : ALU32Inst<(outs IntRegs:$dst),
457 "$dst = "#mnemonic#"($src1)">;
459 let Predicates = [HasV4T], validSubTargets = HasV4SubT, isPredicated = 1,
460 neverHasSideEffects = 1 in {
461 defm Pt_V4 : ALU32_2op_Pred<mnemonic, 0>;
462 defm NotPt_V4 : ALU32_2op_Pred<mnemonic, 1>;
467 defm ASLH : ALU32_2op_base<"aslh">, PredNewRel;
468 defm ASRH : ALU32_2op_base<"asrh">, PredNewRel;
469 defm SXTB : ALU32_2op_base<"sxtb">, PredNewRel;
470 defm SXTH : ALU32_2op_base<"sxth">, PredNewRel;
471 defm ZXTB : ALU32_2op_base<"zxtb">, PredNewRel;
472 defm ZXTH : ALU32_2op_base<"zxth">, PredNewRel;
474 def : Pat <(shl (i32 IntRegs:$src1), (i32 16)),
475 (ASLH IntRegs:$src1)>;
477 def : Pat <(sra (i32 IntRegs:$src1), (i32 16)),
478 (ASRH IntRegs:$src1)>;
480 def : Pat <(sext_inreg (i32 IntRegs:$src1), i8),
481 (SXTB IntRegs:$src1)>;
483 def : Pat <(sext_inreg (i32 IntRegs:$src1), i16),
484 (SXTH IntRegs:$src1)>;
486 //===----------------------------------------------------------------------===//
488 //===----------------------------------------------------------------------===//
491 //===----------------------------------------------------------------------===//
493 //===----------------------------------------------------------------------===//
496 defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", "CMPGTU", setugt>, ImmRegRel;
497 defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", "CMPGT", setgt>, ImmRegRel;
498 defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", "CMPEQ", seteq>, ImmRegRel;
500 // SDNode for converting immediate C to C-1.
501 def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
502 // Return the byte immediate const-1 as an SDNode.
503 int32_t imm = N->getSExtValue();
504 return XformSToSM1Imm(imm);
507 // SDNode for converting immediate C to C-1.
508 def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
509 // Return the byte immediate const-1 as an SDNode.
510 uint32_t imm = N->getZExtValue();
511 return XformUToUM1Imm(imm);
514 def CTLZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
516 [(set (i32 IntRegs:$dst), (ctlz (i32 IntRegs:$src1)))]>;
518 def CTTZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
520 [(set (i32 IntRegs:$dst), (cttz (i32 IntRegs:$src1)))]>;
522 def CTLZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
524 [(set (i32 IntRegs:$dst), (i32 (trunc (ctlz (i64 DoubleRegs:$src1)))))]>;
526 def CTTZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
528 [(set (i32 IntRegs:$dst), (i32 (trunc (cttz (i64 DoubleRegs:$src1)))))]>;
530 def TSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
531 "$dst = tstbit($src1, $src2)",
532 [(set (i1 PredRegs:$dst),
533 (setne (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>;
535 def TSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
536 "$dst = tstbit($src1, $src2)",
537 [(set (i1 PredRegs:$dst),
538 (setne (and (shl 1, (u5ImmPred:$src2)), (i32 IntRegs:$src1)), 0))]>;
540 //===----------------------------------------------------------------------===//
542 //===----------------------------------------------------------------------===//
545 //===----------------------------------------------------------------------===//
547 //===----------------------------------------------------------------------===//
549 def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
551 "$dst = add($src1, $src2)",
552 [(set (i64 DoubleRegs:$dst), (add (i64 DoubleRegs:$src1),
553 (i64 DoubleRegs:$src2)))]>;
558 defm CMPEHexagon4 : CMP64_rr<"cmp.eq", seteq>;
559 defm CMPGT64 : CMP64_rr<"cmp.gt", setgt>;
560 defm CMPGTU64 : CMP64_rr<"cmp.gtu", setugt>;
562 // Logical operations.
563 def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
565 "$dst = and($src1, $src2)",
566 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
567 (i64 DoubleRegs:$src2)))]>;
569 def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
571 "$dst = or($src1, $src2)",
572 [(set (i64 DoubleRegs:$dst), (or (i64 DoubleRegs:$src1),
573 (i64 DoubleRegs:$src2)))]>;
575 def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
577 "$dst = xor($src1, $src2)",
578 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
579 (i64 DoubleRegs:$src2)))]>;
582 def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
583 "$dst = max($src2, $src1)",
584 [(set (i32 IntRegs:$dst),
585 (i32 (select (i1 (setlt (i32 IntRegs:$src2),
586 (i32 IntRegs:$src1))),
587 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
589 def MAXUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
590 "$dst = maxu($src2, $src1)",
591 [(set (i32 IntRegs:$dst),
592 (i32 (select (i1 (setult (i32 IntRegs:$src2),
593 (i32 IntRegs:$src1))),
594 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
596 def MAXd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
598 "$dst = max($src2, $src1)",
599 [(set (i64 DoubleRegs:$dst),
600 (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
601 (i64 DoubleRegs:$src1))),
602 (i64 DoubleRegs:$src1),
603 (i64 DoubleRegs:$src2))))]>;
605 def MAXUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
607 "$dst = maxu($src2, $src1)",
608 [(set (i64 DoubleRegs:$dst),
609 (i64 (select (i1 (setult (i64 DoubleRegs:$src2),
610 (i64 DoubleRegs:$src1))),
611 (i64 DoubleRegs:$src1),
612 (i64 DoubleRegs:$src2))))]>;
615 def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
616 "$dst = min($src2, $src1)",
617 [(set (i32 IntRegs:$dst),
618 (i32 (select (i1 (setgt (i32 IntRegs:$src2),
619 (i32 IntRegs:$src1))),
620 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
622 def MINUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
623 "$dst = minu($src2, $src1)",
624 [(set (i32 IntRegs:$dst),
625 (i32 (select (i1 (setugt (i32 IntRegs:$src2),
626 (i32 IntRegs:$src1))),
627 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
629 def MINd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
631 "$dst = min($src2, $src1)",
632 [(set (i64 DoubleRegs:$dst),
633 (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
634 (i64 DoubleRegs:$src1))),
635 (i64 DoubleRegs:$src1),
636 (i64 DoubleRegs:$src2))))]>;
638 def MINUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
640 "$dst = minu($src2, $src1)",
641 [(set (i64 DoubleRegs:$dst),
642 (i64 (select (i1 (setugt (i64 DoubleRegs:$src2),
643 (i64 DoubleRegs:$src1))),
644 (i64 DoubleRegs:$src1),
645 (i64 DoubleRegs:$src2))))]>;
648 def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
650 "$dst = sub($src1, $src2)",
651 [(set (i64 DoubleRegs:$dst), (sub (i64 DoubleRegs:$src1),
652 (i64 DoubleRegs:$src2)))]>;
654 // Subtract halfword.
656 //===----------------------------------------------------------------------===//
658 //===----------------------------------------------------------------------===//
660 //===----------------------------------------------------------------------===//
662 //===----------------------------------------------------------------------===//
664 //===----------------------------------------------------------------------===//
666 //===----------------------------------------------------------------------===//
668 //===----------------------------------------------------------------------===//
670 //===----------------------------------------------------------------------===//
672 //===----------------------------------------------------------------------===//
674 //===----------------------------------------------------------------------===//
676 //===----------------------------------------------------------------------===//
678 //===----------------------------------------------------------------------===//
679 // Logical reductions on predicates.
681 // Looping instructions.
683 // Pipelined looping instructions.
685 // Logical operations on predicates.
686 def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
687 "$dst = and($src1, $src2)",
688 [(set (i1 PredRegs:$dst), (and (i1 PredRegs:$src1),
689 (i1 PredRegs:$src2)))]>;
691 let neverHasSideEffects = 1 in
692 def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
694 "$dst = and($src1, !$src2)",
697 def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
698 "$dst = any8($src1)",
701 def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
702 "$dst = all8($src1)",
705 def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
707 "$dst = vitpack($src1, $src2)",
710 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
713 "$dst = valignb($src1, $src2, $src3)",
716 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
719 "$dst = vspliceb($src1, $src2, $src3)",
722 def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
723 "$dst = mask($src1)",
726 def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
728 [(set (i1 PredRegs:$dst), (not (i1 PredRegs:$src1)))]>;
730 def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
731 "$dst = or($src1, $src2)",
732 [(set (i1 PredRegs:$dst), (or (i1 PredRegs:$src1),
733 (i1 PredRegs:$src2)))]>;
735 def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
736 "$dst = xor($src1, $src2)",
737 [(set (i1 PredRegs:$dst), (xor (i1 PredRegs:$src1),
738 (i1 PredRegs:$src2)))]>;
741 // User control register transfer.
742 //===----------------------------------------------------------------------===//
744 //===----------------------------------------------------------------------===//
746 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
747 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
748 def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone,
751 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
752 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
754 let InputType = "imm", isBarrier = 1, isPredicable = 1,
755 Defs = [PC], isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
757 class T_JMP <dag InsDag, list<dag> JumpList = []>
758 : JInst<(outs), InsDag,
759 "jump $dst" , JumpList> {
764 let Inst{27-25} = 0b100;
765 let Inst{24-16} = dst{23-15};
766 let Inst{13-1} = dst{14-2};
769 let InputType = "imm", isExtendable = 1, opExtendable = 1, isExtentSigned = 1,
770 Defs = [PC], isPredicated = 1, opExtentBits = 17 in
771 class T_JMP_c <bit PredNot, bit isPredNew, bit isTaken>:
772 JInst<(outs ), (ins PredRegs:$src, brtarget:$dst),
773 !if(PredNot, "if (!$src", "if ($src")#
774 !if(isPredNew, ".new) ", ") ")#"jump"#
775 !if(isPredNew, !if(isTaken, ":t ", ":nt "), " ")#"$dst"> {
777 let isBrTaken = !if(isPredNew, !if(isTaken, "true", "false"), "");
778 let isPredicatedFalse = PredNot;
779 let isPredicatedNew = isPredNew;
785 let Inst{27-24} = 0b1100;
786 let Inst{21} = PredNot;
787 let Inst{12} = !if(isPredNew, isTaken, zero);
788 let Inst{11} = isPredNew;
790 let Inst{23-22} = dst{16-15};
791 let Inst{20-16} = dst{14-10};
792 let Inst{13} = dst{9};
793 let Inst{7-1} = dst{8-2};
796 let isBarrier = 1, Defs = [PC], isPredicable = 1, InputType = "reg" in
797 class T_JMPr<dag InsDag = (ins IntRegs:$dst)>
798 : JRInst<(outs ), InsDag,
804 let Inst{27-21} = 0b0010100;
805 let Inst{20-16} = dst;
808 let Defs = [PC], isPredicated = 1, InputType = "reg" in
809 class T_JMPr_c <bit PredNot, bit isPredNew, bit isTaken>:
810 JRInst <(outs ), (ins PredRegs:$src, IntRegs:$dst),
811 !if(PredNot, "if (!$src", "if ($src")#
812 !if(isPredNew, ".new) ", ") ")#"jumpr"#
813 !if(isPredNew, !if(isTaken, ":t ", ":nt "), " ")#"$dst"> {
815 let isBrTaken = !if(isPredNew, !if(isTaken, "true", "false"), "");
816 let isPredicatedFalse = PredNot;
817 let isPredicatedNew = isPredNew;
823 let Inst{27-22} = 0b001101;
824 let Inst{21} = PredNot;
825 let Inst{20-16} = dst;
826 let Inst{12} = !if(isPredNew, isTaken, zero);
827 let Inst{11} = isPredNew;
829 let Predicates = !if(isPredNew, [HasV3T], [HasV2T]);
830 let validSubTargets = !if(isPredNew, HasV3SubT, HasV2SubT);
833 multiclass JMP_Pred<bit PredNot> {
834 def _#NAME : T_JMP_c<PredNot, 0, 0>;
836 def _#NAME#new_t : T_JMP_c<PredNot, 1, 1>; // taken
837 def _#NAME#new_nt : T_JMP_c<PredNot, 1, 0>; // not taken
840 multiclass JMP_base<string BaseOp> {
841 let BaseOpcode = BaseOp in {
842 def NAME : T_JMP<(ins brtarget:$dst), [(br bb:$dst)]>;
843 defm t : JMP_Pred<0>;
844 defm f : JMP_Pred<1>;
848 multiclass JMPR_Pred<bit PredNot> {
849 def NAME: T_JMPr_c<PredNot, 0, 0>;
851 def NAME#new_tV3 : T_JMPr_c<PredNot, 1, 1>; // taken
852 def NAME#new_ntV3 : T_JMPr_c<PredNot, 1, 0>; // not taken
855 multiclass JMPR_base<string BaseOp> {
856 let BaseOpcode = BaseOp in {
858 defm _t : JMPR_Pred<0>;
859 defm _f : JMPR_Pred<1>;
863 let isTerminator = 1, neverHasSideEffects = 1 in {
865 defm JMP : JMP_base<"JMP">, PredNewRel;
867 let isBranch = 1, isIndirectBranch = 1 in
868 defm JMPR : JMPR_base<"JMPr">, PredNewRel;
870 let isReturn = 1, isCodeGenOnly = 1 in
871 defm JMPret : JMPR_base<"JMPret">, PredNewRel;
877 def : Pat <(brcond (i1 PredRegs:$src1), bb:$offset),
878 (JMP_t (i1 PredRegs:$src1), bb:$offset)>;
880 // A return through builtin_eh_return.
881 let isReturn = 1, isTerminator = 1, isBarrier = 1, neverHasSideEffects = 1,
882 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
883 def EH_RETURN_JMPR : T_JMPr;
885 def : Pat<(eh_return),
886 (EH_RETURN_JMPR (i32 R31))>;
888 def : Pat<(HexagonBR_JT (i32 IntRegs:$dst)),
889 (JMPR (i32 IntRegs:$dst))>;
891 def : Pat<(brind (i32 IntRegs:$dst)),
892 (JMPR (i32 IntRegs:$dst))>;
894 //===----------------------------------------------------------------------===//
896 //===----------------------------------------------------------------------===//
898 //===----------------------------------------------------------------------===//
900 //===----------------------------------------------------------------------===//
902 // Load -- MEMri operand
903 multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
904 bit isNot, bit isPredNew> {
905 let isPredicatedNew = isPredNew in
906 def NAME : LDInst2<(outs RC:$dst),
907 (ins PredRegs:$src1, MEMri:$addr),
908 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
909 ") ")#"$dst = "#mnemonic#"($addr)",
913 multiclass LD_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
914 let isPredicatedFalse = PredNot in {
915 defm _c#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
917 defm _cdn#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
921 let isExtendable = 1, neverHasSideEffects = 1 in
922 multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
923 bits<5> ImmBits, bits<5> PredImmBits> {
925 let CextOpcode = CextOp, BaseOpcode = CextOp in {
926 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
928 def NAME : LDInst2<(outs RC:$dst), (ins MEMri:$addr),
929 "$dst = "#mnemonic#"($addr)",
932 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
933 isPredicated = 1 in {
934 defm Pt : LD_MEMri_Pred<mnemonic, RC, 0 >;
935 defm NotPt : LD_MEMri_Pred<mnemonic, RC, 1 >;
940 let addrMode = BaseImmOffset, isMEMri = "true" in {
941 let accessSize = ByteAccess in {
942 defm LDrib: LD_MEMri < "memb", "LDrib", IntRegs, 11, 6>, AddrModeRel;
943 defm LDriub: LD_MEMri < "memub" , "LDriub", IntRegs, 11, 6>, AddrModeRel;
946 let accessSize = HalfWordAccess in {
947 defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
948 defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel;
951 let accessSize = WordAccess in
952 defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;
954 let accessSize = DoubleWordAccess in
955 defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;
958 def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
959 (LDrib ADDRriS11_0:$addr) >;
961 def : Pat < (i32 (zextloadi8 ADDRriS11_0:$addr)),
962 (LDriub ADDRriS11_0:$addr) >;
964 def : Pat < (i32 (sextloadi16 ADDRriS11_1:$addr)),
965 (LDrih ADDRriS11_1:$addr) >;
967 def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)),
968 (LDriuh ADDRriS11_1:$addr) >;
970 def : Pat < (i32 (load ADDRriS11_2:$addr)),
971 (LDriw ADDRriS11_2:$addr) >;
973 def : Pat < (i64 (load ADDRriS11_3:$addr)),
974 (LDrid ADDRriS11_3:$addr) >;
977 // Load - Base with Immediate offset addressing mode
978 multiclass LD_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
979 bit isNot, bit isPredNew> {
980 let isPredicatedNew = isPredNew in
981 def NAME : LDInst2<(outs RC:$dst),
982 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
983 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
984 ") ")#"$dst = "#mnemonic#"($src2+#$src3)",
988 multiclass LD_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
990 let isPredicatedFalse = PredNot in {
991 defm _c#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
993 defm _cdn#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
997 let isExtendable = 1, neverHasSideEffects = 1 in
998 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
999 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
1000 bits<5> PredImmBits> {
1002 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1003 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
1004 isPredicable = 1, AddedComplexity = 20 in
1005 def NAME : LDInst2<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1006 "$dst = "#mnemonic#"($src1+#$offset)",
1009 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
1010 isPredicated = 1 in {
1011 defm Pt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 0 >;
1012 defm NotPt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 1 >;
1017 let addrMode = BaseImmOffset in {
1018 let accessSize = ByteAccess in {
1019 defm LDrib_indexed: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext,
1020 11, 6>, AddrModeRel;
1021 defm LDriub_indexed: LD_Idxd <"memub" , "LDriub", IntRegs, s11_0Ext, u6_0Ext,
1022 11, 6>, AddrModeRel;
1024 let accessSize = HalfWordAccess in {
1025 defm LDrih_indexed: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
1026 12, 7>, AddrModeRel;
1027 defm LDriuh_indexed: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext,
1028 12, 7>, AddrModeRel;
1030 let accessSize = WordAccess in
1031 defm LDriw_indexed: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
1032 13, 8>, AddrModeRel;
1034 let accessSize = DoubleWordAccess in
1035 defm LDrid_indexed: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,
1036 14, 9>, AddrModeRel;
1039 let AddedComplexity = 20 in {
1040 def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
1041 (LDrib_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
1043 def : Pat < (i32 (zextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
1044 (LDriub_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
1046 def : Pat < (i32 (sextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
1047 (LDrih_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
1049 def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
1050 (LDriuh_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
1052 def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
1053 (LDriw_indexed IntRegs:$src1, s11_2ExtPred:$offset) >;
1055 def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
1056 (LDrid_indexed IntRegs:$src1, s11_3ExtPred:$offset) >;
1059 //===----------------------------------------------------------------------===//
1060 // Post increment load
1061 //===----------------------------------------------------------------------===//
1063 multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1064 bit isNot, bit isPredNew> {
1065 let isPredicatedNew = isPredNew in
1066 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1067 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1068 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1069 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1074 multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,
1075 Operand ImmOp, bit PredNot> {
1076 let isPredicatedFalse = PredNot in {
1077 defm _c#NAME : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1079 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1080 defm _cdn#NAME#_V4 : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1084 multiclass LD_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1087 let BaseOpcode = "POST_"#BaseOp in {
1088 let isPredicable = 1 in
1089 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1090 (ins IntRegs:$src1, ImmOp:$offset),
1091 "$dst = "#mnemonic#"($src1++#$offset)",
1095 let isPredicated = 1 in {
1096 defm Pt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1097 defm NotPt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1102 let hasCtrlDep = 1, neverHasSideEffects = 1, addrMode = PostInc in {
1103 defm POST_LDrib : LD_PostInc<"memb", "LDrib", IntRegs, s4_0Imm>,
1105 defm POST_LDriub : LD_PostInc<"memub", "LDriub", IntRegs, s4_0Imm>,
1107 defm POST_LDrih : LD_PostInc<"memh", "LDrih", IntRegs, s4_1Imm>,
1109 defm POST_LDriuh : LD_PostInc<"memuh", "LDriuh", IntRegs, s4_1Imm>,
1111 defm POST_LDriw : LD_PostInc<"memw", "LDriw", IntRegs, s4_2Imm>,
1113 defm POST_LDrid : LD_PostInc<"memd", "LDrid", DoubleRegs, s4_3Imm>,
1117 def : Pat< (i32 (extloadi1 ADDRriS11_0:$addr)),
1118 (i32 (LDrib ADDRriS11_0:$addr)) >;
1120 // Load byte any-extend.
1121 def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
1122 (i32 (LDrib ADDRriS11_0:$addr)) >;
1124 // Indexed load byte any-extend.
1125 let AddedComplexity = 20 in
1126 def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1127 (i32 (LDrib_indexed IntRegs:$src1, s11_0ImmPred:$offset)) >;
1129 def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
1130 (i32 (LDrih ADDRriS11_1:$addr))>;
1132 let AddedComplexity = 20 in
1133 def : Pat < (i32 (extloadi16 (add IntRegs:$src1, s11_1ImmPred:$offset))),
1134 (i32 (LDrih_indexed IntRegs:$src1, s11_1ImmPred:$offset)) >;
1136 let AddedComplexity = 10 in
1137 def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
1138 (i32 (LDriub ADDRriS11_0:$addr))>;
1140 let AddedComplexity = 20 in
1141 def : Pat < (i32 (zextloadi1 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1142 (i32 (LDriub_indexed IntRegs:$src1, s11_0ImmPred:$offset))>;
1145 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
1146 isPseudo = 1, Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1147 def LDriw_pred : LDInst2<(outs PredRegs:$dst),
1149 "Error; should not emit",
1152 // Deallocate stack frame.
1153 let Defs = [R29, R30, R31], Uses = [R29], neverHasSideEffects = 1 in {
1154 def DEALLOCFRAME : LDInst2<(outs), (ins),
1159 // Load and unpack bytes to halfwords.
1160 //===----------------------------------------------------------------------===//
1162 //===----------------------------------------------------------------------===//
1164 //===----------------------------------------------------------------------===//
1166 //===----------------------------------------------------------------------===//
1167 //===----------------------------------------------------------------------===//
1169 //===----------------------------------------------------------------------===//
1171 //===----------------------------------------------------------------------===//
1173 //===----------------------------------------------------------------------===//
1174 //===----------------------------------------------------------------------===//
1176 //===----------------------------------------------------------------------===//
1178 //===----------------------------------------------------------------------===//
1180 //===----------------------------------------------------------------------===//
1181 // Multiply and use lower result.
1183 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in
1184 def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Ext:$src2),
1185 "$dst =+ mpyi($src1, #$src2)",
1186 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1187 u8ExtPred:$src2))]>;
1190 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1191 "$dst =- mpyi($src1, #$src2)",
1192 [(set (i32 IntRegs:$dst), (ineg (mul (i32 IntRegs:$src1),
1193 u8ImmPred:$src2)))]>;
1196 // s9 is NOT the same as m9 - but it works.. so far.
1197 // Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
1198 // depending on the value of m9. See Arch Spec.
1199 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
1200 CextOpcode = "MPYI", InputType = "imm" in
1201 def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
1202 "$dst = mpyi($src1, #$src2)",
1203 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1204 s9ExtPred:$src2))]>, ImmRegRel;
1207 let CextOpcode = "MPYI", InputType = "reg" in
1208 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1209 "$dst = mpyi($src1, $src2)",
1210 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1211 (i32 IntRegs:$src2)))]>, ImmRegRel;
1214 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8,
1215 CextOpcode = "MPYI_acc", InputType = "imm" in
1216 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
1217 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1218 "$dst += mpyi($src2, #$src3)",
1219 [(set (i32 IntRegs:$dst),
1220 (add (mul (i32 IntRegs:$src2), u8ExtPred:$src3),
1221 (i32 IntRegs:$src1)))],
1222 "$src1 = $dst">, ImmRegRel;
1225 let CextOpcode = "MPYI_acc", InputType = "reg" in
1226 def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
1227 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1228 "$dst += mpyi($src2, $src3)",
1229 [(set (i32 IntRegs:$dst),
1230 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1231 (i32 IntRegs:$src1)))],
1232 "$src1 = $dst">, ImmRegRel;
1235 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8 in
1236 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
1237 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1238 "$dst -= mpyi($src2, #$src3)",
1239 [(set (i32 IntRegs:$dst),
1240 (sub (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1241 u8ExtPred:$src3)))],
1244 // Multiply and use upper result.
1245 // Rd=mpy(Rs,Rt.H):<<1:rnd:sat
1246 // Rd=mpy(Rs,Rt.L):<<1:rnd:sat
1248 def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1249 "$dst = mpy($src1, $src2)",
1250 [(set (i32 IntRegs:$dst), (mulhs (i32 IntRegs:$src1),
1251 (i32 IntRegs:$src2)))]>;
1253 // Rd=mpy(Rs,Rt):rnd
1255 def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1256 "$dst = mpyu($src1, $src2)",
1257 [(set (i32 IntRegs:$dst), (mulhu (i32 IntRegs:$src1),
1258 (i32 IntRegs:$src2)))]>;
1260 // Multiply and use full result.
1262 def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1263 "$dst = mpyu($src1, $src2)",
1264 [(set (i64 DoubleRegs:$dst),
1265 (mul (i64 (anyext (i32 IntRegs:$src1))),
1266 (i64 (anyext (i32 IntRegs:$src2)))))]>;
1269 def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1270 "$dst = mpy($src1, $src2)",
1271 [(set (i64 DoubleRegs:$dst),
1272 (mul (i64 (sext (i32 IntRegs:$src1))),
1273 (i64 (sext (i32 IntRegs:$src2)))))]>;
1275 // Multiply and accumulate, use full result.
1276 // Rxx[+-]=mpy(Rs,Rt)
1278 def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
1279 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1280 "$dst += mpy($src2, $src3)",
1281 [(set (i64 DoubleRegs:$dst),
1282 (add (mul (i64 (sext (i32 IntRegs:$src2))),
1283 (i64 (sext (i32 IntRegs:$src3)))),
1284 (i64 DoubleRegs:$src1)))],
1288 def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
1289 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1290 "$dst -= mpy($src2, $src3)",
1291 [(set (i64 DoubleRegs:$dst),
1292 (sub (i64 DoubleRegs:$src1),
1293 (mul (i64 (sext (i32 IntRegs:$src2))),
1294 (i64 (sext (i32 IntRegs:$src3))))))],
1297 // Rxx[+-]=mpyu(Rs,Rt)
1299 def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1300 IntRegs:$src2, IntRegs:$src3),
1301 "$dst += mpyu($src2, $src3)",
1302 [(set (i64 DoubleRegs:$dst),
1303 (add (mul (i64 (anyext (i32 IntRegs:$src2))),
1304 (i64 (anyext (i32 IntRegs:$src3)))),
1305 (i64 DoubleRegs:$src1)))], "$src1 = $dst">;
1308 def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
1309 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1310 "$dst -= mpyu($src2, $src3)",
1311 [(set (i64 DoubleRegs:$dst),
1312 (sub (i64 DoubleRegs:$src1),
1313 (mul (i64 (anyext (i32 IntRegs:$src2))),
1314 (i64 (anyext (i32 IntRegs:$src3))))))],
1318 let InputType = "reg", CextOpcode = "ADD_acc" in
1319 def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1320 IntRegs:$src2, IntRegs:$src3),
1321 "$dst += add($src2, $src3)",
1322 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1323 (i32 IntRegs:$src3)),
1324 (i32 IntRegs:$src1)))],
1325 "$src1 = $dst">, ImmRegRel;
1327 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
1328 InputType = "imm", CextOpcode = "ADD_acc" in
1329 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1330 IntRegs:$src2, s8Ext:$src3),
1331 "$dst += add($src2, #$src3)",
1332 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1333 s8_16ExtPred:$src3),
1334 (i32 IntRegs:$src1)))],
1335 "$src1 = $dst">, ImmRegRel;
1337 let CextOpcode = "SUB_acc", InputType = "reg" in
1338 def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1339 IntRegs:$src2, IntRegs:$src3),
1340 "$dst -= add($src2, $src3)",
1341 [(set (i32 IntRegs:$dst),
1342 (sub (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1343 (i32 IntRegs:$src3))))],
1344 "$src1 = $dst">, ImmRegRel;
1346 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
1347 CextOpcode = "SUB_acc", InputType = "imm" in
1348 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1349 IntRegs:$src2, s8Ext:$src3),
1350 "$dst -= add($src2, #$src3)",
1351 [(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
1352 (add (i32 IntRegs:$src2),
1353 s8_16ExtPred:$src3)))],
1354 "$src1 = $dst">, ImmRegRel;
1356 //===----------------------------------------------------------------------===//
1358 //===----------------------------------------------------------------------===//
1360 //===----------------------------------------------------------------------===//
1362 //===----------------------------------------------------------------------===//
1363 //===----------------------------------------------------------------------===//
1365 //===----------------------------------------------------------------------===//
1367 //===----------------------------------------------------------------------===//
1369 //===----------------------------------------------------------------------===//
1370 //===----------------------------------------------------------------------===//
1372 //===----------------------------------------------------------------------===//
1374 //===----------------------------------------------------------------------===//
1376 //===----------------------------------------------------------------------===//
1377 //===----------------------------------------------------------------------===//
1379 //===----------------------------------------------------------------------===//
1381 //===----------------------------------------------------------------------===//
1383 //===----------------------------------------------------------------------===//
1385 // Store doubleword.
1387 //===----------------------------------------------------------------------===//
1388 // Post increment store
1389 //===----------------------------------------------------------------------===//
1391 multiclass ST_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1392 bit isNot, bit isPredNew> {
1393 let isPredicatedNew = isPredNew in
1394 def NAME : STInst2PI<(outs IntRegs:$dst),
1395 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
1396 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1397 ") ")#mnemonic#"($src2++#$offset) = $src3",
1402 multiclass ST_PostInc_Pred<string mnemonic, RegisterClass RC,
1403 Operand ImmOp, bit PredNot> {
1404 let isPredicatedFalse = PredNot in {
1405 defm _c#NAME : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1407 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1408 defm _cdn#NAME#_V4 : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1412 let hasCtrlDep = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1413 multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1416 let hasCtrlDep = 1, BaseOpcode = "POST_"#BaseOp in {
1417 let isPredicable = 1 in
1418 def NAME : STInst2PI<(outs IntRegs:$dst),
1419 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
1420 mnemonic#"($src1++#$offset) = $src2",
1424 let isPredicated = 1 in {
1425 defm Pt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1426 defm NotPt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1431 defm POST_STbri: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel;
1432 defm POST_SThri: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
1433 defm POST_STwri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
1435 let isNVStorable = 0 in
1436 defm POST_STdri: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm>, AddrModeRel;
1438 def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2,
1439 s4_3ImmPred:$offset),
1440 (POST_STbri IntRegs:$src2, s4_0ImmPred:$offset, IntRegs:$src1)>;
1442 def : Pat<(post_truncsti16 (i32 IntRegs:$src1), IntRegs:$src2,
1443 s4_3ImmPred:$offset),
1444 (POST_SThri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
1446 def : Pat<(post_store (i32 IntRegs:$src1), IntRegs:$src2, s4_2ImmPred:$offset),
1447 (POST_STwri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
1449 def : Pat<(post_store (i64 DoubleRegs:$src1), IntRegs:$src2,
1450 s4_3ImmPred:$offset),
1451 (POST_STdri IntRegs:$src2, s4_3ImmPred:$offset, DoubleRegs:$src1)>;
1453 //===----------------------------------------------------------------------===//
1454 // multiclass for the store instructions with MEMri operand.
1455 //===----------------------------------------------------------------------===//
1456 multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot,
1458 let isPredicatedNew = isPredNew in
1459 def NAME : STInst2<(outs),
1460 (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
1461 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1462 ") ")#mnemonic#"($addr) = $src2",
1466 multiclass ST_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1467 let isPredicatedFalse = PredNot in {
1468 defm _c#NAME : ST_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
1471 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1472 defm _cdn#NAME#_V4 : ST_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
1476 let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1477 multiclass ST_MEMri<string mnemonic, string CextOp, RegisterClass RC,
1478 bits<5> ImmBits, bits<5> PredImmBits> {
1480 let CextOpcode = CextOp, BaseOpcode = CextOp in {
1481 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1483 def NAME : STInst2<(outs),
1484 (ins MEMri:$addr, RC:$src),
1485 mnemonic#"($addr) = $src",
1488 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
1489 isPredicated = 1 in {
1490 defm Pt : ST_MEMri_Pred<mnemonic, RC, 0>;
1491 defm NotPt : ST_MEMri_Pred<mnemonic, RC, 1>;
1496 let addrMode = BaseImmOffset, isMEMri = "true" in {
1497 let accessSize = ByteAccess in
1498 defm STrib: ST_MEMri < "memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
1500 let accessSize = HalfWordAccess in
1501 defm STrih: ST_MEMri < "memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
1503 let accessSize = WordAccess in
1504 defm STriw: ST_MEMri < "memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
1506 let accessSize = DoubleWordAccess, isNVStorable = 0 in
1507 defm STrid: ST_MEMri < "memd", "STrid", DoubleRegs, 14, 9>, AddrModeRel;
1510 def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
1511 (STrib ADDRriS11_0:$addr, (i32 IntRegs:$src1))>;
1513 def : Pat<(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr),
1514 (STrih ADDRriS11_1:$addr, (i32 IntRegs:$src1))>;
1516 def : Pat<(store (i32 IntRegs:$src1), ADDRriS11_2:$addr),
1517 (STriw ADDRriS11_2:$addr, (i32 IntRegs:$src1))>;
1519 def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
1520 (STrid ADDRriS11_3:$addr, (i64 DoubleRegs:$src1))>;
1523 //===----------------------------------------------------------------------===//
1524 // multiclass for the store instructions with base+immediate offset
1526 //===----------------------------------------------------------------------===//
1527 multiclass ST_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
1528 bit isNot, bit isPredNew> {
1529 let isPredicatedNew = isPredNew in
1530 def NAME : STInst2<(outs),
1531 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
1532 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1533 ") ")#mnemonic#"($src2+#$src3) = $src4",
1537 multiclass ST_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
1539 let isPredicatedFalse = PredNot, isPredicated = 1 in {
1540 defm _c#NAME : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
1543 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1544 defm _cdn#NAME#_V4 : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
1548 let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1549 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1550 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
1551 bits<5> PredImmBits> {
1553 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1554 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1556 def NAME : STInst2<(outs),
1557 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1558 mnemonic#"($src1+#$src2) = $src3",
1561 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits in {
1562 defm Pt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 0>;
1563 defm NotPt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 1>;
1568 let addrMode = BaseImmOffset, InputType = "reg" in {
1569 let accessSize = ByteAccess in
1570 defm STrib_indexed: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext,
1571 u6_0Ext, 11, 6>, AddrModeRel, ImmRegRel;
1573 let accessSize = HalfWordAccess in
1574 defm STrih_indexed: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext,
1575 u6_1Ext, 12, 7>, AddrModeRel, ImmRegRel;
1577 let accessSize = WordAccess in
1578 defm STriw_indexed: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext,
1579 u6_2Ext, 13, 8>, AddrModeRel, ImmRegRel;
1581 let accessSize = DoubleWordAccess, isNVStorable = 0 in
1582 defm STrid_indexed: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
1583 u6_3Ext, 14, 9>, AddrModeRel;
1586 let AddedComplexity = 10 in {
1587 def : Pat<(truncstorei8 (i32 IntRegs:$src1), (add IntRegs:$src2,
1588 s11_0ExtPred:$offset)),
1589 (STrib_indexed IntRegs:$src2, s11_0ImmPred:$offset,
1590 (i32 IntRegs:$src1))>;
1592 def : Pat<(truncstorei16 (i32 IntRegs:$src1), (add IntRegs:$src2,
1593 s11_1ExtPred:$offset)),
1594 (STrih_indexed IntRegs:$src2, s11_1ImmPred:$offset,
1595 (i32 IntRegs:$src1))>;
1597 def : Pat<(store (i32 IntRegs:$src1), (add IntRegs:$src2,
1598 s11_2ExtPred:$offset)),
1599 (STriw_indexed IntRegs:$src2, s11_2ImmPred:$offset,
1600 (i32 IntRegs:$src1))>;
1602 def : Pat<(store (i64 DoubleRegs:$src1), (add IntRegs:$src2,
1603 s11_3ExtPred:$offset)),
1604 (STrid_indexed IntRegs:$src2, s11_3ImmPred:$offset,
1605 (i64 DoubleRegs:$src1))>;
1608 // memh(Rx++#s4:1)=Rt.H
1612 let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1613 def STriw_pred : STInst2<(outs),
1614 (ins MEMri:$addr, PredRegs:$src1),
1615 "Error; should not emit",
1618 // Allocate stack frame.
1619 let Defs = [R29, R30], Uses = [R31, R30], neverHasSideEffects = 1 in {
1620 def ALLOCFRAME : STInst2<(outs),
1622 "allocframe(#$amt)",
1625 //===----------------------------------------------------------------------===//
1627 //===----------------------------------------------------------------------===//
1629 //===----------------------------------------------------------------------===//
1631 //===----------------------------------------------------------------------===//
1633 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
1634 "$dst = not($src1)",
1635 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
1638 // Sign extend word to doubleword.
1639 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
1640 "$dst = sxtw($src1)",
1641 [(set (i64 DoubleRegs:$dst), (sext (i32 IntRegs:$src1)))]>;
1642 //===----------------------------------------------------------------------===//
1644 //===----------------------------------------------------------------------===//
1646 //===----------------------------------------------------------------------===//
1648 //===----------------------------------------------------------------------===//
1650 def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1651 "$dst = clrbit($src1, #$src2)",
1652 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
1654 (shl 1, u5ImmPred:$src2))))]>;
1656 def CLRBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1657 "$dst = clrbit($src1, #$src2)",
1660 // Map from r0 = and(r1, 2147483647) to r0 = clrbit(r1, #31).
1661 def : Pat <(and (i32 IntRegs:$src1), 2147483647),
1662 (CLRBIT_31 (i32 IntRegs:$src1), 31)>;
1665 def SETBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1666 "$dst = setbit($src1, #$src2)",
1667 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
1668 (shl 1, u5ImmPred:$src2)))]>;
1670 // Map from r0 = or(r1, -2147483648) to r0 = setbit(r1, #31).
1671 def SETBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1672 "$dst = setbit($src1, #$src2)",
1675 def : Pat <(or (i32 IntRegs:$src1), -2147483648),
1676 (SETBIT_31 (i32 IntRegs:$src1), 31)>;
1679 def TOGBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1680 "$dst = setbit($src1, #$src2)",
1681 [(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
1682 (shl 1, u5ImmPred:$src2)))]>;
1684 // Map from r0 = xor(r1, -2147483648) to r0 = togglebit(r1, #31).
1685 def TOGBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1686 "$dst = togglebit($src1, #$src2)",
1689 def : Pat <(xor (i32 IntRegs:$src1), -2147483648),
1690 (TOGBIT_31 (i32 IntRegs:$src1), 31)>;
1692 // Predicate transfer.
1693 let neverHasSideEffects = 1 in
1694 def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
1695 "$dst = $src1 /* Should almost never emit this. */",
1698 def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1),
1699 "$dst = $src1 /* Should almost never emit this. */",
1700 [(set (i1 PredRegs:$dst), (trunc (i32 IntRegs:$src1)))]>;
1701 //===----------------------------------------------------------------------===//
1703 //===----------------------------------------------------------------------===//
1705 //===----------------------------------------------------------------------===//
1707 //===----------------------------------------------------------------------===//
1708 // Shift by immediate.
1709 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1710 "$dst = asr($src1, #$src2)",
1711 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1712 u5ImmPred:$src2))]>;
1714 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1715 "$dst = asr($src1, #$src2)",
1716 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1717 u6ImmPred:$src2))]>;
1719 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1720 "$dst = asl($src1, #$src2)",
1721 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1722 u5ImmPred:$src2))]>;
1724 def ASLd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1725 "$dst = asl($src1, #$src2)",
1726 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1727 u6ImmPred:$src2))]>;
1729 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1730 "$dst = lsr($src1, #$src2)",
1731 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1732 u5ImmPred:$src2))]>;
1734 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1735 "$dst = lsr($src1, #$src2)",
1736 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1737 u6ImmPred:$src2))]>;
1739 // Shift by immediate and add.
1740 let AddedComplexity = 100 in
1741 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
1743 "$dst = addasl($src1, $src2, #$src3)",
1744 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
1745 (shl (i32 IntRegs:$src2),
1746 u3ImmPred:$src3)))]>;
1748 // Shift by register.
1749 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1750 "$dst = asl($src1, $src2)",
1751 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1752 (i32 IntRegs:$src2)))]>;
1754 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1755 "$dst = asr($src1, $src2)",
1756 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1757 (i32 IntRegs:$src2)))]>;
1759 def LSL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1760 "$dst = lsl($src1, $src2)",
1761 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1762 (i32 IntRegs:$src2)))]>;
1764 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1765 "$dst = lsr($src1, $src2)",
1766 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1767 (i32 IntRegs:$src2)))]>;
1769 def ASLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1770 "$dst = asl($src1, $src2)",
1771 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1772 (i32 IntRegs:$src2)))]>;
1774 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1775 "$dst = lsl($src1, $src2)",
1776 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1777 (i32 IntRegs:$src2)))]>;
1779 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1781 "$dst = asr($src1, $src2)",
1782 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1783 (i32 IntRegs:$src2)))]>;
1785 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1787 "$dst = lsr($src1, $src2)",
1788 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1789 (i32 IntRegs:$src2)))]>;
1791 //===----------------------------------------------------------------------===//
1793 //===----------------------------------------------------------------------===//
1795 //===----------------------------------------------------------------------===//
1797 //===----------------------------------------------------------------------===//
1798 //===----------------------------------------------------------------------===//
1800 //===----------------------------------------------------------------------===//
1802 //===----------------------------------------------------------------------===//
1804 //===----------------------------------------------------------------------===//
1805 //===----------------------------------------------------------------------===//
1807 //===----------------------------------------------------------------------===//
1809 //===----------------------------------------------------------------------===//
1811 //===----------------------------------------------------------------------===//
1813 //===----------------------------------------------------------------------===//
1815 //===----------------------------------------------------------------------===//
1816 def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
1817 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
1820 let hasSideEffects = 1, isSolo = 1 in
1821 def BARRIER : SYSInst<(outs), (ins),
1823 [(HexagonBARRIER)]>;
1825 //===----------------------------------------------------------------------===//
1827 //===----------------------------------------------------------------------===//
1829 // TFRI64 - assembly mapped.
1830 let isReMaterializable = 1 in
1831 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
1833 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
1835 // Pseudo instruction to encode a set of conditional transfers.
1836 // This instruction is used instead of a mux and trades-off codesize
1837 // for performance. We conduct this transformation optimistically in
1838 // the hope that these instructions get promoted to dot-new transfers.
1839 let AddedComplexity = 100, isPredicated = 1 in
1840 def TFR_condset_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
1843 "Error; should not emit",
1844 [(set (i32 IntRegs:$dst),
1845 (i32 (select (i1 PredRegs:$src1),
1846 (i32 IntRegs:$src2),
1847 (i32 IntRegs:$src3))))]>;
1848 let AddedComplexity = 100, isPredicated = 1 in
1849 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
1850 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
1851 "Error; should not emit",
1852 [(set (i32 IntRegs:$dst),
1853 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
1854 s12ImmPred:$src3)))]>;
1856 let AddedComplexity = 100, isPredicated = 1 in
1857 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
1858 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
1859 "Error; should not emit",
1860 [(set (i32 IntRegs:$dst),
1861 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
1862 (i32 IntRegs:$src3))))]>;
1864 let AddedComplexity = 100, isPredicated = 1 in
1865 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
1866 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
1867 "Error; should not emit",
1868 [(set (i32 IntRegs:$dst),
1869 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
1870 s12ImmPred:$src3)))]>;
1872 // Generate frameindex addresses.
1873 let isReMaterializable = 1 in
1874 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
1875 "$dst = add($src1)",
1876 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
1881 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
1882 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
1883 "loop0($offset, #$src2)",
1887 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
1888 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
1889 "loop0($offset, $src2)",
1893 let isBranch = 1, isTerminator = 1, neverHasSideEffects = 1,
1894 Defs = [PC, LC0], Uses = [SA0, LC0] in {
1895 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
1900 // Support for generating global address.
1901 // Taken from X86InstrInfo.td.
1902 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [
1906 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
1907 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
1909 // HI/LO Instructions
1910 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1911 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
1912 "$dst.l = #LO($global)",
1915 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1916 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
1917 "$dst.h = #HI($global)",
1920 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1921 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
1922 "$dst.l = #LO($imm_value)",
1926 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1927 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
1928 "$dst.h = #HI($imm_value)",
1931 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1932 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
1933 "$dst.l = #LO($jt)",
1936 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1937 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
1938 "$dst.h = #HI($jt)",
1942 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1943 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
1944 "$dst.l = #LO($label)",
1947 let isReMaterializable = 1, isMoveImm = 1 , neverHasSideEffects = 1 in
1948 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
1949 "$dst.h = #HI($label)",
1952 // This pattern is incorrect. When we add small data, we should change
1953 // this pattern to use memw(#foo).
1954 // This is for sdata.
1955 let isMoveImm = 1 in
1956 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
1957 "$dst = CONST32(#$global)",
1958 [(set (i32 IntRegs:$dst),
1959 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
1961 // This is for non-sdata.
1962 let isReMaterializable = 1, isMoveImm = 1 in
1963 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
1964 "$dst = CONST32(#$global)",
1965 [(set (i32 IntRegs:$dst),
1966 (HexagonCONST32 tglobaladdr:$global))]>;
1968 let isReMaterializable = 1, isMoveImm = 1 in
1969 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
1970 "$dst = CONST32(#$jt)",
1971 [(set (i32 IntRegs:$dst),
1972 (HexagonCONST32 tjumptable:$jt))]>;
1974 let isReMaterializable = 1, isMoveImm = 1 in
1975 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
1976 "$dst = CONST32(#$global)",
1977 [(set (i32 IntRegs:$dst),
1978 (HexagonCONST32_GP tglobaladdr:$global))]>;
1980 let isReMaterializable = 1, isMoveImm = 1 in
1981 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
1982 "$dst = CONST32(#$global)",
1983 [(set (i32 IntRegs:$dst), imm:$global) ]>;
1985 // Map BlockAddress lowering to CONST32_Int_Real
1986 def : Pat<(HexagonCONST32_GP tblockaddress:$addr),
1987 (CONST32_Int_Real tblockaddress:$addr)>;
1989 let isReMaterializable = 1, isMoveImm = 1 in
1990 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
1991 "$dst = CONST32($label)",
1992 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
1994 let isReMaterializable = 1, isMoveImm = 1 in
1995 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
1996 "$dst = CONST64(#$global)",
1997 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
1999 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
2000 "$dst = xor($dst, $dst)",
2001 [(set (i1 PredRegs:$dst), 0)]>;
2003 def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2004 "$dst = mpy($src1, $src2)",
2005 [(set (i32 IntRegs:$dst),
2006 (trunc (i64 (srl (i64 (mul (i64 (sext (i32 IntRegs:$src1))),
2007 (i64 (sext (i32 IntRegs:$src2))))),
2010 // Pseudo instructions.
2011 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
2013 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
2014 SDTCisVT<1, i32> ]>;
2016 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
2017 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2019 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
2020 [SDNPHasChain, SDNPOutGlue]>;
2022 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2024 def call : SDNode<"HexagonISD::CALL", SDT_SPCall,
2025 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
2027 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
2028 // Optional Flag and Variable Arguments.
2029 // Its 1 Operand has pointer type.
2030 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
2031 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
2033 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
2034 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
2035 "Should never be emitted",
2036 [(callseq_start timm:$amt)]>;
2039 let Defs = [R29, R30, R31], Uses = [R29] in {
2040 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2041 "Should never be emitted",
2042 [(callseq_end timm:$amt1, timm:$amt2)]>;
2045 let isCall = 1, neverHasSideEffects = 1,
2046 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2047 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2048 def CALL : JInst<(outs), (ins calltarget:$dst),
2052 // Call subroutine from register.
2053 let isCall = 1, neverHasSideEffects = 1,
2054 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2055 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2056 def CALLR : JRInst<(outs), (ins IntRegs:$dst),
2062 // Indirect tail-call.
2063 let isCodeGenOnly = 1, isCall = 1, isReturn = 1 in
2064 def TCRETURNR : T_JMPr;
2066 // Direct tail-calls.
2067 let isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
2068 isTerminator = 1, isCodeGenOnly = 1 in {
2069 def TCRETURNtg : T_JMP<(ins calltarget:$dst)>;
2070 def TCRETURNtext : T_JMP<(ins calltarget:$dst)>;
2073 // Map call instruction.
2074 def : Pat<(call (i32 IntRegs:$dst)),
2075 (CALLR (i32 IntRegs:$dst))>, Requires<[HasV2TOnly]>;
2076 def : Pat<(call tglobaladdr:$dst),
2077 (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
2078 def : Pat<(call texternalsym:$dst),
2079 (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>;
2081 def : Pat<(HexagonTCRet tglobaladdr:$dst),
2082 (TCRETURNtg tglobaladdr:$dst)>;
2083 def : Pat<(HexagonTCRet texternalsym:$dst),
2084 (TCRETURNtext texternalsym:$dst)>;
2085 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
2086 (TCRETURNR (i32 IntRegs:$dst))>;
2088 // Atomic load and store support
2089 // 8 bit atomic load
2090 def : Pat<(atomic_load_8 ADDRriS11_0:$src1),
2091 (i32 (LDriub ADDRriS11_0:$src1))>;
2093 def : Pat<(atomic_load_8 (add (i32 IntRegs:$src1), s11_0ImmPred:$offset)),
2094 (i32 (LDriub_indexed (i32 IntRegs:$src1), s11_0ImmPred:$offset))>;
2096 // 16 bit atomic load
2097 def : Pat<(atomic_load_16 ADDRriS11_1:$src1),
2098 (i32 (LDriuh ADDRriS11_1:$src1))>;
2100 def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)),
2101 (i32 (LDriuh_indexed (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
2103 def : Pat<(atomic_load_32 ADDRriS11_2:$src1),
2104 (i32 (LDriw ADDRriS11_2:$src1))>;
2106 def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),
2107 (i32 (LDriw_indexed (i32 IntRegs:$src1), s11_2ImmPred:$offset))>;
2109 // 64 bit atomic load
2110 def : Pat<(atomic_load_64 ADDRriS11_3:$src1),
2111 (i64 (LDrid ADDRriS11_3:$src1))>;
2113 def : Pat<(atomic_load_64 (add (i32 IntRegs:$src1), s11_3ImmPred:$offset)),
2114 (i64 (LDrid_indexed (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
2117 def : Pat<(atomic_store_8 ADDRriS11_0:$src2, (i32 IntRegs:$src1)),
2118 (STrib ADDRriS11_0:$src2, (i32 IntRegs:$src1))>;
2120 def : Pat<(atomic_store_8 (add (i32 IntRegs:$src2), s11_0ImmPred:$offset),
2121 (i32 IntRegs:$src1)),
2122 (STrib_indexed (i32 IntRegs:$src2), s11_0ImmPred:$offset,
2123 (i32 IntRegs:$src1))>;
2126 def : Pat<(atomic_store_16 ADDRriS11_1:$src2, (i32 IntRegs:$src1)),
2127 (STrih ADDRriS11_1:$src2, (i32 IntRegs:$src1))>;
2129 def : Pat<(atomic_store_16 (i32 IntRegs:$src1),
2130 (add (i32 IntRegs:$src2), s11_1ImmPred:$offset)),
2131 (STrih_indexed (i32 IntRegs:$src2), s11_1ImmPred:$offset,
2132 (i32 IntRegs:$src1))>;
2134 def : Pat<(atomic_store_32 ADDRriS11_2:$src2, (i32 IntRegs:$src1)),
2135 (STriw ADDRriS11_2:$src2, (i32 IntRegs:$src1))>;
2137 def : Pat<(atomic_store_32 (add (i32 IntRegs:$src2), s11_2ImmPred:$offset),
2138 (i32 IntRegs:$src1)),
2139 (STriw_indexed (i32 IntRegs:$src2), s11_2ImmPred:$offset,
2140 (i32 IntRegs:$src1))>;
2145 def : Pat<(atomic_store_64 ADDRriS11_3:$src2, (i64 DoubleRegs:$src1)),
2146 (STrid ADDRriS11_3:$src2, (i64 DoubleRegs:$src1))>;
2148 def : Pat<(atomic_store_64 (add (i32 IntRegs:$src2), s11_3ImmPred:$offset),
2149 (i64 DoubleRegs:$src1)),
2150 (STrid_indexed (i32 IntRegs:$src2), s11_3ImmPred:$offset,
2151 (i64 DoubleRegs:$src1))>;
2153 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
2154 def : Pat <(and (i32 IntRegs:$src1), 65535),
2155 (ZXTH (i32 IntRegs:$src1))>;
2157 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
2158 def : Pat <(and (i32 IntRegs:$src1), 255),
2159 (ZXTB (i32 IntRegs:$src1))>;
2161 // Map Add(p1, true) to p1 = not(p1).
2162 // Add(p1, false) should never be produced,
2163 // if it does, it got to be mapped to NOOP.
2164 def : Pat <(add (i1 PredRegs:$src1), -1),
2165 (NOT_p (i1 PredRegs:$src1))>;
2167 // Map from p0 = setlt(r0, r1) r2 = mux(p0, r3, r4) =>
2168 // p0 = cmp.lt(r0, r1), r0 = mux(p0, r2, r1).
2169 // cmp.lt(r0, r1) -> cmp.gt(r1, r0)
2170 def : Pat <(select (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2171 (i32 IntRegs:$src3),
2172 (i32 IntRegs:$src4)),
2173 (i32 (TFR_condset_rr (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)),
2174 (i32 IntRegs:$src4), (i32 IntRegs:$src3)))>,
2175 Requires<[HasV2TOnly]>;
2177 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
2178 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
2179 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
2182 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
2183 // => r0 = TFR_condset_ri(p0, r1, #i)
2184 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
2185 (i32 IntRegs:$src3)),
2186 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
2187 s12ImmPred:$src2))>;
2189 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
2190 // => r0 = TFR_condset_ir(p0, #i, r1)
2191 def : Pat <(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s12ImmPred:$src3),
2192 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
2193 (i32 IntRegs:$src2)))>;
2195 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
2196 def : Pat <(brcond (not (i1 PredRegs:$src1)), bb:$offset),
2197 (JMP_f (i1 PredRegs:$src1), bb:$offset)>;
2199 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
2200 def : Pat <(and (i1 PredRegs:$src1), (not (i1 PredRegs:$src2))),
2201 (i1 (AND_pnotp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2204 let AddedComplexity = 100 in
2205 def : Pat <(i64 (zextloadi1 (HexagonCONST32 tglobaladdr:$global))),
2206 (i64 (COMBINE_rr (TFRI 0),
2207 (LDriub_indexed (CONST32_set tglobaladdr:$global), 0)))>,
2210 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
2211 let AddedComplexity = 10 in
2212 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
2213 (i32 (AND_rr (i32 (LDrib ADDRriS11_0:$addr)), (TFRI 0x1)))>;
2215 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
2216 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
2217 (i64 (SXTW (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
2219 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
2220 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
2221 (i64 (SXTW (i32 (SXTH (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2222 subreg_loreg))))))>;
2224 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
2225 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
2226 (i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2227 subreg_loreg))))))>;
2229 // We want to prevent emitting pnot's as much as possible.
2230 // Map brcond with an unsupported setcc to a JMP_f.
2231 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2233 (JMP_f (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2236 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
2238 (JMP_f (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
2240 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
2241 (JMP_f (i1 PredRegs:$src1), bb:$offset)>;
2243 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
2244 (JMP_t (i1 PredRegs:$src1), bb:$offset)>;
2246 // cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1)
2247 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
2249 (JMP_f (CMPGTri (i32 IntRegs:$src1),
2250 (DEC_CONST_SIGNED s8ImmPred:$src2)), bb:$offset)>;
2252 // cmp.lt(r0, r1) -> cmp.gt(r1, r0)
2253 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2255 (JMP_t (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)), bb:$offset)>;
2257 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2259 (JMP_f (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
2262 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2264 (JMP_f (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2267 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2269 (JMP_f (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2272 // Map from a 64-bit select to an emulated 64-bit mux.
2273 // Hexagon does not support 64-bit MUXes; so emulate with combines.
2274 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
2275 (i64 DoubleRegs:$src3)),
2276 (i64 (COMBINE_rr (i32 (MUX_rr (i1 PredRegs:$src1),
2277 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2279 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2281 (i32 (MUX_rr (i1 PredRegs:$src1),
2282 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2284 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2285 subreg_loreg))))))>;
2287 // Map from a 1-bit select to logical ops.
2288 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
2289 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
2290 (i1 PredRegs:$src3)),
2291 (OR_pp (AND_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
2292 (AND_pp (NOT_p (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
2294 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
2295 def : Pat<(i1 (load ADDRriS11_2:$addr)),
2296 (i1 (TFR_PdRs (i32 (LDrib ADDRriS11_2:$addr))))>;
2298 // Map for truncating from 64 immediates to 32 bit immediates.
2299 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
2300 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
2302 // Map for truncating from i64 immediates to i1 bit immediates.
2303 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
2304 (i1 (TFR_PdRs (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2307 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
2308 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2309 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2312 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
2313 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2314 (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2316 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
2317 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2318 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2321 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
2322 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2323 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2326 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
2327 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2328 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2331 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
2332 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2333 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2335 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
2336 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
2337 (STrib ADDRriS11_2:$addr, (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0)) )>;
2339 // Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs).
2340 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
2341 // Better way to do this?
2342 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
2343 (i64 (SXTW (i32 IntRegs:$src1)))>;
2345 // Map cmple -> cmpgt.
2346 // rs <= rt -> !(rs > rt).
2347 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
2348 (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), s10ExtPred:$src2)))>;
2350 // rs <= rt -> !(rs > rt).
2351 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2352 (i1 (NOT_p (CMPGTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2354 // Rss <= Rtt -> !(Rss > Rtt).
2355 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2356 (i1 (NOT_p (CMPGT64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2358 // Map cmpne -> cmpeq.
2359 // Hexagon_TODO: We should improve on this.
2360 // rs != rt -> !(rs == rt).
2361 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
2362 (i1 (NOT_p(i1 (CMPEQri (i32 IntRegs:$src1), s10ExtPred:$src2))))>;
2364 // Map cmpne(Rs) -> !cmpeqe(Rs).
2365 // rs != rt -> !(rs == rt).
2366 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2367 (i1 (NOT_p (i1 (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
2369 // Convert setne back to xor for hexagon since we compute w/ pred registers.
2370 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
2371 (i1 (XOR_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2373 // Map cmpne(Rss) -> !cmpew(Rss).
2374 // rs != rt -> !(rs == rt).
2375 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2376 (i1 (NOT_p (i1 (CMPEHexagon4rr (i64 DoubleRegs:$src1),
2377 (i64 DoubleRegs:$src2)))))>;
2379 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
2380 // rs >= rt -> !(rt > rs).
2381 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2382 (i1 (NOT_p (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
2384 // cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
2385 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)),
2386 (i1 (CMPGTri (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
2388 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
2389 // rss >= rtt -> !(rtt > rss).
2390 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2391 (i1 (NOT_p (i1 (CMPGT64rr (i64 DoubleRegs:$src2),
2392 (i64 DoubleRegs:$src1)))))>;
2394 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
2395 // !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
2396 // rs < rt -> !(rs >= rt).
2397 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
2398 (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2))))>;
2400 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
2401 // rs < rt -> rt > rs.
2402 // We can let assembler map it, or we can do in the compiler itself.
2403 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2404 (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2406 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
2407 // rss < rtt -> (rtt > rss).
2408 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2409 (i1 (CMPGT64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2411 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
2412 // rs < rt -> rt > rs.
2413 // We can let assembler map it, or we can do in the compiler itself.
2414 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2415 (i1 (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2417 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
2418 // rs < rt -> rt > rs.
2419 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2420 (i1 (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2422 // Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs)
2423 def : Pat <(i1 (setuge (i32 IntRegs:$src1), 0)),
2424 (i1 (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src1)))>;
2426 // Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1)
2427 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ExtPred:$src2)),
2428 (i1 (CMPGTUri (i32 IntRegs:$src1), (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
2430 // Generate cmpgtu(Rs, #u9)
2431 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)),
2432 (i1 (CMPGTUri (i32 IntRegs:$src1), u9ExtPred:$src2))>;
2434 // Map from Rs >= Rt -> !(Rt > Rs).
2435 // rs >= rt -> !(rt > rs).
2436 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2437 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
2439 // Map from Rs >= Rt -> !(Rt > Rs).
2440 // rs >= rt -> !(rt > rs).
2441 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2442 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
2444 // Map from cmpleu(Rs, Rt) -> !cmpgtu(Rs, Rt).
2445 // Map from (Rs <= Rt) -> !(Rs > Rt).
2446 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2447 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2449 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
2450 // Map from (Rs <= Rt) -> !(Rs > Rt).
2451 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2452 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2456 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
2457 (i32 (MUX_ii (i1 PredRegs:$src1), -1, 0))>;
2460 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
2461 (i64 (COMBINE_rr (TFRI -1), (MUX_ii (i1 PredRegs:$src1), -1, 0)))>;
2463 // Convert sign-extended load back to load and sign extend.
2465 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
2466 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2468 // Convert any-extended load back to load and sign extend.
2470 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
2471 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2473 // Convert sign-extended load back to load and sign extend.
2475 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
2476 (i64 (SXTW (LDrih ADDRriS11_1:$src1)))>;
2478 // Convert sign-extended load back to load and sign extend.
2480 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
2481 (i64 (SXTW (LDriw ADDRriS11_2:$src1)))>;
2486 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2487 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2490 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
2491 (i64 (COMBINE_rr (TFRI 0), (MUX_ii (i1 PredRegs:$src1), 1, 0)))>,
2495 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
2496 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>,
2500 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
2501 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>,
2504 let AddedComplexity = 20 in
2505 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
2506 s11_0ExtPred:$offset))),
2507 (i64 (COMBINE_rr (TFRI 0), (LDriub_indexed IntRegs:$src1,
2508 s11_0ExtPred:$offset)))>,
2512 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
2513 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>,
2516 let AddedComplexity = 20 in
2517 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
2518 s11_0ExtPred:$offset))),
2519 (i64 (COMBINE_rr (TFRI 0), (LDriub_indexed IntRegs:$src1,
2520 s11_0ExtPred:$offset)))>,
2524 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
2525 (i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>,
2528 let AddedComplexity = 20 in
2529 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
2530 s11_1ExtPred:$offset))),
2531 (i64 (COMBINE_rr (TFRI 0), (LDriuh_indexed IntRegs:$src1,
2532 s11_1ExtPred:$offset)))>,
2536 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
2537 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>,
2540 let AddedComplexity = 100 in
2541 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
2542 (i64 (COMBINE_rr (TFRI 0), (LDriw_indexed IntRegs:$src1,
2543 s11_2ExtPred:$offset)))>,
2546 let AddedComplexity = 10 in
2547 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
2548 (i32 (LDriw ADDRriS11_0:$src1))>;
2550 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2551 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2552 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2554 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2555 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
2556 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2558 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
2559 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
2560 (i64 (SXTW (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))))>;
2563 let AddedComplexity = 100 in
2564 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2566 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
2567 s11_2ExtPred:$offset2)))))),
2568 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2569 (LDriw_indexed IntRegs:$src2,
2570 s11_2ExtPred:$offset2)))>;
2572 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2574 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
2575 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2576 (LDriw ADDRriS11_2:$srcLow)))>;
2578 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2580 (i64 (zext (i32 IntRegs:$srcLow))))),
2581 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2584 let AddedComplexity = 100 in
2585 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2587 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
2588 s11_2ExtPred:$offset2)))))),
2589 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2590 (LDriw_indexed IntRegs:$src2,
2591 s11_2ExtPred:$offset2)))>;
2593 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2595 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
2596 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2597 (LDriw ADDRriS11_2:$srcLow)))>;
2599 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2601 (i64 (zext (i32 IntRegs:$srcLow))))),
2602 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2605 // Any extended 64-bit load.
2606 // anyext i32 -> i64
2607 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
2608 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>,
2611 // When there is an offset we should prefer the pattern below over the pattern above.
2612 // The complexity of the above is 13 (gleaned from HexagonGenDAGIsel.inc)
2613 // So this complexity below is comfortably higher to allow for choosing the below.
2614 // If this is not done then we generate addresses such as
2615 // ********************************************
2616 // r1 = add (r0, #4)
2617 // r1 = memw(r1 + #0)
2619 // r1 = memw(r0 + #4)
2620 // ********************************************
2621 let AddedComplexity = 100 in
2622 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
2623 (i64 (COMBINE_rr (TFRI 0), (LDriw_indexed IntRegs:$src1,
2624 s11_2ExtPred:$offset)))>,
2627 // anyext i16 -> i64.
2628 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
2629 (i64 (COMBINE_rr (TFRI 0), (LDrih ADDRriS11_2:$src1)))>,
2632 let AddedComplexity = 20 in
2633 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
2634 s11_1ExtPred:$offset))),
2635 (i64 (COMBINE_rr (TFRI 0), (LDrih_indexed IntRegs:$src1,
2636 s11_1ExtPred:$offset)))>,
2639 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
2640 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
2641 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>,
2644 // Multiply 64-bit unsigned and use upper result.
2645 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2660 (COMBINE_rr (TFRI 0),
2666 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2668 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2669 subreg_loreg)))), 32)),
2671 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2672 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2673 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2674 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2675 32)), subreg_loreg)))),
2676 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2677 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2679 // Multiply 64-bit signed and use upper result.
2680 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2684 (COMBINE_rr (TFRI 0),
2694 (COMBINE_rr (TFRI 0),
2700 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2702 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2703 subreg_loreg)))), 32)),
2705 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2706 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2707 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2708 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2709 32)), subreg_loreg)))),
2710 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2711 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2713 // Hexagon specific ISD nodes.
2714 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
2715 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
2716 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
2717 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
2718 SDTHexagonADJDYNALLOC>;
2719 // Needed to tag these instructions for stack layout.
2720 let usesCustomInserter = 1 in
2721 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
2723 "$dst = add($src1, #$src2)",
2724 [(set (i32 IntRegs:$dst),
2725 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
2726 s16ImmPred:$src2))]>;
2728 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
2729 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
2730 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
2732 [(set (i32 IntRegs:$dst),
2733 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
2735 let AddedComplexity = 100 in
2736 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
2737 (COPY (i32 IntRegs:$src1))>;
2739 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
2741 def : Pat<(HexagonWrapperJT tjumptable:$dst),
2742 (i32 (CONST32_set_jt tjumptable:$dst))>;
2746 // Multi-class for logical operators :
2747 // Shift by immediate/register and accumulate/logical
2748 multiclass xtype_imm<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
2749 def _ri : SInst_acc<(outs IntRegs:$dst),
2750 (ins IntRegs:$src1, IntRegs:$src2, u5Imm:$src3),
2751 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
2752 [(set (i32 IntRegs:$dst),
2753 (OpNode2 (i32 IntRegs:$src1),
2754 (OpNode1 (i32 IntRegs:$src2),
2755 u5ImmPred:$src3)))],
2758 def d_ri : SInst_acc<(outs DoubleRegs:$dst),
2759 (ins DoubleRegs:$src1, DoubleRegs:$src2, u6Imm:$src3),
2760 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
2761 [(set (i64 DoubleRegs:$dst), (OpNode2 (i64 DoubleRegs:$src1),
2762 (OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
2766 // Multi-class for logical operators :
2767 // Shift by register and accumulate/logical (32/64 bits)
2768 multiclass xtype_reg<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
2769 def _rr : SInst_acc<(outs IntRegs:$dst),
2770 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2771 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
2772 [(set (i32 IntRegs:$dst),
2773 (OpNode2 (i32 IntRegs:$src1),
2774 (OpNode1 (i32 IntRegs:$src2),
2775 (i32 IntRegs:$src3))))],
2778 def d_rr : SInst_acc<(outs DoubleRegs:$dst),
2779 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2780 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
2781 [(set (i64 DoubleRegs:$dst),
2782 (OpNode2 (i64 DoubleRegs:$src1),
2783 (OpNode1 (i64 DoubleRegs:$src2),
2784 (i32 IntRegs:$src3))))],
2789 multiclass basic_xtype_imm<string OpcStr, SDNode OpNode> {
2790 let AddedComplexity = 100 in
2791 defm _ADD : xtype_imm< !strconcat("+= ", OpcStr), OpNode, add>;
2792 defm _SUB : xtype_imm< !strconcat("-= ", OpcStr), OpNode, sub>;
2793 defm _AND : xtype_imm< !strconcat("&= ", OpcStr), OpNode, and>;
2794 defm _OR : xtype_imm< !strconcat("|= ", OpcStr), OpNode, or>;
2797 multiclass basic_xtype_reg<string OpcStr, SDNode OpNode> {
2798 let AddedComplexity = 100 in
2799 defm _ADD : xtype_reg< !strconcat("+= ", OpcStr), OpNode, add>;
2800 defm _SUB : xtype_reg< !strconcat("-= ", OpcStr), OpNode, sub>;
2801 defm _AND : xtype_reg< !strconcat("&= ", OpcStr), OpNode, and>;
2802 defm _OR : xtype_reg< !strconcat("|= ", OpcStr), OpNode, or>;
2805 multiclass xtype_xor_imm<string OpcStr, SDNode OpNode> {
2806 let AddedComplexity = 100 in
2807 defm _XOR : xtype_imm< !strconcat("^= ", OpcStr), OpNode, xor>;
2810 defm ASL : basic_xtype_imm<"asl", shl>, basic_xtype_reg<"asl", shl>,
2811 xtype_xor_imm<"asl", shl>;
2813 defm LSR : basic_xtype_imm<"lsr", srl>, basic_xtype_reg<"lsr", srl>,
2814 xtype_xor_imm<"lsr", srl>;
2816 defm ASR : basic_xtype_imm<"asr", sra>, basic_xtype_reg<"asr", sra>;
2817 defm LSL : basic_xtype_reg<"lsl", shl>;
2819 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
2820 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
2821 (i32 (MPYI_rin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
2823 //===----------------------------------------------------------------------===//
2824 // V3 Instructions +
2825 //===----------------------------------------------------------------------===//
2827 include "HexagonInstrInfoV3.td"
2829 //===----------------------------------------------------------------------===//
2830 // V3 Instructions -
2831 //===----------------------------------------------------------------------===//
2833 //===----------------------------------------------------------------------===//
2834 // V4 Instructions +
2835 //===----------------------------------------------------------------------===//
2837 include "HexagonInstrInfoV4.td"
2839 //===----------------------------------------------------------------------===//
2840 // V4 Instructions -
2841 //===----------------------------------------------------------------------===//
2843 //===----------------------------------------------------------------------===//
2844 // V5 Instructions +
2845 //===----------------------------------------------------------------------===//
2847 include "HexagonInstrInfoV5.td"
2849 //===----------------------------------------------------------------------===//
2850 // V5 Instructions -
2851 //===----------------------------------------------------------------------===//