1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonImmediates.td"
17 //===----------------------------------------------------------------------===//
18 // Hexagon Instruction Predicate Definitions.
19 //===----------------------------------------------------------------------===//
20 def HasV2T : Predicate<"Subtarget.hasV2TOps()">;
21 def HasV2TOnly : Predicate<"Subtarget.hasV2TOpsOnly()">;
22 def NoV2T : Predicate<"!Subtarget.hasV2TOps()">;
23 def HasV3T : Predicate<"Subtarget.hasV3TOps()">;
24 def HasV3TOnly : Predicate<"Subtarget.hasV3TOpsOnly()">;
25 def NoV3T : Predicate<"!Subtarget.hasV3TOps()">;
26 def HasV4T : Predicate<"Subtarget.hasV4TOps()">;
27 def NoV4T : Predicate<"!Subtarget.hasV4TOps()">;
28 def UseMEMOP : Predicate<"Subtarget.useMemOps()">;
31 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
32 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>;
33 def ADDRriS11_0 : ComplexPattern<i32, 2, "SelectADDRriS11_0", [frameindex], []>;
34 def ADDRriS11_1 : ComplexPattern<i32, 2, "SelectADDRriS11_1", [frameindex], []>;
35 def ADDRriS11_2 : ComplexPattern<i32, 2, "SelectADDRriS11_2", [frameindex], []>;
36 def ADDRriS11_3 : ComplexPattern<i32, 2, "SelectADDRriS11_3", [frameindex], []>;
37 def ADDRriU6_0 : ComplexPattern<i32, 2, "SelectADDRriU6_0", [frameindex], []>;
38 def ADDRriU6_1 : ComplexPattern<i32, 2, "SelectADDRriU6_1", [frameindex], []>;
39 def ADDRriU6_2 : ComplexPattern<i32, 2, "SelectADDRriU6_2", [frameindex], []>;
42 def MEMrr : Operand<i32> {
43 let PrintMethod = "printHexagonMEMrrOperand";
44 let MIOperandInfo = (ops IntRegs, IntRegs);
48 def MEMri : Operand<i32> {
49 let PrintMethod = "printHexagonMEMriOperand";
50 let MIOperandInfo = (ops IntRegs, IntRegs);
53 def MEMri_s11_2 : Operand<i32>,
54 ComplexPattern<i32, 2, "SelectMEMriS11_2", []> {
55 let PrintMethod = "printHexagonMEMriOperand";
56 let MIOperandInfo = (ops IntRegs, s11Imm);
59 def FrameIndex : Operand<i32> {
60 let PrintMethod = "printHexagonFrameIndexOperand";
61 let MIOperandInfo = (ops IntRegs, s11Imm);
64 let PrintMethod = "printGlobalOperand" in
65 def globaladdress : Operand<i32>;
67 let PrintMethod = "printJumpTable" in
68 def jumptablebase : Operand<i32>;
70 def brtarget : Operand<OtherVT>;
71 def calltarget : Operand<i32>;
73 def bblabel : Operand<i32>;
74 def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf , [], "BasicBlockSDNode">;
76 def symbolHi32 : Operand<i32> {
77 let PrintMethod = "printSymbolHi";
79 def symbolLo32 : Operand<i32> {
80 let PrintMethod = "printSymbolLo";
83 // Multi-class for logical operators.
84 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
85 def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
86 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
87 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
88 def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
89 !strconcat("$dst = ", !strconcat(OpcStr, "(#$b, $c)")),
90 [(set IntRegs:$dst, (OpNode s10Imm:$b, IntRegs:$c))]>;
93 // Multi-class for compare ops.
94 let isCompare = 1 in {
95 multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
96 def rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
97 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
98 [(set PredRegs:$dst, (OpNode DoubleRegs:$b, DoubleRegs:$c))]>;
100 multiclass CMP32_rr<string OpcStr, PatFrag OpNode> {
101 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
102 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
103 [(set PredRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
106 multiclass CMP32_rr_ri_s10<string OpcStr, PatFrag OpNode> {
107 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
108 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
109 [(set PredRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
110 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Imm:$c),
111 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
112 [(set PredRegs:$dst, (OpNode IntRegs:$b, s10ImmPred:$c))]>;
115 multiclass CMP32_rr_ri_u9<string OpcStr, PatFrag OpNode> {
116 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
117 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
118 [(set PredRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
119 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Imm:$c),
120 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
121 [(set PredRegs:$dst, (OpNode IntRegs:$b, u9ImmPred:$c))]>;
124 multiclass CMP32_ri_u9<string OpcStr, PatFrag OpNode> {
125 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Imm:$c),
126 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
127 [(set PredRegs:$dst, (OpNode IntRegs:$b, u9ImmPred:$c))]>;
130 multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
131 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Imm:$c),
132 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
133 [(set PredRegs:$dst, (OpNode IntRegs:$b, s8ImmPred:$c))]>;
137 //===----------------------------------------------------------------------===//
139 //===----------------------------------------------------------------------===//
141 //===----------------------------------------------------------------------===//
142 // http://qualnet.qualcomm.com/~erich/v1/htmldocs/index.html
143 // http://qualnet.qualcomm.com/~erich/v2/htmldocs/index.html
144 // http://qualnet.qualcomm.com/~erich/v3/htmldocs/index.html
145 // http://qualnet.qualcomm.com/~erich/v4/htmldocs/index.html
146 // http://qualnet.qualcomm.com/~erich/v5/htmldocs/index.html
147 //===----------------------------------------------------------------------===//
149 //===----------------------------------------------------------------------===//
151 //===----------------------------------------------------------------------===//
153 let isPredicable = 1 in
154 def ADD_rr : ALU32_rr<(outs IntRegs:$dst),
155 (ins IntRegs:$src1, IntRegs:$src2),
156 "$dst = add($src1, $src2)",
157 [(set IntRegs:$dst, (add IntRegs:$src1, IntRegs:$src2))]>;
159 let isPredicable = 1 in
160 def ADD_ri : ALU32_ri<(outs IntRegs:$dst),
161 (ins IntRegs:$src1, s16Imm:$src2),
162 "$dst = add($src1, #$src2)",
163 [(set IntRegs:$dst, (add IntRegs:$src1, s16ImmPred:$src2))]>;
165 // Logical operations.
166 let isPredicable = 1 in
167 def XOR_rr : ALU32_rr<(outs IntRegs:$dst),
168 (ins IntRegs:$src1, IntRegs:$src2),
169 "$dst = xor($src1, $src2)",
170 [(set IntRegs:$dst, (xor IntRegs:$src1, IntRegs:$src2))]>;
172 let isPredicable = 1 in
173 def AND_rr : ALU32_rr<(outs IntRegs:$dst),
174 (ins IntRegs:$src1, IntRegs:$src2),
175 "$dst = and($src1, $src2)",
176 [(set IntRegs:$dst, (and IntRegs:$src1, IntRegs:$src2))]>;
178 def OR_ri : ALU32_ri<(outs IntRegs:$dst),
179 (ins IntRegs:$src1, s8Imm:$src2),
180 "$dst = or($src1, #$src2)",
181 [(set IntRegs:$dst, (or IntRegs:$src1, s8ImmPred:$src2))]>;
183 def NOT_rr : ALU32_rr<(outs IntRegs:$dst),
186 [(set IntRegs:$dst, (not IntRegs:$src1))]>;
188 def AND_ri : ALU32_ri<(outs IntRegs:$dst),
189 (ins IntRegs:$src1, s10Imm:$src2),
190 "$dst = and($src1, #$src2)",
191 [(set IntRegs:$dst, (and IntRegs:$src1, s10ImmPred:$src2))]>;
193 let isPredicable = 1 in
194 def OR_rr : ALU32_rr<(outs IntRegs:$dst),
195 (ins IntRegs:$src1, IntRegs:$src2),
196 "$dst = or($src1, $src2)",
197 [(set IntRegs:$dst, (or IntRegs:$src1, IntRegs:$src2))]>;
200 def NEG : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
202 [(set IntRegs:$dst, (ineg IntRegs:$src1))]>;
204 let neverHasSideEffects = 1 in
205 def NOP : ALU32_rr<(outs), (ins),
210 let isPredicable = 1 in
211 def SUB_rr : ALU32_rr<(outs IntRegs:$dst),
212 (ins IntRegs:$src1, IntRegs:$src2),
213 "$dst = sub($src1, $src2)",
214 [(set IntRegs:$dst, (sub IntRegs:$src1, IntRegs:$src2))]>;
216 // Transfer immediate.
217 let isReMaterializable = 1, isPredicable = 1 in
218 def TFRI : ALU32_ri<(outs IntRegs:$dst), (ins s16Imm:$src1),
220 [(set IntRegs:$dst, s16ImmPred:$src1)]>;
222 // Transfer register.
223 let neverHasSideEffects = 1, isPredicable = 1 in
224 def TFR : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1),
228 // Transfer control register.
229 let neverHasSideEffects = 1 in
230 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
233 //===----------------------------------------------------------------------===//
235 //===----------------------------------------------------------------------===//
238 //===----------------------------------------------------------------------===//
240 //===----------------------------------------------------------------------===//
243 let isPredicable = 1, neverHasSideEffects = 1 in
244 def COMBINE_rr : ALU32_rr<(outs DoubleRegs:$dst),
245 (ins IntRegs:$src1, IntRegs:$src2),
246 "$dst = combine($src1, $src2)",
250 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
253 "$dst = vmux($src1, $src2, $src3)",
256 def MUX_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
257 IntRegs:$src2, IntRegs:$src3),
258 "$dst = mux($src1, $src2, $src3)",
259 [(set IntRegs:$dst, (select PredRegs:$src1, IntRegs:$src2,
262 def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Imm:$src2,
264 "$dst = mux($src1, #$src2, $src3)",
265 [(set IntRegs:$dst, (select PredRegs:$src1,
266 s8ImmPred:$src2, IntRegs:$src3))]>;
268 def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
270 "$dst = mux($src1, $src2, #$src3)",
271 [(set IntRegs:$dst, (select PredRegs:$src1, IntRegs:$src2,
274 def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Imm:$src2,
276 "$dst = mux($src1, #$src2, #$src3)",
277 [(set IntRegs:$dst, (select PredRegs:$src1, s8ImmPred:$src2,
281 let isPredicable = 1 in
282 def ASLH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
283 "$dst = aslh($src1)",
284 [(set IntRegs:$dst, (shl 16, IntRegs:$src1))]>;
286 let isPredicable = 1 in
287 def ASRH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
288 "$dst = asrh($src1)",
289 [(set IntRegs:$dst, (sra 16, IntRegs:$src1))]>;
292 let isPredicable = 1 in
293 def SXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
294 "$dst = sxtb($src1)",
295 [(set IntRegs:$dst, (sext_inreg IntRegs:$src1, i8))]>;
297 let isPredicable = 1 in
298 def SXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
299 "$dst = sxth($src1)",
300 [(set IntRegs:$dst, (sext_inreg IntRegs:$src1, i16))]>;
303 let isPredicable = 1, neverHasSideEffects = 1 in
304 def ZXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
305 "$dst = zxtb($src1)",
308 let isPredicable = 1, neverHasSideEffects = 1 in
309 def ZXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
310 "$dst = zxth($src1)",
312 //===----------------------------------------------------------------------===//
314 //===----------------------------------------------------------------------===//
317 //===----------------------------------------------------------------------===//
319 //===----------------------------------------------------------------------===//
322 let neverHasSideEffects = 1 in
323 def ADD_ri_cPt : ALU32_ri<(outs IntRegs:$dst),
324 (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
325 "if ($src1) $dst = add($src2, #$src3)",
328 let neverHasSideEffects = 1 in
329 def ADD_ri_cNotPt : ALU32_ri<(outs IntRegs:$dst),
330 (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
331 "if (!$src1) $dst = add($src2, #$src3)",
334 let neverHasSideEffects = 1 in
335 def ADD_ri_cdnPt : ALU32_ri<(outs IntRegs:$dst),
336 (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
337 "if ($src1.new) $dst = add($src2, #$src3)",
340 let neverHasSideEffects = 1 in
341 def ADD_ri_cdnNotPt : ALU32_ri<(outs IntRegs:$dst),
342 (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
343 "if (!$src1.new) $dst = add($src2, #$src3)",
346 let neverHasSideEffects = 1 in
347 def ADD_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
348 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
349 "if ($src1) $dst = add($src2, $src3)",
352 let neverHasSideEffects = 1 in
353 def ADD_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
354 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
355 "if (!$src1) $dst = add($src2, $src3)",
358 let neverHasSideEffects = 1 in
359 def ADD_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
360 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
361 "if ($src1.new) $dst = add($src2, $src3)",
364 let neverHasSideEffects = 1 in
365 def ADD_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
366 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
367 "if (!$src1.new) $dst = add($src2, $src3)",
371 // Conditional combine.
373 let neverHasSideEffects = 1 in
374 def COMBINE_rr_cPt : ALU32_rr<(outs DoubleRegs:$dst),
375 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
376 "if ($src1) $dst = combine($src2, $src3)",
379 let neverHasSideEffects = 1 in
380 def COMBINE_rr_cNotPt : ALU32_rr<(outs DoubleRegs:$dst),
381 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
382 "if (!$src1) $dst = combine($src2, $src3)",
385 let neverHasSideEffects = 1 in
386 def COMBINE_rr_cdnPt : ALU32_rr<(outs DoubleRegs:$dst),
387 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
388 "if ($src1.new) $dst = combine($src2, $src3)",
391 let neverHasSideEffects = 1 in
392 def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst),
393 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
394 "if (!$src1.new) $dst = combine($src2, $src3)",
397 // Conditional logical operations.
399 def XOR_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
400 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
401 "if ($src1) $dst = xor($src2, $src3)",
404 def XOR_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
405 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
406 "if (!$src1) $dst = xor($src2, $src3)",
409 def XOR_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
410 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
411 "if ($src1.new) $dst = xor($src2, $src3)",
414 def XOR_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
415 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
416 "if (!$src1.new) $dst = xor($src2, $src3)",
419 def AND_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
420 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
421 "if ($src1) $dst = and($src2, $src3)",
424 def AND_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
425 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
426 "if (!$src1) $dst = and($src2, $src3)",
429 def AND_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
430 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
431 "if ($src1.new) $dst = and($src2, $src3)",
434 def AND_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
435 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
436 "if (!$src1.new) $dst = and($src2, $src3)",
439 def OR_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
440 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
441 "if ($src1) $dst = or($src2, $src3)",
444 def OR_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
445 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
446 "if (!$src1) $dst = or($src2, $src3)",
449 def OR_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
450 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
451 "if ($src1.new) $dst = or($src2, $src3)",
454 def OR_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
455 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
456 "if (!$src1.new) $dst = or($src2, $src3)",
460 // Conditional subtract.
462 def SUB_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
463 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
464 "if ($src1) $dst = sub($src2, $src3)",
467 def SUB_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
468 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
469 "if (!$src1) $dst = sub($src2, $src3)",
472 def SUB_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
473 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
474 "if ($src1.new) $dst = sub($src2, $src3)",
477 def SUB_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
478 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
479 "if (!$src1.new) $dst = sub($src2, $src3)",
483 // Conditional transfer.
485 let neverHasSideEffects = 1 in
486 def TFR_cPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2),
487 "if ($src1) $dst = $src2",
490 let neverHasSideEffects = 1 in
491 def TFR_cNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
493 "if (!$src1) $dst = $src2",
496 let neverHasSideEffects = 1 in
497 def TFRI_cPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, s12Imm:$src2),
498 "if ($src1) $dst = #$src2",
501 let neverHasSideEffects = 1 in
502 def TFRI_cNotPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
504 "if (!$src1) $dst = #$src2",
507 let neverHasSideEffects = 1 in
508 def TFR_cdnPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
510 "if ($src1.new) $dst = $src2",
513 let neverHasSideEffects = 1 in
514 def TFR_cdnNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
516 "if (!$src1.new) $dst = $src2",
519 let neverHasSideEffects = 1 in
520 def TFRI_cdnPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
522 "if ($src1.new) $dst = #$src2",
525 let neverHasSideEffects = 1 in
526 def TFRI_cdnNotPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
528 "if (!$src1.new) $dst = #$src2",
532 defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", setugt>;
533 defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", setgt>;
534 defm CMPLT : CMP32_rr<"cmp.lt", setlt>;
535 defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", seteq>;
536 defm CMPGE : CMP32_ri_s8<"cmp.ge", setge>;
537 defm CMPGEU : CMP32_ri_u9<"cmp.geu", setuge>;
538 //===----------------------------------------------------------------------===//
540 //===----------------------------------------------------------------------===//
542 //===----------------------------------------------------------------------===//
544 //===----------------------------------------------------------------------===//
545 // Vector add halfwords
547 // Vector averagehalfwords
549 // Vector subtract halfwords
550 //===----------------------------------------------------------------------===//
552 //===----------------------------------------------------------------------===//
555 //===----------------------------------------------------------------------===//
557 //===----------------------------------------------------------------------===//
559 def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
561 "$dst = add($src1, $src2)",
562 [(set DoubleRegs:$dst, (add DoubleRegs:$src1,
563 DoubleRegs:$src2))]>;
568 defm CMPEHexagon4 : CMP64_rr<"cmp.eq", seteq>;
569 defm CMPGT64 : CMP64_rr<"cmp.gt", setgt>;
570 defm CMPGTU64 : CMP64_rr<"cmp.gtu", setugt>;
572 // Logical operations.
573 def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
575 "$dst = and($src1, $src2)",
576 [(set DoubleRegs:$dst, (and DoubleRegs:$src1,
577 DoubleRegs:$src2))]>;
579 def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
581 "$dst = or($src1, $src2)",
582 [(set DoubleRegs:$dst, (or DoubleRegs:$src1, DoubleRegs:$src2))]>;
584 def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
586 "$dst = xor($src1, $src2)",
587 [(set DoubleRegs:$dst, (xor DoubleRegs:$src1,
588 DoubleRegs:$src2))]>;
591 def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
592 "$dst = max($src2, $src1)",
593 [(set IntRegs:$dst, (select (i1 (setlt IntRegs:$src2,
595 IntRegs:$src1, IntRegs:$src2))]>;
598 def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
599 "$dst = min($src2, $src1)",
600 [(set IntRegs:$dst, (select (i1 (setgt IntRegs:$src2,
602 IntRegs:$src1, IntRegs:$src2))]>;
605 def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
607 "$dst = sub($src1, $src2)",
608 [(set DoubleRegs:$dst, (sub DoubleRegs:$src1,
609 DoubleRegs:$src2))]>;
611 // Subtract halfword.
613 // Transfer register.
614 let neverHasSideEffects = 1 in
615 def TFR_64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
618 //===----------------------------------------------------------------------===//
620 //===----------------------------------------------------------------------===//
622 //===----------------------------------------------------------------------===//
624 //===----------------------------------------------------------------------===//
626 //===----------------------------------------------------------------------===//
628 //===----------------------------------------------------------------------===//
630 //===----------------------------------------------------------------------===//
632 //===----------------------------------------------------------------------===//
634 //===----------------------------------------------------------------------===//
636 //===----------------------------------------------------------------------===//
638 //===----------------------------------------------------------------------===//
640 //===----------------------------------------------------------------------===//
642 //===----------------------------------------------------------------------===//
644 //===----------------------------------------------------------------------===//
646 //===----------------------------------------------------------------------===//
648 //===----------------------------------------------------------------------===//
650 //===----------------------------------------------------------------------===//
652 //===----------------------------------------------------------------------===//
654 //===----------------------------------------------------------------------===//
656 //===----------------------------------------------------------------------===//
658 //===----------------------------------------------------------------------===//
660 //===----------------------------------------------------------------------===//
662 //===----------------------------------------------------------------------===//
664 //===----------------------------------------------------------------------===//
665 // Logical reductions on predicates.
667 // Looping instructions.
669 // Pipelined looping instructions.
671 // Logical operations on predicates.
672 def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
673 "$dst = and($src1, $src2)",
674 [(set PredRegs:$dst, (and PredRegs:$src1, PredRegs:$src2))]>;
676 let neverHasSideEffects = 1 in
677 def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
679 "$dst = and($src1, !$src2)",
682 def NOT_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
684 [(set PredRegs:$dst, (not PredRegs:$src1))]>;
686 def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
687 "$dst = any8($src1)",
690 def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
691 "$dst = all8($src1)",
694 def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
696 "$dst = vitpack($src1, $src2)",
699 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
702 "$dst = valignb($src1, $src2, $src3)",
705 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
708 "$dst = vspliceb($src1, $src2, $src3)",
711 def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
712 "$dst = mask($src1)",
715 def NOT_Ps : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
717 [(set PredRegs:$dst, (not PredRegs:$src1))]>;
719 def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
720 "$dst = or($src1, $src2)",
721 [(set PredRegs:$dst, (or PredRegs:$src1, PredRegs:$src2))]>;
723 def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
724 "$dst = xor($src1, $src2)",
725 [(set PredRegs:$dst, (xor PredRegs:$src1, PredRegs:$src2))]>;
728 // User control register transfer.
729 //===----------------------------------------------------------------------===//
731 //===----------------------------------------------------------------------===//
734 //===----------------------------------------------------------------------===//
736 //===----------------------------------------------------------------------===//
738 let isBranch = 1, isTerminator=1, isBarrier = 1, isPredicable = 1 in {
739 def JMP : JInst< (outs),
740 (ins brtarget:$offset),
746 let isBranch = 1, isTerminator=1, Defs = [PC] in {
747 def JMP_Pred : JInst< (outs),
748 (ins PredRegs:$src, brtarget:$offset),
749 "if ($src) jump $offset",
750 [(brcond PredRegs:$src, bb:$offset)]>;
754 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
755 def JMP_PredNot : JInst< (outs),
756 (ins PredRegs:$src, brtarget:$offset),
757 "if (!$src) jump $offset",
761 let isTerminator = 1, isBranch = 1, neverHasSideEffects = 1, Defs = [PC] in {
762 def BRCOND : JInst < (outs), (ins PredRegs:$pred, brtarget:$dst),
763 "if ($pred) jump $dst",
767 // Jump to address conditioned on new predicate.
769 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
770 def JMP_PredPt : JInst< (outs),
771 (ins PredRegs:$src, brtarget:$offset),
772 "if ($src.new) jump:t $offset",
777 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
778 def JMP_PredNotPt : JInst< (outs),
779 (ins PredRegs:$src, brtarget:$offset),
780 "if (!$src.new) jump:t $offset",
785 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
786 def JMP_PredPnt : JInst< (outs),
787 (ins PredRegs:$src, brtarget:$offset),
788 "if ($src.new) jump:nt $offset",
793 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
794 def JMP_PredNotPnt : JInst< (outs),
795 (ins PredRegs:$src, brtarget:$offset),
796 "if (!$src.new) jump:nt $offset",
799 //===----------------------------------------------------------------------===//
801 //===----------------------------------------------------------------------===//
803 //===----------------------------------------------------------------------===//
805 //===----------------------------------------------------------------------===//
806 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
807 [SDNPHasChain, SDNPOptInGlue]>;
809 // Jump to address from register.
810 let isReturn = 1, isTerminator = 1, isBarrier = 1,
811 Defs = [PC], Uses = [R31] in {
812 def JMPR: JRInst<(outs), (ins),
817 // Jump to address from register.
818 let isReturn = 1, isTerminator = 1, isBarrier = 1,
819 Defs = [PC], Uses = [R31] in {
820 def JMPR_cPt: JRInst<(outs), (ins PredRegs:$src1),
821 "if ($src1) jumpr r31",
825 // Jump to address from register.
826 let isReturn = 1, isTerminator = 1, isBarrier = 1,
827 Defs = [PC], Uses = [R31] in {
828 def JMPR_cNotPt: JRInst<(outs), (ins PredRegs:$src1),
829 "if (!$src1) jumpr r31",
833 //===----------------------------------------------------------------------===//
835 //===----------------------------------------------------------------------===//
837 //===----------------------------------------------------------------------===//
839 //===----------------------------------------------------------------------===//
841 /// Make sure that in post increment load, the first operand is always the post
842 /// increment operand.
845 let isPredicable = 1 in
846 def LDrid : LDInst<(outs DoubleRegs:$dst),
848 "$dst = memd($addr)",
849 [(set DoubleRegs:$dst, (load ADDRriS11_3:$addr))]>;
851 let isPredicable = 1, AddedComplexity = 20 in
852 def LDrid_indexed : LDInst<(outs DoubleRegs:$dst),
853 (ins IntRegs:$src1, s11_3Imm:$offset),
854 "$dst=memd($src1+#$offset)",
855 [(set DoubleRegs:$dst, (load (add IntRegs:$src1,
856 s11_3ImmPred:$offset)))]>;
858 let mayLoad = 1, neverHasSideEffects = 1 in
859 def LDrid_GP : LDInst<(outs DoubleRegs:$dst),
860 (ins globaladdress:$global, u16Imm:$offset),
861 "$dst=memd(#$global+$offset)",
864 let mayLoad = 1, neverHasSideEffects = 1 in
865 def LDd_GP : LDInst<(outs DoubleRegs:$dst),
866 (ins globaladdress:$global),
867 "$dst=memd(#$global)",
870 let isPredicable = 1, mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
871 def POST_LDrid : LDInstPI<(outs DoubleRegs:$dst, IntRegs:$dst2),
872 (ins IntRegs:$src1, s4Imm:$offset),
873 "$dst = memd($src1++#$offset)",
877 // Load doubleword conditionally.
878 let mayLoad = 1, neverHasSideEffects = 1 in
879 def LDrid_cPt : LDInst<(outs DoubleRegs:$dst),
880 (ins PredRegs:$src1, MEMri:$addr),
881 "if ($src1) $dst = memd($addr)",
885 let mayLoad = 1, neverHasSideEffects = 1 in
886 def LDrid_cNotPt : LDInst<(outs DoubleRegs:$dst),
887 (ins PredRegs:$src1, MEMri:$addr),
888 "if (!$src1) $dst = memd($addr)",
891 let mayLoad = 1, neverHasSideEffects = 1 in
892 def LDrid_indexed_cPt : LDInst<(outs DoubleRegs:$dst),
893 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
894 "if ($src1) $dst=memd($src2+#$src3)",
897 let mayLoad = 1, neverHasSideEffects = 1 in
898 def LDrid_indexed_cNotPt : LDInst<(outs DoubleRegs:$dst),
899 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
900 "if (!$src1) $dst=memd($src2+#$src3)",
903 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
904 def POST_LDrid_cPt : LDInstPI<(outs DoubleRegs:$dst1, IntRegs:$dst2),
905 (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),
906 "if ($src1) $dst1 = memd($src2++#$src3)",
910 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
911 def POST_LDrid_cNotPt : LDInstPI<(outs DoubleRegs:$dst1, IntRegs:$dst2),
912 (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),
913 "if (!$src1) $dst1 = memd($src2++#$src3)",
917 let mayLoad = 1, neverHasSideEffects = 1 in
918 def LDrid_cdnPt : LDInst<(outs DoubleRegs:$dst),
919 (ins PredRegs:$src1, MEMri:$addr),
920 "if ($src1.new) $dst = memd($addr)",
923 let mayLoad = 1, neverHasSideEffects = 1 in
924 def LDrid_cdnNotPt : LDInst<(outs DoubleRegs:$dst),
925 (ins PredRegs:$src1, MEMri:$addr),
926 "if (!$src1.new) $dst = memd($addr)",
929 let mayLoad = 1, neverHasSideEffects = 1 in
930 def LDrid_indexed_cdnPt : LDInst<(outs DoubleRegs:$dst),
931 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
932 "if ($src1.new) $dst=memd($src2+#$src3)",
935 let mayLoad = 1, neverHasSideEffects = 1 in
936 def LDrid_indexed_cdnNotPt : LDInst<(outs DoubleRegs:$dst),
937 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
938 "if (!$src1.new) $dst=memd($src2+#$src3)",
943 let isPredicable = 1 in
944 def LDrib : LDInst<(outs IntRegs:$dst),
946 "$dst = memb($addr)",
947 [(set IntRegs:$dst, (sextloadi8 ADDRriS11_0:$addr))]>;
949 def LDrib_ae : LDInst<(outs IntRegs:$dst),
951 "$dst = memb($addr)",
952 [(set IntRegs:$dst, (extloadi8 ADDRriS11_0:$addr))]>;
954 // Indexed load byte.
955 let isPredicable = 1, AddedComplexity = 20 in
956 def LDrib_indexed : LDInst<(outs IntRegs:$dst),
957 (ins IntRegs:$src1, s11_0Imm:$offset),
958 "$dst=memb($src1+#$offset)",
959 [(set IntRegs:$dst, (sextloadi8 (add IntRegs:$src1,
960 s11_0ImmPred:$offset)))]>;
963 // Indexed load byte any-extend.
964 let AddedComplexity = 20 in
965 def LDrib_ae_indexed : LDInst<(outs IntRegs:$dst),
966 (ins IntRegs:$src1, s11_0Imm:$offset),
967 "$dst=memb($src1+#$offset)",
968 [(set IntRegs:$dst, (extloadi8 (add IntRegs:$src1,
969 s11_0ImmPred:$offset)))]>;
971 let mayLoad = 1, neverHasSideEffects = 1 in
972 def LDrib_GP : LDInst<(outs IntRegs:$dst),
973 (ins globaladdress:$global, u16Imm:$offset),
974 "$dst=memb(#$global+$offset)",
977 let mayLoad = 1, neverHasSideEffects = 1 in
978 def LDb_GP : LDInst<(outs IntRegs:$dst),
979 (ins globaladdress:$global),
980 "$dst=memb(#$global)",
983 let mayLoad = 1, neverHasSideEffects = 1 in
984 def LDub_GP : LDInst<(outs IntRegs:$dst),
985 (ins globaladdress:$global),
986 "$dst=memub(#$global)",
989 let isPredicable = 1, mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
990 def POST_LDrib : LDInstPI<(outs IntRegs:$dst, IntRegs:$dst2),
991 (ins IntRegs:$src1, s4Imm:$offset),
992 "$dst = memb($src1++#$offset)",
996 // Load byte conditionally.
997 let mayLoad = 1, neverHasSideEffects = 1 in
998 def LDrib_cPt : LDInst<(outs IntRegs:$dst),
999 (ins PredRegs:$src1, MEMri:$addr),
1000 "if ($src1) $dst = memb($addr)",
1003 let mayLoad = 1, neverHasSideEffects = 1 in
1004 def LDrib_cNotPt : LDInst<(outs IntRegs:$dst),
1005 (ins PredRegs:$src1, MEMri:$addr),
1006 "if (!$src1) $dst = memb($addr)",
1009 let mayLoad = 1, neverHasSideEffects = 1 in
1010 def LDrib_indexed_cPt : LDInst<(outs IntRegs:$dst),
1011 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1012 "if ($src1) $dst = memb($src2+#$src3)",
1015 let mayLoad = 1, neverHasSideEffects = 1 in
1016 def LDrib_indexed_cNotPt : LDInst<(outs IntRegs:$dst),
1017 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1018 "if (!$src1) $dst = memb($src2+#$src3)",
1021 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1022 def POST_LDrib_cPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1023 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1024 "if ($src1) $dst1 = memb($src2++#$src3)",
1028 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1029 def POST_LDrib_cNotPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1030 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1031 "if (!$src1) $dst1 = memb($src2++#$src3)",
1035 let mayLoad = 1, neverHasSideEffects = 1 in
1036 def LDrib_cdnPt : LDInst<(outs IntRegs:$dst),
1037 (ins PredRegs:$src1, MEMri:$addr),
1038 "if ($src1.new) $dst = memb($addr)",
1041 let mayLoad = 1, neverHasSideEffects = 1 in
1042 def LDrib_cdnNotPt : LDInst<(outs IntRegs:$dst),
1043 (ins PredRegs:$src1, MEMri:$addr),
1044 "if (!$src1.new) $dst = memb($addr)",
1047 let mayLoad = 1, neverHasSideEffects = 1 in
1048 def LDrib_indexed_cdnPt : LDInst<(outs IntRegs:$dst),
1049 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1050 "if ($src1.new) $dst = memb($src2+#$src3)",
1053 let mayLoad = 1, neverHasSideEffects = 1 in
1054 def LDrib_indexed_cdnNotPt : LDInst<(outs IntRegs:$dst),
1055 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1056 "if (!$src1.new) $dst = memb($src2+#$src3)",
1061 let isPredicable = 1 in
1062 def LDrih : LDInst<(outs IntRegs:$dst),
1064 "$dst = memh($addr)",
1065 [(set IntRegs:$dst, (sextloadi16 ADDRriS11_1:$addr))]>;
1067 let isPredicable = 1, AddedComplexity = 20 in
1068 def LDrih_indexed : LDInst<(outs IntRegs:$dst),
1069 (ins IntRegs:$src1, s11_1Imm:$offset),
1070 "$dst=memh($src1+#$offset)",
1071 [(set IntRegs:$dst, (sextloadi16 (add IntRegs:$src1,
1072 s11_1ImmPred:$offset)))] >;
1074 def LDrih_ae : LDInst<(outs IntRegs:$dst),
1076 "$dst = memh($addr)",
1077 [(set IntRegs:$dst, (extloadi16 ADDRriS11_1:$addr))]>;
1079 let AddedComplexity = 20 in
1080 def LDrih_ae_indexed : LDInst<(outs IntRegs:$dst),
1081 (ins IntRegs:$src1, s11_1Imm:$offset),
1082 "$dst=memh($src1+#$offset)",
1083 [(set IntRegs:$dst, (extloadi16 (add IntRegs:$src1,
1084 s11_1ImmPred:$offset)))] >;
1086 let mayLoad = 1, neverHasSideEffects = 1 in
1087 def LDrih_GP : LDInst<(outs IntRegs:$dst),
1088 (ins globaladdress:$global, u16Imm:$offset),
1089 "$dst=memh(#$global+$offset)",
1092 let mayLoad = 1, neverHasSideEffects = 1 in
1093 def LDh_GP : LDInst<(outs IntRegs:$dst),
1094 (ins globaladdress:$global),
1095 "$dst=memh(#$global)",
1098 let mayLoad = 1, neverHasSideEffects = 1 in
1099 def LDuh_GP : LDInst<(outs IntRegs:$dst),
1100 (ins globaladdress:$global),
1101 "$dst=memuh(#$global)",
1105 let isPredicable = 1, mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1106 def POST_LDrih : LDInstPI<(outs IntRegs:$dst, IntRegs:$dst2),
1107 (ins IntRegs:$src1, s4Imm:$offset),
1108 "$dst = memh($src1++#$offset)",
1112 // Load halfword conditionally.
1113 let mayLoad = 1, neverHasSideEffects = 1 in
1114 def LDrih_cPt : LDInst<(outs IntRegs:$dst),
1115 (ins PredRegs:$src1, MEMri:$addr),
1116 "if ($src1) $dst = memh($addr)",
1119 let mayLoad = 1, neverHasSideEffects = 1 in
1120 def LDrih_cNotPt : LDInst<(outs IntRegs:$dst),
1121 (ins PredRegs:$src1, MEMri:$addr),
1122 "if (!$src1) $dst = memh($addr)",
1125 let mayLoad = 1, neverHasSideEffects = 1 in
1126 def LDrih_indexed_cPt : LDInst<(outs IntRegs:$dst),
1127 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1128 "if ($src1) $dst = memh($src2+#$src3)",
1131 let mayLoad = 1, neverHasSideEffects = 1 in
1132 def LDrih_indexed_cNotPt : LDInst<(outs IntRegs:$dst),
1133 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1134 "if (!$src1) $dst = memh($src2+#$src3)",
1137 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1138 def POST_LDrih_cPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1139 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1140 "if ($src1) $dst1 = memh($src2++#$src3)",
1144 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1145 def POST_LDrih_cNotPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1146 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1147 "if (!$src1) $dst1 = memh($src2++#$src3)",
1151 let mayLoad = 1, neverHasSideEffects = 1 in
1152 def LDrih_cdnPt : LDInst<(outs IntRegs:$dst),
1153 (ins PredRegs:$src1, MEMri:$addr),
1154 "if ($src1.new) $dst = memh($addr)",
1157 let mayLoad = 1, neverHasSideEffects = 1 in
1158 def LDrih_cdnNotPt : LDInst<(outs IntRegs:$dst),
1159 (ins PredRegs:$src1, MEMri:$addr),
1160 "if (!$src1.new) $dst = memh($addr)",
1163 let mayLoad = 1, neverHasSideEffects = 1 in
1164 def LDrih_indexed_cdnPt : LDInst<(outs IntRegs:$dst),
1165 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1166 "if ($src1.new) $dst = memh($src2+#$src3)",
1169 let mayLoad = 1, neverHasSideEffects = 1 in
1170 def LDrih_indexed_cdnNotPt : LDInst<(outs IntRegs:$dst),
1171 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1172 "if (!$src1.new) $dst = memh($src2+#$src3)",
1175 // Load unsigned byte.
1176 let isPredicable = 1 in
1177 def LDriub : LDInst<(outs IntRegs:$dst),
1179 "$dst = memub($addr)",
1180 [(set IntRegs:$dst, (zextloadi8 ADDRriS11_0:$addr))]>;
1182 let isPredicable = 1 in
1183 def LDriubit : LDInst<(outs IntRegs:$dst),
1185 "$dst = memub($addr)",
1186 [(set IntRegs:$dst, (zextloadi1 ADDRriS11_0:$addr))]>;
1188 let isPredicable = 1, AddedComplexity = 20 in
1189 def LDriub_indexed : LDInst<(outs IntRegs:$dst),
1190 (ins IntRegs:$src1, s11_0Imm:$offset),
1191 "$dst=memub($src1+#$offset)",
1192 [(set IntRegs:$dst, (zextloadi8 (add IntRegs:$src1,
1193 s11_0ImmPred:$offset)))]>;
1195 let AddedComplexity = 20 in
1196 def LDriubit_indexed : LDInst<(outs IntRegs:$dst),
1197 (ins IntRegs:$src1, s11_0Imm:$offset),
1198 "$dst=memub($src1+#$offset)",
1199 [(set IntRegs:$dst, (zextloadi1 (add IntRegs:$src1,
1200 s11_0ImmPred:$offset)))]>;
1202 def LDriub_ae : LDInst<(outs IntRegs:$dst),
1204 "$dst = memub($addr)",
1205 [(set IntRegs:$dst, (extloadi8 ADDRriS11_0:$addr))]>;
1208 let AddedComplexity = 20 in
1209 def LDriub_ae_indexed : LDInst<(outs IntRegs:$dst),
1210 (ins IntRegs:$src1, s11_0Imm:$offset),
1211 "$dst=memub($src1+#$offset)",
1212 [(set IntRegs:$dst, (extloadi8 (add IntRegs:$src1,
1213 s11_0ImmPred:$offset)))]>;
1215 let mayLoad = 1, neverHasSideEffects = 1 in
1216 def LDriub_GP : LDInst<(outs IntRegs:$dst),
1217 (ins globaladdress:$global, u16Imm:$offset),
1218 "$dst=memub(#$global+$offset)",
1221 let isPredicable = 1, mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1222 def POST_LDriub : LDInstPI<(outs IntRegs:$dst, IntRegs:$dst2),
1223 (ins IntRegs:$src1, s4Imm:$offset),
1224 "$dst = memub($src1++#$offset)",
1228 // Load unsigned byte conditionally.
1229 let mayLoad = 1, neverHasSideEffects = 1 in
1230 def LDriub_cPt : LDInst<(outs IntRegs:$dst),
1231 (ins PredRegs:$src1, MEMri:$addr),
1232 "if ($src1) $dst = memub($addr)",
1235 let mayLoad = 1, neverHasSideEffects = 1 in
1236 def LDriub_cNotPt : LDInst<(outs IntRegs:$dst),
1237 (ins PredRegs:$src1, MEMri:$addr),
1238 "if (!$src1) $dst = memub($addr)",
1241 let mayLoad = 1, neverHasSideEffects = 1 in
1242 def LDriub_indexed_cPt : LDInst<(outs IntRegs:$dst),
1243 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1244 "if ($src1) $dst = memub($src2+#$src3)",
1247 let mayLoad = 1, neverHasSideEffects = 1 in
1248 def LDriub_indexed_cNotPt : LDInst<(outs IntRegs:$dst),
1249 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1250 "if (!$src1) $dst = memub($src2+#$src3)",
1253 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1254 def POST_LDriub_cPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1255 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1256 "if ($src1) $dst1 = memub($src2++#$src3)",
1260 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1261 def POST_LDriub_cNotPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1262 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1263 "if (!$src1) $dst1 = memub($src2++#$src3)",
1267 let mayLoad = 1, neverHasSideEffects = 1 in
1268 def LDriub_cdnPt : LDInst<(outs IntRegs:$dst),
1269 (ins PredRegs:$src1, MEMri:$addr),
1270 "if ($src1.new) $dst = memub($addr)",
1273 let mayLoad = 1, neverHasSideEffects = 1 in
1274 def LDriub_cdnNotPt : LDInst<(outs IntRegs:$dst),
1275 (ins PredRegs:$src1, MEMri:$addr),
1276 "if (!$src1.new) $dst = memub($addr)",
1279 let mayLoad = 1, neverHasSideEffects = 1 in
1280 def LDriub_indexed_cdnPt : LDInst<(outs IntRegs:$dst),
1281 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1282 "if ($src1.new) $dst = memub($src2+#$src3)",
1285 let mayLoad = 1, neverHasSideEffects = 1 in
1286 def LDriub_indexed_cdnNotPt : LDInst<(outs IntRegs:$dst),
1287 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1288 "if (!$src1.new) $dst = memub($src2+#$src3)",
1291 // Load unsigned halfword.
1292 let isPredicable = 1 in
1293 def LDriuh : LDInst<(outs IntRegs:$dst),
1295 "$dst = memuh($addr)",
1296 [(set IntRegs:$dst, (zextloadi16 ADDRriS11_1:$addr))]>;
1298 // Indexed load unsigned halfword.
1299 let isPredicable = 1, AddedComplexity = 20 in
1300 def LDriuh_indexed : LDInst<(outs IntRegs:$dst),
1301 (ins IntRegs:$src1, s11_1Imm:$offset),
1302 "$dst=memuh($src1+#$offset)",
1303 [(set IntRegs:$dst, (zextloadi16 (add IntRegs:$src1,
1304 s11_1ImmPred:$offset)))]>;
1306 def LDriuh_ae : LDInst<(outs IntRegs:$dst),
1308 "$dst = memuh($addr)",
1309 [(set IntRegs:$dst, (extloadi16 ADDRriS11_1:$addr))]>;
1312 // Indexed load unsigned halfword any-extend.
1313 let AddedComplexity = 20 in
1314 def LDriuh_ae_indexed : LDInst<(outs IntRegs:$dst),
1315 (ins IntRegs:$src1, s11_1Imm:$offset),
1316 "$dst=memuh($src1+#$offset)",
1317 [(set IntRegs:$dst, (extloadi16 (add IntRegs:$src1,
1318 s11_1ImmPred:$offset)))] >;
1320 let mayLoad = 1, neverHasSideEffects = 1 in
1321 def LDriuh_GP : LDInst<(outs IntRegs:$dst),
1322 (ins globaladdress:$global, u16Imm:$offset),
1323 "$dst=memuh(#$global+$offset)",
1326 let isPredicable = 1, mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1327 def POST_LDriuh : LDInstPI<(outs IntRegs:$dst, IntRegs:$dst2),
1328 (ins IntRegs:$src1, s4Imm:$offset),
1329 "$dst = memuh($src1++#$offset)",
1333 // Load unsigned halfword conditionally.
1334 let mayLoad = 1, neverHasSideEffects = 1 in
1335 def LDriuh_cPt : LDInst<(outs IntRegs:$dst),
1336 (ins PredRegs:$src1, MEMri:$addr),
1337 "if ($src1) $dst = memuh($addr)",
1340 let mayLoad = 1, neverHasSideEffects = 1 in
1341 def LDriuh_cNotPt : LDInst<(outs IntRegs:$dst),
1342 (ins PredRegs:$src1, MEMri:$addr),
1343 "if (!$src1) $dst = memuh($addr)",
1346 let mayLoad = 1, neverHasSideEffects = 1 in
1347 def LDriuh_indexed_cPt : LDInst<(outs IntRegs:$dst),
1348 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1349 "if ($src1) $dst = memuh($src2+#$src3)",
1352 let mayLoad = 1, neverHasSideEffects = 1 in
1353 def LDriuh_indexed_cNotPt : LDInst<(outs IntRegs:$dst),
1354 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1355 "if (!$src1) $dst = memuh($src2+#$src3)",
1358 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1359 def POST_LDriuh_cPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1360 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1361 "if ($src1) $dst1 = memuh($src2++#$src3)",
1365 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1366 def POST_LDriuh_cNotPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1367 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1368 "if (!$src1) $dst1 = memuh($src2++#$src3)",
1372 let mayLoad = 1, neverHasSideEffects = 1 in
1373 def LDriuh_cdnPt : LDInst<(outs IntRegs:$dst),
1374 (ins PredRegs:$src1, MEMri:$addr),
1375 "if ($src1.new) $dst = memuh($addr)",
1378 let mayLoad = 1, neverHasSideEffects = 1 in
1379 def LDriuh_cdnNotPt : LDInst<(outs IntRegs:$dst),
1380 (ins PredRegs:$src1, MEMri:$addr),
1381 "if (!$src1.new) $dst = memuh($addr)",
1384 let mayLoad = 1, neverHasSideEffects = 1 in
1385 def LDriuh_indexed_cdnPt : LDInst<(outs IntRegs:$dst),
1386 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1387 "if ($src1.new) $dst = memuh($src2+#$src3)",
1390 let mayLoad = 1, neverHasSideEffects = 1 in
1391 def LDriuh_indexed_cdnNotPt : LDInst<(outs IntRegs:$dst),
1392 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1393 "if (!$src1.new) $dst = memuh($src2+#$src3)",
1398 let isPredicable = 1 in
1399 def LDriw : LDInst<(outs IntRegs:$dst),
1400 (ins MEMri:$addr), "$dst = memw($addr)",
1401 [(set IntRegs:$dst, (load ADDRriS11_2:$addr))]>;
1404 let mayLoad = 1, Defs = [R10,R11] in
1405 def LDriw_pred : LDInst<(outs PredRegs:$dst),
1407 "Error; should not emit",
1411 let isPredicable = 1, AddedComplexity = 20 in
1412 def LDriw_indexed : LDInst<(outs IntRegs:$dst),
1413 (ins IntRegs:$src1, s11_2Imm:$offset),
1414 "$dst=memw($src1+#$offset)",
1415 [(set IntRegs:$dst, (load (add IntRegs:$src1,
1416 s11_2ImmPred:$offset)))]>;
1418 let mayLoad = 1, neverHasSideEffects = 1 in
1419 def LDriw_GP : LDInst<(outs IntRegs:$dst),
1420 (ins globaladdress:$global, u16Imm:$offset),
1421 "$dst=memw(#$global+$offset)",
1424 let mayLoad = 1, neverHasSideEffects = 1 in
1425 def LDw_GP : LDInst<(outs IntRegs:$dst),
1426 (ins globaladdress:$global),
1427 "$dst=memw(#$global)",
1430 let isPredicable = 1, mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1431 def POST_LDriw : LDInstPI<(outs IntRegs:$dst, IntRegs:$dst2),
1432 (ins IntRegs:$src1, s4Imm:$offset),
1433 "$dst = memw($src1++#$offset)",
1437 // Load word conditionally.
1439 let mayLoad = 1, neverHasSideEffects = 1 in
1440 def LDriw_cPt : LDInst<(outs IntRegs:$dst),
1441 (ins PredRegs:$src1, MEMri:$addr),
1442 "if ($src1) $dst = memw($addr)",
1445 let mayLoad = 1, neverHasSideEffects = 1 in
1446 def LDriw_cNotPt : LDInst<(outs IntRegs:$dst),
1447 (ins PredRegs:$src1, MEMri:$addr),
1448 "if (!$src1) $dst = memw($addr)",
1451 let mayLoad = 1, neverHasSideEffects = 1 in
1452 def LDriw_indexed_cPt : LDInst<(outs IntRegs:$dst),
1453 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1454 "if ($src1) $dst=memw($src2+#$src3)",
1457 let mayLoad = 1, neverHasSideEffects = 1 in
1458 def LDriw_indexed_cNotPt : LDInst<(outs IntRegs:$dst),
1459 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1460 "if (!$src1) $dst=memw($src2+#$src3)",
1463 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1464 def POST_LDriw_cPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1465 (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3),
1466 "if ($src1) $dst1 = memw($src2++#$src3)",
1470 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1471 def POST_LDriw_cNotPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1472 (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3),
1473 "if (!$src1) $dst1 = memw($src2++#$src3)",
1477 let mayLoad = 1, neverHasSideEffects = 1 in
1478 def LDriw_cdnPt : LDInst<(outs IntRegs:$dst),
1479 (ins PredRegs:$src1, MEMri:$addr),
1480 "if ($src1.new) $dst = memw($addr)",
1483 let mayLoad = 1, neverHasSideEffects = 1 in
1484 def LDriw_cdnNotPt : LDInst<(outs IntRegs:$dst),
1485 (ins PredRegs:$src1, MEMri:$addr),
1486 "if (!$src1.new) $dst = memw($addr)",
1489 let mayLoad = 1, neverHasSideEffects = 1 in
1490 def LDriw_indexed_cdnPt : LDInst<(outs IntRegs:$dst),
1491 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1492 "if ($src1.new) $dst=memw($src2+#$src3)",
1495 let mayLoad = 1, neverHasSideEffects = 1 in
1496 def LDriw_indexed_cdnNotPt : LDInst<(outs IntRegs:$dst),
1497 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1498 "if (!$src1.new) $dst=memw($src2+#$src3)",
1501 // Deallocate stack frame.
1502 let Defs = [R29, R30, R31], Uses = [R29], neverHasSideEffects = 1 in {
1503 def DEALLOCFRAME : LDInst<(outs), (ins i32imm:$amt1),
1508 // Load and unpack bytes to halfwords.
1509 //===----------------------------------------------------------------------===//
1511 //===----------------------------------------------------------------------===//
1513 //===----------------------------------------------------------------------===//
1515 //===----------------------------------------------------------------------===//
1516 //===----------------------------------------------------------------------===//
1518 //===----------------------------------------------------------------------===//
1520 //===----------------------------------------------------------------------===//
1522 //===----------------------------------------------------------------------===//
1523 //===----------------------------------------------------------------------===//
1525 //===----------------------------------------------------------------------===//
1527 //===----------------------------------------------------------------------===//
1529 //===----------------------------------------------------------------------===//
1530 // Multiply and use lower result.
1532 def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1533 "$dst =+ mpyi($src1, #$src2)",
1534 [(set IntRegs:$dst, (mul IntRegs:$src1, u8ImmPred:$src2))]>;
1537 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, n8Imm:$src2),
1538 "$dst =- mpyi($src1, #$src2)",
1540 (mul IntRegs:$src1, n8ImmPred:$src2))]>;
1543 // s9 is NOT the same as m9 - but it works.. so far.
1544 // Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
1545 // depending on the value of m9. See Arch Spec.
1546 def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Imm:$src2),
1547 "$dst = mpyi($src1, #$src2)",
1548 [(set IntRegs:$dst, (mul IntRegs:$src1, s9ImmPred:$src2))]>;
1551 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1552 "$dst = mpyi($src1, $src2)",
1553 [(set IntRegs:$dst, (mul IntRegs:$src1, IntRegs:$src2))]>;
1556 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
1557 (ins IntRegs:$src1, IntRegs:$src2, u8Imm:$src3),
1558 "$dst += mpyi($src2, #$src3)",
1560 (add (mul IntRegs:$src2, u8ImmPred:$src3), IntRegs:$src1))],
1564 def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
1565 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1566 "$dst += mpyi($src2, $src3)",
1568 (add (mul IntRegs:$src2, IntRegs:$src3), IntRegs:$src1))],
1572 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
1573 (ins IntRegs:$src1, IntRegs:$src2, u8Imm:$src3),
1574 "$dst -= mpyi($src2, #$src3)",
1576 (sub IntRegs:$src1, (mul IntRegs:$src2, u8ImmPred:$src3)))],
1579 // Multiply and use upper result.
1580 // Rd=mpy(Rs,Rt.H):<<1:rnd:sat
1581 // Rd=mpy(Rs,Rt.L):<<1:rnd:sat
1583 def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1584 "$dst = mpy($src1, $src2)",
1585 [(set IntRegs:$dst, (mulhs IntRegs:$src1, IntRegs:$src2))]>;
1587 // Rd=mpy(Rs,Rt):rnd
1589 def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1590 "$dst = mpyu($src1, $src2)",
1591 [(set IntRegs:$dst, (mulhu IntRegs:$src1, IntRegs:$src2))]>;
1593 // Multiply and use full result.
1595 def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1596 "$dst = mpyu($src1, $src2)",
1597 [(set DoubleRegs:$dst, (mul (i64 (anyext IntRegs:$src1)),
1598 (i64 (anyext IntRegs:$src2))))]>;
1601 def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1602 "$dst = mpy($src1, $src2)",
1603 [(set DoubleRegs:$dst, (mul (i64 (sext IntRegs:$src1)),
1604 (i64 (sext IntRegs:$src2))))]>;
1607 // Multiply and accumulate, use full result.
1608 // Rxx[+-]=mpy(Rs,Rt)
1610 def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
1611 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1612 "$dst += mpy($src2, $src3)",
1613 [(set DoubleRegs:$dst,
1614 (add (mul (i64 (sext IntRegs:$src2)), (i64 (sext IntRegs:$src3))),
1615 DoubleRegs:$src1))],
1619 def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
1620 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1621 "$dst -= mpy($src2, $src3)",
1622 [(set DoubleRegs:$dst,
1623 (sub DoubleRegs:$src1,
1624 (mul (i64 (sext IntRegs:$src2)), (i64 (sext IntRegs:$src3)))))],
1627 // Rxx[+-]=mpyu(Rs,Rt)
1629 def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1630 IntRegs:$src2, IntRegs:$src3),
1631 "$dst += mpyu($src2, $src3)",
1632 [(set DoubleRegs:$dst, (add (mul (i64 (anyext IntRegs:$src2)),
1633 (i64 (anyext IntRegs:$src3))),
1634 DoubleRegs:$src1))],"$src1 = $dst">;
1637 def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
1638 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1639 "$dst += mpyu($src2, $src3)",
1640 [(set DoubleRegs:$dst,
1641 (sub DoubleRegs:$src1,
1642 (mul (i64 (anyext IntRegs:$src2)),
1643 (i64 (anyext IntRegs:$src3)))))],
1647 def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1648 IntRegs:$src2, IntRegs:$src3),
1649 "$dst += add($src2, $src3)",
1650 [(set IntRegs:$dst, (add (add IntRegs:$src2, IntRegs:$src3),
1654 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1655 IntRegs:$src2, s8Imm:$src3),
1656 "$dst += add($src2, #$src3)",
1657 [(set IntRegs:$dst, (add (add IntRegs:$src2, s8ImmPred:$src3),
1661 def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1662 IntRegs:$src2, IntRegs:$src3),
1663 "$dst -= add($src2, $src3)",
1664 [(set IntRegs:$dst, (sub IntRegs:$src1, (add IntRegs:$src2,
1668 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1669 IntRegs:$src2, s8Imm:$src3),
1670 "$dst -= add($src2, #$src3)",
1671 [(set IntRegs:$dst, (sub IntRegs:$src1,
1672 (add IntRegs:$src2, s8ImmPred:$src3)))],
1675 //===----------------------------------------------------------------------===//
1677 //===----------------------------------------------------------------------===//
1679 //===----------------------------------------------------------------------===//
1681 //===----------------------------------------------------------------------===//
1682 //===----------------------------------------------------------------------===//
1684 //===----------------------------------------------------------------------===//
1686 //===----------------------------------------------------------------------===//
1688 //===----------------------------------------------------------------------===//
1689 //===----------------------------------------------------------------------===//
1691 //===----------------------------------------------------------------------===//
1693 //===----------------------------------------------------------------------===//
1695 //===----------------------------------------------------------------------===//
1696 //===----------------------------------------------------------------------===//
1698 //===----------------------------------------------------------------------===//
1700 //===----------------------------------------------------------------------===//
1702 //===----------------------------------------------------------------------===//
1704 /// Assumptions::: ****** DO NOT IGNORE ********
1705 /// 1. Make sure that in post increment store, the zero'th operand is always the
1706 /// post increment operand.
1707 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
1710 // Store doubleword.
1711 let isPredicable = 1 in
1712 def STrid : STInst<(outs),
1713 (ins MEMri:$addr, DoubleRegs:$src1),
1714 "memd($addr) = $src1",
1715 [(store DoubleRegs:$src1, ADDRriS11_3:$addr)]>;
1717 // Indexed store double word.
1718 let AddedComplexity = 10, isPredicable = 1 in
1719 def STrid_indexed : STInst<(outs),
1720 (ins IntRegs:$src1, s11_3Imm:$src2, DoubleRegs:$src3),
1721 "memd($src1+#$src2) = $src3",
1722 [(store DoubleRegs:$src3,
1723 (add IntRegs:$src1, s11_3ImmPred:$src2))]>;
1725 let mayStore = 1, neverHasSideEffects = 1 in
1726 def STrid_GP : STInst<(outs),
1727 (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),
1728 "memd(#$global+$offset) = $src",
1731 let hasCtrlDep = 1, isPredicable = 1 in
1732 def POST_STdri : STInstPI<(outs IntRegs:$dst),
1733 (ins DoubleRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1734 "memd($src2++#$offset) = $src1",
1736 (post_store DoubleRegs:$src1, IntRegs:$src2, s4_3ImmPred:$offset))],
1739 // Store doubleword conditionally.
1740 // if ([!]Pv) memd(Rs+#u6:3)=Rtt
1741 // if (Pv) memd(Rs+#u6:3)=Rtt
1742 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1743 def STrid_cPt : STInst<(outs),
1744 (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
1745 "if ($src1) memd($addr) = $src2",
1748 // if (!Pv) memd(Rs+#u6:3)=Rtt
1749 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1750 def STrid_cNotPt : STInst<(outs),
1751 (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
1752 "if (!$src1) memd($addr) = $src2",
1755 // if (Pv) memd(Rs+#u6:3)=Rtt
1756 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1757 def STrid_indexed_cPt : STInst<(outs),
1758 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
1760 "if ($src1) memd($src2+#$src3) = $src4",
1763 // if (!Pv) memd(Rs+#u6:3)=Rtt
1764 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1765 def STrid_indexed_cNotPt : STInst<(outs),
1766 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
1768 "if (!$src1) memd($src2+#$src3) = $src4",
1771 // if ([!]Pv) memd(Rx++#s4:3)=Rtt
1772 // if (Pv) memd(Rx++#s4:3)=Rtt
1773 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1774 def POST_STdri_cPt : STInstPI<(outs IntRegs:$dst),
1775 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1777 "if ($src1) memd($src3++#$offset) = $src2",
1781 // if (!Pv) memd(Rx++#s4:3)=Rtt
1782 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1783 def POST_STdri_cNotPt : STInstPI<(outs IntRegs:$dst),
1784 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1786 "if (!$src1) memd($src3++#$offset) = $src2",
1792 // memb(Rs+#s11:0)=Rt
1793 let isPredicable = 1 in
1794 def STrib : STInst<(outs),
1795 (ins MEMri:$addr, IntRegs:$src1),
1796 "memb($addr) = $src1",
1797 [(truncstorei8 IntRegs:$src1, ADDRriS11_0:$addr)]>;
1799 let AddedComplexity = 10, isPredicable = 1 in
1800 def STrib_indexed : STInst<(outs),
1801 (ins IntRegs:$src1, s11_0Imm:$src2, IntRegs:$src3),
1802 "memb($src1+#$src2) = $src3",
1803 [(truncstorei8 IntRegs:$src3, (add IntRegs:$src1,
1804 s11_0ImmPred:$src2))]>;
1806 // memb(gp+#u16:0)=Rt
1807 let mayStore = 1, neverHasSideEffects = 1 in
1808 def STrib_GP : STInst<(outs),
1809 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1810 "memb(#$global+$offset) = $src",
1813 let mayStore = 1, neverHasSideEffects = 1 in
1814 def STb_GP : STInst<(outs),
1815 (ins globaladdress:$global, IntRegs:$src),
1816 "memb(#$global) = $src",
1819 // memb(Rx++#s4:0)=Rt
1820 let hasCtrlDep = 1, isPredicable = 1 in
1821 def POST_STbri : STInstPI<(outs IntRegs:$dst), (ins IntRegs:$src1,
1824 "memb($src2++#$offset) = $src1",
1826 (post_truncsti8 IntRegs:$src1, IntRegs:$src2,
1827 s4_0ImmPred:$offset))],
1830 // Store byte conditionally.
1831 // if ([!]Pv) memb(Rs+#u6:0)=Rt
1832 // if (Pv) memb(Rs+#u6:0)=Rt
1833 let mayStore = 1, neverHasSideEffects = 1 in
1834 def STrib_cPt : STInst<(outs),
1835 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1836 "if ($src1) memb($addr) = $src2",
1839 // if (!Pv) memb(Rs+#u6:0)=Rt
1840 let mayStore = 1, neverHasSideEffects = 1 in
1841 def STrib_cNotPt : STInst<(outs),
1842 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1843 "if (!$src1) memb($addr) = $src2",
1846 // if (Pv) memb(Rs+#u6:0)=Rt
1847 let mayStore = 1, neverHasSideEffects = 1 in
1848 def STrib_indexed_cPt : STInst<(outs),
1849 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1850 "if ($src1) memb($src2+#$src3) = $src4",
1853 // if (!Pv) memb(Rs+#u6:0)=Rt
1854 let mayStore = 1, neverHasSideEffects = 1 in
1855 def STrib_indexed_cNotPt : STInst<(outs),
1856 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1857 "if (!$src1) memb($src2+#$src3) = $src4",
1860 // if ([!]Pv) memb(Rx++#s4:0)=Rt
1861 // if (Pv) memb(Rx++#s4:0)=Rt
1862 let mayStore = 1, hasCtrlDep = 1 in
1863 def POST_STbri_cPt : STInstPI<(outs IntRegs:$dst),
1864 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1865 "if ($src1) memb($src3++#$offset) = $src2",
1868 // if (!Pv) memb(Rx++#s4:0)=Rt
1869 let mayStore = 1, hasCtrlDep = 1 in
1870 def POST_STbri_cNotPt : STInstPI<(outs IntRegs:$dst),
1871 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1872 "if (!$src1) memb($src3++#$offset) = $src2",
1877 // memh(Rs+#s11:1)=Rt
1878 let isPredicable = 1 in
1879 def STrih : STInst<(outs),
1880 (ins MEMri:$addr, IntRegs:$src1),
1881 "memh($addr) = $src1",
1882 [(truncstorei16 IntRegs:$src1, ADDRriS11_1:$addr)]>;
1885 let AddedComplexity = 10, isPredicable = 1 in
1886 def STrih_indexed : STInst<(outs),
1887 (ins IntRegs:$src1, s11_1Imm:$src2, IntRegs:$src3),
1888 "memh($src1+#$src2) = $src3",
1889 [(truncstorei16 IntRegs:$src3, (add IntRegs:$src1,
1890 s11_1ImmPred:$src2))]>;
1892 let mayStore = 1, neverHasSideEffects = 1 in
1893 def STrih_GP : STInst<(outs),
1894 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1895 "memh(#$global+$offset) = $src",
1898 let mayStore = 1, neverHasSideEffects = 1 in
1899 def STh_GP : STInst<(outs),
1900 (ins globaladdress:$global, IntRegs:$src),
1901 "memh(#$global) = $src",
1904 // memh(Rx++#s4:1)=Rt.H
1905 // memh(Rx++#s4:1)=Rt
1906 let hasCtrlDep = 1, isPredicable = 1 in
1907 def POST_SThri : STInstPI<(outs IntRegs:$dst),
1908 (ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1909 "memh($src2++#$offset) = $src1",
1911 (post_truncsti16 IntRegs:$src1, IntRegs:$src2,
1912 s4_1ImmPred:$offset))],
1915 // Store halfword conditionally.
1916 // if ([!]Pv) memh(Rs+#u6:1)=Rt
1917 // if (Pv) memh(Rs+#u6:1)=Rt
1918 let mayStore = 1, neverHasSideEffects = 1 in
1919 def STrih_cPt : STInst<(outs),
1920 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1921 "if ($src1) memh($addr) = $src2",
1924 // if (!Pv) memh(Rs+#u6:1)=Rt
1925 let mayStore = 1, neverHasSideEffects = 1 in
1926 def STrih_cNotPt : STInst<(outs),
1927 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1928 "if (!$src1) memh($addr) = $src2",
1931 // if (Pv) memh(Rs+#u6:1)=Rt
1932 let mayStore = 1, neverHasSideEffects = 1 in
1933 def STrih_indexed_cPt : STInst<(outs),
1934 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
1935 "if ($src1) memh($src2+#$src3) = $src4",
1938 // if (!Pv) memh(Rs+#u6:1)=Rt
1939 let mayStore = 1, neverHasSideEffects = 1 in
1940 def STrih_indexed_cNotPt : STInst<(outs),
1941 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
1942 "if (!$src1) memh($src2+#$src3) = $src4",
1945 // if ([!]Pv) memh(Rx++#s4:1)=Rt
1946 // if (Pv) memh(Rx++#s4:1)=Rt
1947 let mayStore = 1, hasCtrlDep = 1 in
1948 def POST_SThri_cPt : STInstPI<(outs IntRegs:$dst),
1949 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1950 "if ($src1) memh($src3++#$offset) = $src2",
1953 // if (!Pv) memh(Rx++#s4:1)=Rt
1954 let mayStore = 1, hasCtrlDep = 1 in
1955 def POST_SThri_cNotPt : STInstPI<(outs IntRegs:$dst),
1956 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1957 "if (!$src1) memh($src3++#$offset) = $src2",
1963 let Defs = [R10,R11] in
1964 def STriw_pred : STInst<(outs),
1965 (ins MEMri:$addr, PredRegs:$src1),
1966 "Error; should not emit",
1969 // memw(Rs+#s11:2)=Rt
1970 let isPredicable = 1 in
1971 def STriw : STInst<(outs),
1972 (ins MEMri:$addr, IntRegs:$src1),
1973 "memw($addr) = $src1",
1974 [(store IntRegs:$src1, ADDRriS11_2:$addr)]>;
1976 let AddedComplexity = 10, isPredicable = 1 in
1977 def STriw_indexed : STInst<(outs),
1978 (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
1979 "memw($src1+#$src2) = $src3",
1980 [(store IntRegs:$src3, (add IntRegs:$src1, s11_2ImmPred:$src2))]>;
1982 def STriwt : STInst<(outs),
1983 (ins MEMri:$addr, DoubleRegs:$src1),
1984 "memw($addr) = $src1",
1985 [(truncstorei32 DoubleRegs:$src1, ADDRriS11_2:$addr)]>;
1987 let mayStore = 1, neverHasSideEffects = 1 in
1988 def STriw_GP : STInst<(outs),
1989 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1990 "memw(#$global+$offset) = $src",
1993 let hasCtrlDep = 1, isPredicable = 1 in
1994 def POST_STwri : STInstPI<(outs IntRegs:$dst),
1995 (ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1996 "memw($src2++#$offset) = $src1",
1998 (post_store IntRegs:$src1, IntRegs:$src2, s4_2ImmPred:$offset))],
2001 // Store word conditionally.
2002 // if ([!]Pv) memw(Rs+#u6:2)=Rt
2003 // if (Pv) memw(Rs+#u6:2)=Rt
2004 let mayStore = 1, neverHasSideEffects = 1 in
2005 def STriw_cPt : STInst<(outs),
2006 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2007 "if ($src1) memw($addr) = $src2",
2010 // if (!Pv) memw(Rs+#u6:2)=Rt
2011 let mayStore = 1, neverHasSideEffects = 1 in
2012 def STriw_cNotPt : STInst<(outs),
2013 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2014 "if (!$src1) memw($addr) = $src2",
2017 // if (Pv) memw(Rs+#u6:2)=Rt
2018 let mayStore = 1, neverHasSideEffects = 1 in
2019 def STriw_indexed_cPt : STInst<(outs),
2020 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2021 "if ($src1) memw($src2+#$src3) = $src4",
2024 // if (!Pv) memw(Rs+#u6:2)=Rt
2025 let mayStore = 1, neverHasSideEffects = 1 in
2026 def STriw_indexed_cNotPt : STInst<(outs),
2027 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2028 "if (!$src1) memw($src2+#$src3) = $src4",
2031 // if ([!]Pv) memw(Rx++#s4:2)=Rt
2032 // if (Pv) memw(Rx++#s4:2)=Rt
2033 let mayStore = 1, hasCtrlDep = 1 in
2034 def POST_STwri_cPt : STInstPI<(outs IntRegs:$dst),
2035 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2036 "if ($src1) memw($src3++#$offset) = $src2",
2039 // if (!Pv) memw(Rx++#s4:2)=Rt
2040 let mayStore = 1, hasCtrlDep = 1 in
2041 def POST_STwri_cNotPt : STInstPI<(outs IntRegs:$dst),
2042 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2043 "if (!$src1) memw($src3++#$offset) = $src2",
2048 // Allocate stack frame.
2049 let Defs = [R29, R30], Uses = [R31, R30], neverHasSideEffects = 1 in {
2050 def ALLOCFRAME : STInst<(outs),
2052 "allocframe(#$amt)",
2055 //===----------------------------------------------------------------------===//
2057 //===----------------------------------------------------------------------===//
2059 //===----------------------------------------------------------------------===//
2061 //===----------------------------------------------------------------------===//
2063 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
2064 "$dst = not($src1)",
2065 [(set DoubleRegs:$dst, (not DoubleRegs:$src1))]>;
2068 // Sign extend word to doubleword.
2069 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
2070 "$dst = sxtw($src1)",
2071 [(set DoubleRegs:$dst, (sext IntRegs:$src1))]>;
2072 //===----------------------------------------------------------------------===//
2074 //===----------------------------------------------------------------------===//
2076 //===----------------------------------------------------------------------===//
2078 //===----------------------------------------------------------------------===//
2079 //===----------------------------------------------------------------------===//
2081 //===----------------------------------------------------------------------===//
2084 //===----------------------------------------------------------------------===//
2086 //===----------------------------------------------------------------------===//
2087 //===----------------------------------------------------------------------===//
2089 //===----------------------------------------------------------------------===//
2091 //===----------------------------------------------------------------------===//
2093 //===----------------------------------------------------------------------===//
2094 //===----------------------------------------------------------------------===//
2096 //===----------------------------------------------------------------------===//
2098 //===----------------------------------------------------------------------===//
2100 //===----------------------------------------------------------------------===//
2101 // Predicate transfer.
2102 let neverHasSideEffects = 1 in
2103 def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
2104 "$dst = $src1 // Should almost never emit this",
2107 def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1),
2108 "$dst = $src1 // Should almost never emit!",
2109 [(set PredRegs:$dst, (trunc IntRegs:$src1))]>;
2110 //===----------------------------------------------------------------------===//
2112 //===----------------------------------------------------------------------===//
2114 //===----------------------------------------------------------------------===//
2116 //===----------------------------------------------------------------------===//
2117 // Shift by immediate.
2118 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2119 "$dst = asr($src1, #$src2)",
2120 [(set IntRegs:$dst, (sra IntRegs:$src1, u5ImmPred:$src2))]>;
2122 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2123 "$dst = asr($src1, #$src2)",
2124 [(set DoubleRegs:$dst, (sra DoubleRegs:$src1, u6ImmPred:$src2))]>;
2126 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2127 "$dst = asl($src1, #$src2)",
2128 [(set IntRegs:$dst, (shl IntRegs:$src1, u5ImmPred:$src2))]>;
2130 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2131 "$dst = lsr($src1, #$src2)",
2132 [(set IntRegs:$dst, (srl IntRegs:$src1, u5ImmPred:$src2))]>;
2134 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2135 "$dst = lsr($src1, #$src2)",
2136 [(set DoubleRegs:$dst, (srl DoubleRegs:$src1, u6ImmPred:$src2))]>;
2138 def LSRd_ri_acc : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2141 "$dst += lsr($src2, #$src3)",
2142 [(set DoubleRegs:$dst, (add DoubleRegs:$src1,
2143 (srl DoubleRegs:$src2,
2144 u6ImmPred:$src3)))],
2147 // Shift by immediate and accumulate.
2148 def ASR_rr_acc : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$src1,
2151 "$dst += asr($src2, $src3)",
2152 [], "$src1 = $dst">;
2154 // Shift by immediate and add.
2155 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
2157 "$dst = addasl($src1, $src2, #$src3)",
2158 [(set IntRegs:$dst, (add IntRegs:$src1,
2160 u3ImmPred:$src3)))]>;
2162 // Shift by register.
2163 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2164 "$dst = asl($src1, $src2)",
2165 [(set IntRegs:$dst, (shl IntRegs:$src1, IntRegs:$src2))]>;
2167 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2168 "$dst = asr($src1, $src2)",
2169 [(set IntRegs:$dst, (sra IntRegs:$src1, IntRegs:$src2))]>;
2172 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2173 "$dst = lsr($src1, $src2)",
2174 [(set IntRegs:$dst, (srl IntRegs:$src1, IntRegs:$src2))]>;
2176 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2177 "$dst = lsl($src1, $src2)",
2178 [(set DoubleRegs:$dst, (shl DoubleRegs:$src1, IntRegs:$src2))]>;
2180 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2182 "$dst = asr($src1, $src2)",
2183 [(set DoubleRegs:$dst, (sra DoubleRegs:$src1, IntRegs:$src2))]>;
2185 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2187 "$dst = lsr($src1, $src2)",
2188 [(set DoubleRegs:$dst, (srl DoubleRegs:$src1, IntRegs:$src2))]>;
2190 //===----------------------------------------------------------------------===//
2192 //===----------------------------------------------------------------------===//
2194 //===----------------------------------------------------------------------===//
2196 //===----------------------------------------------------------------------===//
2197 //===----------------------------------------------------------------------===//
2199 //===----------------------------------------------------------------------===//
2201 //===----------------------------------------------------------------------===//
2203 //===----------------------------------------------------------------------===//
2204 //===----------------------------------------------------------------------===//
2206 //===----------------------------------------------------------------------===//
2208 //===----------------------------------------------------------------------===//
2210 //===----------------------------------------------------------------------===//
2212 //===----------------------------------------------------------------------===//
2214 //===----------------------------------------------------------------------===//
2215 def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
2216 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
2219 let hasSideEffects = 1 in
2220 def BARRIER : STInst<(outs), (ins),
2222 [(HexagonBARRIER)]>;
2224 //===----------------------------------------------------------------------===//
2226 //===----------------------------------------------------------------------===//
2228 // TFRI64 - assembly mapped.
2229 let isReMaterializable = 1 in
2230 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
2232 [(set DoubleRegs:$dst, s8Imm64Pred:$src1)]>;
2234 // Pseudo instruction to encode a set of conditional transfers.
2235 // This instruction is used instead of a mux and trades-off codesize
2236 // for performance. We conduct this transformation optimistically in
2237 // the hope that these instructions get promoted to dot-new transfers.
2238 let AddedComplexity = 100 in
2239 def TFR_condset_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
2242 "Error; should not emit",
2243 [(set IntRegs:$dst, (select PredRegs:$src1, IntRegs:$src2,
2246 let AddedComplexity = 100 in
2247 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
2248 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
2249 "Error; should not emit",
2250 [(set IntRegs:$dst, (select PredRegs:$src1,
2252 s12ImmPred:$src3))]>;
2254 // Generate frameindex addresses.
2255 let isReMaterializable = 1 in
2256 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
2257 "$dst = add($src1)",
2258 [(set IntRegs:$dst, ADDRri:$src1)]>;
2263 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
2264 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
2265 "loop0($offset, #$src2)",
2269 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
2270 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
2271 "loop0($offset, $src2)",
2275 let isBranch = 1, isTerminator = 1, neverHasSideEffects = 1,
2276 Defs = [PC, LC0], Uses = [SA0, LC0] in {
2277 def ENDLOOP0 : CRInst<(outs), (ins brtarget:$offset),
2282 // Support for generating global address.
2283 // Taken from X86InstrInfo.td.
2284 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
2286 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
2287 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
2289 // This pattern is incorrect. When we add small data, we should change
2290 // this pattern to use memw(#foo).
2291 let isMoveImm = 1 in
2292 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2293 "$dst = CONST32(#$global)",
2295 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
2297 let isReMaterializable = 1, isMoveImm = 1 in
2298 def CONST32_set : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2299 "$dst = CONST32(#$global)",
2301 (HexagonCONST32 tglobaladdr:$global))]>;
2303 let isReMaterializable = 1, isMoveImm = 1 in
2304 def CONST32_set_jt : LDInst<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2305 "$dst = CONST32(#$jt)",
2307 (HexagonCONST32 tjumptable:$jt))]>;
2309 let isReMaterializable = 1, isMoveImm = 1 in
2310 def CONST32GP_set : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2311 "$dst = CONST32(#$global)",
2313 (HexagonCONST32_GP tglobaladdr:$global))]>;
2315 let isReMaterializable = 1, isMoveImm = 1 in
2316 def CONST32_Int_Real : LDInst<(outs IntRegs:$dst), (ins i32imm:$global),
2317 "$dst = CONST32(#$global)",
2318 [(set IntRegs:$dst, imm:$global) ]>;
2320 let isReMaterializable = 1, isMoveImm = 1 in
2321 def CONST32_Label : LDInst<(outs IntRegs:$dst), (ins bblabel:$label),
2322 "$dst = CONST32($label)",
2323 [(set IntRegs:$dst, (HexagonCONST32 bbl:$label))]>;
2325 let isReMaterializable = 1, isMoveImm = 1 in
2326 def CONST64_Int_Real : LDInst<(outs DoubleRegs:$dst), (ins i64imm:$global),
2327 "$dst = CONST64(#$global)",
2328 [(set DoubleRegs:$dst, imm:$global) ]>;
2330 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
2331 "$dst = xor($dst, $dst)",
2332 [(set PredRegs:$dst, 0)]>;
2334 def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2335 "$dst = mpy($src1, $src2)",
2337 (trunc (i64 (srl (i64 (mul (i64 (sext IntRegs:$src1)),
2338 (i64 (sext IntRegs:$src2)))),
2341 // Pseudo instructions.
2342 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
2344 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
2345 SDTCisVT<1, i32> ]>;
2347 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
2348 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2350 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
2351 [SDNPHasChain, SDNPOutGlue]>;
2353 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2355 def call : SDNode<"HexagonISD::CALL", SDT_SPCall,
2356 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
2358 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
2359 // Optional Flag and Variable Arguments.
2360 // Its 1 Operand has pointer type.
2361 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
2362 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
2364 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
2365 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
2366 "Should never be emitted",
2367 [(callseq_start timm:$amt)]>;
2370 let Defs = [R29, R30, R31], Uses = [R29] in {
2371 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2372 "Should never be emitted",
2373 [(callseq_end timm:$amt1, timm:$amt2)]>;
2376 let isCall = 1, neverHasSideEffects = 1,
2377 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2378 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2379 def CALL : JInst<(outs), (ins calltarget:$dst, variable_ops),
2383 // Call subroutine from register.
2384 let isCall = 1, neverHasSideEffects = 1,
2385 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2386 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2387 def CALLR : JRInst<(outs), (ins IntRegs:$dst, variable_ops),
2393 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
2394 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2395 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2396 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst, variable_ops),
2397 "jump $dst // TAILCALL", []>;
2399 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
2400 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2401 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2402 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst, variable_ops),
2403 "jump $dst // TAILCALL", []>;
2406 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
2407 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2408 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2409 def TCRETURNR : JInst<(outs), (ins IntRegs:$dst, variable_ops),
2410 "jumpr $dst // TAILCALL", []>;
2412 // Map call instruction.
2413 def : Pat<(call IntRegs:$dst),
2414 (CALLR IntRegs:$dst)>, Requires<[HasV2TOnly]>;
2415 def : Pat<(call tglobaladdr:$dst),
2416 (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
2417 def : Pat<(call texternalsym:$dst),
2418 (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>;
2420 def : Pat<(HexagonTCRet tglobaladdr:$dst),
2421 (TCRETURNtg tglobaladdr:$dst)>;
2422 def : Pat<(HexagonTCRet texternalsym:$dst),
2423 (TCRETURNtext texternalsym:$dst)>;
2424 def : Pat<(HexagonTCRet IntRegs:$dst),
2425 (TCRETURNR IntRegs:$dst)>;
2427 // Map from r0 = and(r1, 65535) to r0 = zxth(r1).
2428 def : Pat <(and IntRegs:$src1, 65535),
2429 (ZXTH IntRegs:$src1)>;
2431 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
2432 def : Pat <(and IntRegs:$src1, 255),
2433 (ZXTB IntRegs:$src1)>;
2435 // Map Add(p1, true) to p1 = not(p1).
2436 // Add(p1, false) should never be produced,
2437 // if it does, it got to be mapped to NOOP.
2438 def : Pat <(add PredRegs:$src1, -1),
2439 (NOT_pp PredRegs:$src1)>;
2441 // Map from p0 = setlt(r0, r1) r2 = mux(p0, r3, r4) =>
2442 // p0 = cmp.lt(r0, r1), r0 = mux(p0, r2, r1).
2443 def : Pat <(select (i1 (setlt IntRegs:$src1, IntRegs:$src2)), IntRegs:$src3,
2445 (TFR_condset_rr (CMPLTrr IntRegs:$src1, IntRegs:$src2), IntRegs:$src4,
2446 IntRegs:$src3)>, Requires<[HasV2TOnly]>;
2448 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
2449 def : Pat <(select (not PredRegs:$src1), s8ImmPred:$src2, s8ImmPred:$src3),
2450 (TFR_condset_ii PredRegs:$src1, s8ImmPred:$src3, s8ImmPred:$src2)>;
2452 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
2453 def : Pat <(brcond (not PredRegs:$src1), bb:$offset),
2454 (JMP_PredNot PredRegs:$src1, bb:$offset)>;
2456 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
2457 def : Pat <(and PredRegs:$src1, (not PredRegs:$src2)),
2458 (AND_pnotp PredRegs:$src1, PredRegs:$src2)>;
2460 // Map from store(globaladdress + x) -> memd(#foo + x).
2461 let AddedComplexity = 100 in
2462 def : Pat <(store DoubleRegs:$src1,
2463 (add (HexagonCONST32_GP tglobaladdr:$global),
2464 u16ImmPred:$offset)),
2465 (STrid_GP tglobaladdr:$global, u16ImmPred:$offset, DoubleRegs:$src1)>;
2467 // Map from store(globaladdress) -> memd(#foo + 0).
2468 let AddedComplexity = 100 in
2469 def : Pat <(store DoubleRegs:$src1, (HexagonCONST32_GP tglobaladdr:$global)),
2470 (STrid_GP tglobaladdr:$global, 0, DoubleRegs:$src1)>;
2472 // Map from store(globaladdress + x) -> memw(#foo + x).
2473 let AddedComplexity = 100 in
2474 def : Pat <(store IntRegs:$src1, (add (HexagonCONST32_GP tglobaladdr:$global),
2475 u16ImmPred:$offset)),
2476 (STriw_GP tglobaladdr:$global, u16ImmPred:$offset, IntRegs:$src1)>;
2478 // Map from store(globaladdress) -> memw(#foo + 0).
2479 let AddedComplexity = 100 in
2480 def : Pat <(store IntRegs:$src1, (HexagonCONST32_GP tglobaladdr:$global)),
2481 (STriw_GP tglobaladdr:$global, 0, IntRegs:$src1)>;
2483 // Map from store(globaladdress) -> memw(#foo + 0).
2484 let AddedComplexity = 100 in
2485 def : Pat <(store IntRegs:$src1, (HexagonCONST32_GP tglobaladdr:$global)),
2486 (STriw_GP tglobaladdr:$global, 0, IntRegs:$src1)>;
2488 // Map from store(globaladdress + x) -> memh(#foo + x).
2489 let AddedComplexity = 100 in
2490 def : Pat <(truncstorei16 IntRegs:$src1,
2491 (add (HexagonCONST32_GP tglobaladdr:$global),
2492 u16ImmPred:$offset)),
2493 (STrih_GP tglobaladdr:$global, u16ImmPred:$offset, IntRegs:$src1)>;
2495 // Map from store(globaladdress) -> memh(#foo).
2496 let AddedComplexity = 100 in
2497 def : Pat <(truncstorei16 IntRegs:$src1,
2498 (HexagonCONST32_GP tglobaladdr:$global)),
2499 (STh_GP tglobaladdr:$global, IntRegs:$src1)>;
2501 // Map from store(globaladdress + x) -> memb(#foo + x).
2502 let AddedComplexity = 100 in
2503 def : Pat <(truncstorei8 IntRegs:$src1,
2504 (add (HexagonCONST32_GP tglobaladdr:$global),
2505 u16ImmPred:$offset)),
2506 (STrib_GP tglobaladdr:$global, u16ImmPred:$offset, IntRegs:$src1)>;
2508 // Map from store(globaladdress) -> memb(#foo).
2509 let AddedComplexity = 100 in
2510 def : Pat <(truncstorei8 IntRegs:$src1,
2511 (HexagonCONST32_GP tglobaladdr:$global)),
2512 (STb_GP tglobaladdr:$global, IntRegs:$src1)>;
2514 // Map from load(globaladdress + x) -> memw(#foo + x).
2515 let AddedComplexity = 100 in
2516 def : Pat <(load (add (HexagonCONST32_GP tglobaladdr:$global),
2517 u16ImmPred:$offset)),
2518 (LDriw_GP tglobaladdr:$global, u16ImmPred:$offset)>;
2520 // Map from load(globaladdress) -> memw(#foo + 0).
2521 let AddedComplexity = 100 in
2522 def : Pat <(load (HexagonCONST32_GP tglobaladdr:$global)),
2523 (LDw_GP tglobaladdr:$global)>;
2525 // Map from load(globaladdress + x) -> memd(#foo + x).
2526 let AddedComplexity = 100 in
2527 def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),
2528 u16ImmPred:$offset))),
2529 (LDrid_GP tglobaladdr:$global, u16ImmPred:$offset)>;
2531 // Map from load(globaladdress) -> memw(#foo + 0).
2532 let AddedComplexity = 100 in
2533 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
2534 (LDd_GP tglobaladdr:$global)>;
2537 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress + 0), Pd = Rd.
2538 let AddedComplexity = 100 in
2539 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
2540 (TFR_PdRs (LDrib_GP tglobaladdr:$global, 0))>;
2542 // Map from load(globaladdress + x) -> memh(#foo + x).
2543 let AddedComplexity = 100 in
2544 def : Pat <(sextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2545 u16ImmPred:$offset)),
2546 (LDrih_GP tglobaladdr:$global, u16ImmPred:$offset)>;
2548 // Map from load(globaladdress) -> memh(#foo + 0).
2549 let AddedComplexity = 100 in
2550 def : Pat <(sextloadi16 (HexagonCONST32_GP tglobaladdr:$global)),
2551 (LDrih_GP tglobaladdr:$global, 0)>;
2553 // Map from load(globaladdress + x) -> memuh(#foo + x).
2554 let AddedComplexity = 100 in
2555 def : Pat <(zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2556 u16ImmPred:$offset)),
2557 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset)>;
2559 // Map from load(globaladdress) -> memuh(#foo + 0).
2560 let AddedComplexity = 100 in
2561 def : Pat <(zextloadi16 (HexagonCONST32_GP tglobaladdr:$global)),
2562 (LDriuh_GP tglobaladdr:$global, 0)>;
2564 // Map from load(globaladdress + x) -> memuh(#foo + x).
2565 let AddedComplexity = 100 in
2566 def : Pat <(extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2567 u16ImmPred:$offset)),
2568 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset)>;
2570 // Map from load(globaladdress) -> memuh(#foo + 0).
2571 let AddedComplexity = 100 in
2572 def : Pat <(extloadi16 (HexagonCONST32_GP tglobaladdr:$global)),
2573 (LDriuh_GP tglobaladdr:$global, 0)>;
2574 // Map from load(globaladdress + x) -> memub(#foo + x).
2575 let AddedComplexity = 100 in
2576 def : Pat <(zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2577 u16ImmPred:$offset)),
2578 (LDriub_GP tglobaladdr:$global, u16ImmPred:$offset)>;
2580 // Map from load(globaladdress) -> memuh(#foo + 0).
2581 let AddedComplexity = 100 in
2582 def : Pat <(zextloadi8 (HexagonCONST32_GP tglobaladdr:$global)),
2583 (LDriub_GP tglobaladdr:$global, 0)>;
2585 // Map from load(globaladdress + x) -> memb(#foo + x).
2586 let AddedComplexity = 100 in
2587 def : Pat <(sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2588 u16ImmPred:$offset)),
2589 (LDrib_GP tglobaladdr:$global, u16ImmPred:$offset)>;
2591 // Map from load(globaladdress) -> memb(#foo).
2592 let AddedComplexity = 100 in
2593 def : Pat <(extloadi8 (HexagonCONST32_GP tglobaladdr:$global)),
2594 (LDb_GP tglobaladdr:$global)>;
2596 // Map from load(globaladdress) -> memb(#foo).
2597 let AddedComplexity = 100 in
2598 def : Pat <(sextloadi8 (HexagonCONST32_GP tglobaladdr:$global)),
2599 (LDb_GP tglobaladdr:$global)>;
2601 // Map from load(globaladdress) -> memub(#foo).
2602 let AddedComplexity = 100 in
2603 def : Pat <(zextloadi8 (HexagonCONST32_GP tglobaladdr:$global)),
2604 (LDub_GP tglobaladdr:$global)>;
2606 // When the Interprocedural Global Variable optimizer realizes that a
2607 // certain global variable takes only two constant values, it shrinks the
2608 // global to a boolean. Catch those loads here in the following 3 patterns.
2609 let AddedComplexity = 100 in
2610 def : Pat <(extloadi1 (HexagonCONST32_GP tglobaladdr:$global)),
2611 (LDb_GP tglobaladdr:$global)>;
2613 let AddedComplexity = 100 in
2614 def : Pat <(sextloadi1 (HexagonCONST32_GP tglobaladdr:$global)),
2615 (LDb_GP tglobaladdr:$global)>;
2617 let AddedComplexity = 100 in
2618 def : Pat <(zextloadi1 (HexagonCONST32_GP tglobaladdr:$global)),
2619 (LDub_GP tglobaladdr:$global)>;
2621 // Map from load(globaladdress) -> memh(#foo).
2622 let AddedComplexity = 100 in
2623 def : Pat <(extloadi16 (HexagonCONST32_GP tglobaladdr:$global)),
2624 (LDh_GP tglobaladdr:$global)>;
2626 // Map from load(globaladdress) -> memh(#foo).
2627 let AddedComplexity = 100 in
2628 def : Pat <(sextloadi16 (HexagonCONST32_GP tglobaladdr:$global)),
2629 (LDh_GP tglobaladdr:$global)>;
2631 // Map from load(globaladdress) -> memuh(#foo).
2632 let AddedComplexity = 100 in
2633 def : Pat <(zextloadi16 (HexagonCONST32_GP tglobaladdr:$global)),
2634 (LDuh_GP tglobaladdr:$global)>;
2636 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
2637 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
2638 (AND_rr (LDrib ADDRriS11_0:$addr), (TFRI 0x1))>;
2640 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
2641 def : Pat <(i64 (sext_inreg DoubleRegs:$src1, i32)),
2642 (i64 (SXTW (EXTRACT_SUBREG DoubleRegs:$src1, subreg_loreg)))>;
2644 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
2645 def : Pat <(i64 (sext_inreg DoubleRegs:$src1, i16)),
2646 (i64 (SXTW (SXTH (EXTRACT_SUBREG DoubleRegs:$src1, subreg_loreg))))>;
2648 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
2649 def : Pat <(i64 (sext_inreg DoubleRegs:$src1, i8)),
2650 (i64 (SXTW (SXTB (EXTRACT_SUBREG DoubleRegs:$src1, subreg_loreg))))>;
2652 // We want to prevent emiting pnot's as much as possible.
2653 // Map brcond with an unsupported setcc to a JMP_PredNot.
2654 def : Pat <(brcond (i1 (setne IntRegs:$src1, IntRegs:$src2)), bb:$offset),
2655 (JMP_PredNot (CMPEQrr IntRegs:$src1, IntRegs:$src2), bb:$offset)>;
2657 def : Pat <(brcond (i1 (setne IntRegs:$src1, s10ImmPred:$src2)), bb:$offset),
2658 (JMP_PredNot (CMPEQri IntRegs:$src1, s10ImmPred:$src2), bb:$offset)>;
2660 def : Pat <(brcond (i1 (setne PredRegs:$src1, (i1 -1))), bb:$offset),
2661 (JMP_PredNot PredRegs:$src1, bb:$offset)>;
2663 def : Pat <(brcond (i1 (setne PredRegs:$src1, (i1 0))), bb:$offset),
2664 (JMP_Pred PredRegs:$src1, bb:$offset)>;
2666 def : Pat <(brcond (i1 (setlt IntRegs:$src1, s8ImmPred:$src2)), bb:$offset),
2667 (JMP_PredNot (CMPGEri IntRegs:$src1, s8ImmPred:$src2), bb:$offset)>;
2669 def : Pat <(brcond (i1 (setlt IntRegs:$src1, IntRegs:$src2)), bb:$offset),
2670 (JMP_Pred (CMPLTrr IntRegs:$src1, IntRegs:$src2), bb:$offset)>;
2672 def : Pat <(brcond (i1 (setuge DoubleRegs:$src1, DoubleRegs:$src2)),
2674 (JMP_PredNot (CMPGTU64rr DoubleRegs:$src2, DoubleRegs:$src1),
2677 def : Pat <(brcond (i1 (setule IntRegs:$src1, IntRegs:$src2)), bb:$offset),
2678 (JMP_PredNot (CMPGTUrr IntRegs:$src1, IntRegs:$src2), bb:$offset)>;
2680 def : Pat <(brcond (i1 (setule DoubleRegs:$src1, DoubleRegs:$src2)),
2682 (JMP_PredNot (CMPGTU64rr DoubleRegs:$src1, DoubleRegs:$src2),
2685 // Map from a 64-bit select to an emulated 64-bit mux.
2686 // Hexagon does not support 64-bit MUXes; so emulate with combines.
2687 def : Pat <(select PredRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
2689 (MUX_rr PredRegs:$src1,
2690 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_hireg),
2691 (EXTRACT_SUBREG DoubleRegs:$src3, subreg_hireg)),
2692 (MUX_rr PredRegs:$src1,
2693 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_loreg),
2694 (EXTRACT_SUBREG DoubleRegs:$src3, subreg_loreg)))>;
2696 // Map from a 1-bit select to logical ops.
2697 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
2698 def : Pat <(select PredRegs:$src1, PredRegs:$src2, PredRegs:$src3),
2699 (OR_pp (AND_pp PredRegs:$src1, PredRegs:$src2),
2700 (AND_pp (NOT_pp PredRegs:$src1), PredRegs:$src3))>;
2702 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
2703 def : Pat<(i1 (load ADDRriS11_2:$addr)),
2704 (i1 (TFR_PdRs (i32 (LDrib ADDRriS11_2:$addr))))>;
2706 // Map for truncating from 64 immediates to 32 bit immediates.
2707 def : Pat<(i32 (trunc DoubleRegs:$src)),
2708 (i32 (EXTRACT_SUBREG DoubleRegs:$src, subreg_loreg))>;
2710 // Map for truncating from i64 immediates to i1 bit immediates.
2711 def : Pat<(i1 (trunc DoubleRegs:$src)),
2712 (i1 (TFR_PdRs (i32(EXTRACT_SUBREG DoubleRegs:$src, subreg_loreg))))>;
2714 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
2715 def : Pat<(truncstorei8 DoubleRegs:$src, ADDRriS11_0:$addr),
2716 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src,
2719 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
2720 def : Pat<(truncstorei16 DoubleRegs:$src, ADDRriS11_0:$addr),
2721 (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src,
2724 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
2725 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2726 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2728 let AddedComplexity = 100 in
2729 // Map from i1 = constant<-1>; memw(CONST32(#foo)) = i1 -> r0 = 1;
2731 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
2732 (STb_GP tglobaladdr:$global, (TFRI 1))>;
2735 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
2736 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2737 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2739 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
2740 def : Pat<(store PredRegs:$src1, ADDRriS11_2:$addr),
2741 (STrib ADDRriS11_2:$addr, (i32 (MUX_ii PredRegs:$src1, 1, 0)) )>;
2743 // Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs).
2744 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
2745 // Better way to do this?
2746 def : Pat<(i64 (anyext IntRegs:$src1)),
2747 (i64 (SXTW IntRegs:$src1))>;
2749 // Map cmple -> cmpgt.
2750 // rs <= rt -> !(rs > rt).
2751 def : Pat<(i1 (setle IntRegs:$src1, s10ImmPred:$src2)),
2752 (i1 (NOT_Ps (CMPGTri IntRegs:$src1, s10ImmPred:$src2)))>;
2754 // rs <= rt -> !(rs > rt).
2755 def : Pat<(i1 (setle IntRegs:$src1, IntRegs:$src2)),
2756 (i1 (NOT_Ps (CMPGTrr IntRegs:$src1, IntRegs:$src2)))>;
2758 // Rss <= Rtt -> !(Rss > Rtt).
2759 def : Pat<(i1 (setle DoubleRegs:$src1, DoubleRegs:$src2)),
2760 (i1 (NOT_Ps (CMPGT64rr DoubleRegs:$src1, DoubleRegs:$src2)))>;
2762 // Map cmpne -> cmpeq.
2763 // Hexagon_TODO: We should improve on this.
2764 // rs != rt -> !(rs == rt).
2765 def : Pat <(i1 (setne IntRegs:$src1, s10ImmPred:$src2)),
2766 (i1 (NOT_Ps(i1 (CMPEQri IntRegs:$src1, s10ImmPred:$src2))))>;
2768 // Map cmpne(Rs) -> !cmpeqe(Rs).
2769 // rs != rt -> !(rs == rt).
2770 def : Pat <(i1 (setne IntRegs:$src1, IntRegs:$src2)),
2771 (i1 (NOT_Ps(i1 (CMPEQrr IntRegs:$src1, IntRegs:$src2))))>;
2773 // Convert setne back to xor for hexagon since we compute w/ pred registers.
2774 def : Pat <(i1 (setne PredRegs:$src1, PredRegs:$src2)),
2775 (i1 (XOR_pp PredRegs:$src1, PredRegs:$src2))>;
2777 // Map cmpne(Rss) -> !cmpew(Rss).
2778 // rs != rt -> !(rs == rt).
2779 def : Pat <(i1 (setne DoubleRegs:$src1, DoubleRegs:$src2)),
2780 (i1 (NOT_Ps(i1 (CMPEHexagon4rr DoubleRegs:$src1, DoubleRegs:$src2))))>;
2782 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
2783 // rs >= rt -> !(rt > rs).
2784 def : Pat <(i1 (setge IntRegs:$src1, IntRegs:$src2)),
2785 (i1 (NOT_Ps(i1 (CMPGTrr IntRegs:$src2, IntRegs:$src1))))>;
2787 def : Pat <(i1 (setge IntRegs:$src1, s8ImmPred:$src2)),
2788 (i1 (CMPGEri IntRegs:$src1, s8ImmPred:$src2))>;
2790 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
2791 // rss >= rtt -> !(rtt > rss).
2792 def : Pat <(i1 (setge DoubleRegs:$src1, DoubleRegs:$src2)),
2793 (i1 (NOT_Ps(i1 (CMPGT64rr DoubleRegs:$src2, DoubleRegs:$src1))))>;
2795 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
2796 // rs < rt -> !(rs >= rt).
2797 def : Pat <(i1 (setlt IntRegs:$src1, s8ImmPred:$src2)),
2798 (i1 (NOT_Ps (CMPGEri IntRegs:$src1, s8ImmPred:$src2)))>;
2800 // Map cmplt(Rs, Rt) -> cmplt(Rs, Rt).
2801 // rs < rt -> rs < rt. Let assembler map it.
2802 def : Pat <(i1 (setlt IntRegs:$src1, IntRegs:$src2)),
2803 (i1 (CMPLTrr IntRegs:$src2, IntRegs:$src1))>;
2805 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
2806 // rss < rtt -> (rtt > rss).
2807 def : Pat <(i1 (setlt DoubleRegs:$src1, DoubleRegs:$src2)),
2808 (i1 (CMPGT64rr DoubleRegs:$src2, DoubleRegs:$src1))>;
2810 // Map from cmpltu(Rs, Rd) -> !cmpgtu(Rs, Rd - 1).
2811 // rs < rt -> rt > rs.
2812 def : Pat <(i1 (setult IntRegs:$src1, IntRegs:$src2)),
2813 (i1 (CMPGTUrr IntRegs:$src2, IntRegs:$src1))>;
2815 // Map from cmpltu(Rss, Rdd) -> !cmpgtu(Rss, Rdd - 1).
2816 // rs < rt -> rt > rs.
2817 def : Pat <(i1 (setult DoubleRegs:$src1, DoubleRegs:$src2)),
2818 (i1 (CMPGTU64rr DoubleRegs:$src2, DoubleRegs:$src1))>;
2820 // Map from Rs >= Rt -> !(Rt > Rs).
2821 // rs >= rt -> !(rt > rs).
2822 def : Pat <(i1 (setuge IntRegs:$src1, IntRegs:$src2)),
2823 (i1 (NOT_Ps (CMPGTUrr IntRegs:$src2, IntRegs:$src1)))>;
2825 // Map from Rs >= Rt -> !(Rt > Rs).
2826 // rs >= rt -> !(rt > rs).
2827 def : Pat <(i1 (setuge DoubleRegs:$src1, DoubleRegs:$src2)),
2828 (i1 (NOT_Ps (CMPGTU64rr DoubleRegs:$src2, DoubleRegs:$src1)))>;
2830 // Map from cmpleu(Rs, Rs) -> !cmpgtu(Rs, Rs).
2831 // Map from (Rs <= Rt) -> !(Rs > Rt).
2832 def : Pat <(i1 (setule IntRegs:$src1, IntRegs:$src2)),
2833 (i1 (NOT_Ps (CMPGTUrr IntRegs:$src1, IntRegs:$src2)))>;
2835 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
2836 // Map from (Rs <= Rt) -> !(Rs > Rt).
2837 def : Pat <(i1 (setule DoubleRegs:$src1, DoubleRegs:$src2)),
2838 (i1 (NOT_Ps (CMPGTU64rr DoubleRegs:$src1, DoubleRegs:$src2)))>;
2842 def : Pat <(i32 (sext PredRegs:$src1)),
2843 (i32 (MUX_ii PredRegs:$src1, -1, 0))>;
2845 // Convert sign-extended load back to load and sign extend.
2847 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
2848 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2850 // Convert any-extended load back to load and sign extend.
2852 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
2853 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2855 // Convert sign-extended load back to load and sign extend.
2857 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
2858 (i64 (SXTW (LDrih ADDRriS11_1:$src1)))>;
2860 // Convert sign-extended load back to load and sign extend.
2862 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
2863 (i64 (SXTW (LDriw ADDRriS11_2:$src1)))>;
2868 def : Pat <(i32 (zext PredRegs:$src1)),
2869 (i32 (MUX_ii PredRegs:$src1, 1, 0))>;
2872 def : Pat <(i64 (zext PredRegs:$src1)),
2873 (i64 (COMBINE_rr (TFRI 0), (MUX_ii PredRegs:$src1, 1, 0)))>;
2876 def : Pat <(i64 (zext IntRegs:$src1)),
2877 (i64 (COMBINE_rr (TFRI 0), IntRegs:$src1))>;
2880 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
2881 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>;
2884 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
2885 (i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>;
2888 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
2889 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>;
2891 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
2892 (i32 (LDriw ADDRriS11_0:$src1))>;
2894 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2895 def : Pat <(i32 (zext PredRegs:$src1)),
2896 (i32 (MUX_ii PredRegs:$src1, 1, 0))>;
2898 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2899 def : Pat <(i32 (anyext PredRegs:$src1)),
2900 (i32 (MUX_ii PredRegs:$src1, 1, 0))>;
2902 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
2903 def : Pat <(i64 (anyext PredRegs:$src1)),
2904 (i64 (SXTW (i32 (MUX_ii PredRegs:$src1, 1, 0))))>;
2907 // Any extended 64-bit load.
2908 // anyext i32 -> i64
2909 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
2910 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>;
2912 // anyext i16 -> i64.
2913 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
2914 (i64 (COMBINE_rr (TFRI 0), (LDrih ADDRriS11_2:$src1)))>;
2916 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
2917 def : Pat<(i64 (zext IntRegs:$src1)),
2918 (i64 (COMBINE_rr (TFRI 0), IntRegs:$src1))>;
2920 // Multiply 64-bit unsigned and use upper result.
2921 def : Pat <(mulhu DoubleRegs:$src1, DoubleRegs:$src2),
2922 (MPYU64_acc(COMBINE_rr (TFRI 0),
2924 (LSRd_ri(MPYU64_acc(MPYU64_acc(COMBINE_rr (TFRI 0),
2925 (EXTRACT_SUBREG (LSRd_ri(MPYU64
2926 (EXTRACT_SUBREG DoubleRegs:$src1,
2928 (EXTRACT_SUBREG DoubleRegs:$src2,
2930 32) ,subreg_loreg)),
2931 (EXTRACT_SUBREG DoubleRegs:$src1,
2933 (EXTRACT_SUBREG DoubleRegs:$src2,
2935 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_loreg),
2936 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_hireg)),
2938 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg),
2939 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_hireg)
2942 // Multiply 64-bit signed and use upper result.
2943 def : Pat <(mulhs DoubleRegs:$src1, DoubleRegs:$src2),
2944 (MPY64_acc(COMBINE_rr (TFRI 0),
2946 (LSRd_ri(MPY64_acc(MPY64_acc(COMBINE_rr (TFRI 0),
2947 (EXTRACT_SUBREG (LSRd_ri(MPYU64
2948 (EXTRACT_SUBREG DoubleRegs:$src1,
2950 (EXTRACT_SUBREG DoubleRegs:$src2,
2952 32) ,subreg_loreg)),
2953 (EXTRACT_SUBREG DoubleRegs:$src1,
2955 (EXTRACT_SUBREG DoubleRegs:$src2,
2957 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_loreg),
2958 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_hireg)),
2960 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg),
2961 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_hireg)
2964 // Hexagon specific ISD nodes.
2965 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
2966 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
2967 SDTHexagonADJDYNALLOC>;
2968 // Needed to tag these instructions for stack layout.
2969 let usesCustomInserter = 1 in
2970 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
2972 "$dst = add($src1, #$src2)",
2973 [(set IntRegs:$dst, (Hexagon_ADJDYNALLOC IntRegs:$src1,
2974 s16ImmPred:$src2))]>;
2976 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, []>;
2977 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
2978 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
2980 [(set IntRegs:$dst, (Hexagon_ARGEXTEND IntRegs:$src1))]>;
2982 let AddedComplexity = 100 in
2983 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND IntRegs:$src1), i16)),
2984 (TFR IntRegs:$src1)>;
2987 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2988 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
2990 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
2991 def BR_JT : JRInst<(outs), (ins IntRegs:$src),
2993 [(HexagonBR_JT IntRegs:$src)]>;
2994 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
2996 def : Pat<(HexagonWrapperJT tjumptable:$dst),
2997 (CONST32_set_jt tjumptable:$dst)>;
3000 //===----------------------------------------------------------------------===//
3001 // V3 Instructions +
3002 //===----------------------------------------------------------------------===//
3004 include "HexagonInstrInfoV3.td"
3006 //===----------------------------------------------------------------------===//
3007 // V3 Instructions -
3008 //===----------------------------------------------------------------------===//
3010 //===----------------------------------------------------------------------===//
3011 // V4 Instructions +
3012 //===----------------------------------------------------------------------===//
3014 include "HexagonInstrInfoV4.td"