1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
17 // Multi-class for logical operators.
18 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
19 def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
20 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
21 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),
23 def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
24 !strconcat("$dst = ", !strconcat(OpcStr, "(#$b, $c)")),
25 [(set (i32 IntRegs:$dst), (OpNode s10Imm:$b,
29 // Multi-class for compare ops.
30 let isCompare = 1 in {
31 multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
32 def rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
33 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
34 [(set (i1 PredRegs:$dst),
35 (OpNode (i64 DoubleRegs:$b), (i64 DoubleRegs:$c)))]>;
37 multiclass CMP32_rr<string OpcStr, PatFrag OpNode> {
38 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
39 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
40 [(set (i1 PredRegs:$dst),
41 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
44 multiclass CMP32_rr_ri_s10<string OpcStr, string CextOp, PatFrag OpNode> {
45 let CextOpcode = CextOp in {
46 let InputType = "reg" in
47 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
48 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
49 [(set (i1 PredRegs:$dst),
50 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
52 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1,
53 opExtentBits = 10, InputType = "imm" in
54 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Ext:$c),
55 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
56 [(set (i1 PredRegs:$dst),
57 (OpNode (i32 IntRegs:$b), s10ExtPred:$c))]>;
61 multiclass CMP32_rr_ri_u9<string OpcStr, string CextOp, PatFrag OpNode> {
62 let CextOpcode = CextOp in {
63 let InputType = "reg" in
64 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
65 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
66 [(set (i1 PredRegs:$dst),
67 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
69 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0,
70 opExtentBits = 9, InputType = "imm" in
71 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Ext:$c),
72 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
73 [(set (i1 PredRegs:$dst),
74 (OpNode (i32 IntRegs:$b), u9ExtPred:$c))]>;
78 multiclass CMP32_ri_u8<string OpcStr, PatFrag OpNode> {
79 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in
80 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u8Ext:$c),
81 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
82 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
86 multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
87 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
88 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Ext:$c),
89 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
90 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
95 //===----------------------------------------------------------------------===//
96 // ALU32/ALU (Instructions with register-register form)
97 //===----------------------------------------------------------------------===//
98 multiclass ALU32_Pbase<string mnemonic, bit isNot,
101 let PNewValue = !if(isPredNew, "new", "") in
102 def NAME : ALU32_rr<(outs IntRegs:$dst),
103 (ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
104 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
105 ") $dst = ")#mnemonic#"($src2, $src3)",
109 multiclass ALU32_Pred<string mnemonic, bit PredNot> {
110 let PredSense = !if(PredNot, "false", "true") in {
111 defm _c#NAME : ALU32_Pbase<mnemonic, PredNot, 0>;
113 defm _cdn#NAME : ALU32_Pbase<mnemonic, PredNot, 1>;
117 let InputType = "reg" in
118 multiclass ALU32_base<string mnemonic, string CextOp, SDNode OpNode> {
119 let CextOpcode = CextOp, BaseOpcode = CextOp#_rr in {
120 let isPredicable = 1 in
121 def NAME : ALU32_rr<(outs IntRegs:$dst),
122 (ins IntRegs:$src1, IntRegs:$src2),
123 "$dst = "#mnemonic#"($src1, $src2)",
124 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
125 (i32 IntRegs:$src2)))]>;
127 let neverHasSideEffects = 1, isPredicated = 1 in {
128 defm Pt : ALU32_Pred<mnemonic, 0>;
129 defm NotPt : ALU32_Pred<mnemonic, 1>;
134 let isCommutable = 1 in {
135 defm ADD_rr : ALU32_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
136 defm AND_rr : ALU32_base<"and", "AND", and>, ImmRegRel, PredNewRel;
137 defm XOR_rr : ALU32_base<"xor", "XOR", xor>, ImmRegRel, PredNewRel;
138 defm OR_rr : ALU32_base<"or", "OR", or>, ImmRegRel, PredNewRel;
141 defm SUB_rr : ALU32_base<"sub", "SUB", sub>, ImmRegRel, PredNewRel;
143 //===----------------------------------------------------------------------===//
144 // ALU32/ALU (ADD with register-immediate form)
145 //===----------------------------------------------------------------------===//
146 multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
147 let PNewValue = !if(isPredNew, "new", "") in
148 def NAME : ALU32_ri<(outs IntRegs:$dst),
149 (ins PredRegs:$src1, IntRegs:$src2, s8Ext: $src3),
150 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
151 ") $dst = ")#mnemonic#"($src2, #$src3)",
155 multiclass ALU32ri_Pred<string mnemonic, bit PredNot> {
156 let PredSense = !if(PredNot, "false", "true") in {
157 defm _c#NAME : ALU32ri_Pbase<mnemonic, PredNot, 0>;
159 defm _cdn#NAME : ALU32ri_Pbase<mnemonic, PredNot, 1>;
163 let isExtendable = 1, InputType = "imm" in
164 multiclass ALU32ri_base<string mnemonic, string CextOp, SDNode OpNode> {
165 let CextOpcode = CextOp, BaseOpcode = CextOp#_ri in {
166 let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
168 def NAME : ALU32_ri<(outs IntRegs:$dst),
169 (ins IntRegs:$src1, s16Ext:$src2),
170 "$dst = "#mnemonic#"($src1, #$src2)",
171 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
172 (s16ExtPred:$src2)))]>;
174 let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
175 neverHasSideEffects = 1, isPredicated = 1 in {
176 defm Pt : ALU32ri_Pred<mnemonic, 0>;
177 defm NotPt : ALU32ri_Pred<mnemonic, 1>;
182 defm ADD_ri : ALU32ri_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
184 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
185 CextOpcode = "OR", InputType = "imm" in
186 def OR_ri : ALU32_ri<(outs IntRegs:$dst),
187 (ins IntRegs:$src1, s10Ext:$src2),
188 "$dst = or($src1, #$src2)",
189 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
190 s10ExtPred:$src2))]>, ImmRegRel;
192 def NOT_rr : ALU32_rr<(outs IntRegs:$dst),
195 [(set (i32 IntRegs:$dst), (not (i32 IntRegs:$src1)))]>;
197 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
198 InputType = "imm", CextOpcode = "AND" in
199 def AND_ri : ALU32_ri<(outs IntRegs:$dst),
200 (ins IntRegs:$src1, s10Ext:$src2),
201 "$dst = and($src1, #$src2)",
202 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
203 s10ExtPred:$src2))]>, ImmRegRel;
205 def NEG : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
207 [(set (i32 IntRegs:$dst), (ineg (i32 IntRegs:$src1)))]>;
209 let neverHasSideEffects = 1 in
210 def NOP : ALU32_rr<(outs), (ins),
214 // Rd32=sub(#s10,Rs32)
215 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
216 CextOpcode = "SUB", InputType = "imm" in
217 def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
218 (ins s10Ext:$src1, IntRegs:$src2),
219 "$dst = sub(#$src1, $src2)",
220 [(set IntRegs:$dst, (sub s10ExtPred:$src1, IntRegs:$src2))]>,
224 multiclass TFR_Pred<bit PredNot> {
225 let PredSense = !if(PredNot, "false", "true") in {
226 def _c#NAME : ALU32_rr<(outs IntRegs:$dst),
227 (ins PredRegs:$src1, IntRegs:$src2),
228 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
231 let PNewValue = "new" in
232 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
233 (ins PredRegs:$src1, IntRegs:$src2),
234 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
239 let InputType = "reg", neverHasSideEffects = 1 in
240 multiclass TFR_base<string CextOp> {
241 let CextOpcode = CextOp, BaseOpcode = CextOp in {
242 let isPredicable = 1 in
243 def NAME : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
247 let isPredicated = 1 in {
248 defm Pt : TFR_Pred<0>;
249 defm NotPt : TFR_Pred<1>;
254 class T_TFR64_Pred<bit PredNot, bit isPredNew>
255 : ALU32_rr<(outs DoubleRegs:$dst),
256 (ins PredRegs:$src1, DoubleRegs:$src2),
257 !if(PredNot, "if (!$src1", "if ($src1")#
258 !if(isPredNew, ".new) ", ") ")#"$dst = $src2", []>
265 let Inst{27-24} = 0b1101;
266 let Inst{13} = isPredNew;
267 let Inst{7} = PredNot;
269 let Inst{6-5} = src1;
270 let Inst{20-17} = src2{4-1};
272 let Inst{12-9} = src2{4-1};
276 multiclass TFR64_Pred<bit PredNot> {
277 let PredSense = !if(PredNot, "false", "true") in {
278 def _c#NAME : T_TFR64_Pred<PredNot, 0>;
280 let PNewValue = "new" in
281 def _cdn#NAME : T_TFR64_Pred<PredNot, 1>; // Predicate new
285 let neverHasSideEffects = 1 in
286 multiclass TFR64_base<string BaseName> {
287 let BaseOpcode = BaseName in {
288 let isPredicable = 1 in
289 def NAME : ALU32Inst <(outs DoubleRegs:$dst),
290 (ins DoubleRegs:$src1),
296 let Inst{27-23} = 0b01010;
298 let Inst{20-17} = src1{4-1};
300 let Inst{12-9} = src1{4-1};
304 let isPredicated = 1 in {
305 defm Pt : TFR64_Pred<0>;
306 defm NotPt : TFR64_Pred<1>;
311 multiclass TFRI_Pred<bit PredNot> {
312 let isMoveImm = 1, PredSense = !if(PredNot, "false", "true") in {
313 def _c#NAME : ALU32_ri<(outs IntRegs:$dst),
314 (ins PredRegs:$src1, s12Ext:$src2),
315 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = #$src2",
319 let PNewValue = "new" in
320 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
321 (ins PredRegs:$src1, s12Ext:$src2),
322 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = #$src2",
327 let InputType = "imm", isExtendable = 1, isExtentSigned = 1 in
328 multiclass TFRI_base<string CextOp> {
329 let CextOpcode = CextOp, BaseOpcode = CextOp#I in {
330 let isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16,
331 isMoveImm = 1, isPredicable = 1, isReMaterializable = 1 in
332 def NAME : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
334 [(set (i32 IntRegs:$dst), s16ExtPred:$src1)]>;
336 let opExtendable = 2, opExtentBits = 12, neverHasSideEffects = 1,
337 isPredicated = 1 in {
338 defm Pt : TFRI_Pred<0>;
339 defm NotPt : TFRI_Pred<1>;
344 defm TFRI : TFRI_base<"TFR">, ImmRegRel, PredNewRel;
345 defm TFR : TFR_base<"TFR">, ImmRegRel, PredNewRel;
346 defm TFR64 : TFR64_base<"TFR64">, PredNewRel;
348 // Transfer control register.
349 let neverHasSideEffects = 1 in
350 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
353 //===----------------------------------------------------------------------===//
355 //===----------------------------------------------------------------------===//
358 //===----------------------------------------------------------------------===//
360 //===----------------------------------------------------------------------===//
364 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
365 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
367 def HexagonWrapperCombineII :
368 SDNode<"HexagonISD::WrapperCombineII", SDTHexagonI64I32I32>;
369 def HexagonWrapperCombineRR :
370 SDNode<"HexagonISD::WrapperCombineRR", SDTHexagonI64I32I32>;
372 // Combines the two integer registers SRC1 and SRC2 into a double register.
373 let isPredicable = 1 in
374 def COMBINE_rr : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1,
376 "$dst = combine($src1, $src2)",
377 [(set (i64 DoubleRegs:$dst),
378 (i64 (HexagonWrapperCombineRR (i32 IntRegs:$src1),
379 (i32 IntRegs:$src2))))]>;
381 // Rd=combine(Rt.[HL], Rs.[HL])
382 class COMBINE_halves<string A, string B>: ALU32_rr<(outs IntRegs:$dst),
385 "$dst = combine($src1."# A #", $src2."# B #")", []>;
387 let isPredicable = 1 in {
388 def COMBINE_hh : COMBINE_halves<"H", "H">;
389 def COMBINE_hl : COMBINE_halves<"H", "L">;
390 def COMBINE_lh : COMBINE_halves<"L", "H">;
391 def COMBINE_ll : COMBINE_halves<"L", "L">;
394 def : Pat<(i32 (trunc (i64 (srl (i64 DoubleRegs:$a), (i32 16))))),
395 (COMBINE_lh (EXTRACT_SUBREG (i64 DoubleRegs:$a), subreg_hireg),
396 (EXTRACT_SUBREG (i64 DoubleRegs:$a), subreg_loreg))>;
398 // Combines the two immediates SRC1 and SRC2 into a double register.
399 class COMBINE_imm<Operand imm1, Operand imm2, PatLeaf pat1, PatLeaf pat2> :
400 ALU32_ii<(outs DoubleRegs:$dst), (ins imm1:$src1, imm2:$src2),
401 "$dst = combine(#$src1, #$src2)",
402 [(set (i64 DoubleRegs:$dst),
403 (i64 (HexagonWrapperCombineII (i32 pat1:$src1), (i32 pat2:$src2))))]>;
405 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8 in
406 def COMBINE_Ii : COMBINE_imm<s8Ext, s8Imm, s8ExtPred, s8ImmPred>;
409 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
412 "$dst = vmux($src1, $src2, $src3)",
415 let CextOpcode = "MUX", InputType = "reg" in
416 def MUX_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
417 IntRegs:$src2, IntRegs:$src3),
418 "$dst = mux($src1, $src2, $src3)",
419 [(set (i32 IntRegs:$dst),
420 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
421 (i32 IntRegs:$src3))))]>, ImmRegRel;
423 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
424 CextOpcode = "MUX", InputType = "imm" in
425 def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
427 "$dst = mux($src1, #$src2, $src3)",
428 [(set (i32 IntRegs:$dst),
429 (i32 (select (i1 PredRegs:$src1), s8ExtPred:$src2,
430 (i32 IntRegs:$src3))))]>, ImmRegRel;
432 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
433 CextOpcode = "MUX", InputType = "imm" in
434 def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
436 "$dst = mux($src1, $src2, #$src3)",
437 [(set (i32 IntRegs:$dst),
438 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
439 s8ExtPred:$src3)))]>, ImmRegRel;
441 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
442 def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
444 "$dst = mux($src1, #$src2, #$src3)",
445 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
447 s8ImmPred:$src3)))]>;
449 // ALU32 - aslh, asrh, sxtb, sxth, zxtb, zxth
450 multiclass ALU32_2op_Pbase<string mnemonic, bit isNot, bit isPredNew> {
451 let isPredicatedNew = isPredNew in
452 def NAME : ALU32Inst<(outs IntRegs:$dst),
453 (ins PredRegs:$src1, IntRegs:$src2),
454 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
455 ") $dst = ")#mnemonic#"($src2)">,
459 multiclass ALU32_2op_Pred<string mnemonic, bit PredNot> {
460 let isPredicatedFalse = PredNot in {
461 defm _c#NAME : ALU32_2op_Pbase<mnemonic, PredNot, 0>;
463 defm _cdn#NAME : ALU32_2op_Pbase<mnemonic, PredNot, 1>;
467 multiclass ALU32_2op_base<string mnemonic> {
468 let BaseOpcode = mnemonic in {
469 let isPredicable = 1, neverHasSideEffects = 1 in
470 def NAME : ALU32Inst<(outs IntRegs:$dst),
472 "$dst = "#mnemonic#"($src1)">;
474 let Predicates = [HasV4T], validSubTargets = HasV4SubT, isPredicated = 1,
475 neverHasSideEffects = 1 in {
476 defm Pt_V4 : ALU32_2op_Pred<mnemonic, 0>;
477 defm NotPt_V4 : ALU32_2op_Pred<mnemonic, 1>;
482 defm ASLH : ALU32_2op_base<"aslh">, PredNewRel;
483 defm ASRH : ALU32_2op_base<"asrh">, PredNewRel;
484 defm SXTB : ALU32_2op_base<"sxtb">, PredNewRel;
485 defm SXTH : ALU32_2op_base<"sxth">, PredNewRel;
486 defm ZXTB : ALU32_2op_base<"zxtb">, PredNewRel;
487 defm ZXTH : ALU32_2op_base<"zxth">, PredNewRel;
489 def : Pat <(shl (i32 IntRegs:$src1), (i32 16)),
490 (ASLH IntRegs:$src1)>;
492 def : Pat <(sra (i32 IntRegs:$src1), (i32 16)),
493 (ASRH IntRegs:$src1)>;
495 def : Pat <(sext_inreg (i32 IntRegs:$src1), i8),
496 (SXTB IntRegs:$src1)>;
498 def : Pat <(sext_inreg (i32 IntRegs:$src1), i16),
499 (SXTH IntRegs:$src1)>;
501 //===----------------------------------------------------------------------===//
503 //===----------------------------------------------------------------------===//
506 //===----------------------------------------------------------------------===//
508 //===----------------------------------------------------------------------===//
510 // Conditional combine.
511 let neverHasSideEffects = 1, isPredicated = 1 in
512 def COMBINE_rr_cPt : ALU32_rr<(outs DoubleRegs:$dst),
513 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
514 "if ($src1) $dst = combine($src2, $src3)",
517 let neverHasSideEffects = 1, isPredicated = 1 in
518 def COMBINE_rr_cNotPt : ALU32_rr<(outs DoubleRegs:$dst),
519 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
520 "if (!$src1) $dst = combine($src2, $src3)",
523 let neverHasSideEffects = 1, isPredicated = 1 in
524 def COMBINE_rr_cdnPt : ALU32_rr<(outs DoubleRegs:$dst),
525 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
526 "if ($src1.new) $dst = combine($src2, $src3)",
529 let neverHasSideEffects = 1, isPredicated = 1 in
530 def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst),
531 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
532 "if (!$src1.new) $dst = combine($src2, $src3)",
536 defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", "CMPGTU", setugt>, ImmRegRel;
537 defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", "CMPGT", setgt>, ImmRegRel;
538 defm CMPLT : CMP32_rr<"cmp.lt", setlt>;
539 defm CMPLTU : CMP32_rr<"cmp.ltu", setult>;
540 defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", "CMPEQ", seteq>, ImmRegRel;
541 defm CMPGE : CMP32_ri_s8<"cmp.ge", setge>;
542 defm CMPGEU : CMP32_ri_u8<"cmp.geu", setuge>;
544 def CTLZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
546 [(set (i32 IntRegs:$dst), (ctlz (i32 IntRegs:$src1)))]>;
548 def CTTZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
550 [(set (i32 IntRegs:$dst), (cttz (i32 IntRegs:$src1)))]>;
552 def CTLZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
554 [(set (i32 IntRegs:$dst), (i32 (trunc (ctlz (i64 DoubleRegs:$src1)))))]>;
556 def CTTZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
558 [(set (i32 IntRegs:$dst), (i32 (trunc (cttz (i64 DoubleRegs:$src1)))))]>;
560 def TSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
561 "$dst = tstbit($src1, $src2)",
562 [(set (i1 PredRegs:$dst),
563 (setne (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>;
565 def TSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
566 "$dst = tstbit($src1, $src2)",
567 [(set (i1 PredRegs:$dst),
568 (setne (and (shl 1, (u5ImmPred:$src2)), (i32 IntRegs:$src1)), 0))]>;
570 //===----------------------------------------------------------------------===//
572 //===----------------------------------------------------------------------===//
575 //===----------------------------------------------------------------------===//
577 //===----------------------------------------------------------------------===//
579 def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
581 "$dst = add($src1, $src2)",
582 [(set (i64 DoubleRegs:$dst), (add (i64 DoubleRegs:$src1),
583 (i64 DoubleRegs:$src2)))]>;
588 defm CMPEHexagon4 : CMP64_rr<"cmp.eq", seteq>;
589 defm CMPGT64 : CMP64_rr<"cmp.gt", setgt>;
590 defm CMPGTU64 : CMP64_rr<"cmp.gtu", setugt>;
592 // Logical operations.
593 def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
595 "$dst = and($src1, $src2)",
596 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
597 (i64 DoubleRegs:$src2)))]>;
599 def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
601 "$dst = or($src1, $src2)",
602 [(set (i64 DoubleRegs:$dst), (or (i64 DoubleRegs:$src1),
603 (i64 DoubleRegs:$src2)))]>;
605 def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
607 "$dst = xor($src1, $src2)",
608 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
609 (i64 DoubleRegs:$src2)))]>;
612 def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
613 "$dst = max($src2, $src1)",
614 [(set (i32 IntRegs:$dst),
615 (i32 (select (i1 (setlt (i32 IntRegs:$src2),
616 (i32 IntRegs:$src1))),
617 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
619 def MAXUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
620 "$dst = maxu($src2, $src1)",
621 [(set (i32 IntRegs:$dst),
622 (i32 (select (i1 (setult (i32 IntRegs:$src2),
623 (i32 IntRegs:$src1))),
624 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
626 def MAXd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
628 "$dst = max($src2, $src1)",
629 [(set (i64 DoubleRegs:$dst),
630 (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
631 (i64 DoubleRegs:$src1))),
632 (i64 DoubleRegs:$src1),
633 (i64 DoubleRegs:$src2))))]>;
635 def MAXUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
637 "$dst = maxu($src2, $src1)",
638 [(set (i64 DoubleRegs:$dst),
639 (i64 (select (i1 (setult (i64 DoubleRegs:$src2),
640 (i64 DoubleRegs:$src1))),
641 (i64 DoubleRegs:$src1),
642 (i64 DoubleRegs:$src2))))]>;
645 def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
646 "$dst = min($src2, $src1)",
647 [(set (i32 IntRegs:$dst),
648 (i32 (select (i1 (setgt (i32 IntRegs:$src2),
649 (i32 IntRegs:$src1))),
650 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
652 def MINUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
653 "$dst = minu($src2, $src1)",
654 [(set (i32 IntRegs:$dst),
655 (i32 (select (i1 (setugt (i32 IntRegs:$src2),
656 (i32 IntRegs:$src1))),
657 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
659 def MINd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
661 "$dst = min($src2, $src1)",
662 [(set (i64 DoubleRegs:$dst),
663 (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
664 (i64 DoubleRegs:$src1))),
665 (i64 DoubleRegs:$src1),
666 (i64 DoubleRegs:$src2))))]>;
668 def MINUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
670 "$dst = minu($src2, $src1)",
671 [(set (i64 DoubleRegs:$dst),
672 (i64 (select (i1 (setugt (i64 DoubleRegs:$src2),
673 (i64 DoubleRegs:$src1))),
674 (i64 DoubleRegs:$src1),
675 (i64 DoubleRegs:$src2))))]>;
678 def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
680 "$dst = sub($src1, $src2)",
681 [(set (i64 DoubleRegs:$dst), (sub (i64 DoubleRegs:$src1),
682 (i64 DoubleRegs:$src2)))]>;
684 // Subtract halfword.
686 //===----------------------------------------------------------------------===//
688 //===----------------------------------------------------------------------===//
690 //===----------------------------------------------------------------------===//
692 //===----------------------------------------------------------------------===//
694 //===----------------------------------------------------------------------===//
696 //===----------------------------------------------------------------------===//
698 //===----------------------------------------------------------------------===//
700 //===----------------------------------------------------------------------===//
702 //===----------------------------------------------------------------------===//
704 //===----------------------------------------------------------------------===//
706 //===----------------------------------------------------------------------===//
708 //===----------------------------------------------------------------------===//
709 // Logical reductions on predicates.
711 // Looping instructions.
713 // Pipelined looping instructions.
715 // Logical operations on predicates.
716 def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
717 "$dst = and($src1, $src2)",
718 [(set (i1 PredRegs:$dst), (and (i1 PredRegs:$src1),
719 (i1 PredRegs:$src2)))]>;
721 let neverHasSideEffects = 1 in
722 def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
724 "$dst = and($src1, !$src2)",
727 def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
728 "$dst = any8($src1)",
731 def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
732 "$dst = all8($src1)",
735 def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
737 "$dst = vitpack($src1, $src2)",
740 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
743 "$dst = valignb($src1, $src2, $src3)",
746 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
749 "$dst = vspliceb($src1, $src2, $src3)",
752 def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
753 "$dst = mask($src1)",
756 def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
758 [(set (i1 PredRegs:$dst), (not (i1 PredRegs:$src1)))]>;
760 def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
761 "$dst = or($src1, $src2)",
762 [(set (i1 PredRegs:$dst), (or (i1 PredRegs:$src1),
763 (i1 PredRegs:$src2)))]>;
765 def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
766 "$dst = xor($src1, $src2)",
767 [(set (i1 PredRegs:$dst), (xor (i1 PredRegs:$src1),
768 (i1 PredRegs:$src2)))]>;
771 // User control register transfer.
772 //===----------------------------------------------------------------------===//
774 //===----------------------------------------------------------------------===//
777 //===----------------------------------------------------------------------===//
779 //===----------------------------------------------------------------------===//
781 let isBranch = 1, isTerminator=1, isBarrier = 1, isPredicable = 1 in {
782 def JMP : JInst< (outs),
783 (ins brtarget:$offset),
789 let isBranch = 1, isTerminator=1, Defs = [PC],
790 isPredicated = 1 in {
791 def JMP_c : JInst< (outs),
792 (ins PredRegs:$src, brtarget:$offset),
793 "if ($src) jump $offset",
794 [(brcond (i1 PredRegs:$src), bb:$offset)]>;
798 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
799 isPredicated = 1 in {
800 def JMP_cNot : JInst< (outs),
801 (ins PredRegs:$src, brtarget:$offset),
802 "if (!$src) jump $offset",
806 let isTerminator = 1, isBranch = 1, neverHasSideEffects = 1, Defs = [PC],
807 isPredicated = 1 in {
808 def BRCOND : JInst < (outs), (ins PredRegs:$pred, brtarget:$dst),
809 "if ($pred) jump $dst",
813 // Jump to address conditioned on new predicate.
815 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
816 isPredicated = 1 in {
817 def JMP_cdnPt : JInst< (outs),
818 (ins PredRegs:$src, brtarget:$offset),
819 "if ($src.new) jump:t $offset",
824 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
825 isPredicated = 1 in {
826 def JMP_cdnNotPt : JInst< (outs),
827 (ins PredRegs:$src, brtarget:$offset),
828 "if (!$src.new) jump:t $offset",
833 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
834 isPredicated = 1 in {
835 def JMP_cdnPnt : JInst< (outs),
836 (ins PredRegs:$src, brtarget:$offset),
837 "if ($src.new) jump:nt $offset",
842 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
843 isPredicated = 1 in {
844 def JMP_cdnNotPnt : JInst< (outs),
845 (ins PredRegs:$src, brtarget:$offset),
846 "if (!$src.new) jump:nt $offset",
849 //===----------------------------------------------------------------------===//
851 //===----------------------------------------------------------------------===//
853 //===----------------------------------------------------------------------===//
855 //===----------------------------------------------------------------------===//
856 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
857 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
859 // Jump to address from register.
860 let isPredicable =1, isReturn = 1, isTerminator = 1, isBarrier = 1,
861 Defs = [PC], Uses = [R31] in {
862 def JMPR: JRInst<(outs), (ins),
867 // Jump to address from register.
868 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
869 Defs = [PC], Uses = [R31] in {
870 def JMPR_cPt: JRInst<(outs), (ins PredRegs:$src1),
871 "if ($src1) jumpr r31",
875 // Jump to address from register.
876 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
877 Defs = [PC], Uses = [R31] in {
878 def JMPR_cNotPt: JRInst<(outs), (ins PredRegs:$src1),
879 "if (!$src1) jumpr r31",
883 //===----------------------------------------------------------------------===//
885 //===----------------------------------------------------------------------===//
887 //===----------------------------------------------------------------------===//
889 //===----------------------------------------------------------------------===//
891 // Load -- MEMri operand
892 multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
893 bit isNot, bit isPredNew> {
894 let PNewValue = !if(isPredNew, "new", "") in
895 def NAME : LDInst2<(outs RC:$dst),
896 (ins PredRegs:$src1, MEMri:$addr),
897 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
898 ") ")#"$dst = "#mnemonic#"($addr)",
902 multiclass LD_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
903 let PredSense = !if(PredNot, "false", "true") in {
904 defm _c#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
906 defm _cdn#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
910 let isExtendable = 1, neverHasSideEffects = 1 in
911 multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
912 bits<5> ImmBits, bits<5> PredImmBits> {
914 let CextOpcode = CextOp, BaseOpcode = CextOp in {
915 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
917 def NAME : LDInst2<(outs RC:$dst), (ins MEMri:$addr),
918 "$dst = "#mnemonic#"($addr)",
921 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
922 isPredicated = 1 in {
923 defm Pt : LD_MEMri_Pred<mnemonic, RC, 0 >;
924 defm NotPt : LD_MEMri_Pred<mnemonic, RC, 1 >;
929 let addrMode = BaseImmOffset, isMEMri = "true" in {
930 defm LDrib: LD_MEMri < "memb", "LDrib", IntRegs, 11, 6>, AddrModeRel;
931 defm LDriub: LD_MEMri < "memub" , "LDriub", IntRegs, 11, 6>, AddrModeRel;
932 defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
933 defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel;
934 defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;
935 defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;
938 def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
939 (LDrib ADDRriS11_0:$addr) >;
941 def : Pat < (i32 (zextloadi8 ADDRriS11_0:$addr)),
942 (LDriub ADDRriS11_0:$addr) >;
944 def : Pat < (i32 (sextloadi16 ADDRriS11_1:$addr)),
945 (LDrih ADDRriS11_1:$addr) >;
947 def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)),
948 (LDriuh ADDRriS11_1:$addr) >;
950 def : Pat < (i32 (load ADDRriS11_2:$addr)),
951 (LDriw ADDRriS11_2:$addr) >;
953 def : Pat < (i64 (load ADDRriS11_3:$addr)),
954 (LDrid ADDRriS11_3:$addr) >;
957 // Load - Base with Immediate offset addressing mode
958 multiclass LD_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
959 bit isNot, bit isPredNew> {
960 let PNewValue = !if(isPredNew, "new", "") in
961 def NAME : LDInst2<(outs RC:$dst),
962 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
963 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
964 ") ")#"$dst = "#mnemonic#"($src2+#$src3)",
968 multiclass LD_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
970 let PredSense = !if(PredNot, "false", "true") in {
971 defm _c#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
973 defm _cdn#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
977 let isExtendable = 1, neverHasSideEffects = 1 in
978 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
979 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
980 bits<5> PredImmBits> {
982 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
983 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
984 isPredicable = 1, AddedComplexity = 20 in
985 def NAME : LDInst2<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
986 "$dst = "#mnemonic#"($src1+#$offset)",
989 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
990 isPredicated = 1 in {
991 defm Pt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 0 >;
992 defm NotPt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 1 >;
997 let addrMode = BaseImmOffset in {
998 defm LDrib_indexed: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext,
1000 defm LDriub_indexed: LD_Idxd <"memub" , "LDriub", IntRegs, s11_0Ext, u6_0Ext,
1001 11, 6>, AddrModeRel;
1002 defm LDrih_indexed: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
1003 12, 7>, AddrModeRel;
1004 defm LDriuh_indexed: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext,
1005 12, 7>, AddrModeRel;
1006 defm LDriw_indexed: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
1007 13, 8>, AddrModeRel;
1008 defm LDrid_indexed: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,
1009 14, 9>, AddrModeRel;
1012 let AddedComplexity = 20 in {
1013 def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
1014 (LDrib_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
1016 def : Pat < (i32 (zextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
1017 (LDriub_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
1019 def : Pat < (i32 (sextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
1020 (LDrih_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
1022 def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
1023 (LDriuh_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
1025 def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
1026 (LDriw_indexed IntRegs:$src1, s11_2ExtPred:$offset) >;
1028 def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
1029 (LDrid_indexed IntRegs:$src1, s11_3ExtPred:$offset) >;
1032 //===----------------------------------------------------------------------===//
1033 // Post increment load
1034 // Make sure that in post increment load, the first operand is always the post
1035 // increment operand.
1036 //===----------------------------------------------------------------------===//
1038 multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1039 bit isNot, bit isPredNew> {
1040 let PNewValue = !if(isPredNew, "new", "") in
1041 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1042 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1043 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1044 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1049 multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,
1050 Operand ImmOp, bit PredNot> {
1051 let PredSense = !if(PredNot, "false", "true") in {
1052 defm _c#NAME : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1054 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1055 defm _cdn#NAME#_V4 : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1059 multiclass LD_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1062 let BaseOpcode = "POST_"#BaseOp in {
1063 let isPredicable = 1 in
1064 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1065 (ins IntRegs:$src1, ImmOp:$offset),
1066 "$dst = "#mnemonic#"($src1++#$offset)",
1070 let isPredicated = 1 in {
1071 defm Pt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1072 defm NotPt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1077 let hasCtrlDep = 1, neverHasSideEffects = 1 in {
1078 defm POST_LDrib : LD_PostInc<"memb", "LDrib", IntRegs, s4_0Imm>,
1080 defm POST_LDriub : LD_PostInc<"memub", "LDriub", IntRegs, s4_0Imm>,
1082 defm POST_LDrih : LD_PostInc<"memh", "LDrih", IntRegs, s4_1Imm>,
1084 defm POST_LDriuh : LD_PostInc<"memuh", "LDriuh", IntRegs, s4_1Imm>,
1086 defm POST_LDriw : LD_PostInc<"memw", "LDriw", IntRegs, s4_2Imm>,
1088 defm POST_LDrid : LD_PostInc<"memd", "LDrid", DoubleRegs, s4_3Imm>,
1092 def : Pat< (i32 (extloadi1 ADDRriS11_0:$addr)),
1093 (i32 (LDrib ADDRriS11_0:$addr)) >;
1095 // Load byte any-extend.
1096 def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
1097 (i32 (LDrib ADDRriS11_0:$addr)) >;
1099 // Indexed load byte any-extend.
1100 let AddedComplexity = 20 in
1101 def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1102 (i32 (LDrib_indexed IntRegs:$src1, s11_0ImmPred:$offset)) >;
1104 def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
1105 (i32 (LDrih ADDRriS11_1:$addr))>;
1107 let AddedComplexity = 20 in
1108 def : Pat < (i32 (extloadi16 (add IntRegs:$src1, s11_1ImmPred:$offset))),
1109 (i32 (LDrih_indexed IntRegs:$src1, s11_1ImmPred:$offset)) >;
1111 let AddedComplexity = 10 in
1112 def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
1113 (i32 (LDriub ADDRriS11_0:$addr))>;
1115 let AddedComplexity = 20 in
1116 def : Pat < (i32 (zextloadi1 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1117 (i32 (LDriub_indexed IntRegs:$src1, s11_0ImmPred:$offset))>;
1120 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
1121 isPseudo = 1, Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1122 def LDriw_pred : LDInst2<(outs PredRegs:$dst),
1124 "Error; should not emit",
1127 // Deallocate stack frame.
1128 let Defs = [R29, R30, R31], Uses = [R29], neverHasSideEffects = 1 in {
1129 def DEALLOCFRAME : LDInst2<(outs), (ins),
1134 // Load and unpack bytes to halfwords.
1135 //===----------------------------------------------------------------------===//
1137 //===----------------------------------------------------------------------===//
1139 //===----------------------------------------------------------------------===//
1141 //===----------------------------------------------------------------------===//
1142 //===----------------------------------------------------------------------===//
1144 //===----------------------------------------------------------------------===//
1146 //===----------------------------------------------------------------------===//
1148 //===----------------------------------------------------------------------===//
1149 //===----------------------------------------------------------------------===//
1151 //===----------------------------------------------------------------------===//
1153 //===----------------------------------------------------------------------===//
1155 //===----------------------------------------------------------------------===//
1156 // Multiply and use lower result.
1158 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in
1159 def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Ext:$src2),
1160 "$dst =+ mpyi($src1, #$src2)",
1161 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1162 u8ExtPred:$src2))]>;
1165 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1166 "$dst =- mpyi($src1, #$src2)",
1167 [(set (i32 IntRegs:$dst), (ineg (mul (i32 IntRegs:$src1),
1168 u8ImmPred:$src2)))]>;
1171 // s9 is NOT the same as m9 - but it works.. so far.
1172 // Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
1173 // depending on the value of m9. See Arch Spec.
1174 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
1175 CextOpcode = "MPYI", InputType = "imm" in
1176 def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
1177 "$dst = mpyi($src1, #$src2)",
1178 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1179 s9ExtPred:$src2))]>, ImmRegRel;
1182 let CextOpcode = "MPYI", InputType = "reg" in
1183 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1184 "$dst = mpyi($src1, $src2)",
1185 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1186 (i32 IntRegs:$src2)))]>, ImmRegRel;
1189 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8,
1190 CextOpcode = "MPYI_acc", InputType = "imm" in
1191 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
1192 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1193 "$dst += mpyi($src2, #$src3)",
1194 [(set (i32 IntRegs:$dst),
1195 (add (mul (i32 IntRegs:$src2), u8ExtPred:$src3),
1196 (i32 IntRegs:$src1)))],
1197 "$src1 = $dst">, ImmRegRel;
1200 let CextOpcode = "MPYI_acc", InputType = "reg" in
1201 def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
1202 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1203 "$dst += mpyi($src2, $src3)",
1204 [(set (i32 IntRegs:$dst),
1205 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1206 (i32 IntRegs:$src1)))],
1207 "$src1 = $dst">, ImmRegRel;
1210 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8 in
1211 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
1212 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1213 "$dst -= mpyi($src2, #$src3)",
1214 [(set (i32 IntRegs:$dst),
1215 (sub (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1216 u8ExtPred:$src3)))],
1219 // Multiply and use upper result.
1220 // Rd=mpy(Rs,Rt.H):<<1:rnd:sat
1221 // Rd=mpy(Rs,Rt.L):<<1:rnd:sat
1223 def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1224 "$dst = mpy($src1, $src2)",
1225 [(set (i32 IntRegs:$dst), (mulhs (i32 IntRegs:$src1),
1226 (i32 IntRegs:$src2)))]>;
1228 // Rd=mpy(Rs,Rt):rnd
1230 def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1231 "$dst = mpyu($src1, $src2)",
1232 [(set (i32 IntRegs:$dst), (mulhu (i32 IntRegs:$src1),
1233 (i32 IntRegs:$src2)))]>;
1235 // Multiply and use full result.
1237 def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1238 "$dst = mpyu($src1, $src2)",
1239 [(set (i64 DoubleRegs:$dst),
1240 (mul (i64 (anyext (i32 IntRegs:$src1))),
1241 (i64 (anyext (i32 IntRegs:$src2)))))]>;
1244 def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1245 "$dst = mpy($src1, $src2)",
1246 [(set (i64 DoubleRegs:$dst),
1247 (mul (i64 (sext (i32 IntRegs:$src1))),
1248 (i64 (sext (i32 IntRegs:$src2)))))]>;
1250 // Multiply and accumulate, use full result.
1251 // Rxx[+-]=mpy(Rs,Rt)
1253 def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
1254 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1255 "$dst += mpy($src2, $src3)",
1256 [(set (i64 DoubleRegs:$dst),
1257 (add (mul (i64 (sext (i32 IntRegs:$src2))),
1258 (i64 (sext (i32 IntRegs:$src3)))),
1259 (i64 DoubleRegs:$src1)))],
1263 def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
1264 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1265 "$dst -= mpy($src2, $src3)",
1266 [(set (i64 DoubleRegs:$dst),
1267 (sub (i64 DoubleRegs:$src1),
1268 (mul (i64 (sext (i32 IntRegs:$src2))),
1269 (i64 (sext (i32 IntRegs:$src3))))))],
1272 // Rxx[+-]=mpyu(Rs,Rt)
1274 def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1275 IntRegs:$src2, IntRegs:$src3),
1276 "$dst += mpyu($src2, $src3)",
1277 [(set (i64 DoubleRegs:$dst),
1278 (add (mul (i64 (anyext (i32 IntRegs:$src2))),
1279 (i64 (anyext (i32 IntRegs:$src3)))),
1280 (i64 DoubleRegs:$src1)))], "$src1 = $dst">;
1283 def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
1284 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1285 "$dst -= mpyu($src2, $src3)",
1286 [(set (i64 DoubleRegs:$dst),
1287 (sub (i64 DoubleRegs:$src1),
1288 (mul (i64 (anyext (i32 IntRegs:$src2))),
1289 (i64 (anyext (i32 IntRegs:$src3))))))],
1293 let InputType = "reg", CextOpcode = "ADD_acc" in
1294 def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1295 IntRegs:$src2, IntRegs:$src3),
1296 "$dst += add($src2, $src3)",
1297 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1298 (i32 IntRegs:$src3)),
1299 (i32 IntRegs:$src1)))],
1300 "$src1 = $dst">, ImmRegRel;
1302 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
1303 InputType = "imm", CextOpcode = "ADD_acc" in
1304 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1305 IntRegs:$src2, s8Ext:$src3),
1306 "$dst += add($src2, #$src3)",
1307 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1308 s8_16ExtPred:$src3),
1309 (i32 IntRegs:$src1)))],
1310 "$src1 = $dst">, ImmRegRel;
1312 let CextOpcode = "SUB_acc", InputType = "reg" in
1313 def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1314 IntRegs:$src2, IntRegs:$src3),
1315 "$dst -= add($src2, $src3)",
1316 [(set (i32 IntRegs:$dst),
1317 (sub (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1318 (i32 IntRegs:$src3))))],
1319 "$src1 = $dst">, ImmRegRel;
1321 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
1322 CextOpcode = "SUB_acc", InputType = "imm" in
1323 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1324 IntRegs:$src2, s8Ext:$src3),
1325 "$dst -= add($src2, #$src3)",
1326 [(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
1327 (add (i32 IntRegs:$src2),
1328 s8_16ExtPred:$src3)))],
1329 "$src1 = $dst">, ImmRegRel;
1331 //===----------------------------------------------------------------------===//
1333 //===----------------------------------------------------------------------===//
1335 //===----------------------------------------------------------------------===//
1337 //===----------------------------------------------------------------------===//
1338 //===----------------------------------------------------------------------===//
1340 //===----------------------------------------------------------------------===//
1342 //===----------------------------------------------------------------------===//
1344 //===----------------------------------------------------------------------===//
1345 //===----------------------------------------------------------------------===//
1347 //===----------------------------------------------------------------------===//
1349 //===----------------------------------------------------------------------===//
1351 //===----------------------------------------------------------------------===//
1352 //===----------------------------------------------------------------------===//
1354 //===----------------------------------------------------------------------===//
1356 //===----------------------------------------------------------------------===//
1358 //===----------------------------------------------------------------------===//
1360 // Store doubleword.
1362 //===----------------------------------------------------------------------===//
1363 // Post increment store
1364 //===----------------------------------------------------------------------===//
1366 multiclass ST_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1367 bit isNot, bit isPredNew> {
1368 let PNewValue = !if(isPredNew, "new", "") in
1369 def NAME : STInst2PI<(outs IntRegs:$dst),
1370 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
1371 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1372 ") ")#mnemonic#"($src2++#$offset) = $src3",
1377 multiclass ST_PostInc_Pred<string mnemonic, RegisterClass RC,
1378 Operand ImmOp, bit PredNot> {
1379 let PredSense = !if(PredNot, "false", "true") in {
1380 defm _c#NAME# : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1382 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1383 defm _cdn#NAME#_V4 : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1387 let hasCtrlDep = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1388 multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1391 let hasCtrlDep = 1, BaseOpcode = "POST_"#BaseOp in {
1392 let isPredicable = 1 in
1393 def NAME : STInst2PI<(outs IntRegs:$dst),
1394 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
1395 #mnemonic#"($src1++#$offset) = $src2",
1399 let isPredicated = 1 in {
1400 defm Pt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1401 defm NotPt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1406 defm POST_STbri: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel;
1407 defm POST_SThri: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
1408 defm POST_STwri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
1410 let isNVStorable = 0 in
1411 defm POST_STdri: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm>, AddrModeRel;
1413 def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2,
1414 s4_3ImmPred:$offset),
1415 (POST_STbri IntRegs:$src2, s4_0ImmPred:$offset, IntRegs:$src1)>;
1417 def : Pat<(post_truncsti16 (i32 IntRegs:$src1), IntRegs:$src2,
1418 s4_3ImmPred:$offset),
1419 (POST_SThri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
1421 def : Pat<(post_store (i32 IntRegs:$src1), IntRegs:$src2, s4_2ImmPred:$offset),
1422 (POST_STwri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
1424 def : Pat<(post_store (i64 DoubleRegs:$src1), IntRegs:$src2,
1425 s4_3ImmPred:$offset),
1426 (POST_STdri IntRegs:$src2, s4_3ImmPred:$offset, DoubleRegs:$src1)>;
1428 //===----------------------------------------------------------------------===//
1429 // multiclass for the store instructions with MEMri operand.
1430 //===----------------------------------------------------------------------===//
1431 multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot,
1433 let PNewValue = !if(isPredNew, "new", "") in
1434 def NAME : STInst2<(outs),
1435 (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
1436 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1437 ") ")#mnemonic#"($addr) = $src2",
1441 multiclass ST_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1442 let PredSense = !if(PredNot, "false", "true") in {
1443 defm _c#NAME : ST_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
1446 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1447 defm _cdn#NAME#_V4 : ST_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
1451 let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1452 multiclass ST_MEMri<string mnemonic, string CextOp, RegisterClass RC,
1453 bits<5> ImmBits, bits<5> PredImmBits> {
1455 let CextOpcode = CextOp, BaseOpcode = CextOp in {
1456 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1458 def NAME : STInst2<(outs),
1459 (ins MEMri:$addr, RC:$src),
1460 mnemonic#"($addr) = $src",
1463 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
1464 isPredicated = 1 in {
1465 defm Pt : ST_MEMri_Pred<mnemonic, RC, 0>;
1466 defm NotPt : ST_MEMri_Pred<mnemonic, RC, 1>;
1471 let addrMode = BaseImmOffset, isMEMri = "true" in {
1472 defm STrib: ST_MEMri < "memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
1473 defm STrih: ST_MEMri < "memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
1474 defm STriw: ST_MEMri < "memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
1476 let isNVStorable = 0 in
1477 defm STrid: ST_MEMri < "memd", "STrid", DoubleRegs, 14, 9>, AddrModeRel;
1480 def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
1481 (STrib ADDRriS11_0:$addr, (i32 IntRegs:$src1))>;
1483 def : Pat<(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr),
1484 (STrih ADDRriS11_1:$addr, (i32 IntRegs:$src1))>;
1486 def : Pat<(store (i32 IntRegs:$src1), ADDRriS11_2:$addr),
1487 (STriw ADDRriS11_2:$addr, (i32 IntRegs:$src1))>;
1489 def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
1490 (STrid ADDRriS11_3:$addr, (i64 DoubleRegs:$src1))>;
1493 //===----------------------------------------------------------------------===//
1494 // multiclass for the store instructions with base+immediate offset
1496 //===----------------------------------------------------------------------===//
1497 multiclass ST_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
1498 bit isNot, bit isPredNew> {
1499 let PNewValue = !if(isPredNew, "new", "") in
1500 def NAME : STInst2<(outs),
1501 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
1502 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1503 ") ")#mnemonic#"($src2+#$src3) = $src4",
1507 multiclass ST_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
1509 let PredSense = !if(PredNot, "false", "true"), isPredicated = 1 in {
1510 defm _c#NAME : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
1513 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1514 defm _cdn#NAME#_V4 : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
1518 let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1519 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1520 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
1521 bits<5> PredImmBits> {
1523 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1524 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1526 def NAME : STInst2<(outs),
1527 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1528 mnemonic#"($src1+#$src2) = $src3",
1531 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits in {
1532 defm Pt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 0>;
1533 defm NotPt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 1>;
1538 let addrMode = BaseImmOffset, InputType = "reg" in {
1539 defm STrib_indexed: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext,
1540 u6_0Ext, 11, 6>, AddrModeRel, ImmRegRel;
1541 defm STrih_indexed: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext,
1542 u6_1Ext, 12, 7>, AddrModeRel, ImmRegRel;
1543 defm STriw_indexed: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext,
1544 u6_2Ext, 13, 8>, AddrModeRel, ImmRegRel;
1545 let isNVStorable = 0 in
1546 defm STrid_indexed: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
1547 u6_3Ext, 14, 9>, AddrModeRel;
1550 let AddedComplexity = 10 in {
1551 def : Pat<(truncstorei8 (i32 IntRegs:$src1), (add IntRegs:$src2,
1552 s11_0ExtPred:$offset)),
1553 (STrib_indexed IntRegs:$src2, s11_0ImmPred:$offset,
1554 (i32 IntRegs:$src1))>;
1556 def : Pat<(truncstorei16 (i32 IntRegs:$src1), (add IntRegs:$src2,
1557 s11_1ExtPred:$offset)),
1558 (STrih_indexed IntRegs:$src2, s11_1ImmPred:$offset,
1559 (i32 IntRegs:$src1))>;
1561 def : Pat<(store (i32 IntRegs:$src1), (add IntRegs:$src2,
1562 s11_2ExtPred:$offset)),
1563 (STriw_indexed IntRegs:$src2, s11_2ImmPred:$offset,
1564 (i32 IntRegs:$src1))>;
1566 def : Pat<(store (i64 DoubleRegs:$src1), (add IntRegs:$src2,
1567 s11_3ExtPred:$offset)),
1568 (STrid_indexed IntRegs:$src2, s11_3ImmPred:$offset,
1569 (i64 DoubleRegs:$src1))>;
1572 // memh(Rx++#s4:1)=Rt.H
1576 let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1577 def STriw_pred : STInst2<(outs),
1578 (ins MEMri:$addr, PredRegs:$src1),
1579 "Error; should not emit",
1582 // Allocate stack frame.
1583 let Defs = [R29, R30], Uses = [R31, R30], neverHasSideEffects = 1 in {
1584 def ALLOCFRAME : STInst2<(outs),
1586 "allocframe(#$amt)",
1589 //===----------------------------------------------------------------------===//
1591 //===----------------------------------------------------------------------===//
1593 //===----------------------------------------------------------------------===//
1595 //===----------------------------------------------------------------------===//
1597 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
1598 "$dst = not($src1)",
1599 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
1602 // Sign extend word to doubleword.
1603 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
1604 "$dst = sxtw($src1)",
1605 [(set (i64 DoubleRegs:$dst), (sext (i32 IntRegs:$src1)))]>;
1606 //===----------------------------------------------------------------------===//
1608 //===----------------------------------------------------------------------===//
1610 //===----------------------------------------------------------------------===//
1612 //===----------------------------------------------------------------------===//
1614 def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1615 "$dst = clrbit($src1, #$src2)",
1616 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
1618 (shl 1, u5ImmPred:$src2))))]>;
1620 def CLRBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1621 "$dst = clrbit($src1, #$src2)",
1624 // Map from r0 = and(r1, 2147483647) to r0 = clrbit(r1, #31).
1625 def : Pat <(and (i32 IntRegs:$src1), 2147483647),
1626 (CLRBIT_31 (i32 IntRegs:$src1), 31)>;
1629 def SETBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1630 "$dst = setbit($src1, #$src2)",
1631 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
1632 (shl 1, u5ImmPred:$src2)))]>;
1634 // Map from r0 = or(r1, -2147483648) to r0 = setbit(r1, #31).
1635 def SETBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1636 "$dst = setbit($src1, #$src2)",
1639 def : Pat <(or (i32 IntRegs:$src1), -2147483648),
1640 (SETBIT_31 (i32 IntRegs:$src1), 31)>;
1643 def TOGBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1644 "$dst = setbit($src1, #$src2)",
1645 [(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
1646 (shl 1, u5ImmPred:$src2)))]>;
1648 // Map from r0 = xor(r1, -2147483648) to r0 = togglebit(r1, #31).
1649 def TOGBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1650 "$dst = togglebit($src1, #$src2)",
1653 def : Pat <(xor (i32 IntRegs:$src1), -2147483648),
1654 (TOGBIT_31 (i32 IntRegs:$src1), 31)>;
1656 // Predicate transfer.
1657 let neverHasSideEffects = 1 in
1658 def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
1659 "$dst = $src1 /* Should almost never emit this. */",
1662 def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1),
1663 "$dst = $src1 /* Should almost never emit this. */",
1664 [(set (i1 PredRegs:$dst), (trunc (i32 IntRegs:$src1)))]>;
1665 //===----------------------------------------------------------------------===//
1667 //===----------------------------------------------------------------------===//
1669 //===----------------------------------------------------------------------===//
1671 //===----------------------------------------------------------------------===//
1672 // Shift by immediate.
1673 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1674 "$dst = asr($src1, #$src2)",
1675 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1676 u5ImmPred:$src2))]>;
1678 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1679 "$dst = asr($src1, #$src2)",
1680 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1681 u6ImmPred:$src2))]>;
1683 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1684 "$dst = asl($src1, #$src2)",
1685 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1686 u5ImmPred:$src2))]>;
1688 def ASLd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1689 "$dst = asl($src1, #$src2)",
1690 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1691 u6ImmPred:$src2))]>;
1693 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1694 "$dst = lsr($src1, #$src2)",
1695 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1696 u5ImmPred:$src2))]>;
1698 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1699 "$dst = lsr($src1, #$src2)",
1700 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1701 u6ImmPred:$src2))]>;
1703 // Shift by immediate and add.
1704 let AddedComplexity = 100 in
1705 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
1707 "$dst = addasl($src1, $src2, #$src3)",
1708 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
1709 (shl (i32 IntRegs:$src2),
1710 u3ImmPred:$src3)))]>;
1712 // Shift by register.
1713 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1714 "$dst = asl($src1, $src2)",
1715 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1716 (i32 IntRegs:$src2)))]>;
1718 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1719 "$dst = asr($src1, $src2)",
1720 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1721 (i32 IntRegs:$src2)))]>;
1723 def LSL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1724 "$dst = lsl($src1, $src2)",
1725 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1726 (i32 IntRegs:$src2)))]>;
1728 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1729 "$dst = lsr($src1, $src2)",
1730 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1731 (i32 IntRegs:$src2)))]>;
1733 def ASLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1734 "$dst = asl($src1, $src2)",
1735 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1736 (i32 IntRegs:$src2)))]>;
1738 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1739 "$dst = lsl($src1, $src2)",
1740 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1741 (i32 IntRegs:$src2)))]>;
1743 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1745 "$dst = asr($src1, $src2)",
1746 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1747 (i32 IntRegs:$src2)))]>;
1749 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1751 "$dst = lsr($src1, $src2)",
1752 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1753 (i32 IntRegs:$src2)))]>;
1755 //===----------------------------------------------------------------------===//
1757 //===----------------------------------------------------------------------===//
1759 //===----------------------------------------------------------------------===//
1761 //===----------------------------------------------------------------------===//
1762 //===----------------------------------------------------------------------===//
1764 //===----------------------------------------------------------------------===//
1766 //===----------------------------------------------------------------------===//
1768 //===----------------------------------------------------------------------===//
1769 //===----------------------------------------------------------------------===//
1771 //===----------------------------------------------------------------------===//
1773 //===----------------------------------------------------------------------===//
1775 //===----------------------------------------------------------------------===//
1777 //===----------------------------------------------------------------------===//
1779 //===----------------------------------------------------------------------===//
1780 def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
1781 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
1784 let hasSideEffects = 1, isSolo = 1 in
1785 def BARRIER : SYSInst<(outs), (ins),
1787 [(HexagonBARRIER)]>;
1789 //===----------------------------------------------------------------------===//
1791 //===----------------------------------------------------------------------===//
1793 // TFRI64 - assembly mapped.
1794 let isReMaterializable = 1 in
1795 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
1797 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
1799 // Pseudo instruction to encode a set of conditional transfers.
1800 // This instruction is used instead of a mux and trades-off codesize
1801 // for performance. We conduct this transformation optimistically in
1802 // the hope that these instructions get promoted to dot-new transfers.
1803 let AddedComplexity = 100, isPredicated = 1 in
1804 def TFR_condset_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
1807 "Error; should not emit",
1808 [(set (i32 IntRegs:$dst),
1809 (i32 (select (i1 PredRegs:$src1),
1810 (i32 IntRegs:$src2),
1811 (i32 IntRegs:$src3))))]>;
1812 let AddedComplexity = 100, isPredicated = 1 in
1813 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
1814 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
1815 "Error; should not emit",
1816 [(set (i32 IntRegs:$dst),
1817 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
1818 s12ImmPred:$src3)))]>;
1820 let AddedComplexity = 100, isPredicated = 1 in
1821 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
1822 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
1823 "Error; should not emit",
1824 [(set (i32 IntRegs:$dst),
1825 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
1826 (i32 IntRegs:$src3))))]>;
1828 let AddedComplexity = 100, isPredicated = 1 in
1829 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
1830 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
1831 "Error; should not emit",
1832 [(set (i32 IntRegs:$dst),
1833 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
1834 s12ImmPred:$src3)))]>;
1836 // Generate frameindex addresses.
1837 let isReMaterializable = 1 in
1838 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
1839 "$dst = add($src1)",
1840 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
1845 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
1846 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
1847 "loop0($offset, #$src2)",
1851 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
1852 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
1853 "loop0($offset, $src2)",
1857 let isBranch = 1, isTerminator = 1, neverHasSideEffects = 1,
1858 Defs = [PC, LC0], Uses = [SA0, LC0] in {
1859 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
1864 // Support for generating global address.
1865 // Taken from X86InstrInfo.td.
1866 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [
1870 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
1871 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
1873 // HI/LO Instructions
1874 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1875 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
1876 "$dst.l = #LO($global)",
1879 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1880 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
1881 "$dst.h = #HI($global)",
1884 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1885 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
1886 "$dst.l = #LO($imm_value)",
1890 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1891 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
1892 "$dst.h = #HI($imm_value)",
1895 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1896 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
1897 "$dst.l = #LO($jt)",
1900 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1901 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
1902 "$dst.h = #HI($jt)",
1906 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1907 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
1908 "$dst.l = #LO($label)",
1911 let isReMaterializable = 1, isMoveImm = 1 , neverHasSideEffects = 1 in
1912 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
1913 "$dst.h = #HI($label)",
1916 // This pattern is incorrect. When we add small data, we should change
1917 // this pattern to use memw(#foo).
1918 // This is for sdata.
1919 let isMoveImm = 1 in
1920 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
1921 "$dst = CONST32(#$global)",
1922 [(set (i32 IntRegs:$dst),
1923 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
1925 // This is for non-sdata.
1926 let isReMaterializable = 1, isMoveImm = 1 in
1927 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
1928 "$dst = CONST32(#$global)",
1929 [(set (i32 IntRegs:$dst),
1930 (HexagonCONST32 tglobaladdr:$global))]>;
1932 let isReMaterializable = 1, isMoveImm = 1 in
1933 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
1934 "$dst = CONST32(#$jt)",
1935 [(set (i32 IntRegs:$dst),
1936 (HexagonCONST32 tjumptable:$jt))]>;
1938 let isReMaterializable = 1, isMoveImm = 1 in
1939 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
1940 "$dst = CONST32(#$global)",
1941 [(set (i32 IntRegs:$dst),
1942 (HexagonCONST32_GP tglobaladdr:$global))]>;
1944 let isReMaterializable = 1, isMoveImm = 1 in
1945 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
1946 "$dst = CONST32(#$global)",
1947 [(set (i32 IntRegs:$dst), imm:$global) ]>;
1949 // Map BlockAddress lowering to CONST32_Int_Real
1950 def : Pat<(HexagonCONST32_GP tblockaddress:$addr),
1951 (CONST32_Int_Real tblockaddress:$addr)>;
1953 let isReMaterializable = 1, isMoveImm = 1 in
1954 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
1955 "$dst = CONST32($label)",
1956 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
1958 let isReMaterializable = 1, isMoveImm = 1 in
1959 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
1960 "$dst = CONST64(#$global)",
1961 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
1963 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
1964 "$dst = xor($dst, $dst)",
1965 [(set (i1 PredRegs:$dst), 0)]>;
1967 def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1968 "$dst = mpy($src1, $src2)",
1969 [(set (i32 IntRegs:$dst),
1970 (trunc (i64 (srl (i64 (mul (i64 (sext (i32 IntRegs:$src1))),
1971 (i64 (sext (i32 IntRegs:$src2))))),
1974 // Pseudo instructions.
1975 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
1977 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
1978 SDTCisVT<1, i32> ]>;
1980 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
1981 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
1983 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
1984 [SDNPHasChain, SDNPOutGlue]>;
1986 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
1988 def call : SDNode<"HexagonISD::CALL", SDT_SPCall,
1989 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
1991 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
1992 // Optional Flag and Variable Arguments.
1993 // Its 1 Operand has pointer type.
1994 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
1995 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1997 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
1998 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
1999 "Should never be emitted",
2000 [(callseq_start timm:$amt)]>;
2003 let Defs = [R29, R30, R31], Uses = [R29] in {
2004 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2005 "Should never be emitted",
2006 [(callseq_end timm:$amt1, timm:$amt2)]>;
2009 let isCall = 1, neverHasSideEffects = 1,
2010 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2011 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2012 def CALL : JInst<(outs), (ins calltarget:$dst),
2016 // Call subroutine from register.
2017 let isCall = 1, neverHasSideEffects = 1,
2018 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2019 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2020 def CALLR : JRInst<(outs), (ins IntRegs:$dst),
2026 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2027 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst),
2028 "jump $dst // TAILCALL", []>;
2030 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2031 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst),
2032 "jump $dst // TAILCALL", []>;
2035 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2036 def TCRETURNR : JInst<(outs), (ins IntRegs:$dst),
2037 "jumpr $dst // TAILCALL", []>;
2039 // Map call instruction.
2040 def : Pat<(call (i32 IntRegs:$dst)),
2041 (CALLR (i32 IntRegs:$dst))>, Requires<[HasV2TOnly]>;
2042 def : Pat<(call tglobaladdr:$dst),
2043 (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
2044 def : Pat<(call texternalsym:$dst),
2045 (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>;
2047 def : Pat<(HexagonTCRet tglobaladdr:$dst),
2048 (TCRETURNtg tglobaladdr:$dst)>;
2049 def : Pat<(HexagonTCRet texternalsym:$dst),
2050 (TCRETURNtext texternalsym:$dst)>;
2051 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
2052 (TCRETURNR (i32 IntRegs:$dst))>;
2054 // Atomic load and store support
2055 // 8 bit atomic load
2056 def : Pat<(atomic_load_8 ADDRriS11_0:$src1),
2057 (i32 (LDriub ADDRriS11_0:$src1))>;
2059 def : Pat<(atomic_load_8 (add (i32 IntRegs:$src1), s11_0ImmPred:$offset)),
2060 (i32 (LDriub_indexed (i32 IntRegs:$src1), s11_0ImmPred:$offset))>;
2062 // 16 bit atomic load
2063 def : Pat<(atomic_load_16 ADDRriS11_1:$src1),
2064 (i32 (LDriuh ADDRriS11_1:$src1))>;
2066 def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)),
2067 (i32 (LDriuh_indexed (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
2069 def : Pat<(atomic_load_32 ADDRriS11_2:$src1),
2070 (i32 (LDriw ADDRriS11_2:$src1))>;
2072 def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),
2073 (i32 (LDriw_indexed (i32 IntRegs:$src1), s11_2ImmPred:$offset))>;
2075 // 64 bit atomic load
2076 def : Pat<(atomic_load_64 ADDRriS11_3:$src1),
2077 (i64 (LDrid ADDRriS11_3:$src1))>;
2079 def : Pat<(atomic_load_64 (add (i32 IntRegs:$src1), s11_3ImmPred:$offset)),
2080 (i64 (LDrid_indexed (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
2083 def : Pat<(atomic_store_8 ADDRriS11_0:$src2, (i32 IntRegs:$src1)),
2084 (STrib ADDRriS11_0:$src2, (i32 IntRegs:$src1))>;
2086 def : Pat<(atomic_store_8 (add (i32 IntRegs:$src2), s11_0ImmPred:$offset),
2087 (i32 IntRegs:$src1)),
2088 (STrib_indexed (i32 IntRegs:$src2), s11_0ImmPred:$offset,
2089 (i32 IntRegs:$src1))>;
2092 def : Pat<(atomic_store_16 ADDRriS11_1:$src2, (i32 IntRegs:$src1)),
2093 (STrih ADDRriS11_1:$src2, (i32 IntRegs:$src1))>;
2095 def : Pat<(atomic_store_16 (i32 IntRegs:$src1),
2096 (add (i32 IntRegs:$src2), s11_1ImmPred:$offset)),
2097 (STrih_indexed (i32 IntRegs:$src2), s11_1ImmPred:$offset,
2098 (i32 IntRegs:$src1))>;
2100 def : Pat<(atomic_store_32 ADDRriS11_2:$src2, (i32 IntRegs:$src1)),
2101 (STriw ADDRriS11_2:$src2, (i32 IntRegs:$src1))>;
2103 def : Pat<(atomic_store_32 (add (i32 IntRegs:$src2), s11_2ImmPred:$offset),
2104 (i32 IntRegs:$src1)),
2105 (STriw_indexed (i32 IntRegs:$src2), s11_2ImmPred:$offset,
2106 (i32 IntRegs:$src1))>;
2111 def : Pat<(atomic_store_64 ADDRriS11_3:$src2, (i64 DoubleRegs:$src1)),
2112 (STrid ADDRriS11_3:$src2, (i64 DoubleRegs:$src1))>;
2114 def : Pat<(atomic_store_64 (add (i32 IntRegs:$src2), s11_3ImmPred:$offset),
2115 (i64 DoubleRegs:$src1)),
2116 (STrid_indexed (i32 IntRegs:$src2), s11_3ImmPred:$offset,
2117 (i64 DoubleRegs:$src1))>;
2119 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
2120 def : Pat <(and (i32 IntRegs:$src1), 65535),
2121 (ZXTH (i32 IntRegs:$src1))>;
2123 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
2124 def : Pat <(and (i32 IntRegs:$src1), 255),
2125 (ZXTB (i32 IntRegs:$src1))>;
2127 // Map Add(p1, true) to p1 = not(p1).
2128 // Add(p1, false) should never be produced,
2129 // if it does, it got to be mapped to NOOP.
2130 def : Pat <(add (i1 PredRegs:$src1), -1),
2131 (NOT_p (i1 PredRegs:$src1))>;
2133 // Map from p0 = setlt(r0, r1) r2 = mux(p0, r3, r4) =>
2134 // p0 = cmp.lt(r0, r1), r0 = mux(p0, r2, r1).
2135 def : Pat <(select (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2136 (i32 IntRegs:$src3),
2137 (i32 IntRegs:$src4)),
2138 (i32 (TFR_condset_rr (CMPLTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2139 (i32 IntRegs:$src4), (i32 IntRegs:$src3)))>,
2140 Requires<[HasV2TOnly]>;
2142 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
2143 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
2144 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
2147 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
2148 // => r0 = TFR_condset_ri(p0, r1, #i)
2149 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
2150 (i32 IntRegs:$src3)),
2151 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
2152 s12ImmPred:$src2))>;
2154 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
2155 // => r0 = TFR_condset_ir(p0, #i, r1)
2156 def : Pat <(select (not PredRegs:$src1), IntRegs:$src2, s12ImmPred:$src3),
2157 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
2158 (i32 IntRegs:$src2)))>;
2160 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
2161 def : Pat <(brcond (not PredRegs:$src1), bb:$offset),
2162 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
2164 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
2165 def : Pat <(and PredRegs:$src1, (not PredRegs:$src2)),
2166 (i1 (AND_pnotp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2168 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
2169 let AddedComplexity = 10 in
2170 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
2171 (i32 (AND_rr (i32 (LDrib ADDRriS11_0:$addr)), (TFRI 0x1)))>;
2173 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
2174 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
2175 (i64 (SXTW (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
2177 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
2178 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
2179 (i64 (SXTW (i32 (SXTH (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2180 subreg_loreg))))))>;
2182 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
2183 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
2184 (i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2185 subreg_loreg))))))>;
2187 // We want to prevent emitting pnot's as much as possible.
2188 // Map brcond with an unsupported setcc to a JMP_cNot.
2189 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2191 (JMP_cNot (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2194 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
2196 (JMP_cNot (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
2198 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
2199 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
2201 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
2202 (JMP_c (i1 PredRegs:$src1), bb:$offset)>;
2204 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
2206 (JMP_cNot (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2), bb:$offset)>;
2208 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2210 (JMP_c (CMPLTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)), bb:$offset)>;
2212 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2214 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
2217 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2219 (JMP_cNot (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2222 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2224 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2227 // Map from a 64-bit select to an emulated 64-bit mux.
2228 // Hexagon does not support 64-bit MUXes; so emulate with combines.
2229 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
2230 (i64 DoubleRegs:$src3)),
2231 (i64 (COMBINE_rr (i32 (MUX_rr (i1 PredRegs:$src1),
2232 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2234 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2236 (i32 (MUX_rr (i1 PredRegs:$src1),
2237 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2239 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2240 subreg_loreg))))))>;
2242 // Map from a 1-bit select to logical ops.
2243 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
2244 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
2245 (i1 PredRegs:$src3)),
2246 (OR_pp (AND_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
2247 (AND_pp (NOT_p (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
2249 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
2250 def : Pat<(i1 (load ADDRriS11_2:$addr)),
2251 (i1 (TFR_PdRs (i32 (LDrib ADDRriS11_2:$addr))))>;
2253 // Map for truncating from 64 immediates to 32 bit immediates.
2254 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
2255 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
2257 // Map for truncating from i64 immediates to i1 bit immediates.
2258 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
2259 (i1 (TFR_PdRs (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2262 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
2263 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2264 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2267 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
2268 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2269 (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2271 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
2272 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2273 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2276 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
2277 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2278 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2281 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
2282 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2283 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2286 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
2287 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2288 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2290 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
2291 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
2292 (STrib ADDRriS11_2:$addr, (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0)) )>;
2294 // Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs).
2295 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
2296 // Better way to do this?
2297 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
2298 (i64 (SXTW (i32 IntRegs:$src1)))>;
2300 // Map cmple -> cmpgt.
2301 // rs <= rt -> !(rs > rt).
2302 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ImmPred:$src2)),
2303 (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), s10ImmPred:$src2)))>;
2305 // rs <= rt -> !(rs > rt).
2306 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2307 (i1 (NOT_p (CMPGTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2309 // Rss <= Rtt -> !(Rss > Rtt).
2310 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2311 (i1 (NOT_p (CMPGT64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2313 // Map cmpne -> cmpeq.
2314 // Hexagon_TODO: We should improve on this.
2315 // rs != rt -> !(rs == rt).
2316 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
2317 (i1 (NOT_p(i1 (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2))))>;
2319 // Map cmpne(Rs) -> !cmpeqe(Rs).
2320 // rs != rt -> !(rs == rt).
2321 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2322 (i1 (NOT_p (i1 (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
2324 // Convert setne back to xor for hexagon since we compute w/ pred registers.
2325 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
2326 (i1 (XOR_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2328 // Map cmpne(Rss) -> !cmpew(Rss).
2329 // rs != rt -> !(rs == rt).
2330 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2331 (i1 (NOT_p (i1 (CMPEHexagon4rr (i64 DoubleRegs:$src1),
2332 (i64 DoubleRegs:$src2)))))>;
2334 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
2335 // rs >= rt -> !(rt > rs).
2336 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2337 (i1 (NOT_p (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
2339 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ImmPred:$src2)),
2340 (i1 (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2))>;
2342 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
2343 // rss >= rtt -> !(rtt > rss).
2344 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2345 (i1 (NOT_p (i1 (CMPGT64rr (i64 DoubleRegs:$src2),
2346 (i64 DoubleRegs:$src1)))))>;
2348 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
2349 // rs < rt -> !(rs >= rt).
2350 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
2351 (i1 (NOT_p (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2)))>;
2353 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
2354 // rs < rt -> rt > rs.
2355 // We can let assembler map it, or we can do in the compiler itself.
2356 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2357 (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2359 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
2360 // rss < rtt -> (rtt > rss).
2361 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2362 (i1 (CMPGT64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2364 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
2365 // rs < rt -> rt > rs.
2366 // We can let assembler map it, or we can do in the compiler itself.
2367 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2368 (i1 (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2370 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
2371 // rs < rt -> rt > rs.
2372 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2373 (i1 (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2375 // Generate cmpgeu(Rs, #u8)
2376 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ImmPred:$src2)),
2377 (i1 (CMPGEUri (i32 IntRegs:$src1), u8ImmPred:$src2))>;
2379 // Generate cmpgtu(Rs, #u9)
2380 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ImmPred:$src2)),
2381 (i1 (CMPGTUri (i32 IntRegs:$src1), u9ImmPred:$src2))>;
2383 // Map from Rs >= Rt -> !(Rt > Rs).
2384 // rs >= rt -> !(rt > rs).
2385 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2386 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
2388 // Map from Rs >= Rt -> !(Rt > Rs).
2389 // rs >= rt -> !(rt > rs).
2390 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2391 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
2393 // Map from cmpleu(Rs, Rs) -> !cmpgtu(Rs, Rs).
2394 // Map from (Rs <= Rt) -> !(Rs > Rt).
2395 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2396 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2398 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
2399 // Map from (Rs <= Rt) -> !(Rs > Rt).
2400 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2401 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2405 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
2406 (i32 (MUX_ii (i1 PredRegs:$src1), -1, 0))>;
2409 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
2410 (i64 (COMBINE_rr (TFRI -1), (MUX_ii (i1 PredRegs:$src1), -1, 0)))>;
2412 // Convert sign-extended load back to load and sign extend.
2414 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
2415 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2417 // Convert any-extended load back to load and sign extend.
2419 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
2420 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2422 // Convert sign-extended load back to load and sign extend.
2424 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
2425 (i64 (SXTW (LDrih ADDRriS11_1:$src1)))>;
2427 // Convert sign-extended load back to load and sign extend.
2429 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
2430 (i64 (SXTW (LDriw ADDRriS11_2:$src1)))>;
2435 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2436 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2439 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
2440 (i64 (COMBINE_rr (TFRI 0), (MUX_ii (i1 PredRegs:$src1), 1, 0)))>,
2444 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
2445 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>,
2449 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
2450 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>,
2453 let AddedComplexity = 20 in
2454 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
2455 s11_0ExtPred:$offset))),
2456 (i64 (COMBINE_rr (TFRI 0), (LDriub_indexed IntRegs:$src1,
2457 s11_0ExtPred:$offset)))>,
2461 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
2462 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>,
2465 let AddedComplexity = 20 in
2466 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
2467 s11_0ExtPred:$offset))),
2468 (i64 (COMBINE_rr (TFRI 0), (LDriub_indexed IntRegs:$src1,
2469 s11_0ExtPred:$offset)))>,
2473 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
2474 (i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>,
2477 let AddedComplexity = 20 in
2478 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
2479 s11_1ExtPred:$offset))),
2480 (i64 (COMBINE_rr (TFRI 0), (LDriuh_indexed IntRegs:$src1,
2481 s11_1ExtPred:$offset)))>,
2485 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
2486 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>,
2489 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
2490 (i32 (LDriw ADDRriS11_0:$src1))>;
2492 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2493 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2494 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2496 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2497 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
2498 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2500 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
2501 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
2502 (i64 (SXTW (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))))>;
2505 // Any extended 64-bit load.
2506 // anyext i32 -> i64
2507 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
2508 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>,
2511 // When there is an offset we should prefer the pattern below over the pattern above.
2512 // The complexity of the above is 13 (gleaned from HexagonGenDAGIsel.inc)
2513 // So this complexity below is comfortably higher to allow for choosing the below.
2514 // If this is not done then we generate addresses such as
2515 // ********************************************
2516 // r1 = add (r0, #4)
2517 // r1 = memw(r1 + #0)
2519 // r1 = memw(r0 + #4)
2520 // ********************************************
2521 let AddedComplexity = 100 in
2522 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
2523 (i64 (COMBINE_rr (TFRI 0), (LDriw_indexed IntRegs:$src1,
2524 s11_2ExtPred:$offset)))>,
2527 // anyext i16 -> i64.
2528 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
2529 (i64 (COMBINE_rr (TFRI 0), (LDrih ADDRriS11_2:$src1)))>,
2532 let AddedComplexity = 20 in
2533 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
2534 s11_1ExtPred:$offset))),
2535 (i64 (COMBINE_rr (TFRI 0), (LDrih_indexed IntRegs:$src1,
2536 s11_1ExtPred:$offset)))>,
2539 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
2540 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
2541 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>,
2544 // Multiply 64-bit unsigned and use upper result.
2545 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2560 (COMBINE_rr (TFRI 0),
2566 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2568 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2569 subreg_loreg)))), 32)),
2571 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2572 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2573 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2574 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2575 32)), subreg_loreg)))),
2576 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2577 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2579 // Multiply 64-bit signed and use upper result.
2580 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2584 (COMBINE_rr (TFRI 0),
2594 (COMBINE_rr (TFRI 0),
2600 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2602 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2603 subreg_loreg)))), 32)),
2605 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2606 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2607 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2608 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2609 32)), subreg_loreg)))),
2610 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2611 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2613 // Hexagon specific ISD nodes.
2614 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
2615 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
2616 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
2617 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
2618 SDTHexagonADJDYNALLOC>;
2619 // Needed to tag these instructions for stack layout.
2620 let usesCustomInserter = 1 in
2621 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
2623 "$dst = add($src1, #$src2)",
2624 [(set (i32 IntRegs:$dst),
2625 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
2626 s16ImmPred:$src2))]>;
2628 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
2629 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
2630 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
2632 [(set (i32 IntRegs:$dst),
2633 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
2635 let AddedComplexity = 100 in
2636 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
2637 (COPY (i32 IntRegs:$src1))>;
2639 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2640 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
2642 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
2643 def BR_JT : JRInst<(outs), (ins IntRegs:$src),
2645 [(HexagonBR_JT (i32 IntRegs:$src))]>;
2647 let isBranch=1, isIndirectBranch=1, isTerminator=1 in
2648 def BRIND : JRInst<(outs), (ins IntRegs:$src),
2650 [(brind (i32 IntRegs:$src))]>;
2652 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
2654 def : Pat<(HexagonWrapperJT tjumptable:$dst),
2655 (i32 (CONST32_set_jt tjumptable:$dst))>;
2659 // Multi-class for logical operators :
2660 // Shift by immediate/register and accumulate/logical
2661 multiclass xtype_imm<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
2662 def _ri : SInst_acc<(outs IntRegs:$dst),
2663 (ins IntRegs:$src1, IntRegs:$src2, u5Imm:$src3),
2664 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
2665 [(set (i32 IntRegs:$dst),
2666 (OpNode2 (i32 IntRegs:$src1),
2667 (OpNode1 (i32 IntRegs:$src2),
2668 u5ImmPred:$src3)))],
2671 def d_ri : SInst_acc<(outs DoubleRegs:$dst),
2672 (ins DoubleRegs:$src1, DoubleRegs:$src2, u6Imm:$src3),
2673 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
2674 [(set (i64 DoubleRegs:$dst), (OpNode2 (i64 DoubleRegs:$src1),
2675 (OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
2679 // Multi-class for logical operators :
2680 // Shift by register and accumulate/logical (32/64 bits)
2681 multiclass xtype_reg<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
2682 def _rr : SInst_acc<(outs IntRegs:$dst),
2683 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2684 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
2685 [(set (i32 IntRegs:$dst),
2686 (OpNode2 (i32 IntRegs:$src1),
2687 (OpNode1 (i32 IntRegs:$src2),
2688 (i32 IntRegs:$src3))))],
2691 def d_rr : SInst_acc<(outs DoubleRegs:$dst),
2692 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2693 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
2694 [(set (i64 DoubleRegs:$dst),
2695 (OpNode2 (i64 DoubleRegs:$src1),
2696 (OpNode1 (i64 DoubleRegs:$src2),
2697 (i32 IntRegs:$src3))))],
2702 multiclass basic_xtype_imm<string OpcStr, SDNode OpNode> {
2703 let AddedComplexity = 100 in
2704 defm _ADD : xtype_imm< !strconcat("+= ", OpcStr), OpNode, add>;
2705 defm _SUB : xtype_imm< !strconcat("-= ", OpcStr), OpNode, sub>;
2706 defm _AND : xtype_imm< !strconcat("&= ", OpcStr), OpNode, and>;
2707 defm _OR : xtype_imm< !strconcat("|= ", OpcStr), OpNode, or>;
2710 multiclass basic_xtype_reg<string OpcStr, SDNode OpNode> {
2711 let AddedComplexity = 100 in
2712 defm _ADD : xtype_reg< !strconcat("+= ", OpcStr), OpNode, add>;
2713 defm _SUB : xtype_reg< !strconcat("-= ", OpcStr), OpNode, sub>;
2714 defm _AND : xtype_reg< !strconcat("&= ", OpcStr), OpNode, and>;
2715 defm _OR : xtype_reg< !strconcat("|= ", OpcStr), OpNode, or>;
2718 multiclass xtype_xor_imm<string OpcStr, SDNode OpNode> {
2719 let AddedComplexity = 100 in
2720 defm _XOR : xtype_imm< !strconcat("^= ", OpcStr), OpNode, xor>;
2723 defm ASL : basic_xtype_imm<"asl", shl>, basic_xtype_reg<"asl", shl>,
2724 xtype_xor_imm<"asl", shl>;
2726 defm LSR : basic_xtype_imm<"lsr", srl>, basic_xtype_reg<"lsr", srl>,
2727 xtype_xor_imm<"lsr", srl>;
2729 defm ASR : basic_xtype_imm<"asr", sra>, basic_xtype_reg<"asr", sra>;
2730 defm LSL : basic_xtype_reg<"lsl", shl>;
2732 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
2733 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
2734 (i32 (MPYI_rin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
2736 //===----------------------------------------------------------------------===//
2737 // V3 Instructions +
2738 //===----------------------------------------------------------------------===//
2740 include "HexagonInstrInfoV3.td"
2742 //===----------------------------------------------------------------------===//
2743 // V3 Instructions -
2744 //===----------------------------------------------------------------------===//
2746 //===----------------------------------------------------------------------===//
2747 // V4 Instructions +
2748 //===----------------------------------------------------------------------===//
2750 include "HexagonInstrInfoV4.td"
2752 //===----------------------------------------------------------------------===//
2753 // V4 Instructions -
2754 //===----------------------------------------------------------------------===//
2756 //===----------------------------------------------------------------------===//
2757 // V5 Instructions +
2758 //===----------------------------------------------------------------------===//
2760 include "HexagonInstrInfoV5.td"
2762 //===----------------------------------------------------------------------===//
2763 // V5 Instructions -
2764 //===----------------------------------------------------------------------===//