1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
17 //===----------------------------------------------------------------------===//
19 // Multi-class for logical operators.
20 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
21 def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
22 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
23 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),
25 def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
26 !strconcat("$dst = ", !strconcat(OpcStr, "(#$b, $c)")),
27 [(set (i32 IntRegs:$dst), (OpNode s10Imm:$b,
31 // Multi-class for compare ops.
32 let isCompare = 1 in {
33 multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
34 def rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
35 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
36 [(set (i1 PredRegs:$dst),
37 (OpNode (i64 DoubleRegs:$b), (i64 DoubleRegs:$c)))]>;
40 multiclass CMP32_rr_ri_s10<string OpcStr, string CextOp, PatFrag OpNode> {
41 let CextOpcode = CextOp in {
42 let InputType = "reg" in
43 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
44 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
45 [(set (i1 PredRegs:$dst),
46 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
48 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1,
49 opExtentBits = 10, InputType = "imm" in
50 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Ext:$c),
51 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
52 [(set (i1 PredRegs:$dst),
53 (OpNode (i32 IntRegs:$b), s10ExtPred:$c))]>;
57 multiclass CMP32_rr_ri_u9<string OpcStr, string CextOp, PatFrag OpNode> {
58 let CextOpcode = CextOp in {
59 let InputType = "reg" in
60 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
61 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
62 [(set (i1 PredRegs:$dst),
63 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
65 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0,
66 opExtentBits = 9, InputType = "imm" in
67 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Ext:$c),
68 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
69 [(set (i1 PredRegs:$dst),
70 (OpNode (i32 IntRegs:$b), u9ExtPred:$c))]>;
74 multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
75 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
76 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Ext:$c),
77 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
78 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
83 //===----------------------------------------------------------------------===//
84 // ALU32/ALU (Instructions with register-register form)
85 //===----------------------------------------------------------------------===//
86 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
87 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
89 def HexagonWrapperCombineII :
90 SDNode<"HexagonISD::WrapperCombineII", SDTHexagonI64I32I32>;
92 def HexagonWrapperCombineRR :
93 SDNode<"HexagonISD::WrapperCombineRR", SDTHexagonI64I32I32>;
95 let hasSideEffects = 0, hasNewValue = 1, InputType = "reg" in
96 class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev,
98 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
99 "$Rd = "#mnemonic#"($Rs, $Rt)",
100 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredRel {
101 let isCommutable = IsComm;
102 let BaseOpcode = mnemonic#_rr;
103 let CextOpcode = mnemonic;
111 let Inst{26-24} = MajOp;
112 let Inst{23-21} = MinOp;
113 let Inst{20-16} = !if(OpsRev,Rt,Rs);
114 let Inst{12-8} = !if(OpsRev,Rs,Rt);
118 let hasSideEffects = 0, hasNewValue = 1 in
119 class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp,
120 bit OpsRev, bit PredNot, bit PredNew>
121 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
122 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") "#
123 "$Rd = "#mnemonic#"($Rs, $Rt)",
124 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
125 let isPredicated = 1;
126 let isPredicatedFalse = PredNot;
127 let isPredicatedNew = PredNew;
128 let BaseOpcode = mnemonic#_rr;
129 let CextOpcode = mnemonic;
138 let Inst{26-24} = MajOp;
139 let Inst{23-21} = MinOp;
140 let Inst{20-16} = !if(OpsRev,Rt,Rs);
141 let Inst{13} = PredNew;
142 let Inst{12-8} = !if(OpsRev,Rs,Rt);
143 let Inst{7} = PredNot;
148 multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,
150 def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>;
151 def f : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 0>;
152 def tnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 1>;
153 def fnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 1>;
156 multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp,
157 bit OpsRev, bit IsComm> {
158 let isPredicable = 1 in
159 def A2_#NAME : T_ALU32_3op <mnemonic, MajOp, MinOp, OpsRev, IsComm>;
160 defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>;
163 let isCodeGenOnly = 0 in
164 defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
165 defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>;
166 defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>;
167 defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>;
168 defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>;
170 // Pats for instruction selection.
171 class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
172 : Pat<(ResT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
173 (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
175 def: BinOp32_pat<add, A2_add, i32>;
176 def: BinOp32_pat<and, A2_and, i32>;
177 def: BinOp32_pat<or, A2_or, i32>;
178 def: BinOp32_pat<sub, A2_sub, i32>;
179 def: BinOp32_pat<xor, A2_xor, i32>;
181 multiclass ALU32_Pbase<string mnemonic, RegisterClass RC, bit isNot,
183 let isPredicatedNew = isPredNew in
184 def NAME : ALU32_rr<(outs RC:$dst),
185 (ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
186 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
187 ") $dst = ")#mnemonic#"($src2, $src3)",
191 multiclass ALU32_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
192 let isPredicatedFalse = PredNot in {
193 defm _c#NAME : ALU32_Pbase<mnemonic, RC, PredNot, 0>;
195 defm _cdn#NAME : ALU32_Pbase<mnemonic, RC, PredNot, 1>;
199 //===----------------------------------------------------------------------===//
200 // template class for non-predicated alu32_2op instructions
201 // - aslh, asrh, sxtb, sxth, zxth
202 //===----------------------------------------------------------------------===//
203 let hasNewValue = 1, opNewValue = 0 in
204 class T_ALU32_2op <string mnemonic, bits<3> minOp> :
205 ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
206 "$Rd = "#mnemonic#"($Rs)", [] > {
212 let Inst{27-24} = 0b0000;
213 let Inst{23-21} = minOp;
216 let Inst{20-16} = Rs;
219 //===----------------------------------------------------------------------===//
220 // template class for predicated alu32_2op instructions
221 // - aslh, asrh, sxtb, sxth, zxtb, zxth
222 //===----------------------------------------------------------------------===//
223 let hasSideEffects = 0, validSubTargets = HasV4SubT,
224 hasNewValue = 1, opNewValue = 0 in
225 class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot,
227 ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
228 !if(isPredNot, "if (!$Pu", "if ($Pu")
229 #!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> {
236 let Inst{27-24} = 0b0000;
237 let Inst{23-21} = minOp;
239 let Inst{11} = isPredNot;
240 let Inst{10} = isPredNew;
243 let Inst{20-16} = Rs;
246 multiclass ALU32_2op_Pred<string mnemonic, bits<3> minOp, bit PredNot> {
247 let isPredicatedFalse = PredNot in {
248 def NAME : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 0>;
251 let isPredicatedNew = 1 in
252 def NAME#new : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 1>;
256 multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
257 let BaseOpcode = mnemonic in {
258 let isPredicable = 1, hasSideEffects = 0 in
259 def A2_#NAME : T_ALU32_2op<mnemonic, minOp>;
261 let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
262 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
263 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
268 defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
269 defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
270 defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
271 defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
273 // Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
274 // Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has
275 // predicated forms while 'and' doesn't. Since integrated assembler can't
276 // handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where
277 // immediate operand is set to '255'.
279 let hasNewValue = 1, opNewValue = 0 in
280 class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
281 "$Rd = zxtb($Rs)", [] > { // Rd = and(Rs,255)
288 let Inst{27-22} = 0b011000;
290 let Inst{20-16} = Rs;
291 let Inst{21} = s10{9};
292 let Inst{13-5} = s10{8-0};
295 //Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255)
296 multiclass ZXTB_base <string mnemonic, bits<3> minOp> {
297 let BaseOpcode = mnemonic in {
298 let isPredicable = 1, hasSideEffects = 0 in
299 def A2_#NAME : T_ZXTB;
301 let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
302 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
303 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
308 defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
310 // Combines the two integer registers SRC1 and SRC2 into a double register.
311 let isPredicable = 1 in
312 class T_Combine : ALU32_rr<(outs DoubleRegs:$dst),
313 (ins IntRegs:$src1, IntRegs:$src2),
314 "$dst = combine($src1, $src2)",
315 [(set (i64 DoubleRegs:$dst),
316 (i64 (HexagonWrapperCombineRR (i32 IntRegs:$src1),
317 (i32 IntRegs:$src2))))]>;
319 multiclass Combine_base {
320 let BaseOpcode = "combine" in {
321 def NAME : T_Combine;
322 let neverHasSideEffects = 1, isPredicated = 1 in {
323 defm Pt : ALU32_Pred<"combine", DoubleRegs, 0>;
324 defm NotPt : ALU32_Pred<"combine", DoubleRegs, 1>;
329 defm COMBINE_rr : Combine_base, PredNewRel;
331 // Combines the two immediates SRC1 and SRC2 into a double register.
332 class COMBINE_imm<Operand imm1, Operand imm2, PatLeaf pat1, PatLeaf pat2> :
333 ALU32_ii<(outs DoubleRegs:$dst), (ins imm1:$src1, imm2:$src2),
334 "$dst = combine(#$src1, #$src2)",
335 [(set (i64 DoubleRegs:$dst),
336 (i64 (HexagonWrapperCombineII (i32 pat1:$src1), (i32 pat2:$src2))))]>;
338 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8 in
339 def COMBINE_Ii : COMBINE_imm<s8Ext, s8Imm, s8ExtPred, s8ImmPred>;
341 //===----------------------------------------------------------------------===//
342 // ALU32/ALU (ADD with register-immediate form)
343 //===----------------------------------------------------------------------===//
344 multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
345 let isPredicatedNew = isPredNew in
346 def NAME : ALU32_ri<(outs IntRegs:$dst),
347 (ins PredRegs:$src1, IntRegs:$src2, s8Ext: $src3),
348 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
349 ") $dst = ")#mnemonic#"($src2, #$src3)",
353 multiclass ALU32ri_Pred<string mnemonic, bit PredNot> {
354 let isPredicatedFalse = PredNot in {
355 defm _c#NAME : ALU32ri_Pbase<mnemonic, PredNot, 0>;
357 defm _cdn#NAME : ALU32ri_Pbase<mnemonic, PredNot, 1>;
361 let isExtendable = 1, InputType = "imm" in
362 multiclass ALU32ri_base<string mnemonic, string CextOp, SDNode OpNode> {
363 let CextOpcode = CextOp, BaseOpcode = CextOp#_ri in {
364 let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
366 def NAME : ALU32_ri<(outs IntRegs:$dst),
367 (ins IntRegs:$src1, s16Ext:$src2),
368 "$dst = "#mnemonic#"($src1, #$src2)",
369 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
370 (s16ExtPred:$src2)))]>;
372 let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
373 neverHasSideEffects = 1, isPredicated = 1 in {
374 defm Pt : ALU32ri_Pred<mnemonic, 0>;
375 defm NotPt : ALU32ri_Pred<mnemonic, 1>;
380 defm ADD_ri : ALU32ri_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
382 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
383 CextOpcode = "OR", InputType = "imm" in
384 def OR_ri : ALU32_ri<(outs IntRegs:$dst),
385 (ins IntRegs:$src1, s10Ext:$src2),
386 "$dst = or($src1, #$src2)",
387 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
388 s10ExtPred:$src2))]>, ImmRegRel;
390 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
391 InputType = "imm", CextOpcode = "AND" in
392 def AND_ri : ALU32_ri<(outs IntRegs:$dst),
393 (ins IntRegs:$src1, s10Ext:$src2),
394 "$dst = and($src1, #$src2)",
395 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
396 s10ExtPred:$src2))]>, ImmRegRel;
399 let neverHasSideEffects = 1, isCodeGenOnly = 0 in
400 def NOP : ALU32_rr<(outs), (ins),
404 // Rd32=sub(#s10,Rs32)
405 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
406 CextOpcode = "SUB", InputType = "imm" in
407 def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
408 (ins s10Ext:$src1, IntRegs:$src2),
409 "$dst = sub(#$src1, $src2)",
410 [(set IntRegs:$dst, (sub s10ExtPred:$src1, IntRegs:$src2))]>,
413 // Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
414 def : Pat<(not (i32 IntRegs:$src1)),
415 (SUB_ri -1, (i32 IntRegs:$src1))>;
417 // Rd = neg(Rs) gets mapped to Rd=sub(#0, Rs).
418 // Pattern definition for 'neg' was not necessary.
420 multiclass TFR_Pred<bit PredNot> {
421 let isPredicatedFalse = PredNot in {
422 def _c#NAME : ALU32_rr<(outs IntRegs:$dst),
423 (ins PredRegs:$src1, IntRegs:$src2),
424 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
427 let isPredicatedNew = 1 in
428 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
429 (ins PredRegs:$src1, IntRegs:$src2),
430 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
435 let InputType = "reg", neverHasSideEffects = 1 in
436 multiclass TFR_base<string CextOp> {
437 let CextOpcode = CextOp, BaseOpcode = CextOp in {
438 let isPredicable = 1 in
439 def NAME : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
443 let isPredicated = 1 in {
444 defm Pt : TFR_Pred<0>;
445 defm NotPt : TFR_Pred<1>;
450 class T_TFR64_Pred<bit PredNot, bit isPredNew>
451 : ALU32_rr<(outs DoubleRegs:$dst),
452 (ins PredRegs:$src1, DoubleRegs:$src2),
453 !if(PredNot, "if (!$src1", "if ($src1")#
454 !if(isPredNew, ".new) ", ") ")#"$dst = $src2", []>
461 let Inst{27-24} = 0b1101;
462 let Inst{13} = isPredNew;
463 let Inst{7} = PredNot;
465 let Inst{6-5} = src1;
466 let Inst{20-17} = src2{4-1};
468 let Inst{12-9} = src2{4-1};
472 multiclass TFR64_Pred<bit PredNot> {
473 let isPredicatedFalse = PredNot in {
474 def _c#NAME : T_TFR64_Pred<PredNot, 0>;
476 let isPredicatedNew = 1 in
477 def _cdn#NAME : T_TFR64_Pred<PredNot, 1>; // Predicate new
481 let neverHasSideEffects = 1 in
482 multiclass TFR64_base<string BaseName> {
483 let BaseOpcode = BaseName in {
484 let isPredicable = 1 in
485 def NAME : ALU32Inst <(outs DoubleRegs:$dst),
486 (ins DoubleRegs:$src1),
492 let Inst{27-23} = 0b01010;
494 let Inst{20-17} = src1{4-1};
496 let Inst{12-9} = src1{4-1};
500 let isPredicated = 1 in {
501 defm Pt : TFR64_Pred<0>;
502 defm NotPt : TFR64_Pred<1>;
507 multiclass TFRI_Pred<bit PredNot> {
508 let isMoveImm = 1, isPredicatedFalse = PredNot in {
509 def _c#NAME : ALU32_ri<(outs IntRegs:$dst),
510 (ins PredRegs:$src1, s12Ext:$src2),
511 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = #$src2",
515 let isPredicatedNew = 1 in
516 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
517 (ins PredRegs:$src1, s12Ext:$src2),
518 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = #$src2",
523 let InputType = "imm", isExtendable = 1, isExtentSigned = 1 in
524 multiclass TFRI_base<string CextOp> {
525 let CextOpcode = CextOp, BaseOpcode = CextOp#I in {
526 let isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16,
527 isMoveImm = 1, isPredicable = 1, isReMaterializable = 1 in
528 def NAME : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
530 [(set (i32 IntRegs:$dst), s16ExtPred:$src1)]>;
532 let opExtendable = 2, opExtentBits = 12, neverHasSideEffects = 1,
533 isPredicated = 1 in {
534 defm Pt : TFRI_Pred<0>;
535 defm NotPt : TFRI_Pred<1>;
540 defm TFRI : TFRI_base<"TFR">, ImmRegRel, PredNewRel;
541 defm TFR : TFR_base<"TFR">, ImmRegRel, PredNewRel;
542 defm TFR64 : TFR64_base<"TFR64">, PredNewRel;
544 // Transfer control register.
545 let neverHasSideEffects = 1 in
546 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
549 //===----------------------------------------------------------------------===//
551 //===----------------------------------------------------------------------===//
554 //===----------------------------------------------------------------------===//
556 //===----------------------------------------------------------------------===//
558 let neverHasSideEffects = 1 in
559 def COMBINE_ii : ALU32_ii<(outs DoubleRegs:$dst),
560 (ins s8Imm:$src1, s8Imm:$src2),
561 "$dst = combine(#$src1, #$src2)",
565 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
568 "$dst = vmux($src1, $src2, $src3)",
571 let CextOpcode = "MUX", InputType = "reg" in
572 def MUX_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
573 IntRegs:$src2, IntRegs:$src3),
574 "$dst = mux($src1, $src2, $src3)",
575 [(set (i32 IntRegs:$dst),
576 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
577 (i32 IntRegs:$src3))))]>, ImmRegRel;
579 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
580 CextOpcode = "MUX", InputType = "imm" in
581 def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
583 "$dst = mux($src1, #$src2, $src3)",
584 [(set (i32 IntRegs:$dst),
585 (i32 (select (i1 PredRegs:$src1), s8ExtPred:$src2,
586 (i32 IntRegs:$src3))))]>, ImmRegRel;
588 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
589 CextOpcode = "MUX", InputType = "imm" in
590 def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
592 "$dst = mux($src1, $src2, #$src3)",
593 [(set (i32 IntRegs:$dst),
594 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
595 s8ExtPred:$src3)))]>, ImmRegRel;
597 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
598 def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
600 "$dst = mux($src1, #$src2, #$src3)",
601 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
603 s8ImmPred:$src3)))]>;
605 // ALU32 - aslh, asrh, sxtb, sxth, zxtb, zxth
606 multiclass ALU32_2op_Pbase<string mnemonic, bit isNot, bit isPredNew> {
607 let isPredicatedNew = isPredNew in
608 def NAME : ALU32Inst<(outs IntRegs:$dst),
609 (ins PredRegs:$src1, IntRegs:$src2),
610 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
611 ") $dst = ")#mnemonic#"($src2)">,
615 multiclass ALU32_2op_Pred2<string mnemonic, bit PredNot> {
616 let isPredicatedFalse = PredNot in {
617 defm _c#NAME : ALU32_2op_Pbase<mnemonic, PredNot, 0>;
619 defm _cdn#NAME : ALU32_2op_Pbase<mnemonic, PredNot, 1>;
623 multiclass ALU32_2op_base2<string mnemonic> {
624 let BaseOpcode = mnemonic in {
625 let isPredicable = 1, neverHasSideEffects = 1 in
626 def NAME : ALU32Inst<(outs IntRegs:$dst),
628 "$dst = "#mnemonic#"($src1)">;
630 let Predicates = [HasV4T], validSubTargets = HasV4SubT, isPredicated = 1,
631 neverHasSideEffects = 1 in {
632 defm Pt_V4 : ALU32_2op_Pred2<mnemonic, 0>;
633 defm NotPt_V4 : ALU32_2op_Pred2<mnemonic, 1>;
638 defm ASRH : ALU32_2op_base2<"asrh">, PredNewRel;
640 def : Pat <(shl (i32 IntRegs:$src1), (i32 16)),
641 (A2_aslh IntRegs:$src1)>;
643 def : Pat <(sra (i32 IntRegs:$src1), (i32 16)),
644 (ASRH IntRegs:$src1)>;
646 def : Pat <(sext_inreg (i32 IntRegs:$src1), i8),
647 (A2_sxtb IntRegs:$src1)>;
649 def : Pat <(sext_inreg (i32 IntRegs:$src1), i16),
650 (A2_sxth IntRegs:$src1)>;
652 //===----------------------------------------------------------------------===//
654 //===----------------------------------------------------------------------===//
657 //===----------------------------------------------------------------------===//
659 //===----------------------------------------------------------------------===//
662 defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", "CMPGTU", setugt>, ImmRegRel;
663 defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", "CMPGT", setgt>, ImmRegRel;
664 defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", "CMPEQ", seteq>, ImmRegRel;
666 // SDNode for converting immediate C to C-1.
667 def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
668 // Return the byte immediate const-1 as an SDNode.
669 int32_t imm = N->getSExtValue();
670 return XformSToSM1Imm(imm);
673 // SDNode for converting immediate C to C-1.
674 def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
675 // Return the byte immediate const-1 as an SDNode.
676 uint32_t imm = N->getZExtValue();
677 return XformUToUM1Imm(imm);
680 def CTLZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
682 [(set (i32 IntRegs:$dst), (ctlz (i32 IntRegs:$src1)))]>;
684 def CTTZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
686 [(set (i32 IntRegs:$dst), (cttz (i32 IntRegs:$src1)))]>;
688 def CTLZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
690 [(set (i32 IntRegs:$dst), (i32 (trunc (ctlz (i64 DoubleRegs:$src1)))))]>;
692 def CTTZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
694 [(set (i32 IntRegs:$dst), (i32 (trunc (cttz (i64 DoubleRegs:$src1)))))]>;
696 def TSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
697 "$dst = tstbit($src1, $src2)",
698 [(set (i1 PredRegs:$dst),
699 (setne (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>;
701 def TSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
702 "$dst = tstbit($src1, $src2)",
703 [(set (i1 PredRegs:$dst),
704 (setne (and (shl 1, (u5ImmPred:$src2)), (i32 IntRegs:$src1)), 0))]>;
706 //===----------------------------------------------------------------------===//
708 //===----------------------------------------------------------------------===//
711 //===----------------------------------------------------------------------===//
713 //===----------------------------------------------------------------------===//
715 def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
717 "$dst = add($src1, $src2)",
718 [(set (i64 DoubleRegs:$dst), (add (i64 DoubleRegs:$src1),
719 (i64 DoubleRegs:$src2)))]>;
724 defm CMPEHexagon4 : CMP64_rr<"cmp.eq", seteq>;
725 defm CMPGT64 : CMP64_rr<"cmp.gt", setgt>;
726 defm CMPGTU64 : CMP64_rr<"cmp.gtu", setugt>;
728 // Logical operations.
729 def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
731 "$dst = and($src1, $src2)",
732 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
733 (i64 DoubleRegs:$src2)))]>;
735 def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
737 "$dst = or($src1, $src2)",
738 [(set (i64 DoubleRegs:$dst), (or (i64 DoubleRegs:$src1),
739 (i64 DoubleRegs:$src2)))]>;
741 def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
743 "$dst = xor($src1, $src2)",
744 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
745 (i64 DoubleRegs:$src2)))]>;
748 def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
749 "$dst = max($src2, $src1)",
750 [(set (i32 IntRegs:$dst),
751 (i32 (select (i1 (setlt (i32 IntRegs:$src2),
752 (i32 IntRegs:$src1))),
753 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
755 def MAXUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
756 "$dst = maxu($src2, $src1)",
757 [(set (i32 IntRegs:$dst),
758 (i32 (select (i1 (setult (i32 IntRegs:$src2),
759 (i32 IntRegs:$src1))),
760 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
762 def MAXd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
764 "$dst = max($src2, $src1)",
765 [(set (i64 DoubleRegs:$dst),
766 (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
767 (i64 DoubleRegs:$src1))),
768 (i64 DoubleRegs:$src1),
769 (i64 DoubleRegs:$src2))))]>;
771 def MAXUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
773 "$dst = maxu($src2, $src1)",
774 [(set (i64 DoubleRegs:$dst),
775 (i64 (select (i1 (setult (i64 DoubleRegs:$src2),
776 (i64 DoubleRegs:$src1))),
777 (i64 DoubleRegs:$src1),
778 (i64 DoubleRegs:$src2))))]>;
781 def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
782 "$dst = min($src2, $src1)",
783 [(set (i32 IntRegs:$dst),
784 (i32 (select (i1 (setgt (i32 IntRegs:$src2),
785 (i32 IntRegs:$src1))),
786 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
788 def MINUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
789 "$dst = minu($src2, $src1)",
790 [(set (i32 IntRegs:$dst),
791 (i32 (select (i1 (setugt (i32 IntRegs:$src2),
792 (i32 IntRegs:$src1))),
793 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
795 def MINd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
797 "$dst = min($src2, $src1)",
798 [(set (i64 DoubleRegs:$dst),
799 (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
800 (i64 DoubleRegs:$src1))),
801 (i64 DoubleRegs:$src1),
802 (i64 DoubleRegs:$src2))))]>;
804 def MINUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
806 "$dst = minu($src2, $src1)",
807 [(set (i64 DoubleRegs:$dst),
808 (i64 (select (i1 (setugt (i64 DoubleRegs:$src2),
809 (i64 DoubleRegs:$src1))),
810 (i64 DoubleRegs:$src1),
811 (i64 DoubleRegs:$src2))))]>;
814 def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
816 "$dst = sub($src1, $src2)",
817 [(set (i64 DoubleRegs:$dst), (sub (i64 DoubleRegs:$src1),
818 (i64 DoubleRegs:$src2)))]>;
820 // Subtract halfword.
822 //===----------------------------------------------------------------------===//
824 //===----------------------------------------------------------------------===//
826 //===----------------------------------------------------------------------===//
828 //===----------------------------------------------------------------------===//
830 //===----------------------------------------------------------------------===//
832 //===----------------------------------------------------------------------===//
834 //===----------------------------------------------------------------------===//
836 //===----------------------------------------------------------------------===//
838 //===----------------------------------------------------------------------===//
840 //===----------------------------------------------------------------------===//
842 //===----------------------------------------------------------------------===//
844 //===----------------------------------------------------------------------===//
845 // Logical reductions on predicates.
847 // Looping instructions.
849 // Pipelined looping instructions.
851 // Logical operations on predicates.
852 def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
853 "$dst = and($src1, $src2)",
854 [(set (i1 PredRegs:$dst), (and (i1 PredRegs:$src1),
855 (i1 PredRegs:$src2)))]>;
857 let neverHasSideEffects = 1 in
858 def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
860 "$dst = and($src1, !$src2)",
863 def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
864 "$dst = any8($src1)",
867 def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
868 "$dst = all8($src1)",
871 def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
873 "$dst = vitpack($src1, $src2)",
876 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
879 "$dst = valignb($src1, $src2, $src3)",
882 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
885 "$dst = vspliceb($src1, $src2, $src3)",
888 def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
889 "$dst = mask($src1)",
892 def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
894 [(set (i1 PredRegs:$dst), (not (i1 PredRegs:$src1)))]>;
896 def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
897 "$dst = or($src1, $src2)",
898 [(set (i1 PredRegs:$dst), (or (i1 PredRegs:$src1),
899 (i1 PredRegs:$src2)))]>;
901 def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
902 "$dst = xor($src1, $src2)",
903 [(set (i1 PredRegs:$dst), (xor (i1 PredRegs:$src1),
904 (i1 PredRegs:$src2)))]>;
907 // User control register transfer.
908 //===----------------------------------------------------------------------===//
910 //===----------------------------------------------------------------------===//
912 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
913 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
914 def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone,
917 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
918 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
920 let InputType = "imm", isBarrier = 1, isPredicable = 1,
921 Defs = [PC], isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
922 opExtentBits = 24, isCodeGenOnly = 0 in
923 class T_JMP <dag InsDag, list<dag> JumpList = []>
924 : JInst<(outs), InsDag,
925 "jump $dst" , JumpList> {
930 let Inst{27-25} = 0b100;
931 let Inst{24-16} = dst{23-15};
932 let Inst{13-1} = dst{14-2};
935 let InputType = "imm", isExtendable = 1, opExtendable = 1, isExtentSigned = 1,
936 Defs = [PC], isPredicated = 1, opExtentBits = 17 in
937 class T_JMP_c <bit PredNot, bit isPredNew, bit isTak>:
938 JInst<(outs ), (ins PredRegs:$src, brtarget:$dst),
939 !if(PredNot, "if (!$src", "if ($src")#
940 !if(isPredNew, ".new) ", ") ")#"jump"#
941 !if(isPredNew, !if(isTak, ":t ", ":nt "), " ")#"$dst"> {
944 let isBrTaken = !if(isPredNew, !if(isTaken, "true", "false"), "");
945 let isPredicatedFalse = PredNot;
946 let isPredicatedNew = isPredNew;
952 let Inst{27-24} = 0b1100;
953 let Inst{21} = PredNot;
954 let Inst{12} = !if(isPredNew, isTak, zero);
955 let Inst{11} = isPredNew;
957 let Inst{23-22} = dst{16-15};
958 let Inst{20-16} = dst{14-10};
959 let Inst{13} = dst{9};
960 let Inst{7-1} = dst{8-2};
963 let isBarrier = 1, Defs = [PC], isPredicable = 1, InputType = "reg" in
964 class T_JMPr<dag InsDag = (ins IntRegs:$dst)>
965 : JRInst<(outs ), InsDag,
971 let Inst{27-21} = 0b0010100;
972 let Inst{20-16} = dst;
975 let Defs = [PC], isPredicated = 1, InputType = "reg" in
976 class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>:
977 JRInst <(outs ), (ins PredRegs:$src, IntRegs:$dst),
978 !if(PredNot, "if (!$src", "if ($src")#
979 !if(isPredNew, ".new) ", ") ")#"jumpr"#
980 !if(isPredNew, !if(isTak, ":t ", ":nt "), " ")#"$dst"> {
983 let isBrTaken = !if(isPredNew, !if(isTaken, "true", "false"), "");
984 let isPredicatedFalse = PredNot;
985 let isPredicatedNew = isPredNew;
991 let Inst{27-22} = 0b001101;
992 let Inst{21} = PredNot;
993 let Inst{20-16} = dst;
994 let Inst{12} = !if(isPredNew, isTak, zero);
995 let Inst{11} = isPredNew;
997 let Predicates = !if(isPredNew, [HasV3T], [HasV2T]);
998 let validSubTargets = !if(isPredNew, HasV3SubT, HasV2SubT);
1001 multiclass JMP_Pred<bit PredNot> {
1002 def _#NAME : T_JMP_c<PredNot, 0, 0>;
1004 def _#NAME#new_t : T_JMP_c<PredNot, 1, 1>; // taken
1005 def _#NAME#new_nt : T_JMP_c<PredNot, 1, 0>; // not taken
1008 multiclass JMP_base<string BaseOp> {
1009 let BaseOpcode = BaseOp in {
1010 def NAME : T_JMP<(ins brtarget:$dst), [(br bb:$dst)]>;
1011 defm t : JMP_Pred<0>;
1012 defm f : JMP_Pred<1>;
1016 multiclass JMPR_Pred<bit PredNot> {
1017 def NAME: T_JMPr_c<PredNot, 0, 0>;
1019 def NAME#new_tV3 : T_JMPr_c<PredNot, 1, 1>; // taken
1020 def NAME#new_ntV3 : T_JMPr_c<PredNot, 1, 0>; // not taken
1023 multiclass JMPR_base<string BaseOp> {
1024 let BaseOpcode = BaseOp in {
1026 defm _t : JMPR_Pred<0>;
1027 defm _f : JMPR_Pred<1>;
1031 let isTerminator = 1, neverHasSideEffects = 1 in {
1033 defm JMP : JMP_base<"JMP">, PredNewRel;
1035 let isBranch = 1, isIndirectBranch = 1 in
1036 defm JMPR : JMPR_base<"JMPr">, PredNewRel;
1038 let isReturn = 1, isCodeGenOnly = 1 in
1039 defm JMPret : JMPR_base<"JMPret">, PredNewRel;
1042 def : Pat<(retflag),
1043 (JMPret (i32 R31))>;
1045 def : Pat <(brcond (i1 PredRegs:$src1), bb:$offset),
1046 (JMP_t (i1 PredRegs:$src1), bb:$offset)>;
1048 // A return through builtin_eh_return.
1049 let isReturn = 1, isTerminator = 1, isBarrier = 1, neverHasSideEffects = 1,
1050 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
1051 def EH_RETURN_JMPR : T_JMPr;
1053 def : Pat<(eh_return),
1054 (EH_RETURN_JMPR (i32 R31))>;
1056 def : Pat<(HexagonBR_JT (i32 IntRegs:$dst)),
1057 (JMPR (i32 IntRegs:$dst))>;
1059 def : Pat<(brind (i32 IntRegs:$dst)),
1060 (JMPR (i32 IntRegs:$dst))>;
1062 //===----------------------------------------------------------------------===//
1064 //===----------------------------------------------------------------------===//
1066 //===----------------------------------------------------------------------===//
1068 //===----------------------------------------------------------------------===//
1070 // Load -- MEMri operand
1071 multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
1072 bit isNot, bit isPredNew> {
1073 let isPredicatedNew = isPredNew in
1074 def NAME : LDInst2<(outs RC:$dst),
1075 (ins PredRegs:$src1, MEMri:$addr),
1076 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1077 ") ")#"$dst = "#mnemonic#"($addr)",
1081 multiclass LD_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1082 let isPredicatedFalse = PredNot in {
1083 defm _c#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
1085 defm _cdn#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
1089 let isExtendable = 1, neverHasSideEffects = 1 in
1090 multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
1091 bits<5> ImmBits, bits<5> PredImmBits> {
1093 let CextOpcode = CextOp, BaseOpcode = CextOp in {
1094 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
1096 def NAME : LDInst2<(outs RC:$dst), (ins MEMri:$addr),
1097 "$dst = "#mnemonic#"($addr)",
1100 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
1101 isPredicated = 1 in {
1102 defm Pt : LD_MEMri_Pred<mnemonic, RC, 0 >;
1103 defm NotPt : LD_MEMri_Pred<mnemonic, RC, 1 >;
1108 let addrMode = BaseImmOffset, isMEMri = "true" in {
1109 let accessSize = ByteAccess in {
1110 defm LDrib: LD_MEMri < "memb", "LDrib", IntRegs, 11, 6>, AddrModeRel;
1111 defm LDriub: LD_MEMri < "memub" , "LDriub", IntRegs, 11, 6>, AddrModeRel;
1114 let accessSize = HalfWordAccess in {
1115 defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
1116 defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel;
1119 let accessSize = WordAccess in
1120 defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;
1122 let accessSize = DoubleWordAccess in
1123 defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;
1126 def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
1127 (LDrib ADDRriS11_0:$addr) >;
1129 def : Pat < (i32 (zextloadi8 ADDRriS11_0:$addr)),
1130 (LDriub ADDRriS11_0:$addr) >;
1132 def : Pat < (i32 (sextloadi16 ADDRriS11_1:$addr)),
1133 (LDrih ADDRriS11_1:$addr) >;
1135 def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)),
1136 (LDriuh ADDRriS11_1:$addr) >;
1138 def : Pat < (i32 (load ADDRriS11_2:$addr)),
1139 (LDriw ADDRriS11_2:$addr) >;
1141 def : Pat < (i64 (load ADDRriS11_3:$addr)),
1142 (LDrid ADDRriS11_3:$addr) >;
1145 // Load - Base with Immediate offset addressing mode
1146 multiclass LD_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
1147 bit isNot, bit isPredNew> {
1148 let isPredicatedNew = isPredNew in
1149 def NAME : LDInst2<(outs RC:$dst),
1150 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
1151 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1152 ") ")#"$dst = "#mnemonic#"($src2+#$src3)",
1156 multiclass LD_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
1158 let isPredicatedFalse = PredNot in {
1159 defm _c#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
1161 defm _cdn#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
1165 let isExtendable = 1, neverHasSideEffects = 1 in
1166 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1167 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
1168 bits<5> PredImmBits> {
1170 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1171 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
1172 isPredicable = 1, AddedComplexity = 20 in
1173 def NAME : LDInst2<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1174 "$dst = "#mnemonic#"($src1+#$offset)",
1177 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
1178 isPredicated = 1 in {
1179 defm Pt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 0 >;
1180 defm NotPt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 1 >;
1185 let addrMode = BaseImmOffset in {
1186 let accessSize = ByteAccess in {
1187 defm LDrib_indexed: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext,
1188 11, 6>, AddrModeRel;
1189 defm LDriub_indexed: LD_Idxd <"memub" , "LDriub", IntRegs, s11_0Ext, u6_0Ext,
1190 11, 6>, AddrModeRel;
1192 let accessSize = HalfWordAccess in {
1193 defm LDrih_indexed: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
1194 12, 7>, AddrModeRel;
1195 defm LDriuh_indexed: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext,
1196 12, 7>, AddrModeRel;
1198 let accessSize = WordAccess in
1199 defm LDriw_indexed: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
1200 13, 8>, AddrModeRel;
1202 let accessSize = DoubleWordAccess in
1203 defm LDrid_indexed: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,
1204 14, 9>, AddrModeRel;
1207 let AddedComplexity = 20 in {
1208 def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
1209 (LDrib_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
1211 def : Pat < (i32 (zextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
1212 (LDriub_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
1214 def : Pat < (i32 (sextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
1215 (LDrih_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
1217 def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
1218 (LDriuh_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
1220 def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
1221 (LDriw_indexed IntRegs:$src1, s11_2ExtPred:$offset) >;
1223 def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
1224 (LDrid_indexed IntRegs:$src1, s11_3ExtPred:$offset) >;
1227 //===----------------------------------------------------------------------===//
1228 // Post increment load
1229 //===----------------------------------------------------------------------===//
1231 multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1232 bit isNot, bit isPredNew> {
1233 let isPredicatedNew = isPredNew in
1234 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1235 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1236 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1237 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1242 multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,
1243 Operand ImmOp, bit PredNot> {
1244 let isPredicatedFalse = PredNot in {
1245 defm _c#NAME : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1247 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1248 defm _cdn#NAME#_V4 : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1252 multiclass LD_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1255 let BaseOpcode = "POST_"#BaseOp in {
1256 let isPredicable = 1 in
1257 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1258 (ins IntRegs:$src1, ImmOp:$offset),
1259 "$dst = "#mnemonic#"($src1++#$offset)",
1263 let isPredicated = 1 in {
1264 defm Pt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1265 defm NotPt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1270 let hasCtrlDep = 1, neverHasSideEffects = 1, addrMode = PostInc in {
1271 defm POST_LDrib : LD_PostInc<"memb", "LDrib", IntRegs, s4_0Imm>,
1273 defm POST_LDriub : LD_PostInc<"memub", "LDriub", IntRegs, s4_0Imm>,
1275 defm POST_LDrih : LD_PostInc<"memh", "LDrih", IntRegs, s4_1Imm>,
1277 defm POST_LDriuh : LD_PostInc<"memuh", "LDriuh", IntRegs, s4_1Imm>,
1279 defm POST_LDriw : LD_PostInc<"memw", "LDriw", IntRegs, s4_2Imm>,
1281 defm POST_LDrid : LD_PostInc<"memd", "LDrid", DoubleRegs, s4_3Imm>,
1285 def : Pat< (i32 (extloadi1 ADDRriS11_0:$addr)),
1286 (i32 (LDrib ADDRriS11_0:$addr)) >;
1288 // Load byte any-extend.
1289 def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
1290 (i32 (LDrib ADDRriS11_0:$addr)) >;
1292 // Indexed load byte any-extend.
1293 let AddedComplexity = 20 in
1294 def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1295 (i32 (LDrib_indexed IntRegs:$src1, s11_0ImmPred:$offset)) >;
1297 def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
1298 (i32 (LDrih ADDRriS11_1:$addr))>;
1300 let AddedComplexity = 20 in
1301 def : Pat < (i32 (extloadi16 (add IntRegs:$src1, s11_1ImmPred:$offset))),
1302 (i32 (LDrih_indexed IntRegs:$src1, s11_1ImmPred:$offset)) >;
1304 let AddedComplexity = 10 in
1305 def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
1306 (i32 (LDriub ADDRriS11_0:$addr))>;
1308 let AddedComplexity = 20 in
1309 def : Pat < (i32 (zextloadi1 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1310 (i32 (LDriub_indexed IntRegs:$src1, s11_0ImmPred:$offset))>;
1313 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
1314 isPseudo = 1, Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1315 def LDriw_pred : LDInst2<(outs PredRegs:$dst),
1317 "Error; should not emit",
1320 // Deallocate stack frame.
1321 let Defs = [R29, R30, R31], Uses = [R29], neverHasSideEffects = 1 in {
1322 def DEALLOCFRAME : LDInst2<(outs), (ins),
1327 // Load and unpack bytes to halfwords.
1328 //===----------------------------------------------------------------------===//
1330 //===----------------------------------------------------------------------===//
1332 //===----------------------------------------------------------------------===//
1334 //===----------------------------------------------------------------------===//
1335 //===----------------------------------------------------------------------===//
1337 //===----------------------------------------------------------------------===//
1339 //===----------------------------------------------------------------------===//
1341 //===----------------------------------------------------------------------===//
1342 //===----------------------------------------------------------------------===//
1344 //===----------------------------------------------------------------------===//
1346 //===----------------------------------------------------------------------===//
1348 //===----------------------------------------------------------------------===//
1349 // Multiply and use lower result.
1351 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in
1352 def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Ext:$src2),
1353 "$dst =+ mpyi($src1, #$src2)",
1354 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1355 u8ExtPred:$src2))]>;
1358 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1359 "$dst =- mpyi($src1, #$src2)",
1360 [(set (i32 IntRegs:$dst), (ineg (mul (i32 IntRegs:$src1),
1361 u8ImmPred:$src2)))]>;
1364 // s9 is NOT the same as m9 - but it works.. so far.
1365 // Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
1366 // depending on the value of m9. See Arch Spec.
1367 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
1368 CextOpcode = "MPYI", InputType = "imm" in
1369 def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
1370 "$dst = mpyi($src1, #$src2)",
1371 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1372 s9ExtPred:$src2))]>, ImmRegRel;
1375 let CextOpcode = "MPYI", InputType = "reg" in
1376 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1377 "$dst = mpyi($src1, $src2)",
1378 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1379 (i32 IntRegs:$src2)))]>, ImmRegRel;
1382 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8,
1383 CextOpcode = "MPYI_acc", InputType = "imm" in
1384 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
1385 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1386 "$dst += mpyi($src2, #$src3)",
1387 [(set (i32 IntRegs:$dst),
1388 (add (mul (i32 IntRegs:$src2), u8ExtPred:$src3),
1389 (i32 IntRegs:$src1)))],
1390 "$src1 = $dst">, ImmRegRel;
1393 let CextOpcode = "MPYI_acc", InputType = "reg" in
1394 def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
1395 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1396 "$dst += mpyi($src2, $src3)",
1397 [(set (i32 IntRegs:$dst),
1398 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1399 (i32 IntRegs:$src1)))],
1400 "$src1 = $dst">, ImmRegRel;
1403 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8 in
1404 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
1405 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1406 "$dst -= mpyi($src2, #$src3)",
1407 [(set (i32 IntRegs:$dst),
1408 (sub (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1409 u8ExtPred:$src3)))],
1412 // Multiply and use upper result.
1413 // Rd=mpy(Rs,Rt.H):<<1:rnd:sat
1414 // Rd=mpy(Rs,Rt.L):<<1:rnd:sat
1416 def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1417 "$dst = mpy($src1, $src2)",
1418 [(set (i32 IntRegs:$dst), (mulhs (i32 IntRegs:$src1),
1419 (i32 IntRegs:$src2)))]>;
1421 // Rd=mpy(Rs,Rt):rnd
1423 def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1424 "$dst = mpyu($src1, $src2)",
1425 [(set (i32 IntRegs:$dst), (mulhu (i32 IntRegs:$src1),
1426 (i32 IntRegs:$src2)))]>;
1428 // Multiply and use full result.
1430 def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1431 "$dst = mpyu($src1, $src2)",
1432 [(set (i64 DoubleRegs:$dst),
1433 (mul (i64 (anyext (i32 IntRegs:$src1))),
1434 (i64 (anyext (i32 IntRegs:$src2)))))]>;
1437 def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1438 "$dst = mpy($src1, $src2)",
1439 [(set (i64 DoubleRegs:$dst),
1440 (mul (i64 (sext (i32 IntRegs:$src1))),
1441 (i64 (sext (i32 IntRegs:$src2)))))]>;
1443 // Multiply and accumulate, use full result.
1444 // Rxx[+-]=mpy(Rs,Rt)
1446 def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
1447 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1448 "$dst += mpy($src2, $src3)",
1449 [(set (i64 DoubleRegs:$dst),
1450 (add (mul (i64 (sext (i32 IntRegs:$src2))),
1451 (i64 (sext (i32 IntRegs:$src3)))),
1452 (i64 DoubleRegs:$src1)))],
1456 def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
1457 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1458 "$dst -= mpy($src2, $src3)",
1459 [(set (i64 DoubleRegs:$dst),
1460 (sub (i64 DoubleRegs:$src1),
1461 (mul (i64 (sext (i32 IntRegs:$src2))),
1462 (i64 (sext (i32 IntRegs:$src3))))))],
1465 // Rxx[+-]=mpyu(Rs,Rt)
1467 def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1468 IntRegs:$src2, IntRegs:$src3),
1469 "$dst += mpyu($src2, $src3)",
1470 [(set (i64 DoubleRegs:$dst),
1471 (add (mul (i64 (anyext (i32 IntRegs:$src2))),
1472 (i64 (anyext (i32 IntRegs:$src3)))),
1473 (i64 DoubleRegs:$src1)))], "$src1 = $dst">;
1476 def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
1477 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1478 "$dst -= mpyu($src2, $src3)",
1479 [(set (i64 DoubleRegs:$dst),
1480 (sub (i64 DoubleRegs:$src1),
1481 (mul (i64 (anyext (i32 IntRegs:$src2))),
1482 (i64 (anyext (i32 IntRegs:$src3))))))],
1486 let InputType = "reg", CextOpcode = "ADD_acc" in
1487 def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1488 IntRegs:$src2, IntRegs:$src3),
1489 "$dst += add($src2, $src3)",
1490 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1491 (i32 IntRegs:$src3)),
1492 (i32 IntRegs:$src1)))],
1493 "$src1 = $dst">, ImmRegRel;
1495 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
1496 InputType = "imm", CextOpcode = "ADD_acc" in
1497 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1498 IntRegs:$src2, s8Ext:$src3),
1499 "$dst += add($src2, #$src3)",
1500 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1501 s8_16ExtPred:$src3),
1502 (i32 IntRegs:$src1)))],
1503 "$src1 = $dst">, ImmRegRel;
1505 let CextOpcode = "SUB_acc", InputType = "reg" in
1506 def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1507 IntRegs:$src2, IntRegs:$src3),
1508 "$dst -= add($src2, $src3)",
1509 [(set (i32 IntRegs:$dst),
1510 (sub (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1511 (i32 IntRegs:$src3))))],
1512 "$src1 = $dst">, ImmRegRel;
1514 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
1515 CextOpcode = "SUB_acc", InputType = "imm" in
1516 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1517 IntRegs:$src2, s8Ext:$src3),
1518 "$dst -= add($src2, #$src3)",
1519 [(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
1520 (add (i32 IntRegs:$src2),
1521 s8_16ExtPred:$src3)))],
1522 "$src1 = $dst">, ImmRegRel;
1524 //===----------------------------------------------------------------------===//
1526 //===----------------------------------------------------------------------===//
1528 //===----------------------------------------------------------------------===//
1530 //===----------------------------------------------------------------------===//
1531 //===----------------------------------------------------------------------===//
1533 //===----------------------------------------------------------------------===//
1535 //===----------------------------------------------------------------------===//
1537 //===----------------------------------------------------------------------===//
1538 //===----------------------------------------------------------------------===//
1540 //===----------------------------------------------------------------------===//
1542 //===----------------------------------------------------------------------===//
1544 //===----------------------------------------------------------------------===//
1545 //===----------------------------------------------------------------------===//
1547 //===----------------------------------------------------------------------===//
1549 //===----------------------------------------------------------------------===//
1551 //===----------------------------------------------------------------------===//
1553 // Store doubleword.
1555 //===----------------------------------------------------------------------===//
1556 // Post increment store
1557 //===----------------------------------------------------------------------===//
1559 multiclass ST_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1560 bit isNot, bit isPredNew> {
1561 let isPredicatedNew = isPredNew in
1562 def NAME : STInst2PI<(outs IntRegs:$dst),
1563 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
1564 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1565 ") ")#mnemonic#"($src2++#$offset) = $src3",
1570 multiclass ST_PostInc_Pred<string mnemonic, RegisterClass RC,
1571 Operand ImmOp, bit PredNot> {
1572 let isPredicatedFalse = PredNot in {
1573 defm _c#NAME : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1575 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1576 defm _cdn#NAME#_V4 : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1580 let hasCtrlDep = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1581 multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1584 let hasCtrlDep = 1, BaseOpcode = "POST_"#BaseOp in {
1585 let isPredicable = 1 in
1586 def NAME : STInst2PI<(outs IntRegs:$dst),
1587 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
1588 mnemonic#"($src1++#$offset) = $src2",
1592 let isPredicated = 1 in {
1593 defm Pt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1594 defm NotPt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1599 defm POST_STbri: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel;
1600 defm POST_SThri: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
1601 defm POST_STwri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
1603 let isNVStorable = 0 in
1604 defm POST_STdri: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm>, AddrModeRel;
1606 def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2,
1607 s4_3ImmPred:$offset),
1608 (POST_STbri IntRegs:$src2, s4_0ImmPred:$offset, IntRegs:$src1)>;
1610 def : Pat<(post_truncsti16 (i32 IntRegs:$src1), IntRegs:$src2,
1611 s4_3ImmPred:$offset),
1612 (POST_SThri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
1614 def : Pat<(post_store (i32 IntRegs:$src1), IntRegs:$src2, s4_2ImmPred:$offset),
1615 (POST_STwri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
1617 def : Pat<(post_store (i64 DoubleRegs:$src1), IntRegs:$src2,
1618 s4_3ImmPred:$offset),
1619 (POST_STdri IntRegs:$src2, s4_3ImmPred:$offset, DoubleRegs:$src1)>;
1621 //===----------------------------------------------------------------------===//
1622 // multiclass for the store instructions with MEMri operand.
1623 //===----------------------------------------------------------------------===//
1624 multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot,
1626 let isPredicatedNew = isPredNew in
1627 def NAME : STInst2<(outs),
1628 (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
1629 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1630 ") ")#mnemonic#"($addr) = $src2",
1634 multiclass ST_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1635 let isPredicatedFalse = PredNot in {
1636 defm _c#NAME : ST_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
1639 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1640 defm _cdn#NAME#_V4 : ST_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
1644 let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1645 multiclass ST_MEMri<string mnemonic, string CextOp, RegisterClass RC,
1646 bits<5> ImmBits, bits<5> PredImmBits> {
1648 let CextOpcode = CextOp, BaseOpcode = CextOp in {
1649 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1651 def NAME : STInst2<(outs),
1652 (ins MEMri:$addr, RC:$src),
1653 mnemonic#"($addr) = $src",
1656 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
1657 isPredicated = 1 in {
1658 defm Pt : ST_MEMri_Pred<mnemonic, RC, 0>;
1659 defm NotPt : ST_MEMri_Pred<mnemonic, RC, 1>;
1664 let addrMode = BaseImmOffset, isMEMri = "true" in {
1665 let accessSize = ByteAccess in
1666 defm STrib: ST_MEMri < "memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
1668 let accessSize = HalfWordAccess in
1669 defm STrih: ST_MEMri < "memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
1671 let accessSize = WordAccess in
1672 defm STriw: ST_MEMri < "memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
1674 let accessSize = DoubleWordAccess, isNVStorable = 0 in
1675 defm STrid: ST_MEMri < "memd", "STrid", DoubleRegs, 14, 9>, AddrModeRel;
1678 def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
1679 (STrib ADDRriS11_0:$addr, (i32 IntRegs:$src1))>;
1681 def : Pat<(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr),
1682 (STrih ADDRriS11_1:$addr, (i32 IntRegs:$src1))>;
1684 def : Pat<(store (i32 IntRegs:$src1), ADDRriS11_2:$addr),
1685 (STriw ADDRriS11_2:$addr, (i32 IntRegs:$src1))>;
1687 def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
1688 (STrid ADDRriS11_3:$addr, (i64 DoubleRegs:$src1))>;
1691 //===----------------------------------------------------------------------===//
1692 // multiclass for the store instructions with base+immediate offset
1694 //===----------------------------------------------------------------------===//
1695 multiclass ST_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
1696 bit isNot, bit isPredNew> {
1697 let isPredicatedNew = isPredNew in
1698 def NAME : STInst2<(outs),
1699 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
1700 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1701 ") ")#mnemonic#"($src2+#$src3) = $src4",
1705 multiclass ST_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
1707 let isPredicatedFalse = PredNot, isPredicated = 1 in {
1708 defm _c#NAME : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
1711 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1712 defm _cdn#NAME#_V4 : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
1716 let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1717 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1718 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
1719 bits<5> PredImmBits> {
1721 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1722 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1724 def NAME : STInst2<(outs),
1725 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1726 mnemonic#"($src1+#$src2) = $src3",
1729 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits in {
1730 defm Pt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 0>;
1731 defm NotPt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 1>;
1736 let addrMode = BaseImmOffset, InputType = "reg" in {
1737 let accessSize = ByteAccess in
1738 defm STrib_indexed: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext,
1739 u6_0Ext, 11, 6>, AddrModeRel, ImmRegRel;
1741 let accessSize = HalfWordAccess in
1742 defm STrih_indexed: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext,
1743 u6_1Ext, 12, 7>, AddrModeRel, ImmRegRel;
1745 let accessSize = WordAccess in
1746 defm STriw_indexed: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext,
1747 u6_2Ext, 13, 8>, AddrModeRel, ImmRegRel;
1749 let accessSize = DoubleWordAccess, isNVStorable = 0 in
1750 defm STrid_indexed: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
1751 u6_3Ext, 14, 9>, AddrModeRel;
1754 let AddedComplexity = 10 in {
1755 def : Pat<(truncstorei8 (i32 IntRegs:$src1), (add IntRegs:$src2,
1756 s11_0ExtPred:$offset)),
1757 (STrib_indexed IntRegs:$src2, s11_0ImmPred:$offset,
1758 (i32 IntRegs:$src1))>;
1760 def : Pat<(truncstorei16 (i32 IntRegs:$src1), (add IntRegs:$src2,
1761 s11_1ExtPred:$offset)),
1762 (STrih_indexed IntRegs:$src2, s11_1ImmPred:$offset,
1763 (i32 IntRegs:$src1))>;
1765 def : Pat<(store (i32 IntRegs:$src1), (add IntRegs:$src2,
1766 s11_2ExtPred:$offset)),
1767 (STriw_indexed IntRegs:$src2, s11_2ImmPred:$offset,
1768 (i32 IntRegs:$src1))>;
1770 def : Pat<(store (i64 DoubleRegs:$src1), (add IntRegs:$src2,
1771 s11_3ExtPred:$offset)),
1772 (STrid_indexed IntRegs:$src2, s11_3ImmPred:$offset,
1773 (i64 DoubleRegs:$src1))>;
1776 // memh(Rx++#s4:1)=Rt.H
1780 let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1781 def STriw_pred : STInst2<(outs),
1782 (ins MEMri:$addr, PredRegs:$src1),
1783 "Error; should not emit",
1786 // Allocate stack frame.
1787 let Defs = [R29, R30], Uses = [R31, R30], neverHasSideEffects = 1 in {
1788 def ALLOCFRAME : STInst2<(outs),
1790 "allocframe(#$amt)",
1793 //===----------------------------------------------------------------------===//
1795 //===----------------------------------------------------------------------===//
1797 //===----------------------------------------------------------------------===//
1799 //===----------------------------------------------------------------------===//
1801 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
1802 "$dst = not($src1)",
1803 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
1806 // Sign extend word to doubleword.
1807 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
1808 "$dst = sxtw($src1)",
1809 [(set (i64 DoubleRegs:$dst), (sext (i32 IntRegs:$src1)))]>;
1810 //===----------------------------------------------------------------------===//
1812 //===----------------------------------------------------------------------===//
1814 //===----------------------------------------------------------------------===//
1816 //===----------------------------------------------------------------------===//
1818 def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1819 "$dst = clrbit($src1, #$src2)",
1820 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
1822 (shl 1, u5ImmPred:$src2))))]>;
1824 def CLRBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1825 "$dst = clrbit($src1, #$src2)",
1828 // Map from r0 = and(r1, 2147483647) to r0 = clrbit(r1, #31).
1829 def : Pat <(and (i32 IntRegs:$src1), 2147483647),
1830 (CLRBIT_31 (i32 IntRegs:$src1), 31)>;
1833 def SETBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1834 "$dst = setbit($src1, #$src2)",
1835 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
1836 (shl 1, u5ImmPred:$src2)))]>;
1838 // Map from r0 = or(r1, -2147483648) to r0 = setbit(r1, #31).
1839 def SETBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1840 "$dst = setbit($src1, #$src2)",
1843 def : Pat <(or (i32 IntRegs:$src1), -2147483648),
1844 (SETBIT_31 (i32 IntRegs:$src1), 31)>;
1847 def TOGBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1848 "$dst = setbit($src1, #$src2)",
1849 [(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
1850 (shl 1, u5ImmPred:$src2)))]>;
1852 // Map from r0 = xor(r1, -2147483648) to r0 = togglebit(r1, #31).
1853 def TOGBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1854 "$dst = togglebit($src1, #$src2)",
1857 def : Pat <(xor (i32 IntRegs:$src1), -2147483648),
1858 (TOGBIT_31 (i32 IntRegs:$src1), 31)>;
1860 // Predicate transfer.
1861 let neverHasSideEffects = 1 in
1862 def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
1863 "$dst = $src1 /* Should almost never emit this. */",
1866 def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1),
1867 "$dst = $src1 /* Should almost never emit this. */",
1868 [(set (i1 PredRegs:$dst), (trunc (i32 IntRegs:$src1)))]>;
1869 //===----------------------------------------------------------------------===//
1871 //===----------------------------------------------------------------------===//
1873 //===----------------------------------------------------------------------===//
1875 //===----------------------------------------------------------------------===//
1876 // Shift by immediate.
1877 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1878 "$dst = asr($src1, #$src2)",
1879 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1880 u5ImmPred:$src2))]>;
1882 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1883 "$dst = asr($src1, #$src2)",
1884 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1885 u6ImmPred:$src2))]>;
1887 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1888 "$dst = asl($src1, #$src2)",
1889 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1890 u5ImmPred:$src2))]>;
1892 def ASLd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1893 "$dst = asl($src1, #$src2)",
1894 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1895 u6ImmPred:$src2))]>;
1897 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1898 "$dst = lsr($src1, #$src2)",
1899 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1900 u5ImmPred:$src2))]>;
1902 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1903 "$dst = lsr($src1, #$src2)",
1904 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1905 u6ImmPred:$src2))]>;
1907 // Shift by immediate and add.
1908 let AddedComplexity = 100 in
1909 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
1911 "$dst = addasl($src1, $src2, #$src3)",
1912 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
1913 (shl (i32 IntRegs:$src2),
1914 u3ImmPred:$src3)))]>;
1916 // Shift by register.
1917 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1918 "$dst = asl($src1, $src2)",
1919 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1920 (i32 IntRegs:$src2)))]>;
1922 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1923 "$dst = asr($src1, $src2)",
1924 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1925 (i32 IntRegs:$src2)))]>;
1927 def LSL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1928 "$dst = lsl($src1, $src2)",
1929 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1930 (i32 IntRegs:$src2)))]>;
1932 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1933 "$dst = lsr($src1, $src2)",
1934 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1935 (i32 IntRegs:$src2)))]>;
1937 def ASLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1938 "$dst = asl($src1, $src2)",
1939 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1940 (i32 IntRegs:$src2)))]>;
1942 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1943 "$dst = lsl($src1, $src2)",
1944 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1945 (i32 IntRegs:$src2)))]>;
1947 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1949 "$dst = asr($src1, $src2)",
1950 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1951 (i32 IntRegs:$src2)))]>;
1953 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1955 "$dst = lsr($src1, $src2)",
1956 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1957 (i32 IntRegs:$src2)))]>;
1959 //===----------------------------------------------------------------------===//
1961 //===----------------------------------------------------------------------===//
1963 //===----------------------------------------------------------------------===//
1965 //===----------------------------------------------------------------------===//
1966 //===----------------------------------------------------------------------===//
1968 //===----------------------------------------------------------------------===//
1970 //===----------------------------------------------------------------------===//
1972 //===----------------------------------------------------------------------===//
1973 //===----------------------------------------------------------------------===//
1975 //===----------------------------------------------------------------------===//
1977 //===----------------------------------------------------------------------===//
1979 //===----------------------------------------------------------------------===//
1981 //===----------------------------------------------------------------------===//
1983 //===----------------------------------------------------------------------===//
1984 def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
1985 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
1988 let hasSideEffects = 1, isSolo = 1 in
1989 def BARRIER : SYSInst<(outs), (ins),
1991 [(HexagonBARRIER)]>;
1993 //===----------------------------------------------------------------------===//
1995 //===----------------------------------------------------------------------===//
1997 // TFRI64 - assembly mapped.
1998 let isReMaterializable = 1 in
1999 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
2001 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
2003 // Pseudo instruction to encode a set of conditional transfers.
2004 // This instruction is used instead of a mux and trades-off codesize
2005 // for performance. We conduct this transformation optimistically in
2006 // the hope that these instructions get promoted to dot-new transfers.
2007 let AddedComplexity = 100, isPredicated = 1 in
2008 def TFR_condset_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
2011 "Error; should not emit",
2012 [(set (i32 IntRegs:$dst),
2013 (i32 (select (i1 PredRegs:$src1),
2014 (i32 IntRegs:$src2),
2015 (i32 IntRegs:$src3))))]>;
2016 let AddedComplexity = 100, isPredicated = 1 in
2017 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
2018 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
2019 "Error; should not emit",
2020 [(set (i32 IntRegs:$dst),
2021 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
2022 s12ImmPred:$src3)))]>;
2024 let AddedComplexity = 100, isPredicated = 1 in
2025 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
2026 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
2027 "Error; should not emit",
2028 [(set (i32 IntRegs:$dst),
2029 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
2030 (i32 IntRegs:$src3))))]>;
2032 let AddedComplexity = 100, isPredicated = 1 in
2033 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
2034 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
2035 "Error; should not emit",
2036 [(set (i32 IntRegs:$dst),
2037 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
2038 s12ImmPred:$src3)))]>;
2040 // Generate frameindex addresses.
2041 let isReMaterializable = 1 in
2042 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
2043 "$dst = add($src1)",
2044 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
2049 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
2050 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
2051 "loop0($offset, #$src2)",
2055 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
2056 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
2057 "loop0($offset, $src2)",
2061 let isBranch = 1, isTerminator = 1, neverHasSideEffects = 1,
2062 Defs = [PC, LC0], Uses = [SA0, LC0] in {
2063 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
2068 // Support for generating global address.
2069 // Taken from X86InstrInfo.td.
2070 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [
2074 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
2075 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
2077 // HI/LO Instructions
2078 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2079 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
2080 "$dst.l = #LO($global)",
2083 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2084 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
2085 "$dst.h = #HI($global)",
2088 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2089 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2090 "$dst.l = #LO($imm_value)",
2094 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2095 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2096 "$dst.h = #HI($imm_value)",
2099 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2100 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2101 "$dst.l = #LO($jt)",
2104 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2105 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2106 "$dst.h = #HI($jt)",
2110 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2111 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2112 "$dst.l = #LO($label)",
2115 let isReMaterializable = 1, isMoveImm = 1 , neverHasSideEffects = 1 in
2116 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2117 "$dst.h = #HI($label)",
2120 // This pattern is incorrect. When we add small data, we should change
2121 // this pattern to use memw(#foo).
2122 // This is for sdata.
2123 let isMoveImm = 1 in
2124 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2125 "$dst = CONST32(#$global)",
2126 [(set (i32 IntRegs:$dst),
2127 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
2129 // This is for non-sdata.
2130 let isReMaterializable = 1, isMoveImm = 1 in
2131 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2132 "$dst = CONST32(#$global)",
2133 [(set (i32 IntRegs:$dst),
2134 (HexagonCONST32 tglobaladdr:$global))]>;
2136 let isReMaterializable = 1, isMoveImm = 1 in
2137 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2138 "$dst = CONST32(#$jt)",
2139 [(set (i32 IntRegs:$dst),
2140 (HexagonCONST32 tjumptable:$jt))]>;
2142 let isReMaterializable = 1, isMoveImm = 1 in
2143 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2144 "$dst = CONST32(#$global)",
2145 [(set (i32 IntRegs:$dst),
2146 (HexagonCONST32_GP tglobaladdr:$global))]>;
2148 let isReMaterializable = 1, isMoveImm = 1 in
2149 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
2150 "$dst = CONST32(#$global)",
2151 [(set (i32 IntRegs:$dst), imm:$global) ]>;
2153 // Map BlockAddress lowering to CONST32_Int_Real
2154 def : Pat<(HexagonCONST32_GP tblockaddress:$addr),
2155 (CONST32_Int_Real tblockaddress:$addr)>;
2157 let isReMaterializable = 1, isMoveImm = 1 in
2158 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
2159 "$dst = CONST32($label)",
2160 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
2162 let isReMaterializable = 1, isMoveImm = 1 in
2163 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
2164 "$dst = CONST64(#$global)",
2165 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
2167 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
2168 "$dst = xor($dst, $dst)",
2169 [(set (i1 PredRegs:$dst), 0)]>;
2171 def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2172 "$dst = mpy($src1, $src2)",
2173 [(set (i32 IntRegs:$dst),
2174 (trunc (i64 (srl (i64 (mul (i64 (sext (i32 IntRegs:$src1))),
2175 (i64 (sext (i32 IntRegs:$src2))))),
2178 // Pseudo instructions.
2179 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
2181 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
2182 SDTCisVT<1, i32> ]>;
2184 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
2185 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2187 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
2188 [SDNPHasChain, SDNPOutGlue]>;
2190 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2192 def call : SDNode<"HexagonISD::CALL", SDT_SPCall,
2193 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
2195 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
2196 // Optional Flag and Variable Arguments.
2197 // Its 1 Operand has pointer type.
2198 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
2199 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
2201 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
2202 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
2203 "Should never be emitted",
2204 [(callseq_start timm:$amt)]>;
2207 let Defs = [R29, R30, R31], Uses = [R29] in {
2208 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2209 "Should never be emitted",
2210 [(callseq_end timm:$amt1, timm:$amt2)]>;
2213 let isCall = 1, neverHasSideEffects = 1,
2214 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2215 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2216 def CALL : JInst<(outs), (ins calltarget:$dst),
2220 // Call subroutine from register.
2221 let isCall = 1, neverHasSideEffects = 1,
2222 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2223 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2224 def CALLR : JRInst<(outs), (ins IntRegs:$dst),
2230 // Indirect tail-call.
2231 let isCodeGenOnly = 1, isCall = 1, isReturn = 1 in
2232 def TCRETURNR : T_JMPr;
2234 // Direct tail-calls.
2235 let isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
2236 isTerminator = 1, isCodeGenOnly = 1 in {
2237 def TCRETURNtg : T_JMP<(ins calltarget:$dst)>;
2238 def TCRETURNtext : T_JMP<(ins calltarget:$dst)>;
2241 // Map call instruction.
2242 def : Pat<(call (i32 IntRegs:$dst)),
2243 (CALLR (i32 IntRegs:$dst))>, Requires<[HasV2TOnly]>;
2244 def : Pat<(call tglobaladdr:$dst),
2245 (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
2246 def : Pat<(call texternalsym:$dst),
2247 (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>;
2249 def : Pat<(HexagonTCRet tglobaladdr:$dst),
2250 (TCRETURNtg tglobaladdr:$dst)>;
2251 def : Pat<(HexagonTCRet texternalsym:$dst),
2252 (TCRETURNtext texternalsym:$dst)>;
2253 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
2254 (TCRETURNR (i32 IntRegs:$dst))>;
2256 // Atomic load and store support
2257 // 8 bit atomic load
2258 def : Pat<(atomic_load_8 ADDRriS11_0:$src1),
2259 (i32 (LDriub ADDRriS11_0:$src1))>;
2261 def : Pat<(atomic_load_8 (add (i32 IntRegs:$src1), s11_0ImmPred:$offset)),
2262 (i32 (LDriub_indexed (i32 IntRegs:$src1), s11_0ImmPred:$offset))>;
2264 // 16 bit atomic load
2265 def : Pat<(atomic_load_16 ADDRriS11_1:$src1),
2266 (i32 (LDriuh ADDRriS11_1:$src1))>;
2268 def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)),
2269 (i32 (LDriuh_indexed (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
2271 def : Pat<(atomic_load_32 ADDRriS11_2:$src1),
2272 (i32 (LDriw ADDRriS11_2:$src1))>;
2274 def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),
2275 (i32 (LDriw_indexed (i32 IntRegs:$src1), s11_2ImmPred:$offset))>;
2277 // 64 bit atomic load
2278 def : Pat<(atomic_load_64 ADDRriS11_3:$src1),
2279 (i64 (LDrid ADDRriS11_3:$src1))>;
2281 def : Pat<(atomic_load_64 (add (i32 IntRegs:$src1), s11_3ImmPred:$offset)),
2282 (i64 (LDrid_indexed (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
2285 def : Pat<(atomic_store_8 ADDRriS11_0:$src2, (i32 IntRegs:$src1)),
2286 (STrib ADDRriS11_0:$src2, (i32 IntRegs:$src1))>;
2288 def : Pat<(atomic_store_8 (add (i32 IntRegs:$src2), s11_0ImmPred:$offset),
2289 (i32 IntRegs:$src1)),
2290 (STrib_indexed (i32 IntRegs:$src2), s11_0ImmPred:$offset,
2291 (i32 IntRegs:$src1))>;
2294 def : Pat<(atomic_store_16 ADDRriS11_1:$src2, (i32 IntRegs:$src1)),
2295 (STrih ADDRriS11_1:$src2, (i32 IntRegs:$src1))>;
2297 def : Pat<(atomic_store_16 (i32 IntRegs:$src1),
2298 (add (i32 IntRegs:$src2), s11_1ImmPred:$offset)),
2299 (STrih_indexed (i32 IntRegs:$src2), s11_1ImmPred:$offset,
2300 (i32 IntRegs:$src1))>;
2302 def : Pat<(atomic_store_32 ADDRriS11_2:$src2, (i32 IntRegs:$src1)),
2303 (STriw ADDRriS11_2:$src2, (i32 IntRegs:$src1))>;
2305 def : Pat<(atomic_store_32 (add (i32 IntRegs:$src2), s11_2ImmPred:$offset),
2306 (i32 IntRegs:$src1)),
2307 (STriw_indexed (i32 IntRegs:$src2), s11_2ImmPred:$offset,
2308 (i32 IntRegs:$src1))>;
2313 def : Pat<(atomic_store_64 ADDRriS11_3:$src2, (i64 DoubleRegs:$src1)),
2314 (STrid ADDRriS11_3:$src2, (i64 DoubleRegs:$src1))>;
2316 def : Pat<(atomic_store_64 (add (i32 IntRegs:$src2), s11_3ImmPred:$offset),
2317 (i64 DoubleRegs:$src1)),
2318 (STrid_indexed (i32 IntRegs:$src2), s11_3ImmPred:$offset,
2319 (i64 DoubleRegs:$src1))>;
2321 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
2322 def : Pat <(and (i32 IntRegs:$src1), 65535),
2323 (A2_zxth (i32 IntRegs:$src1))>;
2325 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
2326 def : Pat <(and (i32 IntRegs:$src1), 255),
2327 (A2_zxtb (i32 IntRegs:$src1))>;
2329 // Map Add(p1, true) to p1 = not(p1).
2330 // Add(p1, false) should never be produced,
2331 // if it does, it got to be mapped to NOOP.
2332 def : Pat <(add (i1 PredRegs:$src1), -1),
2333 (NOT_p (i1 PredRegs:$src1))>;
2335 // Map from p0 = setlt(r0, r1) r2 = mux(p0, r3, r4) =>
2336 // p0 = cmp.lt(r0, r1), r0 = mux(p0, r2, r1).
2337 // cmp.lt(r0, r1) -> cmp.gt(r1, r0)
2338 def : Pat <(select (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2339 (i32 IntRegs:$src3),
2340 (i32 IntRegs:$src4)),
2341 (i32 (TFR_condset_rr (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)),
2342 (i32 IntRegs:$src4), (i32 IntRegs:$src3)))>,
2343 Requires<[HasV2TOnly]>;
2345 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
2346 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
2347 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
2350 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
2351 // => r0 = TFR_condset_ri(p0, r1, #i)
2352 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
2353 (i32 IntRegs:$src3)),
2354 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
2355 s12ImmPred:$src2))>;
2357 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
2358 // => r0 = TFR_condset_ir(p0, #i, r1)
2359 def : Pat <(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s12ImmPred:$src3),
2360 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
2361 (i32 IntRegs:$src2)))>;
2363 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
2364 def : Pat <(brcond (not (i1 PredRegs:$src1)), bb:$offset),
2365 (JMP_f (i1 PredRegs:$src1), bb:$offset)>;
2367 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
2368 def : Pat <(and (i1 PredRegs:$src1), (not (i1 PredRegs:$src2))),
2369 (i1 (AND_pnotp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2372 let AddedComplexity = 100 in
2373 def : Pat <(i64 (zextloadi1 (HexagonCONST32 tglobaladdr:$global))),
2374 (i64 (COMBINE_rr (TFRI 0),
2375 (LDriub_indexed (CONST32_set tglobaladdr:$global), 0)))>,
2378 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
2379 let AddedComplexity = 10 in
2380 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
2381 (i32 (A2_and (i32 (LDrib ADDRriS11_0:$addr)), (TFRI 0x1)))>;
2383 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
2384 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
2385 (i64 (SXTW (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
2387 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
2388 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
2389 (i64 (SXTW (i32 (A2_sxth (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2390 subreg_loreg))))))>;
2392 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
2393 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
2394 (i64 (SXTW (i32 (A2_sxtb (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2395 subreg_loreg))))))>;
2397 // We want to prevent emitting pnot's as much as possible.
2398 // Map brcond with an unsupported setcc to a JMP_f.
2399 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2401 (JMP_f (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2404 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
2406 (JMP_f (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
2408 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
2409 (JMP_f (i1 PredRegs:$src1), bb:$offset)>;
2411 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
2412 (JMP_t (i1 PredRegs:$src1), bb:$offset)>;
2414 // cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1)
2415 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
2417 (JMP_f (CMPGTri (i32 IntRegs:$src1),
2418 (DEC_CONST_SIGNED s8ImmPred:$src2)), bb:$offset)>;
2420 // cmp.lt(r0, r1) -> cmp.gt(r1, r0)
2421 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2423 (JMP_t (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)), bb:$offset)>;
2425 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2427 (JMP_f (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
2430 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2432 (JMP_f (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2435 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2437 (JMP_f (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2440 // Map from a 64-bit select to an emulated 64-bit mux.
2441 // Hexagon does not support 64-bit MUXes; so emulate with combines.
2442 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
2443 (i64 DoubleRegs:$src3)),
2444 (i64 (COMBINE_rr (i32 (MUX_rr (i1 PredRegs:$src1),
2445 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2447 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2449 (i32 (MUX_rr (i1 PredRegs:$src1),
2450 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2452 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2453 subreg_loreg))))))>;
2455 // Map from a 1-bit select to logical ops.
2456 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
2457 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
2458 (i1 PredRegs:$src3)),
2459 (OR_pp (AND_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
2460 (AND_pp (NOT_p (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
2462 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
2463 def : Pat<(i1 (load ADDRriS11_2:$addr)),
2464 (i1 (TFR_PdRs (i32 (LDrib ADDRriS11_2:$addr))))>;
2466 // Map for truncating from 64 immediates to 32 bit immediates.
2467 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
2468 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
2470 // Map for truncating from i64 immediates to i1 bit immediates.
2471 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
2472 (i1 (TFR_PdRs (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2475 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
2476 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2477 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2480 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
2481 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2482 (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2484 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
2485 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2486 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2489 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
2490 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2491 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2494 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
2495 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2496 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2499 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
2500 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2501 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2503 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
2504 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
2505 (STrib ADDRriS11_2:$addr, (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0)) )>;
2507 // Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs).
2508 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
2509 // Better way to do this?
2510 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
2511 (i64 (SXTW (i32 IntRegs:$src1)))>;
2513 // Map cmple -> cmpgt.
2514 // rs <= rt -> !(rs > rt).
2515 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
2516 (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), s10ExtPred:$src2)))>;
2518 // rs <= rt -> !(rs > rt).
2519 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2520 (i1 (NOT_p (CMPGTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2522 // Rss <= Rtt -> !(Rss > Rtt).
2523 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2524 (i1 (NOT_p (CMPGT64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2526 // Map cmpne -> cmpeq.
2527 // Hexagon_TODO: We should improve on this.
2528 // rs != rt -> !(rs == rt).
2529 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
2530 (i1 (NOT_p(i1 (CMPEQri (i32 IntRegs:$src1), s10ExtPred:$src2))))>;
2532 // Map cmpne(Rs) -> !cmpeqe(Rs).
2533 // rs != rt -> !(rs == rt).
2534 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2535 (i1 (NOT_p (i1 (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
2537 // Convert setne back to xor for hexagon since we compute w/ pred registers.
2538 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
2539 (i1 (XOR_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2541 // Map cmpne(Rss) -> !cmpew(Rss).
2542 // rs != rt -> !(rs == rt).
2543 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2544 (i1 (NOT_p (i1 (CMPEHexagon4rr (i64 DoubleRegs:$src1),
2545 (i64 DoubleRegs:$src2)))))>;
2547 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
2548 // rs >= rt -> !(rt > rs).
2549 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2550 (i1 (NOT_p (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
2552 // cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
2553 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)),
2554 (i1 (CMPGTri (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
2556 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
2557 // rss >= rtt -> !(rtt > rss).
2558 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2559 (i1 (NOT_p (i1 (CMPGT64rr (i64 DoubleRegs:$src2),
2560 (i64 DoubleRegs:$src1)))))>;
2562 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
2563 // !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
2564 // rs < rt -> !(rs >= rt).
2565 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
2566 (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2))))>;
2568 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
2569 // rs < rt -> rt > rs.
2570 // We can let assembler map it, or we can do in the compiler itself.
2571 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2572 (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2574 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
2575 // rss < rtt -> (rtt > rss).
2576 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2577 (i1 (CMPGT64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2579 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
2580 // rs < rt -> rt > rs.
2581 // We can let assembler map it, or we can do in the compiler itself.
2582 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2583 (i1 (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2585 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
2586 // rs < rt -> rt > rs.
2587 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2588 (i1 (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2590 // Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs)
2591 def : Pat <(i1 (setuge (i32 IntRegs:$src1), 0)),
2592 (i1 (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src1)))>;
2594 // Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1)
2595 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ExtPred:$src2)),
2596 (i1 (CMPGTUri (i32 IntRegs:$src1), (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
2598 // Generate cmpgtu(Rs, #u9)
2599 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)),
2600 (i1 (CMPGTUri (i32 IntRegs:$src1), u9ExtPred:$src2))>;
2602 // Map from Rs >= Rt -> !(Rt > Rs).
2603 // rs >= rt -> !(rt > rs).
2604 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2605 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
2607 // Map from Rs >= Rt -> !(Rt > Rs).
2608 // rs >= rt -> !(rt > rs).
2609 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2610 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
2612 // Map from cmpleu(Rs, Rt) -> !cmpgtu(Rs, Rt).
2613 // Map from (Rs <= Rt) -> !(Rs > Rt).
2614 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2615 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2617 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
2618 // Map from (Rs <= Rt) -> !(Rs > Rt).
2619 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2620 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2624 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
2625 (i32 (MUX_ii (i1 PredRegs:$src1), -1, 0))>;
2628 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
2629 (i64 (COMBINE_rr (TFRI -1), (MUX_ii (i1 PredRegs:$src1), -1, 0)))>;
2631 // Convert sign-extended load back to load and sign extend.
2633 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
2634 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2636 // Convert any-extended load back to load and sign extend.
2638 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
2639 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2641 // Convert sign-extended load back to load and sign extend.
2643 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
2644 (i64 (SXTW (LDrih ADDRriS11_1:$src1)))>;
2646 // Convert sign-extended load back to load and sign extend.
2648 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
2649 (i64 (SXTW (LDriw ADDRriS11_2:$src1)))>;
2654 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2655 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2658 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
2659 (i64 (COMBINE_rr (TFRI 0), (MUX_ii (i1 PredRegs:$src1), 1, 0)))>,
2663 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
2664 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>,
2668 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
2669 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>,
2672 let AddedComplexity = 20 in
2673 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
2674 s11_0ExtPred:$offset))),
2675 (i64 (COMBINE_rr (TFRI 0), (LDriub_indexed IntRegs:$src1,
2676 s11_0ExtPred:$offset)))>,
2680 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
2681 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>,
2684 let AddedComplexity = 20 in
2685 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
2686 s11_0ExtPred:$offset))),
2687 (i64 (COMBINE_rr (TFRI 0), (LDriub_indexed IntRegs:$src1,
2688 s11_0ExtPred:$offset)))>,
2692 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
2693 (i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>,
2696 let AddedComplexity = 20 in
2697 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
2698 s11_1ExtPred:$offset))),
2699 (i64 (COMBINE_rr (TFRI 0), (LDriuh_indexed IntRegs:$src1,
2700 s11_1ExtPred:$offset)))>,
2704 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
2705 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>,
2708 let AddedComplexity = 100 in
2709 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
2710 (i64 (COMBINE_rr (TFRI 0), (LDriw_indexed IntRegs:$src1,
2711 s11_2ExtPred:$offset)))>,
2714 let AddedComplexity = 10 in
2715 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
2716 (i32 (LDriw ADDRriS11_0:$src1))>;
2718 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2719 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2720 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2722 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2723 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
2724 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2726 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
2727 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
2728 (i64 (SXTW (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))))>;
2731 let AddedComplexity = 100 in
2732 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2734 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
2735 s11_2ExtPred:$offset2)))))),
2736 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2737 (LDriw_indexed IntRegs:$src2,
2738 s11_2ExtPred:$offset2)))>;
2740 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2742 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
2743 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2744 (LDriw ADDRriS11_2:$srcLow)))>;
2746 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2748 (i64 (zext (i32 IntRegs:$srcLow))))),
2749 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2752 let AddedComplexity = 100 in
2753 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2755 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
2756 s11_2ExtPred:$offset2)))))),
2757 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2758 (LDriw_indexed IntRegs:$src2,
2759 s11_2ExtPred:$offset2)))>;
2761 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2763 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
2764 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2765 (LDriw ADDRriS11_2:$srcLow)))>;
2767 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2769 (i64 (zext (i32 IntRegs:$srcLow))))),
2770 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2773 // Any extended 64-bit load.
2774 // anyext i32 -> i64
2775 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
2776 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>,
2779 // When there is an offset we should prefer the pattern below over the pattern above.
2780 // The complexity of the above is 13 (gleaned from HexagonGenDAGIsel.inc)
2781 // So this complexity below is comfortably higher to allow for choosing the below.
2782 // If this is not done then we generate addresses such as
2783 // ********************************************
2784 // r1 = add (r0, #4)
2785 // r1 = memw(r1 + #0)
2787 // r1 = memw(r0 + #4)
2788 // ********************************************
2789 let AddedComplexity = 100 in
2790 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
2791 (i64 (COMBINE_rr (TFRI 0), (LDriw_indexed IntRegs:$src1,
2792 s11_2ExtPred:$offset)))>,
2795 // anyext i16 -> i64.
2796 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
2797 (i64 (COMBINE_rr (TFRI 0), (LDrih ADDRriS11_2:$src1)))>,
2800 let AddedComplexity = 20 in
2801 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
2802 s11_1ExtPred:$offset))),
2803 (i64 (COMBINE_rr (TFRI 0), (LDrih_indexed IntRegs:$src1,
2804 s11_1ExtPred:$offset)))>,
2807 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
2808 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
2809 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>,
2812 // Multiply 64-bit unsigned and use upper result.
2813 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2828 (COMBINE_rr (TFRI 0),
2834 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2836 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2837 subreg_loreg)))), 32)),
2839 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2840 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2841 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2842 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2843 32)), subreg_loreg)))),
2844 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2845 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2847 // Multiply 64-bit signed and use upper result.
2848 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2852 (COMBINE_rr (TFRI 0),
2862 (COMBINE_rr (TFRI 0),
2868 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2870 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2871 subreg_loreg)))), 32)),
2873 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2874 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2875 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2876 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2877 32)), subreg_loreg)))),
2878 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2879 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2881 // Hexagon specific ISD nodes.
2882 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
2883 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
2884 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
2885 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
2886 SDTHexagonADJDYNALLOC>;
2887 // Needed to tag these instructions for stack layout.
2888 let usesCustomInserter = 1 in
2889 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
2891 "$dst = add($src1, #$src2)",
2892 [(set (i32 IntRegs:$dst),
2893 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
2894 s16ImmPred:$src2))]>;
2896 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
2897 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
2898 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
2900 [(set (i32 IntRegs:$dst),
2901 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
2903 let AddedComplexity = 100 in
2904 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
2905 (COPY (i32 IntRegs:$src1))>;
2907 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
2909 def : Pat<(HexagonWrapperJT tjumptable:$dst),
2910 (i32 (CONST32_set_jt tjumptable:$dst))>;
2914 // Multi-class for logical operators :
2915 // Shift by immediate/register and accumulate/logical
2916 multiclass xtype_imm<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
2917 def _ri : SInst_acc<(outs IntRegs:$dst),
2918 (ins IntRegs:$src1, IntRegs:$src2, u5Imm:$src3),
2919 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
2920 [(set (i32 IntRegs:$dst),
2921 (OpNode2 (i32 IntRegs:$src1),
2922 (OpNode1 (i32 IntRegs:$src2),
2923 u5ImmPred:$src3)))],
2926 def d_ri : SInst_acc<(outs DoubleRegs:$dst),
2927 (ins DoubleRegs:$src1, DoubleRegs:$src2, u6Imm:$src3),
2928 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
2929 [(set (i64 DoubleRegs:$dst), (OpNode2 (i64 DoubleRegs:$src1),
2930 (OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
2934 // Multi-class for logical operators :
2935 // Shift by register and accumulate/logical (32/64 bits)
2936 multiclass xtype_reg<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
2937 def _rr : SInst_acc<(outs IntRegs:$dst),
2938 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2939 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
2940 [(set (i32 IntRegs:$dst),
2941 (OpNode2 (i32 IntRegs:$src1),
2942 (OpNode1 (i32 IntRegs:$src2),
2943 (i32 IntRegs:$src3))))],
2946 def d_rr : SInst_acc<(outs DoubleRegs:$dst),
2947 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2948 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
2949 [(set (i64 DoubleRegs:$dst),
2950 (OpNode2 (i64 DoubleRegs:$src1),
2951 (OpNode1 (i64 DoubleRegs:$src2),
2952 (i32 IntRegs:$src3))))],
2957 multiclass basic_xtype_imm<string OpcStr, SDNode OpNode> {
2958 let AddedComplexity = 100 in
2959 defm _ADD : xtype_imm< !strconcat("+= ", OpcStr), OpNode, add>;
2960 defm _SUB : xtype_imm< !strconcat("-= ", OpcStr), OpNode, sub>;
2961 defm _AND : xtype_imm< !strconcat("&= ", OpcStr), OpNode, and>;
2962 defm _OR : xtype_imm< !strconcat("|= ", OpcStr), OpNode, or>;
2965 multiclass basic_xtype_reg<string OpcStr, SDNode OpNode> {
2966 let AddedComplexity = 100 in
2967 defm _ADD : xtype_reg< !strconcat("+= ", OpcStr), OpNode, add>;
2968 defm _SUB : xtype_reg< !strconcat("-= ", OpcStr), OpNode, sub>;
2969 defm _AND : xtype_reg< !strconcat("&= ", OpcStr), OpNode, and>;
2970 defm _OR : xtype_reg< !strconcat("|= ", OpcStr), OpNode, or>;
2973 multiclass xtype_xor_imm<string OpcStr, SDNode OpNode> {
2974 let AddedComplexity = 100 in
2975 defm _XOR : xtype_imm< !strconcat("^= ", OpcStr), OpNode, xor>;
2978 defm ASL : basic_xtype_imm<"asl", shl>, basic_xtype_reg<"asl", shl>,
2979 xtype_xor_imm<"asl", shl>;
2981 defm LSR : basic_xtype_imm<"lsr", srl>, basic_xtype_reg<"lsr", srl>,
2982 xtype_xor_imm<"lsr", srl>;
2984 defm ASR : basic_xtype_imm<"asr", sra>, basic_xtype_reg<"asr", sra>;
2985 defm LSL : basic_xtype_reg<"lsl", shl>;
2987 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
2988 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
2989 (i32 (MPYI_rin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
2991 //===----------------------------------------------------------------------===//
2992 // V3 Instructions +
2993 //===----------------------------------------------------------------------===//
2995 include "HexagonInstrInfoV3.td"
2997 //===----------------------------------------------------------------------===//
2998 // V3 Instructions -
2999 //===----------------------------------------------------------------------===//
3001 //===----------------------------------------------------------------------===//
3002 // V4 Instructions +
3003 //===----------------------------------------------------------------------===//
3005 include "HexagonInstrInfoV4.td"
3007 //===----------------------------------------------------------------------===//
3008 // V4 Instructions -
3009 //===----------------------------------------------------------------------===//
3011 //===----------------------------------------------------------------------===//
3012 // V5 Instructions +
3013 //===----------------------------------------------------------------------===//
3015 include "HexagonInstrInfoV5.td"
3017 //===----------------------------------------------------------------------===//
3018 // V5 Instructions -
3019 //===----------------------------------------------------------------------===//