1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonImmediates.td"
17 //===----------------------------------------------------------------------===//
18 // Hexagon Instruction Predicate Definitions.
19 //===----------------------------------------------------------------------===//
20 def HasV2T : Predicate<"Subtarget.hasV2TOps()">;
21 def HasV2TOnly : Predicate<"Subtarget.hasV2TOpsOnly()">;
22 def NoV2T : Predicate<"!Subtarget.hasV2TOps()">;
23 def HasV3T : Predicate<"Subtarget.hasV3TOps()">;
24 def HasV3TOnly : Predicate<"Subtarget.hasV3TOpsOnly()">;
25 def NoV3T : Predicate<"!Subtarget.hasV3TOps()">;
26 def HasV4T : Predicate<"Subtarget.hasV4TOps()">;
27 def NoV4T : Predicate<"!Subtarget.hasV4TOps()">;
28 def HasV5T : Predicate<"Subtarget.hasV5TOps()">;
29 def NoV5T : Predicate<"!Subtarget.hasV5TOps()">;
30 def UseMEMOP : Predicate<"Subtarget.useMemOps()">;
31 def IEEERndNearV5T : Predicate<"Subtarget.modeIEEERndNear()">;
34 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
35 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>;
36 def ADDRriS11_0 : ComplexPattern<i32, 2, "SelectADDRriS11_0", [frameindex], []>;
37 def ADDRriS11_1 : ComplexPattern<i32, 2, "SelectADDRriS11_1", [frameindex], []>;
38 def ADDRriS11_2 : ComplexPattern<i32, 2, "SelectADDRriS11_2", [frameindex], []>;
39 def ADDRriS11_3 : ComplexPattern<i32, 2, "SelectADDRriS11_3", [frameindex], []>;
40 def ADDRriU6_0 : ComplexPattern<i32, 2, "SelectADDRriU6_0", [frameindex], []>;
41 def ADDRriU6_1 : ComplexPattern<i32, 2, "SelectADDRriU6_1", [frameindex], []>;
42 def ADDRriU6_2 : ComplexPattern<i32, 2, "SelectADDRriU6_2", [frameindex], []>;
45 def MEMrr : Operand<i32> {
46 let PrintMethod = "printMEMrrOperand";
47 let MIOperandInfo = (ops IntRegs, IntRegs);
51 def MEMri : Operand<i32> {
52 let PrintMethod = "printMEMriOperand";
53 let MIOperandInfo = (ops IntRegs, IntRegs);
56 def MEMri_s11_2 : Operand<i32>,
57 ComplexPattern<i32, 2, "SelectMEMriS11_2", []> {
58 let PrintMethod = "printMEMriOperand";
59 let MIOperandInfo = (ops IntRegs, s11Imm);
62 def FrameIndex : Operand<i32> {
63 let PrintMethod = "printFrameIndexOperand";
64 let MIOperandInfo = (ops IntRegs, s11Imm);
67 let PrintMethod = "printGlobalOperand" in
68 def globaladdress : Operand<i32>;
70 let PrintMethod = "printJumpTable" in
71 def jumptablebase : Operand<i32>;
73 def brtarget : Operand<OtherVT>;
74 def calltarget : Operand<i32>;
76 def bblabel : Operand<i32>;
77 def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf , [], "BasicBlockSDNode">;
79 def symbolHi32 : Operand<i32> {
80 let PrintMethod = "printSymbolHi";
82 def symbolLo32 : Operand<i32> {
83 let PrintMethod = "printSymbolLo";
86 // Multi-class for logical operators.
87 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
88 def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
89 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
90 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),
92 def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
93 !strconcat("$dst = ", !strconcat(OpcStr, "(#$b, $c)")),
94 [(set (i32 IntRegs:$dst), (OpNode s10Imm:$b,
98 // Multi-class for compare ops.
99 let isCompare = 1 in {
100 multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
101 def rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
102 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
103 [(set (i1 PredRegs:$dst),
104 (OpNode (i64 DoubleRegs:$b), (i64 DoubleRegs:$c)))]>;
106 multiclass CMP32_rr<string OpcStr, PatFrag OpNode> {
107 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
108 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
109 [(set (i1 PredRegs:$dst),
110 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
113 multiclass CMP32_rr_ri_s10<string OpcStr, PatFrag OpNode> {
114 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
115 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
116 [(set (i1 PredRegs:$dst),
117 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
118 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Imm:$c),
119 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
120 [(set (i1 PredRegs:$dst),
121 (OpNode (i32 IntRegs:$b), s10ImmPred:$c))]>;
124 multiclass CMP32_rr_ri_u9<string OpcStr, PatFrag OpNode> {
125 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
126 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
127 [(set (i1 PredRegs:$dst),
128 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
129 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Imm:$c),
130 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
131 [(set (i1 PredRegs:$dst),
132 (OpNode (i32 IntRegs:$b), u9ImmPred:$c))]>;
135 multiclass CMP32_ri_u8<string OpcStr, PatFrag OpNode> {
136 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u8Imm:$c),
137 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
138 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
142 multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
143 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Imm:$c),
144 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
145 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
150 //===----------------------------------------------------------------------===//
152 //===----------------------------------------------------------------------===//
154 //===----------------------------------------------------------------------===//
155 // http://qualnet.qualcomm.com/~erich/v1/htmldocs/index.html
156 // http://qualnet.qualcomm.com/~erich/v2/htmldocs/index.html
157 // http://qualnet.qualcomm.com/~erich/v3/htmldocs/index.html
158 // http://qualnet.qualcomm.com/~erich/v4/htmldocs/index.html
159 // http://qualnet.qualcomm.com/~erich/v5/htmldocs/index.html
160 //===----------------------------------------------------------------------===//
162 //===----------------------------------------------------------------------===//
164 //===----------------------------------------------------------------------===//
166 let isCommutable = 1, isPredicable = 1 in
167 def ADD_rr : ALU32_rr<(outs IntRegs:$dst),
168 (ins IntRegs:$src1, IntRegs:$src2),
169 "$dst = add($src1, $src2)",
170 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
171 (i32 IntRegs:$src2)))]>;
173 let isPredicable = 1 in
174 def ADD_ri : ALU32_ri<(outs IntRegs:$dst),
175 (ins IntRegs:$src1, s16Imm:$src2),
176 "$dst = add($src1, #$src2)",
177 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
178 s16ImmPred:$src2))]>;
180 // Logical operations.
181 let isPredicable = 1 in
182 def XOR_rr : ALU32_rr<(outs IntRegs:$dst),
183 (ins IntRegs:$src1, IntRegs:$src2),
184 "$dst = xor($src1, $src2)",
185 [(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
186 (i32 IntRegs:$src2)))]>;
188 let isCommutable = 1, isPredicable = 1 in
189 def AND_rr : ALU32_rr<(outs IntRegs:$dst),
190 (ins IntRegs:$src1, IntRegs:$src2),
191 "$dst = and($src1, $src2)",
192 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
193 (i32 IntRegs:$src2)))]>;
195 def OR_ri : ALU32_ri<(outs IntRegs:$dst),
196 (ins IntRegs:$src1, s10Imm:$src2),
197 "$dst = or($src1, #$src2)",
198 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
199 s10ImmPred:$src2))]>;
201 def NOT_rr : ALU32_rr<(outs IntRegs:$dst),
204 [(set (i32 IntRegs:$dst), (not (i32 IntRegs:$src1)))]>;
206 def AND_ri : ALU32_ri<(outs IntRegs:$dst),
207 (ins IntRegs:$src1, s10Imm:$src2),
208 "$dst = and($src1, #$src2)",
209 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
210 s10ImmPred:$src2))]>;
212 let isCommutable = 1, isPredicable = 1 in
213 def OR_rr : ALU32_rr<(outs IntRegs:$dst),
214 (ins IntRegs:$src1, IntRegs:$src2),
215 "$dst = or($src1, $src2)",
216 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
217 (i32 IntRegs:$src2)))]>;
220 def NEG : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
222 [(set (i32 IntRegs:$dst), (ineg (i32 IntRegs:$src1)))]>;
224 let neverHasSideEffects = 1 in
225 def NOP : ALU32_rr<(outs), (ins),
230 let isPredicable = 1 in
231 def SUB_rr : ALU32_rr<(outs IntRegs:$dst),
232 (ins IntRegs:$src1, IntRegs:$src2),
233 "$dst = sub($src1, $src2)",
234 [(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
235 (i32 IntRegs:$src2)))]>;
237 // Rd32=sub(#s10,Rs32)
238 def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
239 (ins s10Imm:$src1, IntRegs:$src2),
240 "$dst = sub(#$src1, $src2)",
241 [(set IntRegs:$dst, (sub s10ImmPred:$src1, IntRegs:$src2))]>;
243 // Transfer immediate.
244 let isMoveImm = 1, isReMaterializable = 1, isPredicable = 1 in
245 def TFRI : ALU32_ri<(outs IntRegs:$dst), (ins s16Imm:$src1),
247 [(set (i32 IntRegs:$dst), s16ImmPred:$src1)]>;
249 // Transfer register.
250 let neverHasSideEffects = 1, isPredicable = 1 in
251 def TFR : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1),
255 let neverHasSideEffects = 1, isPredicable = 1 in
256 def TFR64 : ALU32_ri<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
261 // Transfer control register.
262 let neverHasSideEffects = 1 in
263 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
266 //===----------------------------------------------------------------------===//
268 //===----------------------------------------------------------------------===//
271 //===----------------------------------------------------------------------===//
273 //===----------------------------------------------------------------------===//
276 let isPredicable = 1, neverHasSideEffects = 1 in
277 def COMBINE_rr : ALU32_rr<(outs DoubleRegs:$dst),
278 (ins IntRegs:$src1, IntRegs:$src2),
279 "$dst = combine($src1, $src2)",
282 let neverHasSideEffects = 1 in
283 def COMBINE_ii : ALU32_ii<(outs DoubleRegs:$dst),
284 (ins s8Imm:$src1, s8Imm:$src2),
285 "$dst = combine(#$src1, #$src2)",
289 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
292 "$dst = vmux($src1, $src2, $src3)",
295 def MUX_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
296 IntRegs:$src2, IntRegs:$src3),
297 "$dst = mux($src1, $src2, $src3)",
298 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
300 (i32 IntRegs:$src3))))]>;
302 def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Imm:$src2,
304 "$dst = mux($src1, #$src2, $src3)",
305 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
307 (i32 IntRegs:$src3))))]>;
309 def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
311 "$dst = mux($src1, $src2, #$src3)",
312 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
314 s8ImmPred:$src3)))]>;
316 def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Imm:$src2,
318 "$dst = mux($src1, #$src2, #$src3)",
319 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
321 s8ImmPred:$src3)))]>;
324 let isPredicable = 1 in
325 def ASLH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
326 "$dst = aslh($src1)",
327 [(set (i32 IntRegs:$dst), (shl 16, (i32 IntRegs:$src1)))]>;
329 let isPredicable = 1 in
330 def ASRH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
331 "$dst = asrh($src1)",
332 [(set (i32 IntRegs:$dst), (sra 16, (i32 IntRegs:$src1)))]>;
335 let isPredicable = 1 in
336 def SXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
337 "$dst = sxtb($src1)",
338 [(set (i32 IntRegs:$dst), (sext_inreg (i32 IntRegs:$src1), i8))]>;
340 let isPredicable = 1 in
341 def SXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
342 "$dst = sxth($src1)",
343 [(set (i32 IntRegs:$dst), (sext_inreg (i32 IntRegs:$src1), i16))]>;
346 let isPredicable = 1, neverHasSideEffects = 1 in
347 def ZXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
348 "$dst = zxtb($src1)",
351 let isPredicable = 1, neverHasSideEffects = 1 in
352 def ZXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
353 "$dst = zxth($src1)",
355 //===----------------------------------------------------------------------===//
357 //===----------------------------------------------------------------------===//
360 //===----------------------------------------------------------------------===//
362 //===----------------------------------------------------------------------===//
365 let neverHasSideEffects = 1, isPredicated = 1 in
366 def ADD_ri_cPt : ALU32_ri<(outs IntRegs:$dst),
367 (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
368 "if ($src1) $dst = add($src2, #$src3)",
371 let neverHasSideEffects = 1, isPredicated = 1 in
372 def ADD_ri_cNotPt : ALU32_ri<(outs IntRegs:$dst),
373 (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
374 "if (!$src1) $dst = add($src2, #$src3)",
377 let neverHasSideEffects = 1, isPredicated = 1 in
378 def ADD_ri_cdnPt : ALU32_ri<(outs IntRegs:$dst),
379 (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
380 "if ($src1.new) $dst = add($src2, #$src3)",
383 let neverHasSideEffects = 1, isPredicated = 1 in
384 def ADD_ri_cdnNotPt : ALU32_ri<(outs IntRegs:$dst),
385 (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
386 "if (!$src1.new) $dst = add($src2, #$src3)",
389 let neverHasSideEffects = 1, isPredicated = 1 in
390 def ADD_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
391 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
392 "if ($src1) $dst = add($src2, $src3)",
395 let neverHasSideEffects = 1, isPredicated = 1 in
396 def ADD_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
397 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
398 "if (!$src1) $dst = add($src2, $src3)",
401 let neverHasSideEffects = 1, isPredicated = 1 in
402 def ADD_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
403 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
404 "if ($src1.new) $dst = add($src2, $src3)",
407 let neverHasSideEffects = 1, isPredicated = 1 in
408 def ADD_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
409 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
410 "if (!$src1.new) $dst = add($src2, $src3)",
414 // Conditional combine.
416 let neverHasSideEffects = 1, isPredicated = 1 in
417 def COMBINE_rr_cPt : ALU32_rr<(outs DoubleRegs:$dst),
418 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
419 "if ($src1) $dst = combine($src2, $src3)",
422 let neverHasSideEffects = 1, isPredicated = 1 in
423 def COMBINE_rr_cNotPt : ALU32_rr<(outs DoubleRegs:$dst),
424 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
425 "if (!$src1) $dst = combine($src2, $src3)",
428 let neverHasSideEffects = 1, isPredicated = 1 in
429 def COMBINE_rr_cdnPt : ALU32_rr<(outs DoubleRegs:$dst),
430 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
431 "if ($src1.new) $dst = combine($src2, $src3)",
434 let neverHasSideEffects = 1, isPredicated = 1 in
435 def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst),
436 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
437 "if (!$src1.new) $dst = combine($src2, $src3)",
440 // Conditional logical operations.
442 let isPredicated = 1 in
443 def XOR_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
444 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
445 "if ($src1) $dst = xor($src2, $src3)",
448 let isPredicated = 1 in
449 def XOR_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
450 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
451 "if (!$src1) $dst = xor($src2, $src3)",
454 let isPredicated = 1 in
455 def XOR_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
456 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
457 "if ($src1.new) $dst = xor($src2, $src3)",
460 let isPredicated = 1 in
461 def XOR_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
462 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
463 "if (!$src1.new) $dst = xor($src2, $src3)",
466 let isPredicated = 1 in
467 def AND_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
468 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
469 "if ($src1) $dst = and($src2, $src3)",
472 let isPredicated = 1 in
473 def AND_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
474 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
475 "if (!$src1) $dst = and($src2, $src3)",
478 let isPredicated = 1 in
479 def AND_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
480 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
481 "if ($src1.new) $dst = and($src2, $src3)",
484 let isPredicated = 1 in
485 def AND_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
486 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
487 "if (!$src1.new) $dst = and($src2, $src3)",
490 let isPredicated = 1 in
491 def OR_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
492 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
493 "if ($src1) $dst = or($src2, $src3)",
496 let isPredicated = 1 in
497 def OR_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
498 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
499 "if (!$src1) $dst = or($src2, $src3)",
502 let isPredicated = 1 in
503 def OR_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
504 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
505 "if ($src1.new) $dst = or($src2, $src3)",
508 let isPredicated = 1 in
509 def OR_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
510 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
511 "if (!$src1.new) $dst = or($src2, $src3)",
515 // Conditional subtract.
517 let isPredicated = 1 in
518 def SUB_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
519 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
520 "if ($src1) $dst = sub($src2, $src3)",
523 let isPredicated = 1 in
524 def SUB_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
525 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
526 "if (!$src1) $dst = sub($src2, $src3)",
529 let isPredicated = 1 in
530 def SUB_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
531 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
532 "if ($src1.new) $dst = sub($src2, $src3)",
535 let isPredicated = 1 in
536 def SUB_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
537 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
538 "if (!$src1.new) $dst = sub($src2, $src3)",
542 // Conditional transfer.
543 let neverHasSideEffects = 1, isPredicated = 1 in
544 def TFR_cPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2),
545 "if ($src1) $dst = $src2",
548 let neverHasSideEffects = 1, isPredicated = 1 in
549 def TFR_cNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
551 "if (!$src1) $dst = $src2",
555 let neverHasSideEffects = 1, isPredicated = 1 in
556 def TFR64_cPt : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
558 "if ($src1) $dst = $src2",
561 let neverHasSideEffects = 1, isPredicated = 1 in
562 def TFR64_cNotPt : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
564 "if (!$src1) $dst = $src2",
567 let neverHasSideEffects = 1, isPredicated = 1 in
568 def TFRI_cPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, s12Imm:$src2),
569 "if ($src1) $dst = #$src2",
572 let neverHasSideEffects = 1, isPredicated = 1 in
573 def TFRI_cNotPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
575 "if (!$src1) $dst = #$src2",
578 let neverHasSideEffects = 1, isPredicated = 1 in
579 def TFR_cdnPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
581 "if ($src1.new) $dst = $src2",
584 let neverHasSideEffects = 1, isPredicated = 1 in
585 def TFR_cdnNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
587 "if (!$src1.new) $dst = $src2",
590 let neverHasSideEffects = 1, isPredicated = 1 in
591 def TFRI_cdnPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
593 "if ($src1.new) $dst = #$src2",
596 let neverHasSideEffects = 1, isPredicated = 1 in
597 def TFRI_cdnNotPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
599 "if (!$src1.new) $dst = #$src2",
603 defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", setugt>;
604 defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", setgt>;
605 defm CMPLT : CMP32_rr<"cmp.lt", setlt>;
606 defm CMPLTU : CMP32_rr<"cmp.ltu", setult>;
607 defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", seteq>;
608 defm CMPGE : CMP32_ri_s8<"cmp.ge", setge>;
609 defm CMPGEU : CMP32_ri_u8<"cmp.geu", setuge>;
610 //===----------------------------------------------------------------------===//
612 //===----------------------------------------------------------------------===//
614 //===----------------------------------------------------------------------===//
616 //===----------------------------------------------------------------------===//
617 // Vector add halfwords
619 // Vector averagehalfwords
621 // Vector subtract halfwords
622 //===----------------------------------------------------------------------===//
624 //===----------------------------------------------------------------------===//
627 //===----------------------------------------------------------------------===//
629 //===----------------------------------------------------------------------===//
631 def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
633 "$dst = add($src1, $src2)",
634 [(set (i64 DoubleRegs:$dst), (add (i64 DoubleRegs:$src1),
635 (i64 DoubleRegs:$src2)))]>;
640 defm CMPEHexagon4 : CMP64_rr<"cmp.eq", seteq>;
641 defm CMPGT64 : CMP64_rr<"cmp.gt", setgt>;
642 defm CMPGTU64 : CMP64_rr<"cmp.gtu", setugt>;
644 // Logical operations.
645 def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
647 "$dst = and($src1, $src2)",
648 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
649 (i64 DoubleRegs:$src2)))]>;
651 def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
653 "$dst = or($src1, $src2)",
654 [(set (i64 DoubleRegs:$dst), (or (i64 DoubleRegs:$src1),
655 (i64 DoubleRegs:$src2)))]>;
657 def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
659 "$dst = xor($src1, $src2)",
660 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
661 (i64 DoubleRegs:$src2)))]>;
664 def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
665 "$dst = max($src2, $src1)",
666 [(set (i32 IntRegs:$dst),
667 (i32 (select (i1 (setlt (i32 IntRegs:$src2),
668 (i32 IntRegs:$src1))),
669 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
672 def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
673 "$dst = min($src2, $src1)",
674 [(set (i32 IntRegs:$dst),
675 (i32 (select (i1 (setgt (i32 IntRegs:$src2),
676 (i32 IntRegs:$src1))),
677 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
680 def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
682 "$dst = sub($src1, $src2)",
683 [(set (i64 DoubleRegs:$dst), (sub (i64 DoubleRegs:$src1),
684 (i64 DoubleRegs:$src2)))]>;
686 // Subtract halfword.
688 // Transfer register.
689 let neverHasSideEffects = 1 in
690 def TFR_64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
693 //===----------------------------------------------------------------------===//
695 //===----------------------------------------------------------------------===//
697 //===----------------------------------------------------------------------===//
699 //===----------------------------------------------------------------------===//
701 //===----------------------------------------------------------------------===//
703 //===----------------------------------------------------------------------===//
705 //===----------------------------------------------------------------------===//
707 //===----------------------------------------------------------------------===//
709 //===----------------------------------------------------------------------===//
711 //===----------------------------------------------------------------------===//
713 //===----------------------------------------------------------------------===//
715 //===----------------------------------------------------------------------===//
717 //===----------------------------------------------------------------------===//
719 //===----------------------------------------------------------------------===//
721 //===----------------------------------------------------------------------===//
723 //===----------------------------------------------------------------------===//
725 //===----------------------------------------------------------------------===//
727 //===----------------------------------------------------------------------===//
729 //===----------------------------------------------------------------------===//
731 //===----------------------------------------------------------------------===//
733 //===----------------------------------------------------------------------===//
735 //===----------------------------------------------------------------------===//
737 //===----------------------------------------------------------------------===//
739 //===----------------------------------------------------------------------===//
740 // Logical reductions on predicates.
742 // Looping instructions.
744 // Pipelined looping instructions.
746 // Logical operations on predicates.
747 def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
748 "$dst = and($src1, $src2)",
749 [(set (i1 PredRegs:$dst), (and (i1 PredRegs:$src1),
750 (i1 PredRegs:$src2)))]>;
752 let neverHasSideEffects = 1 in
753 def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
755 "$dst = and($src1, !$src2)",
758 def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
759 "$dst = any8($src1)",
762 def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
763 "$dst = all8($src1)",
766 def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
768 "$dst = vitpack($src1, $src2)",
771 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
774 "$dst = valignb($src1, $src2, $src3)",
777 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
780 "$dst = vspliceb($src1, $src2, $src3)",
783 def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
784 "$dst = mask($src1)",
787 def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
789 [(set (i1 PredRegs:$dst), (not (i1 PredRegs:$src1)))]>;
791 def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
792 "$dst = or($src1, $src2)",
793 [(set (i1 PredRegs:$dst), (or (i1 PredRegs:$src1),
794 (i1 PredRegs:$src2)))]>;
796 def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
797 "$dst = xor($src1, $src2)",
798 [(set (i1 PredRegs:$dst), (xor (i1 PredRegs:$src1),
799 (i1 PredRegs:$src2)))]>;
802 // User control register transfer.
803 //===----------------------------------------------------------------------===//
805 //===----------------------------------------------------------------------===//
808 //===----------------------------------------------------------------------===//
810 //===----------------------------------------------------------------------===//
812 let isBranch = 1, isTerminator=1, isBarrier = 1, isPredicable = 1 in {
813 def JMP : JInst< (outs),
814 (ins brtarget:$offset),
820 let isBranch = 1, isTerminator=1, Defs = [PC],
821 isPredicated = 1 in {
822 def JMP_c : JInst< (outs),
823 (ins PredRegs:$src, brtarget:$offset),
824 "if ($src) jump $offset",
825 [(brcond (i1 PredRegs:$src), bb:$offset)]>;
829 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
830 isPredicated = 1 in {
831 def JMP_cNot : JInst< (outs),
832 (ins PredRegs:$src, brtarget:$offset),
833 "if (!$src) jump $offset",
837 let isTerminator = 1, isBranch = 1, neverHasSideEffects = 1, Defs = [PC],
838 isPredicated = 1 in {
839 def BRCOND : JInst < (outs), (ins PredRegs:$pred, brtarget:$dst),
840 "if ($pred) jump $dst",
844 // Jump to address conditioned on new predicate.
846 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
847 isPredicated = 1 in {
848 def JMP_cdnPt : JInst< (outs),
849 (ins PredRegs:$src, brtarget:$offset),
850 "if ($src.new) jump:t $offset",
855 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
856 isPredicated = 1 in {
857 def JMP_cdnNotPt : JInst< (outs),
858 (ins PredRegs:$src, brtarget:$offset),
859 "if (!$src.new) jump:t $offset",
864 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
865 isPredicated = 1 in {
866 def JMP_cdnPnt : JInst< (outs),
867 (ins PredRegs:$src, brtarget:$offset),
868 "if ($src.new) jump:nt $offset",
873 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
874 isPredicated = 1 in {
875 def JMP_cdnNotPnt : JInst< (outs),
876 (ins PredRegs:$src, brtarget:$offset),
877 "if (!$src.new) jump:nt $offset",
880 //===----------------------------------------------------------------------===//
882 //===----------------------------------------------------------------------===//
884 //===----------------------------------------------------------------------===//
886 //===----------------------------------------------------------------------===//
887 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
888 [SDNPHasChain, SDNPOptInGlue]>;
890 // Jump to address from register.
891 let isPredicable =1, isReturn = 1, isTerminator = 1, isBarrier = 1,
892 Defs = [PC], Uses = [R31] in {
893 def JMPR: JRInst<(outs), (ins),
898 // Jump to address from register.
899 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
900 Defs = [PC], Uses = [R31] in {
901 def JMPR_cPt: JRInst<(outs), (ins PredRegs:$src1),
902 "if ($src1) jumpr r31",
906 // Jump to address from register.
907 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
908 Defs = [PC], Uses = [R31] in {
909 def JMPR_cNotPt: JRInst<(outs), (ins PredRegs:$src1),
910 "if (!$src1) jumpr r31",
914 //===----------------------------------------------------------------------===//
916 //===----------------------------------------------------------------------===//
918 //===----------------------------------------------------------------------===//
920 //===----------------------------------------------------------------------===//
922 /// Make sure that in post increment load, the first operand is always the post
923 /// increment operand.
926 let isPredicable = 1 in
927 def LDrid : LDInst<(outs DoubleRegs:$dst),
929 "$dst = memd($addr)",
930 [(set (i64 DoubleRegs:$dst), (i64 (load ADDRriS11_3:$addr)))]>;
932 let isPredicable = 1, AddedComplexity = 20 in
933 def LDrid_indexed : LDInst<(outs DoubleRegs:$dst),
934 (ins IntRegs:$src1, s11_3Imm:$offset),
935 "$dst = memd($src1+#$offset)",
936 [(set (i64 DoubleRegs:$dst),
937 (i64 (load (add (i32 IntRegs:$src1),
938 s11_3ImmPred:$offset))))]>;
940 let neverHasSideEffects = 1 in
941 def LDrid_GP : LDInst2<(outs DoubleRegs:$dst),
942 (ins globaladdress:$global, u16Imm:$offset),
943 "$dst = memd(#$global+$offset)",
947 let neverHasSideEffects = 1 in
948 def LDd_GP : LDInst2<(outs DoubleRegs:$dst),
949 (ins globaladdress:$global),
950 "$dst = memd(#$global)",
954 let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
955 def POST_LDrid : LDInst2PI<(outs DoubleRegs:$dst, IntRegs:$dst2),
956 (ins IntRegs:$src1, s4Imm:$offset),
957 "$dst = memd($src1++#$offset)",
961 // Load doubleword conditionally.
962 let neverHasSideEffects = 1, isPredicated = 1 in
963 def LDrid_cPt : LDInst2<(outs DoubleRegs:$dst),
964 (ins PredRegs:$src1, MEMri:$addr),
965 "if ($src1) $dst = memd($addr)",
969 let neverHasSideEffects = 1, isPredicated = 1 in
970 def LDrid_cNotPt : LDInst2<(outs DoubleRegs:$dst),
971 (ins PredRegs:$src1, MEMri:$addr),
972 "if (!$src1) $dst = memd($addr)",
975 let neverHasSideEffects = 1, isPredicated = 1 in
976 def LDrid_indexed_cPt : LDInst2<(outs DoubleRegs:$dst),
977 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
978 "if ($src1) $dst = memd($src2+#$src3)",
981 let neverHasSideEffects = 1, isPredicated = 1 in
982 def LDrid_indexed_cNotPt : LDInst2<(outs DoubleRegs:$dst),
983 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
984 "if (!$src1) $dst = memd($src2+#$src3)",
987 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
988 def POST_LDrid_cPt : LDInst2PI<(outs DoubleRegs:$dst1, IntRegs:$dst2),
989 (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),
990 "if ($src1) $dst1 = memd($src2++#$src3)",
994 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
995 def POST_LDrid_cNotPt : LDInst2PI<(outs DoubleRegs:$dst1, IntRegs:$dst2),
996 (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),
997 "if (!$src1) $dst1 = memd($src2++#$src3)",
1001 let neverHasSideEffects = 1, isPredicated = 1, isPredicated = 1 in
1002 def LDrid_cdnPt : LDInst2<(outs DoubleRegs:$dst),
1003 (ins PredRegs:$src1, MEMri:$addr),
1004 "if ($src1.new) $dst = memd($addr)",
1007 let neverHasSideEffects = 1, isPredicated = 1 in
1008 def LDrid_cdnNotPt : LDInst2<(outs DoubleRegs:$dst),
1009 (ins PredRegs:$src1, MEMri:$addr),
1010 "if (!$src1.new) $dst = memd($addr)",
1013 let neverHasSideEffects = 1, isPredicated = 1 in
1014 def LDrid_indexed_cdnPt : LDInst2<(outs DoubleRegs:$dst),
1015 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
1016 "if ($src1.new) $dst = memd($src2+#$src3)",
1019 let neverHasSideEffects = 1, isPredicated = 1 in
1020 def LDrid_indexed_cdnNotPt : LDInst2<(outs DoubleRegs:$dst),
1021 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
1022 "if (!$src1.new) $dst = memd($src2+#$src3)",
1027 let isPredicable = 1 in
1028 def LDrib : LDInst<(outs IntRegs:$dst),
1030 "$dst = memb($addr)",
1031 [(set (i32 IntRegs:$dst), (i32 (sextloadi8 ADDRriS11_0:$addr)))]>;
1033 // Load byte any-extend
1034 def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
1035 (i32 (LDrib ADDRriS11_0:$addr)) >;
1037 // Indexed load byte.
1038 let isPredicable = 1, AddedComplexity = 20 in
1039 def LDrib_indexed : LDInst<(outs IntRegs:$dst),
1040 (ins IntRegs:$src1, s11_0Imm:$offset),
1041 "$dst = memb($src1+#$offset)",
1042 [(set (i32 IntRegs:$dst),
1043 (i32 (sextloadi8 (add (i32 IntRegs:$src1),
1044 s11_0ImmPred:$offset))))]>;
1046 // Indexed load byte any-extend.
1047 let AddedComplexity = 20 in
1048 def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1049 (i32 (LDrib_indexed IntRegs:$src1, s11_0ImmPred:$offset)) >;
1051 let neverHasSideEffects = 1 in
1052 def LDrib_GP : LDInst2<(outs IntRegs:$dst),
1053 (ins globaladdress:$global, u16Imm:$offset),
1054 "$dst = memb(#$global+$offset)",
1058 let neverHasSideEffects = 1 in
1059 def LDb_GP : LDInst2<(outs IntRegs:$dst),
1060 (ins globaladdress:$global),
1061 "$dst = memb(#$global)",
1065 let neverHasSideEffects = 1 in
1066 def LDub_GP : LDInst2<(outs IntRegs:$dst),
1067 (ins globaladdress:$global),
1068 "$dst = memub(#$global)",
1072 let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1073 def POST_LDrib : LDInst2PI<(outs IntRegs:$dst, IntRegs:$dst2),
1074 (ins IntRegs:$src1, s4Imm:$offset),
1075 "$dst = memb($src1++#$offset)",
1079 // Load byte conditionally.
1080 let neverHasSideEffects = 1, isPredicated = 1 in
1081 def LDrib_cPt : LDInst2<(outs IntRegs:$dst),
1082 (ins PredRegs:$src1, MEMri:$addr),
1083 "if ($src1) $dst = memb($addr)",
1086 let neverHasSideEffects = 1, isPredicated = 1 in
1087 def LDrib_cNotPt : LDInst2<(outs IntRegs:$dst),
1088 (ins PredRegs:$src1, MEMri:$addr),
1089 "if (!$src1) $dst = memb($addr)",
1092 let neverHasSideEffects = 1, isPredicated = 1 in
1093 def LDrib_indexed_cPt : LDInst2<(outs IntRegs:$dst),
1094 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1095 "if ($src1) $dst = memb($src2+#$src3)",
1098 let neverHasSideEffects = 1, isPredicated = 1 in
1099 def LDrib_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
1100 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1101 "if (!$src1) $dst = memb($src2+#$src3)",
1104 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1105 def POST_LDrib_cPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1106 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1107 "if ($src1) $dst1 = memb($src2++#$src3)",
1111 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1112 def POST_LDrib_cNotPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1113 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1114 "if (!$src1) $dst1 = memb($src2++#$src3)",
1118 let neverHasSideEffects = 1, isPredicated = 1 in
1119 def LDrib_cdnPt : LDInst2<(outs IntRegs:$dst),
1120 (ins PredRegs:$src1, MEMri:$addr),
1121 "if ($src1.new) $dst = memb($addr)",
1124 let neverHasSideEffects = 1, isPredicated = 1 in
1125 def LDrib_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1126 (ins PredRegs:$src1, MEMri:$addr),
1127 "if (!$src1.new) $dst = memb($addr)",
1130 let neverHasSideEffects = 1, isPredicated = 1 in
1131 def LDrib_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
1132 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1133 "if ($src1.new) $dst = memb($src2+#$src3)",
1136 let neverHasSideEffects = 1, isPredicated = 1 in
1137 def LDrib_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1138 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1139 "if (!$src1.new) $dst = memb($src2+#$src3)",
1144 let isPredicable = 1 in
1145 def LDrih : LDInst<(outs IntRegs:$dst),
1147 "$dst = memh($addr)",
1148 [(set (i32 IntRegs:$dst), (i32 (sextloadi16 ADDRriS11_1:$addr)))]>;
1150 let isPredicable = 1, AddedComplexity = 20 in
1151 def LDrih_indexed : LDInst<(outs IntRegs:$dst),
1152 (ins IntRegs:$src1, s11_1Imm:$offset),
1153 "$dst = memh($src1+#$offset)",
1154 [(set (i32 IntRegs:$dst),
1155 (i32 (sextloadi16 (add (i32 IntRegs:$src1),
1156 s11_1ImmPred:$offset))))] >;
1158 def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
1159 (i32 (LDrih ADDRriS11_1:$addr))>;
1161 let AddedComplexity = 20 in
1162 def : Pat < (i32 (extloadi16 (add IntRegs:$src1, s11_1ImmPred:$offset))),
1163 (i32 (LDrih_indexed IntRegs:$src1, s11_1ImmPred:$offset)) >;
1165 let neverHasSideEffects = 1 in
1166 def LDrih_GP : LDInst2<(outs IntRegs:$dst),
1167 (ins globaladdress:$global, u16Imm:$offset),
1168 "$dst = memh(#$global+$offset)",
1172 let neverHasSideEffects = 1 in
1173 def LDh_GP : LDInst2<(outs IntRegs:$dst),
1174 (ins globaladdress:$global),
1175 "$dst = memh(#$global)",
1179 let neverHasSideEffects = 1 in
1180 def LDuh_GP : LDInst2<(outs IntRegs:$dst),
1181 (ins globaladdress:$global),
1182 "$dst = memuh(#$global)",
1186 let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1187 def POST_LDrih : LDInst2PI<(outs IntRegs:$dst, IntRegs:$dst2),
1188 (ins IntRegs:$src1, s4Imm:$offset),
1189 "$dst = memh($src1++#$offset)",
1193 // Load halfword conditionally.
1194 let neverHasSideEffects = 1, isPredicated = 1 in
1195 def LDrih_cPt : LDInst2<(outs IntRegs:$dst),
1196 (ins PredRegs:$src1, MEMri:$addr),
1197 "if ($src1) $dst = memh($addr)",
1200 let neverHasSideEffects = 1, isPredicated = 1 in
1201 def LDrih_cNotPt : LDInst2<(outs IntRegs:$dst),
1202 (ins PredRegs:$src1, MEMri:$addr),
1203 "if (!$src1) $dst = memh($addr)",
1206 let neverHasSideEffects = 1, isPredicated = 1 in
1207 def LDrih_indexed_cPt : LDInst2<(outs IntRegs:$dst),
1208 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1209 "if ($src1) $dst = memh($src2+#$src3)",
1212 let neverHasSideEffects = 1, isPredicated = 1 in
1213 def LDrih_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
1214 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1215 "if (!$src1) $dst = memh($src2+#$src3)",
1218 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1219 def POST_LDrih_cPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1220 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1221 "if ($src1) $dst1 = memh($src2++#$src3)",
1225 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1226 def POST_LDrih_cNotPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1227 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1228 "if (!$src1) $dst1 = memh($src2++#$src3)",
1232 let neverHasSideEffects = 1, isPredicated = 1 in
1233 def LDrih_cdnPt : LDInst2<(outs IntRegs:$dst),
1234 (ins PredRegs:$src1, MEMri:$addr),
1235 "if ($src1.new) $dst = memh($addr)",
1238 let neverHasSideEffects = 1, isPredicated = 1 in
1239 def LDrih_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1240 (ins PredRegs:$src1, MEMri:$addr),
1241 "if (!$src1.new) $dst = memh($addr)",
1244 let neverHasSideEffects = 1, isPredicated = 1 in
1245 def LDrih_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
1246 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1247 "if ($src1.new) $dst = memh($src2+#$src3)",
1250 let neverHasSideEffects = 1, isPredicated = 1 in
1251 def LDrih_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1252 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1253 "if (!$src1.new) $dst = memh($src2+#$src3)",
1256 // Load unsigned byte.
1257 let isPredicable = 1 in
1258 def LDriub : LDInst<(outs IntRegs:$dst),
1260 "$dst = memub($addr)",
1261 [(set (i32 IntRegs:$dst), (i32 (zextloadi8 ADDRriS11_0:$addr)))]>;
1263 def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
1264 (i32 (LDriub ADDRriS11_0:$addr))>;
1266 let isPredicable = 1, AddedComplexity = 20 in
1267 def LDriub_indexed : LDInst<(outs IntRegs:$dst),
1268 (ins IntRegs:$src1, s11_0Imm:$offset),
1269 "$dst = memub($src1+#$offset)",
1270 [(set (i32 IntRegs:$dst),
1271 (i32 (zextloadi8 (add (i32 IntRegs:$src1),
1272 s11_0ImmPred:$offset))))]>;
1274 let AddedComplexity = 20 in
1275 def : Pat < (i32 (zextloadi1 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1276 (i32 (LDriub_indexed IntRegs:$src1, s11_0ImmPred:$offset))>;
1278 let neverHasSideEffects = 1 in
1279 def LDriub_GP : LDInst2<(outs IntRegs:$dst),
1280 (ins globaladdress:$global, u16Imm:$offset),
1281 "$dst = memub(#$global+$offset)",
1285 let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1286 def POST_LDriub : LDInst2PI<(outs IntRegs:$dst, IntRegs:$dst2),
1287 (ins IntRegs:$src1, s4Imm:$offset),
1288 "$dst = memub($src1++#$offset)",
1292 // Load unsigned byte conditionally.
1293 let neverHasSideEffects = 1, isPredicated = 1 in
1294 def LDriub_cPt : LDInst2<(outs IntRegs:$dst),
1295 (ins PredRegs:$src1, MEMri:$addr),
1296 "if ($src1) $dst = memub($addr)",
1299 let neverHasSideEffects = 1, isPredicated = 1 in
1300 def LDriub_cNotPt : LDInst2<(outs IntRegs:$dst),
1301 (ins PredRegs:$src1, MEMri:$addr),
1302 "if (!$src1) $dst = memub($addr)",
1305 let neverHasSideEffects = 1, isPredicated = 1 in
1306 def LDriub_indexed_cPt : LDInst2<(outs IntRegs:$dst),
1307 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1308 "if ($src1) $dst = memub($src2+#$src3)",
1311 let neverHasSideEffects = 1, isPredicated = 1 in
1312 def LDriub_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
1313 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1314 "if (!$src1) $dst = memub($src2+#$src3)",
1317 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1318 def POST_LDriub_cPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1319 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1320 "if ($src1) $dst1 = memub($src2++#$src3)",
1324 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1325 def POST_LDriub_cNotPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1326 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1327 "if (!$src1) $dst1 = memub($src2++#$src3)",
1331 let neverHasSideEffects = 1, isPredicated = 1 in
1332 def LDriub_cdnPt : LDInst2<(outs IntRegs:$dst),
1333 (ins PredRegs:$src1, MEMri:$addr),
1334 "if ($src1.new) $dst = memub($addr)",
1337 let neverHasSideEffects = 1, isPredicated = 1 in
1338 def LDriub_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1339 (ins PredRegs:$src1, MEMri:$addr),
1340 "if (!$src1.new) $dst = memub($addr)",
1343 let neverHasSideEffects = 1, isPredicated = 1 in
1344 def LDriub_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
1345 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1346 "if ($src1.new) $dst = memub($src2+#$src3)",
1349 let neverHasSideEffects = 1, isPredicated = 1 in
1350 def LDriub_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1351 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1352 "if (!$src1.new) $dst = memub($src2+#$src3)",
1355 // Load unsigned halfword.
1356 let isPredicable = 1 in
1357 def LDriuh : LDInst<(outs IntRegs:$dst),
1359 "$dst = memuh($addr)",
1360 [(set (i32 IntRegs:$dst), (i32 (zextloadi16 ADDRriS11_1:$addr)))]>;
1362 // Indexed load unsigned halfword.
1363 let isPredicable = 1, AddedComplexity = 20 in
1364 def LDriuh_indexed : LDInst<(outs IntRegs:$dst),
1365 (ins IntRegs:$src1, s11_1Imm:$offset),
1366 "$dst = memuh($src1+#$offset)",
1367 [(set (i32 IntRegs:$dst),
1368 (i32 (zextloadi16 (add (i32 IntRegs:$src1),
1369 s11_1ImmPred:$offset))))]>;
1371 let neverHasSideEffects = 1 in
1372 def LDriuh_GP : LDInst2<(outs IntRegs:$dst),
1373 (ins globaladdress:$global, u16Imm:$offset),
1374 "$dst = memuh(#$global+$offset)",
1378 let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1379 def POST_LDriuh : LDInst2PI<(outs IntRegs:$dst, IntRegs:$dst2),
1380 (ins IntRegs:$src1, s4Imm:$offset),
1381 "$dst = memuh($src1++#$offset)",
1385 // Load unsigned halfword conditionally.
1386 let neverHasSideEffects = 1, isPredicated = 1 in
1387 def LDriuh_cPt : LDInst2<(outs IntRegs:$dst),
1388 (ins PredRegs:$src1, MEMri:$addr),
1389 "if ($src1) $dst = memuh($addr)",
1392 let neverHasSideEffects = 1, isPredicated = 1 in
1393 def LDriuh_cNotPt : LDInst2<(outs IntRegs:$dst),
1394 (ins PredRegs:$src1, MEMri:$addr),
1395 "if (!$src1) $dst = memuh($addr)",
1398 let neverHasSideEffects = 1, isPredicated = 1 in
1399 def LDriuh_indexed_cPt : LDInst2<(outs IntRegs:$dst),
1400 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1401 "if ($src1) $dst = memuh($src2+#$src3)",
1404 let neverHasSideEffects = 1, isPredicated = 1 in
1405 def LDriuh_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
1406 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1407 "if (!$src1) $dst = memuh($src2+#$src3)",
1410 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1411 def POST_LDriuh_cPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1412 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1413 "if ($src1) $dst1 = memuh($src2++#$src3)",
1417 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1418 def POST_LDriuh_cNotPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1419 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1420 "if (!$src1) $dst1 = memuh($src2++#$src3)",
1424 let neverHasSideEffects = 1, isPredicated = 1 in
1425 def LDriuh_cdnPt : LDInst2<(outs IntRegs:$dst),
1426 (ins PredRegs:$src1, MEMri:$addr),
1427 "if ($src1.new) $dst = memuh($addr)",
1430 let neverHasSideEffects = 1, isPredicated = 1 in
1431 def LDriuh_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1432 (ins PredRegs:$src1, MEMri:$addr),
1433 "if (!$src1.new) $dst = memuh($addr)",
1436 let neverHasSideEffects = 1, isPredicated = 1 in
1437 def LDriuh_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
1438 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1439 "if ($src1.new) $dst = memuh($src2+#$src3)",
1442 let neverHasSideEffects = 1, isPredicated = 1 in
1443 def LDriuh_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1444 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1445 "if (!$src1.new) $dst = memuh($src2+#$src3)",
1450 let isPredicable = 1 in
1451 def LDriw : LDInst<(outs IntRegs:$dst),
1452 (ins MEMri:$addr), "$dst = memw($addr)",
1453 [(set IntRegs:$dst, (i32 (load ADDRriS11_2:$addr)))]>;
1456 let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1457 def LDriw_pred : LDInst2<(outs PredRegs:$dst),
1459 "Error; should not emit",
1463 let isPredicable = 1, AddedComplexity = 20 in
1464 def LDriw_indexed : LDInst<(outs IntRegs:$dst),
1465 (ins IntRegs:$src1, s11_2Imm:$offset),
1466 "$dst = memw($src1+#$offset)",
1467 [(set IntRegs:$dst, (i32 (load (add IntRegs:$src1,
1468 s11_2ImmPred:$offset))))]>;
1470 let neverHasSideEffects = 1 in
1471 def LDriw_GP : LDInst2<(outs IntRegs:$dst),
1472 (ins globaladdress:$global, u16Imm:$offset),
1473 "$dst = memw(#$global+$offset)",
1477 let neverHasSideEffects = 1 in
1478 def LDw_GP : LDInst2<(outs IntRegs:$dst),
1479 (ins globaladdress:$global),
1480 "$dst = memw(#$global)",
1484 let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1485 def POST_LDriw : LDInst2PI<(outs IntRegs:$dst, IntRegs:$dst2),
1486 (ins IntRegs:$src1, s4Imm:$offset),
1487 "$dst = memw($src1++#$offset)",
1491 // Load word conditionally.
1493 let neverHasSideEffects = 1, isPredicated = 1 in
1494 def LDriw_cPt : LDInst2<(outs IntRegs:$dst),
1495 (ins PredRegs:$src1, MEMri:$addr),
1496 "if ($src1) $dst = memw($addr)",
1499 let neverHasSideEffects = 1, isPredicated = 1 in
1500 def LDriw_cNotPt : LDInst2<(outs IntRegs:$dst),
1501 (ins PredRegs:$src1, MEMri:$addr),
1502 "if (!$src1) $dst = memw($addr)",
1505 let neverHasSideEffects = 1, isPredicated = 1 in
1506 def LDriw_indexed_cPt : LDInst2<(outs IntRegs:$dst),
1507 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1508 "if ($src1) $dst = memw($src2+#$src3)",
1511 let neverHasSideEffects = 1, isPredicated = 1 in
1512 def LDriw_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
1513 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1514 "if (!$src1) $dst = memw($src2+#$src3)",
1517 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1518 def POST_LDriw_cPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1519 (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3),
1520 "if ($src1) $dst1 = memw($src2++#$src3)",
1524 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1525 def POST_LDriw_cNotPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1526 (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3),
1527 "if (!$src1) $dst1 = memw($src2++#$src3)",
1531 let neverHasSideEffects = 1, isPredicated = 1 in
1532 def LDriw_cdnPt : LDInst2<(outs IntRegs:$dst),
1533 (ins PredRegs:$src1, MEMri:$addr),
1534 "if ($src1.new) $dst = memw($addr)",
1537 let neverHasSideEffects = 1, isPredicated = 1 in
1538 def LDriw_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1539 (ins PredRegs:$src1, MEMri:$addr),
1540 "if (!$src1.new) $dst = memw($addr)",
1543 let neverHasSideEffects = 1, isPredicated = 1 in
1544 def LDriw_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
1545 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1546 "if ($src1.new) $dst = memw($src2+#$src3)",
1549 let neverHasSideEffects = 1, isPredicated = 1 in
1550 def LDriw_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1551 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1552 "if (!$src1.new) $dst = memw($src2+#$src3)",
1555 // Deallocate stack frame.
1556 let Defs = [R29, R30, R31], Uses = [R29], neverHasSideEffects = 1 in {
1557 def DEALLOCFRAME : LDInst2<(outs), (ins i32imm:$amt1),
1562 // Load and unpack bytes to halfwords.
1563 //===----------------------------------------------------------------------===//
1565 //===----------------------------------------------------------------------===//
1567 //===----------------------------------------------------------------------===//
1569 //===----------------------------------------------------------------------===//
1570 //===----------------------------------------------------------------------===//
1572 //===----------------------------------------------------------------------===//
1574 //===----------------------------------------------------------------------===//
1576 //===----------------------------------------------------------------------===//
1577 //===----------------------------------------------------------------------===//
1579 //===----------------------------------------------------------------------===//
1581 //===----------------------------------------------------------------------===//
1583 //===----------------------------------------------------------------------===//
1584 // Multiply and use lower result.
1586 def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1587 "$dst =+ mpyi($src1, #$src2)",
1588 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1589 u8ImmPred:$src2))]>;
1592 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, n8Imm:$src2),
1593 "$dst =- mpyi($src1, #$src2)",
1594 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1595 n8ImmPred:$src2))]>;
1598 // s9 is NOT the same as m9 - but it works.. so far.
1599 // Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
1600 // depending on the value of m9. See Arch Spec.
1601 def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Imm:$src2),
1602 "$dst = mpyi($src1, #$src2)",
1603 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1604 s9ImmPred:$src2))]>;
1607 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1608 "$dst = mpyi($src1, $src2)",
1609 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1610 (i32 IntRegs:$src2)))]>;
1613 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
1614 (ins IntRegs:$src1, IntRegs:$src2, u8Imm:$src3),
1615 "$dst += mpyi($src2, #$src3)",
1616 [(set (i32 IntRegs:$dst),
1617 (add (mul (i32 IntRegs:$src2), u8ImmPred:$src3),
1618 (i32 IntRegs:$src1)))],
1622 def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
1623 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1624 "$dst += mpyi($src2, $src3)",
1625 [(set (i32 IntRegs:$dst),
1626 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1627 (i32 IntRegs:$src1)))],
1631 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
1632 (ins IntRegs:$src1, IntRegs:$src2, u8Imm:$src3),
1633 "$dst -= mpyi($src2, #$src3)",
1634 [(set (i32 IntRegs:$dst),
1635 (sub (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1636 u8ImmPred:$src3)))],
1639 // Multiply and use upper result.
1640 // Rd=mpy(Rs,Rt.H):<<1:rnd:sat
1641 // Rd=mpy(Rs,Rt.L):<<1:rnd:sat
1643 def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1644 "$dst = mpy($src1, $src2)",
1645 [(set (i32 IntRegs:$dst), (mulhs (i32 IntRegs:$src1),
1646 (i32 IntRegs:$src2)))]>;
1648 // Rd=mpy(Rs,Rt):rnd
1650 def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1651 "$dst = mpyu($src1, $src2)",
1652 [(set (i32 IntRegs:$dst), (mulhu (i32 IntRegs:$src1),
1653 (i32 IntRegs:$src2)))]>;
1655 // Multiply and use full result.
1657 def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1658 "$dst = mpyu($src1, $src2)",
1659 [(set (i64 DoubleRegs:$dst),
1660 (mul (i64 (anyext (i32 IntRegs:$src1))),
1661 (i64 (anyext (i32 IntRegs:$src2)))))]>;
1664 def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1665 "$dst = mpy($src1, $src2)",
1666 [(set (i64 DoubleRegs:$dst),
1667 (mul (i64 (sext (i32 IntRegs:$src1))),
1668 (i64 (sext (i32 IntRegs:$src2)))))]>;
1670 // Multiply and accumulate, use full result.
1671 // Rxx[+-]=mpy(Rs,Rt)
1673 def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
1674 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1675 "$dst += mpy($src2, $src3)",
1676 [(set (i64 DoubleRegs:$dst),
1677 (add (mul (i64 (sext (i32 IntRegs:$src2))),
1678 (i64 (sext (i32 IntRegs:$src3)))),
1679 (i64 DoubleRegs:$src1)))],
1683 def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
1684 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1685 "$dst -= mpy($src2, $src3)",
1686 [(set (i64 DoubleRegs:$dst),
1687 (sub (i64 DoubleRegs:$src1),
1688 (mul (i64 (sext (i32 IntRegs:$src2))),
1689 (i64 (sext (i32 IntRegs:$src3))))))],
1692 // Rxx[+-]=mpyu(Rs,Rt)
1694 def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1695 IntRegs:$src2, IntRegs:$src3),
1696 "$dst += mpyu($src2, $src3)",
1697 [(set (i64 DoubleRegs:$dst),
1698 (add (mul (i64 (anyext (i32 IntRegs:$src2))),
1699 (i64 (anyext (i32 IntRegs:$src3)))),
1700 (i64 DoubleRegs:$src1)))], "$src1 = $dst">;
1703 def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
1704 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1705 "$dst += mpyu($src2, $src3)",
1706 [(set (i64 DoubleRegs:$dst),
1707 (sub (i64 DoubleRegs:$src1),
1708 (mul (i64 (anyext (i32 IntRegs:$src2))),
1709 (i64 (anyext (i32 IntRegs:$src3))))))],
1713 def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1714 IntRegs:$src2, IntRegs:$src3),
1715 "$dst += add($src2, $src3)",
1716 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1717 (i32 IntRegs:$src3)),
1718 (i32 IntRegs:$src1)))],
1721 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1722 IntRegs:$src2, s8Imm:$src3),
1723 "$dst += add($src2, #$src3)",
1724 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1726 (i32 IntRegs:$src1)))],
1729 def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1730 IntRegs:$src2, IntRegs:$src3),
1731 "$dst -= add($src2, $src3)",
1732 [(set (i32 IntRegs:$dst),
1733 (sub (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1734 (i32 IntRegs:$src3))))],
1737 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1738 IntRegs:$src2, s8Imm:$src3),
1739 "$dst -= add($src2, #$src3)",
1740 [(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
1741 (add (i32 IntRegs:$src2),
1742 s8ImmPred:$src3)))],
1745 //===----------------------------------------------------------------------===//
1747 //===----------------------------------------------------------------------===//
1749 //===----------------------------------------------------------------------===//
1751 //===----------------------------------------------------------------------===//
1752 //===----------------------------------------------------------------------===//
1754 //===----------------------------------------------------------------------===//
1756 //===----------------------------------------------------------------------===//
1758 //===----------------------------------------------------------------------===//
1759 //===----------------------------------------------------------------------===//
1761 //===----------------------------------------------------------------------===//
1763 //===----------------------------------------------------------------------===//
1765 //===----------------------------------------------------------------------===//
1766 //===----------------------------------------------------------------------===//
1768 //===----------------------------------------------------------------------===//
1770 //===----------------------------------------------------------------------===//
1772 //===----------------------------------------------------------------------===//
1774 /// Assumptions::: ****** DO NOT IGNORE ********
1775 /// 1. Make sure that in post increment store, the zero'th operand is always the
1776 /// post increment operand.
1777 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
1780 // Store doubleword.
1781 let isPredicable = 1 in
1782 def STrid : STInst<(outs),
1783 (ins MEMri:$addr, DoubleRegs:$src1),
1784 "memd($addr) = $src1",
1785 [(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr)]>;
1787 // Indexed store double word.
1788 let AddedComplexity = 10, isPredicable = 1 in
1789 def STrid_indexed : STInst<(outs),
1790 (ins IntRegs:$src1, s11_3Imm:$src2, DoubleRegs:$src3),
1791 "memd($src1+#$src2) = $src3",
1792 [(store (i64 DoubleRegs:$src3),
1793 (add (i32 IntRegs:$src1), s11_3ImmPred:$src2))]>;
1795 let neverHasSideEffects = 1 in
1796 def STrid_GP : STInst2<(outs),
1797 (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),
1798 "memd(#$global+$offset) = $src",
1802 let mayStore = 1, neverHasSideEffects = 1 in
1803 def STd_GP : STInst<(outs),
1804 (ins globaladdress:$global, DoubleRegs:$src),
1805 "memd(#$global) = $src",
1809 let hasCtrlDep = 1, isPredicable = 1 in
1810 def POST_STdri : STInstPI<(outs IntRegs:$dst),
1811 (ins DoubleRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1812 "memd($src2++#$offset) = $src1",
1814 (post_store (i64 DoubleRegs:$src1), (i32 IntRegs:$src2),
1815 s4_3ImmPred:$offset))],
1818 // Store doubleword conditionally.
1819 // if ([!]Pv) memd(Rs+#u6:3)=Rtt
1820 // if (Pv) memd(Rs+#u6:3)=Rtt
1821 let AddedComplexity = 10, neverHasSideEffects = 1, isPredicated = 1 in
1822 def STrid_cPt : STInst2<(outs),
1823 (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
1824 "if ($src1) memd($addr) = $src2",
1827 // if (!Pv) memd(Rs+#u6:3)=Rtt
1828 let AddedComplexity = 10, neverHasSideEffects = 1, isPredicated = 1 in
1829 def STrid_cNotPt : STInst2<(outs),
1830 (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
1831 "if (!$src1) memd($addr) = $src2",
1834 // if (Pv) memd(Rs+#u6:3)=Rtt
1835 let AddedComplexity = 10, neverHasSideEffects = 1, isPredicated = 1 in
1836 def STrid_indexed_cPt : STInst2<(outs),
1837 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
1839 "if ($src1) memd($src2+#$src3) = $src4",
1842 // if (!Pv) memd(Rs+#u6:3)=Rtt
1843 let AddedComplexity = 10, neverHasSideEffects = 1, isPredicated = 1 in
1844 def STrid_indexed_cNotPt : STInst2<(outs),
1845 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
1847 "if (!$src1) memd($src2+#$src3) = $src4",
1850 // if ([!]Pv) memd(Rx++#s4:3)=Rtt
1851 // if (Pv) memd(Rx++#s4:3)=Rtt
1852 let AddedComplexity = 10, neverHasSideEffects = 1, isPredicated = 1 in
1853 def POST_STdri_cPt : STInst2PI<(outs IntRegs:$dst),
1854 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1856 "if ($src1) memd($src3++#$offset) = $src2",
1860 // if (!Pv) memd(Rx++#s4:3)=Rtt
1861 let AddedComplexity = 10, neverHasSideEffects = 1, isPredicated = 1,
1863 def POST_STdri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1864 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1866 "if (!$src1) memd($src3++#$offset) = $src2",
1872 // memb(Rs+#s11:0)=Rt
1873 let isPredicable = 1 in
1874 def STrib : STInst<(outs),
1875 (ins MEMri:$addr, IntRegs:$src1),
1876 "memb($addr) = $src1",
1877 [(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr)]>;
1879 let AddedComplexity = 10, isPredicable = 1 in
1880 def STrib_indexed : STInst<(outs),
1881 (ins IntRegs:$src1, s11_0Imm:$src2, IntRegs:$src3),
1882 "memb($src1+#$src2) = $src3",
1883 [(truncstorei8 (i32 IntRegs:$src3), (add (i32 IntRegs:$src1),
1884 s11_0ImmPred:$src2))]>;
1886 // memb(gp+#u16:0)=Rt
1887 let neverHasSideEffects = 1 in
1888 def STrib_GP : STInst2<(outs),
1889 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1890 "memb(#$global+$offset) = $src",
1894 let neverHasSideEffects = 1 in
1895 def STb_GP : STInst2<(outs),
1896 (ins globaladdress:$global, IntRegs:$src),
1897 "memb(#$global) = $src",
1901 // memb(Rx++#s4:0)=Rt
1902 let hasCtrlDep = 1, isPredicable = 1 in
1903 def POST_STbri : STInstPI<(outs IntRegs:$dst), (ins IntRegs:$src1,
1906 "memb($src2++#$offset) = $src1",
1908 (post_truncsti8 (i32 IntRegs:$src1), (i32 IntRegs:$src2),
1909 s4_0ImmPred:$offset))],
1912 // Store byte conditionally.
1913 // if ([!]Pv) memb(Rs+#u6:0)=Rt
1914 // if (Pv) memb(Rs+#u6:0)=Rt
1915 let neverHasSideEffects = 1, isPredicated = 1 in
1916 def STrib_cPt : STInst2<(outs),
1917 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1918 "if ($src1) memb($addr) = $src2",
1921 // if (!Pv) memb(Rs+#u6:0)=Rt
1922 let neverHasSideEffects = 1, isPredicated = 1 in
1923 def STrib_cNotPt : STInst2<(outs),
1924 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1925 "if (!$src1) memb($addr) = $src2",
1928 // if (Pv) memb(Rs+#u6:0)=Rt
1929 let neverHasSideEffects = 1, isPredicated = 1 in
1930 def STrib_indexed_cPt : STInst2<(outs),
1931 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1932 "if ($src1) memb($src2+#$src3) = $src4",
1935 // if (!Pv) memb(Rs+#u6:0)=Rt
1936 let neverHasSideEffects = 1, isPredicated = 1 in
1937 def STrib_indexed_cNotPt : STInst2<(outs),
1938 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1939 "if (!$src1) memb($src2+#$src3) = $src4",
1942 // if ([!]Pv) memb(Rx++#s4:0)=Rt
1943 // if (Pv) memb(Rx++#s4:0)=Rt
1944 let hasCtrlDep = 1, isPredicated = 1 in
1945 def POST_STbri_cPt : STInst2PI<(outs IntRegs:$dst),
1946 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1947 "if ($src1) memb($src3++#$offset) = $src2",
1950 // if (!Pv) memb(Rx++#s4:0)=Rt
1951 let hasCtrlDep = 1, isPredicated = 1 in
1952 def POST_STbri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1953 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1954 "if (!$src1) memb($src3++#$offset) = $src2",
1959 // memh(Rs+#s11:1)=Rt
1960 let isPredicable = 1 in
1961 def STrih : STInst<(outs),
1962 (ins MEMri:$addr, IntRegs:$src1),
1963 "memh($addr) = $src1",
1964 [(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr)]>;
1967 let AddedComplexity = 10, isPredicable = 1 in
1968 def STrih_indexed : STInst<(outs),
1969 (ins IntRegs:$src1, s11_1Imm:$src2, IntRegs:$src3),
1970 "memh($src1+#$src2) = $src3",
1971 [(truncstorei16 (i32 IntRegs:$src3), (add (i32 IntRegs:$src1),
1972 s11_1ImmPred:$src2))]>;
1974 let neverHasSideEffects = 1 in
1975 def STrih_GP : STInst2<(outs),
1976 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1977 "memh(#$global+$offset) = $src",
1981 let neverHasSideEffects = 1 in
1982 def STh_GP : STInst2<(outs),
1983 (ins globaladdress:$global, IntRegs:$src),
1984 "memh(#$global) = $src",
1988 // memh(Rx++#s4:1)=Rt.H
1989 // memh(Rx++#s4:1)=Rt
1990 let hasCtrlDep = 1, isPredicable = 1 in
1991 def POST_SThri : STInstPI<(outs IntRegs:$dst),
1992 (ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1993 "memh($src2++#$offset) = $src1",
1995 (post_truncsti16 (i32 IntRegs:$src1), (i32 IntRegs:$src2),
1996 s4_1ImmPred:$offset))],
1999 // Store halfword conditionally.
2000 // if ([!]Pv) memh(Rs+#u6:1)=Rt
2001 // if (Pv) memh(Rs+#u6:1)=Rt
2002 let neverHasSideEffects = 1, isPredicated = 1 in
2003 def STrih_cPt : STInst2<(outs),
2004 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2005 "if ($src1) memh($addr) = $src2",
2008 // if (!Pv) memh(Rs+#u6:1)=Rt
2009 let neverHasSideEffects = 1, isPredicated = 1 in
2010 def STrih_cNotPt : STInst2<(outs),
2011 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2012 "if (!$src1) memh($addr) = $src2",
2015 // if (Pv) memh(Rs+#u6:1)=Rt
2016 let neverHasSideEffects = 1, isPredicated = 1 in
2017 def STrih_indexed_cPt : STInst2<(outs),
2018 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
2019 "if ($src1) memh($src2+#$src3) = $src4",
2022 // if (!Pv) memh(Rs+#u6:1)=Rt
2023 let neverHasSideEffects = 1, isPredicated = 1 in
2024 def STrih_indexed_cNotPt : STInst2<(outs),
2025 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
2026 "if (!$src1) memh($src2+#$src3) = $src4",
2029 // if ([!]Pv) memh(Rx++#s4:1)=Rt
2030 // if (Pv) memh(Rx++#s4:1)=Rt
2031 let hasCtrlDep = 1, isPredicated = 1 in
2032 def POST_SThri_cPt : STInst2PI<(outs IntRegs:$dst),
2033 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2034 "if ($src1) memh($src3++#$offset) = $src2",
2037 // if (!Pv) memh(Rx++#s4:1)=Rt
2038 let hasCtrlDep = 1, isPredicated = 1 in
2039 def POST_SThri_cNotPt : STInst2PI<(outs IntRegs:$dst),
2040 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2041 "if (!$src1) memh($src3++#$offset) = $src2",
2047 let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
2048 def STriw_pred : STInst2<(outs),
2049 (ins MEMri:$addr, PredRegs:$src1),
2050 "Error; should not emit",
2053 // memw(Rs+#s11:2)=Rt
2054 let isPredicable = 1 in
2055 def STriw : STInst<(outs),
2056 (ins MEMri:$addr, IntRegs:$src1),
2057 "memw($addr) = $src1",
2058 [(store (i32 IntRegs:$src1), ADDRriS11_2:$addr)]>;
2060 let AddedComplexity = 10, isPredicable = 1 in
2061 def STriw_indexed : STInst<(outs),
2062 (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
2063 "memw($src1+#$src2) = $src3",
2064 [(store (i32 IntRegs:$src3),
2065 (add (i32 IntRegs:$src1), s11_2ImmPred:$src2))]>;
2067 let neverHasSideEffects = 1 in
2068 def STriw_GP : STInst2<(outs),
2069 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2070 "memw(#$global+$offset) = $src",
2074 let mayStore = 1, neverHasSideEffects = 1 in
2075 def STw_GP : STInst<(outs),
2076 (ins globaladdress:$global, IntRegs:$src),
2077 "memw(#$global) = $src",
2081 let hasCtrlDep = 1, isPredicable = 1 in
2082 def POST_STwri : STInstPI<(outs IntRegs:$dst),
2083 (ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
2084 "memw($src2++#$offset) = $src1",
2086 (post_store (i32 IntRegs:$src1), (i32 IntRegs:$src2),
2087 s4_2ImmPred:$offset))],
2090 // Store word conditionally.
2091 // if ([!]Pv) memw(Rs+#u6:2)=Rt
2092 // if (Pv) memw(Rs+#u6:2)=Rt
2093 let neverHasSideEffects = 1 in
2094 def STriw_cPt : STInst2<(outs),
2095 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2096 "if ($src1) memw($addr) = $src2",
2099 // if (!Pv) memw(Rs+#u6:2)=Rt
2100 let neverHasSideEffects = 1 in
2101 def STriw_cNotPt : STInst2<(outs),
2102 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2103 "if (!$src1) memw($addr) = $src2",
2106 // if (Pv) memw(Rs+#u6:2)=Rt
2107 let neverHasSideEffects = 1 in
2108 def STriw_indexed_cPt : STInst2<(outs),
2109 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2110 "if ($src1) memw($src2+#$src3) = $src4",
2113 // if (!Pv) memw(Rs+#u6:2)=Rt
2114 let neverHasSideEffects = 1 in
2115 def STriw_indexed_cNotPt : STInst2<(outs),
2116 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2117 "if (!$src1) memw($src2+#$src3) = $src4",
2120 // if ([!]Pv) memw(Rx++#s4:2)=Rt
2121 // if (Pv) memw(Rx++#s4:2)=Rt
2122 let hasCtrlDep = 1, isPredicated = 1 in
2123 def POST_STwri_cPt : STInst2PI<(outs IntRegs:$dst),
2124 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2125 "if ($src1) memw($src3++#$offset) = $src2",
2128 // if (!Pv) memw(Rx++#s4:2)=Rt
2129 let hasCtrlDep = 1, isPredicated = 1 in
2130 def POST_STwri_cNotPt : STInst2PI<(outs IntRegs:$dst),
2131 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2132 "if (!$src1) memw($src3++#$offset) = $src2",
2137 // Allocate stack frame.
2138 let Defs = [R29, R30], Uses = [R31, R30], neverHasSideEffects = 1 in {
2139 def ALLOCFRAME : STInst2<(outs),
2141 "allocframe(#$amt)",
2144 //===----------------------------------------------------------------------===//
2146 //===----------------------------------------------------------------------===//
2148 //===----------------------------------------------------------------------===//
2150 //===----------------------------------------------------------------------===//
2152 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
2153 "$dst = not($src1)",
2154 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
2157 // Sign extend word to doubleword.
2158 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
2159 "$dst = sxtw($src1)",
2160 [(set (i64 DoubleRegs:$dst), (sext (i32 IntRegs:$src1)))]>;
2161 //===----------------------------------------------------------------------===//
2163 //===----------------------------------------------------------------------===//
2165 //===----------------------------------------------------------------------===//
2167 //===----------------------------------------------------------------------===//
2169 def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2170 "$dst = clrbit($src1, #$src2)",
2171 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
2173 (shl 1, u5ImmPred:$src2))))]>;
2175 def CLRBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2176 "$dst = clrbit($src1, #$src2)",
2179 // Map from r0 = and(r1, 2147483647) to r0 = clrbit(r1, #31).
2180 def : Pat <(and (i32 IntRegs:$src1), 2147483647),
2181 (CLRBIT_31 (i32 IntRegs:$src1), 31)>;
2184 def SETBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2185 "$dst = setbit($src1, #$src2)",
2186 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
2187 (shl 1, u5ImmPred:$src2)))]>;
2189 // Map from r0 = or(r1, -2147483648) to r0 = setbit(r1, #31).
2190 def SETBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2191 "$dst = setbit($src1, #$src2)",
2194 def : Pat <(or (i32 IntRegs:$src1), -2147483648),
2195 (SETBIT_31 (i32 IntRegs:$src1), 31)>;
2198 def TOGBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2199 "$dst = setbit($src1, #$src2)",
2200 [(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
2201 (shl 1, u5ImmPred:$src2)))]>;
2203 // Map from r0 = xor(r1, -2147483648) to r0 = togglebit(r1, #31).
2204 def TOGBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2205 "$dst = togglebit($src1, #$src2)",
2208 def : Pat <(xor (i32 IntRegs:$src1), -2147483648),
2209 (TOGBIT_31 (i32 IntRegs:$src1), 31)>;
2211 //===----------------------------------------------------------------------===//
2213 //===----------------------------------------------------------------------===//
2216 //===----------------------------------------------------------------------===//
2218 //===----------------------------------------------------------------------===//
2219 //===----------------------------------------------------------------------===//
2221 //===----------------------------------------------------------------------===//
2223 //===----------------------------------------------------------------------===//
2225 //===----------------------------------------------------------------------===//
2226 //===----------------------------------------------------------------------===//
2228 //===----------------------------------------------------------------------===//
2230 //===----------------------------------------------------------------------===//
2232 //===----------------------------------------------------------------------===//
2234 //===----------------------------------------------------------------------===//
2237 //===----------------------------------------------------------------------===//
2239 //===----------------------------------------------------------------------===//
2240 //===----------------------------------------------------------------------===//
2242 //===----------------------------------------------------------------------===//
2244 //===----------------------------------------------------------------------===//
2246 //===----------------------------------------------------------------------===//
2247 //===----------------------------------------------------------------------===//
2249 //===----------------------------------------------------------------------===//
2251 //===----------------------------------------------------------------------===//
2253 //===----------------------------------------------------------------------===//
2254 // Predicate transfer.
2255 let neverHasSideEffects = 1 in
2256 def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
2257 "$dst = $src1 /* Should almost never emit this. */",
2260 def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1),
2261 "$dst = $src1 /* Should almost never emit this. */",
2262 [(set (i1 PredRegs:$dst), (trunc (i32 IntRegs:$src1)))]>;
2263 //===----------------------------------------------------------------------===//
2265 //===----------------------------------------------------------------------===//
2267 //===----------------------------------------------------------------------===//
2269 //===----------------------------------------------------------------------===//
2270 // Shift by immediate.
2271 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2272 "$dst = asr($src1, #$src2)",
2273 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
2274 u5ImmPred:$src2))]>;
2276 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2277 "$dst = asr($src1, #$src2)",
2278 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
2279 u6ImmPred:$src2))]>;
2281 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2282 "$dst = asl($src1, #$src2)",
2283 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
2284 u5ImmPred:$src2))]>;
2286 def ASLd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2287 "$dst = asl($src1, #$src2)",
2288 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
2289 u6ImmPred:$src2))]>;
2291 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2292 "$dst = lsr($src1, #$src2)",
2293 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
2294 u5ImmPred:$src2))]>;
2296 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2297 "$dst = lsr($src1, #$src2)",
2298 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
2299 u6ImmPred:$src2))]>;
2301 def LSRd_ri_acc : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2304 "$dst += lsr($src2, #$src3)",
2305 [(set DoubleRegs:$dst, (add DoubleRegs:$src1,
2306 (srl DoubleRegs:$src2,
2307 u6ImmPred:$src3)))],
2310 // Shift by immediate and accumulate.
2311 def ASR_rr_acc : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$src1,
2314 "$dst += asr($src2, $src3)",
2315 [], "$src1 = $dst">;
2317 // Shift by immediate and add.
2318 let AddedComplexity = 100 in
2319 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
2321 "$dst = addasl($src1, $src2, #$src3)",
2322 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
2323 (shl (i32 IntRegs:$src2),
2324 u3ImmPred:$src3)))]>;
2326 // Shift by register.
2327 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2328 "$dst = asl($src1, $src2)",
2329 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
2330 (i32 IntRegs:$src2)))]>;
2332 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2333 "$dst = asr($src1, $src2)",
2334 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
2335 (i32 IntRegs:$src2)))]>;
2337 def LSL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2338 "$dst = lsl($src1, $src2)",
2339 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
2340 (i32 IntRegs:$src2)))]>;
2342 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2343 "$dst = lsr($src1, $src2)",
2344 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
2345 (i32 IntRegs:$src2)))]>;
2347 def ASLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2348 "$dst = asl($src1, $src2)",
2349 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
2350 (i32 IntRegs:$src2)))]>;
2352 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2353 "$dst = lsl($src1, $src2)",
2354 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
2355 (i32 IntRegs:$src2)))]>;
2357 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2359 "$dst = asr($src1, $src2)",
2360 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
2361 (i32 IntRegs:$src2)))]>;
2363 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2365 "$dst = lsr($src1, $src2)",
2366 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
2367 (i32 IntRegs:$src2)))]>;
2369 //===----------------------------------------------------------------------===//
2371 //===----------------------------------------------------------------------===//
2373 //===----------------------------------------------------------------------===//
2375 //===----------------------------------------------------------------------===//
2376 //===----------------------------------------------------------------------===//
2378 //===----------------------------------------------------------------------===//
2380 //===----------------------------------------------------------------------===//
2382 //===----------------------------------------------------------------------===//
2383 //===----------------------------------------------------------------------===//
2385 //===----------------------------------------------------------------------===//
2387 //===----------------------------------------------------------------------===//
2389 //===----------------------------------------------------------------------===//
2391 //===----------------------------------------------------------------------===//
2393 //===----------------------------------------------------------------------===//
2394 def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
2395 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
2398 let hasSideEffects = 1, isHexagonSolo = 1 in
2399 def BARRIER : SYSInst<(outs), (ins),
2401 [(HexagonBARRIER)]>;
2403 //===----------------------------------------------------------------------===//
2405 //===----------------------------------------------------------------------===//
2407 // TFRI64 - assembly mapped.
2408 let isReMaterializable = 1 in
2409 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
2411 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
2413 // Pseudo instruction to encode a set of conditional transfers.
2414 // This instruction is used instead of a mux and trades-off codesize
2415 // for performance. We conduct this transformation optimistically in
2416 // the hope that these instructions get promoted to dot-new transfers.
2417 let AddedComplexity = 100, isPredicated = 1 in
2418 def TFR_condset_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
2421 "Error; should not emit",
2422 [(set (i32 IntRegs:$dst),
2423 (i32 (select (i1 PredRegs:$src1),
2424 (i32 IntRegs:$src2),
2425 (i32 IntRegs:$src3))))]>;
2426 let AddedComplexity = 100, isPredicated = 1 in
2427 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
2428 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
2429 "Error; should not emit",
2430 [(set (i32 IntRegs:$dst),
2431 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
2432 s12ImmPred:$src3)))]>;
2434 let AddedComplexity = 100, isPredicated = 1 in
2435 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
2436 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
2437 "Error; should not emit",
2438 [(set (i32 IntRegs:$dst),
2439 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
2440 (i32 IntRegs:$src3))))]>;
2442 let AddedComplexity = 100, isPredicated = 1 in
2443 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
2444 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
2445 "Error; should not emit",
2446 [(set (i32 IntRegs:$dst),
2447 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
2448 s12ImmPred:$src3)))]>;
2450 // Generate frameindex addresses.
2451 let isReMaterializable = 1 in
2452 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
2453 "$dst = add($src1)",
2454 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
2459 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
2460 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
2461 "loop0($offset, #$src2)",
2465 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
2466 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
2467 "loop0($offset, $src2)",
2471 let isBranch = 1, isTerminator = 1, neverHasSideEffects = 1,
2472 Defs = [PC, LC0], Uses = [SA0, LC0] in {
2473 def ENDLOOP0 : Marker<(outs), (ins brtarget:$offset),
2478 // Support for generating global address.
2479 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [
2483 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
2484 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
2486 // HI/LO Instructions
2487 let isReMaterializable = 1, mayLoad = 1, neverHasSideEffects = 1 in
2488 def LO : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2489 "$dst.l = #LO($global)",
2492 let isReMaterializable = 1, mayLoad = 1, neverHasSideEffects = 1 in
2493 def HI : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2494 "$dst.h = #HI($global)",
2497 let isReMaterializable = 1, mayLoad = 1, neverHasSideEffects = 1 in
2498 def LOi : LDInst<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2499 "$dst.l = #LO($imm_value)",
2503 let isReMaterializable = 1, mayLoad = 1, neverHasSideEffects = 1 in
2504 def HIi : LDInst<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2505 "$dst.h = #HI($imm_value)",
2508 let isReMaterializable = 1, mayLoad = 1, neverHasSideEffects = 1 in
2509 def LO_jt : LDInst<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2510 "$dst.l = #LO($jt)",
2513 let isReMaterializable = 1, mayLoad = 1, neverHasSideEffects = 1 in
2514 def HI_jt : LDInst<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2515 "$dst.h = #HI($jt)",
2519 let isReMaterializable = 1, mayLoad = 1, neverHasSideEffects = 1 in
2520 def LO_label : LDInst<(outs IntRegs:$dst), (ins bblabel:$label),
2521 "$dst.l = #LO($label)",
2524 let isReMaterializable = 1, mayLoad = 1 , neverHasSideEffects = 1 in
2525 def HI_label : LDInst<(outs IntRegs:$dst), (ins bblabel:$label),
2526 "$dst.h = #HI($label)",
2529 // This pattern is incorrect. When we add small data, we should change
2530 // this pattern to use memw(#foo).
2531 // This is for sdata.
2532 let isMoveImm = 1 in
2533 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2534 "$dst = CONST32(#$global)",
2535 [(set (i32 IntRegs:$dst),
2536 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
2538 // This is for non-sdata.
2539 let isReMaterializable = 1, isMoveImm = 1 in
2540 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2541 "$dst = CONST32(#$global)",
2542 [(set (i32 IntRegs:$dst),
2543 (HexagonCONST32 tglobaladdr:$global))]>;
2545 let isReMaterializable = 1, isMoveImm = 1 in
2546 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2547 "$dst = CONST32(#$jt)",
2548 [(set (i32 IntRegs:$dst),
2549 (HexagonCONST32 tjumptable:$jt))]>;
2551 let isReMaterializable = 1, isMoveImm = 1 in
2552 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2553 "$dst = CONST32(#$global)",
2554 [(set (i32 IntRegs:$dst),
2555 (HexagonCONST32_GP tglobaladdr:$global))]>;
2557 let isReMaterializable = 1, isMoveImm = 1 in
2558 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
2559 "$dst = CONST32(#$global)",
2560 [(set (i32 IntRegs:$dst), imm:$global) ]>;
2562 let isReMaterializable = 1, isMoveImm = 1 in
2563 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
2564 "$dst = CONST32($label)",
2565 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
2567 let isReMaterializable = 1, isMoveImm = 1 in
2568 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
2569 "$dst = CONST64(#$global)",
2570 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
2572 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
2573 "$dst = xor($dst, $dst)",
2574 [(set (i1 PredRegs:$dst), 0)]>;
2576 def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2577 "$dst = mpy($src1, $src2)",
2578 [(set (i32 IntRegs:$dst),
2579 (trunc (i64 (srl (i64 (mul (i64 (sext (i32 IntRegs:$src1))),
2580 (i64 (sext (i32 IntRegs:$src2))))),
2583 // Pseudo instructions.
2584 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
2586 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
2587 SDTCisVT<1, i32> ]>;
2589 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
2590 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2592 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
2593 [SDNPHasChain, SDNPOutGlue]>;
2595 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2597 def call : SDNode<"HexagonISD::CALL", SDT_SPCall,
2598 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
2600 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
2601 // Optional Flag and Variable Arguments.
2602 // Its 1 Operand has pointer type.
2603 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
2604 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
2606 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
2607 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
2608 "Should never be emitted",
2609 [(callseq_start timm:$amt)]>;
2612 let Defs = [R29, R30, R31], Uses = [R29] in {
2613 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2614 "Should never be emitted",
2615 [(callseq_end timm:$amt1, timm:$amt2)]>;
2618 let isCall = 1, neverHasSideEffects = 1,
2619 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2620 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2621 def CALL : JInst<(outs), (ins calltarget:$dst, variable_ops),
2625 // Call subroutine from register.
2626 let isCall = 1, neverHasSideEffects = 1,
2627 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2628 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2629 def CALLR : JRInst<(outs), (ins IntRegs:$dst, variable_ops),
2635 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
2636 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2637 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2638 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst, variable_ops),
2639 "jump $dst // TAILCALL", []>;
2641 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
2642 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2643 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2644 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst, variable_ops),
2645 "jump $dst // TAILCALL", []>;
2648 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
2649 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2650 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2651 def TCRETURNR : JInst<(outs), (ins IntRegs:$dst, variable_ops),
2652 "jumpr $dst // TAILCALL", []>;
2654 // Map call instruction.
2655 def : Pat<(call (i32 IntRegs:$dst)),
2656 (CALLR (i32 IntRegs:$dst))>, Requires<[HasV2TOnly]>;
2657 def : Pat<(call tglobaladdr:$dst),
2658 (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
2659 def : Pat<(call texternalsym:$dst),
2660 (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>;
2662 def : Pat<(HexagonTCRet tglobaladdr:$dst),
2663 (TCRETURNtg tglobaladdr:$dst)>;
2664 def : Pat<(HexagonTCRet texternalsym:$dst),
2665 (TCRETURNtext texternalsym:$dst)>;
2666 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
2667 (TCRETURNR (i32 IntRegs:$dst))>;
2669 // Atomic load and store support
2670 // 8 bit atomic load
2671 def : Pat<(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
2672 (i32 (LDub_GP tglobaladdr:$global))>,
2675 def : Pat<(atomic_load_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2676 u16ImmPred:$offset)),
2677 (i32 (LDriub_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2680 def : Pat<(atomic_load_8 ADDRriS11_0:$src1),
2681 (i32 (LDriub ADDRriS11_0:$src1))>;
2683 def : Pat<(atomic_load_8 (add (i32 IntRegs:$src1), s11_0ImmPred:$offset)),
2684 (i32 (LDriub_indexed (i32 IntRegs:$src1), s11_0ImmPred:$offset))>;
2688 // 16 bit atomic load
2689 def : Pat<(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
2690 (i32 (LDuh_GP tglobaladdr:$global))>,
2693 def : Pat<(atomic_load_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2694 u16ImmPred:$offset)),
2695 (i32 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2698 def : Pat<(atomic_load_16 ADDRriS11_1:$src1),
2699 (i32 (LDriuh ADDRriS11_1:$src1))>;
2701 def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)),
2702 (i32 (LDriuh_indexed (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
2706 // 32 bit atomic load
2707 def : Pat<(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
2708 (i32 (LDw_GP tglobaladdr:$global))>,
2711 def : Pat<(atomic_load_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2712 u16ImmPred:$offset)),
2713 (i32 (LDriw_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2716 def : Pat<(atomic_load_32 ADDRriS11_2:$src1),
2717 (i32 (LDriw ADDRriS11_2:$src1))>;
2719 def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),
2720 (i32 (LDriw_indexed (i32 IntRegs:$src1), s11_2ImmPred:$offset))>;
2723 // 64 bit atomic load
2724 def : Pat<(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
2725 (i64 (LDd_GP tglobaladdr:$global))>,
2728 def : Pat<(atomic_load_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2729 u16ImmPred:$offset)),
2730 (i64 (LDrid_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2733 def : Pat<(atomic_load_64 ADDRriS11_3:$src1),
2734 (i64 (LDrid ADDRriS11_3:$src1))>;
2736 def : Pat<(atomic_load_64 (add (i32 IntRegs:$src1), s11_3ImmPred:$offset)),
2737 (i64 (LDrid_indexed (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
2740 // 64 bit atomic store
2741 def : Pat<(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
2742 (i64 DoubleRegs:$src1)),
2743 (STd_GP tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2746 def : Pat<(atomic_store_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2747 u16ImmPred:$offset),
2748 (i64 DoubleRegs:$src1)),
2749 (STrid_GP tglobaladdr:$global, u16ImmPred:$offset,
2750 (i64 DoubleRegs:$src1))>, Requires<[NoV4T]>;
2752 // 8 bit atomic store
2753 def : Pat<(atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
2754 (i32 IntRegs:$src1)),
2755 (STb_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2758 def : Pat<(atomic_store_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2759 u16ImmPred:$offset),
2760 (i32 IntRegs:$src1)),
2761 (STrib_GP tglobaladdr:$global, u16ImmPred:$offset,
2762 (i32 IntRegs:$src1))>, Requires<[NoV4T]>;
2764 def : Pat<(atomic_store_8 ADDRriS11_0:$src2, (i32 IntRegs:$src1)),
2765 (STrib ADDRriS11_0:$src2, (i32 IntRegs:$src1))>;
2767 def : Pat<(atomic_store_8 (add (i32 IntRegs:$src2), s11_0ImmPred:$offset),
2768 (i32 IntRegs:$src1)),
2769 (STrib_indexed (i32 IntRegs:$src2), s11_0ImmPred:$offset,
2770 (i32 IntRegs:$src1))>;
2773 // 16 bit atomic store
2774 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
2775 (i32 IntRegs:$src1)),
2776 (STh_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2779 def : Pat<(atomic_store_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2780 u16ImmPred:$offset),
2781 (i32 IntRegs:$src1)),
2782 (STrih_GP tglobaladdr:$global, u16ImmPred:$offset,
2783 (i32 IntRegs:$src1))>, Requires<[NoV4T]>;
2785 def : Pat<(atomic_store_16 ADDRriS11_1:$src2, (i32 IntRegs:$src1)),
2786 (STrih ADDRriS11_1:$src2, (i32 IntRegs:$src1))>;
2788 def : Pat<(atomic_store_16 (i32 IntRegs:$src1),
2789 (add (i32 IntRegs:$src2), s11_1ImmPred:$offset)),
2790 (STrih_indexed (i32 IntRegs:$src2), s11_1ImmPred:$offset,
2791 (i32 IntRegs:$src1))>;
2794 // 32 bit atomic store
2795 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
2796 (i32 IntRegs:$src1)),
2797 (STw_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2800 def : Pat<(atomic_store_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2801 u16ImmPred:$offset),
2802 (i32 IntRegs:$src1)),
2803 (STriw_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2806 def : Pat<(atomic_store_32 ADDRriS11_2:$src2, (i32 IntRegs:$src1)),
2807 (STriw ADDRriS11_2:$src2, (i32 IntRegs:$src1))>;
2809 def : Pat<(atomic_store_32 (add (i32 IntRegs:$src2), s11_2ImmPred:$offset),
2810 (i32 IntRegs:$src1)),
2811 (STriw_indexed (i32 IntRegs:$src2), s11_2ImmPred:$offset,
2812 (i32 IntRegs:$src1))>;
2817 def : Pat<(atomic_store_64 ADDRriS11_3:$src2, (i64 DoubleRegs:$src1)),
2818 (STrid ADDRriS11_3:$src2, (i64 DoubleRegs:$src1))>;
2820 def : Pat<(atomic_store_64 (add (i32 IntRegs:$src2), s11_3ImmPred:$offset),
2821 (i64 DoubleRegs:$src1)),
2822 (STrid_indexed (i32 IntRegs:$src2), s11_3ImmPred:$offset,
2823 (i64 DoubleRegs:$src1))>;
2825 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
2826 def : Pat <(and (i32 IntRegs:$src1), 65535),
2827 (ZXTH (i32 IntRegs:$src1))>;
2829 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
2830 def : Pat <(and (i32 IntRegs:$src1), 255),
2831 (ZXTB (i32 IntRegs:$src1))>;
2833 // Map Add(p1, true) to p1 = not(p1).
2834 // Add(p1, false) should never be produced,
2835 // if it does, it got to be mapped to NOOP.
2836 def : Pat <(add (i1 PredRegs:$src1), -1),
2837 (NOT_p (i1 PredRegs:$src1))>;
2839 // Map from p0 = setlt(r0, r1) r2 = mux(p0, r3, r4) =>
2840 // p0 = cmp.lt(r0, r1), r0 = mux(p0, r2, r1).
2841 def : Pat <(select (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2842 (i32 IntRegs:$src3),
2843 (i32 IntRegs:$src4)),
2844 (i32 (TFR_condset_rr (CMPLTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2845 (i32 IntRegs:$src4), (i32 IntRegs:$src3)))>,
2846 Requires<[HasV2TOnly]>;
2848 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
2849 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
2850 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
2853 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
2854 // => r0 = TFR_condset_ri(p0, r1, #i)
2855 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
2856 (i32 IntRegs:$src3)),
2857 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
2858 s12ImmPred:$src2))>;
2860 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
2861 // => r0 = TFR_condset_ir(p0, #i, r1)
2862 def : Pat <(select (not PredRegs:$src1), IntRegs:$src2, s12ImmPred:$src3),
2863 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
2864 (i32 IntRegs:$src2)))>;
2866 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
2867 def : Pat <(brcond (not PredRegs:$src1), bb:$offset),
2868 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
2870 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
2871 def : Pat <(and PredRegs:$src1, (not PredRegs:$src2)),
2872 (i1 (AND_pnotp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2874 // Map from store(globaladdress + x) -> memd(#foo + x).
2875 let AddedComplexity = 100 in
2876 def : Pat <(store (i64 DoubleRegs:$src1),
2877 (add (HexagonCONST32_GP tglobaladdr:$global),
2878 u16ImmPred:$offset)),
2879 (STrid_GP tglobaladdr:$global, u16ImmPred:$offset,
2880 (i64 DoubleRegs:$src1))>, Requires<[NoV4T]>;
2882 // Map from store(globaladdress) -> memd(#foo).
2883 let AddedComplexity = 100 in
2884 def : Pat <(store (i64 DoubleRegs:$src1),
2885 (HexagonCONST32_GP tglobaladdr:$global)),
2886 (STd_GP tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2889 // Map from store(globaladdress + x) -> memw(#foo + x).
2890 let AddedComplexity = 100 in
2891 def : Pat <(store (i32 IntRegs:$src1),
2892 (add (HexagonCONST32_GP tglobaladdr:$global),
2893 u16ImmPred:$offset)),
2894 (STriw_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2897 // Map from store(globaladdress) -> memw(#foo + 0).
2898 let AddedComplexity = 100 in
2899 def : Pat <(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2900 (STriw_GP tglobaladdr:$global, 0, (i32 IntRegs:$src1))>;
2902 // Map from store(globaladdress) -> memw(#foo).
2903 let AddedComplexity = 100 in
2904 def : Pat <(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2905 (STriw_GP tglobaladdr:$global, 0, (i32 IntRegs:$src1))>,
2908 // Map from store(globaladdress + x) -> memh(#foo + x).
2909 let AddedComplexity = 100 in
2910 def : Pat <(truncstorei16 (i32 IntRegs:$src1),
2911 (add (HexagonCONST32_GP tglobaladdr:$global),
2912 u16ImmPred:$offset)),
2913 (STrih_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2916 // Map from store(globaladdress) -> memh(#foo).
2917 let AddedComplexity = 100 in
2918 def : Pat <(truncstorei16 (i32 IntRegs:$src1),
2919 (HexagonCONST32_GP tglobaladdr:$global)),
2920 (STh_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2923 // Map from store(globaladdress + x) -> memb(#foo + x).
2924 let AddedComplexity = 100 in
2925 def : Pat <(truncstorei8 (i32 IntRegs:$src1),
2926 (add (HexagonCONST32_GP tglobaladdr:$global),
2927 u16ImmPred:$offset)),
2928 (STrib_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2931 // Map from store(globaladdress) -> memb(#foo).
2932 let AddedComplexity = 100 in
2933 def : Pat <(truncstorei8 (i32 IntRegs:$src1),
2934 (HexagonCONST32_GP tglobaladdr:$global)),
2935 (STb_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2938 // Map from load(globaladdress + x) -> memw(#foo + x).
2939 let AddedComplexity = 100 in
2940 def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global),
2941 u16ImmPred:$offset))),
2942 (i32 (LDriw_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2945 // Map from load(globaladdress) -> memw(#foo).
2946 let AddedComplexity = 100 in
2947 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
2948 (i32 (LDw_GP tglobaladdr:$global))>,
2951 // Map from load(globaladdress + x) -> memd(#foo + x).
2952 let AddedComplexity = 100 in
2953 def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),
2954 u16ImmPred:$offset))),
2955 (i64 (LDrid_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2958 // Map from load(globaladdress) -> memw(#foo + 0).
2959 let AddedComplexity = 100 in
2960 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
2961 (i64 (LDd_GP tglobaladdr:$global))>,
2964 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd.
2965 let AddedComplexity = 100 in
2966 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
2967 (i1 (TFR_PdRs (i32 (LDb_GP tglobaladdr:$global))))>,
2970 // Map from load(globaladdress + x) -> memh(#foo + x).
2971 let AddedComplexity = 100 in
2972 def : Pat <(i32 (extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2973 u16ImmPred:$offset))),
2974 (i32 (LDrih_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2977 // Map from load(globaladdress + x) -> memh(#foo + x).
2978 let AddedComplexity = 100 in
2979 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2980 (i32 (LDrih_GP tglobaladdr:$global, 0))>,
2983 // Map from load(globaladdress + x) -> memuh(#foo + x).
2984 let AddedComplexity = 100 in
2985 def : Pat <(i32 (zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2986 u16ImmPred:$offset))),
2987 (i32 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2990 // Map from load(globaladdress) -> memuh(#foo).
2991 let AddedComplexity = 100 in
2992 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2993 (i32 (LDriuh_GP tglobaladdr:$global, 0))>,
2996 // Map from load(globaladdress) -> memh(#foo).
2997 let AddedComplexity = 100 in
2998 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2999 (i32 (LDh_GP tglobaladdr:$global))>,
3002 // Map from load(globaladdress) -> memuh(#foo).
3003 let AddedComplexity = 100 in
3004 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3005 (i32 (LDuh_GP tglobaladdr:$global))>,
3008 // Map from load(globaladdress + x) -> memb(#foo + x).
3009 let AddedComplexity = 100 in
3010 def : Pat <(i32 (extloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
3011 u16ImmPred:$offset))),
3012 (i32 (LDrib_GP tglobaladdr:$global, u16ImmPred:$offset))>,
3015 // Map from load(globaladdress + x) -> memb(#foo + x).
3016 let AddedComplexity = 100 in
3017 def : Pat <(i32 (sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
3018 u16ImmPred:$offset))),
3019 (i32 (LDrib_GP tglobaladdr:$global, u16ImmPred:$offset))>,
3022 // Map from load(globaladdress + x) -> memub(#foo + x).
3023 let AddedComplexity = 100 in
3024 def : Pat <(i32 (zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
3025 u16ImmPred:$offset))),
3026 (i32 (LDriub_GP tglobaladdr:$global, u16ImmPred:$offset))>,
3029 // Map from load(globaladdress) -> memb(#foo).
3030 let AddedComplexity = 100 in
3031 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3032 (i32 (LDb_GP tglobaladdr:$global))>,
3035 // Map from load(globaladdress) -> memb(#foo).
3036 let AddedComplexity = 100 in
3037 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3038 (i32 (LDb_GP tglobaladdr:$global))>,
3041 // Map from load(globaladdress) -> memub(#foo).
3042 let AddedComplexity = 100 in
3043 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3044 (i32 (LDub_GP tglobaladdr:$global))>,
3047 // When the Interprocedural Global Variable optimizer realizes that a
3048 // certain global variable takes only two constant values, it shrinks the
3049 // global to a boolean. Catch those loads here in the following 3 patterns.
3050 let AddedComplexity = 100 in
3051 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3052 (i32 (LDb_GP tglobaladdr:$global))>,
3055 let AddedComplexity = 100 in
3056 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3057 (i32 (LDb_GP tglobaladdr:$global))>,
3060 let AddedComplexity = 100 in
3061 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3062 (i32 (LDub_GP tglobaladdr:$global))>,
3065 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
3066 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
3067 (i32 (AND_rr (i32 (LDrib ADDRriS11_0:$addr)), (TFRI 0x1)))>;
3069 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
3070 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
3071 (i64 (SXTW (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
3073 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
3074 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
3075 (i64 (SXTW (i32 (SXTH (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
3076 subreg_loreg))))))>;
3078 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
3079 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
3080 (i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
3081 subreg_loreg))))))>;
3083 // We want to prevent emiting pnot's as much as possible.
3084 // Map brcond with an unsupported setcc to a JMP_cNot.
3085 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3087 (JMP_cNot (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
3090 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
3092 (JMP_cNot (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
3094 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
3095 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
3097 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
3098 (JMP_c (i1 PredRegs:$src1), bb:$offset)>;
3100 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
3102 (JMP_cNot (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2), bb:$offset)>;
3104 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3106 (JMP_c (CMPLTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)), bb:$offset)>;
3108 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3110 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
3113 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3115 (JMP_cNot (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
3118 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3120 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
3123 // Map from a 64-bit select to an emulated 64-bit mux.
3124 // Hexagon does not support 64-bit MUXes; so emulate with combines.
3125 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
3126 (i64 DoubleRegs:$src3)),
3127 (i64 (COMBINE_rr (i32 (MUX_rr (i1 PredRegs:$src1),
3128 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
3130 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
3132 (i32 (MUX_rr (i1 PredRegs:$src1),
3133 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
3135 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
3136 subreg_loreg))))))>;
3138 // Map from a 1-bit select to logical ops.
3139 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
3140 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
3141 (i1 PredRegs:$src3)),
3142 (OR_pp (AND_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
3143 (AND_pp (NOT_p (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
3145 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
3146 def : Pat<(i1 (load ADDRriS11_2:$addr)),
3147 (i1 (TFR_PdRs (i32 (LDrib ADDRriS11_2:$addr))))>;
3149 // Map for truncating from 64 immediates to 32 bit immediates.
3150 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
3151 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
3153 // Map for truncating from i64 immediates to i1 bit immediates.
3154 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
3155 (i1 (TFR_PdRs (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
3158 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
3159 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
3160 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
3163 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
3164 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
3165 (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
3167 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
3168 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
3169 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
3172 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
3173 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
3174 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
3177 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
3178 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
3179 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
3181 let AddedComplexity = 100 in
3182 // Map from i1 = constant<-1>; memw(CONST32(#foo)) = i1 -> r0 = 1;
3184 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
3185 (STb_GP tglobaladdr:$global, (TFRI 1))>,
3188 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
3189 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
3190 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
3192 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
3193 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
3194 (STrib ADDRriS11_2:$addr, (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0)) )>;
3196 // Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs).
3197 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
3198 // Better way to do this?
3199 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
3200 (i64 (SXTW (i32 IntRegs:$src1)))>;
3202 // Map cmple -> cmpgt.
3203 // rs <= rt -> !(rs > rt).
3204 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ImmPred:$src2)),
3205 (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), s10ImmPred:$src2)))>;
3207 // rs <= rt -> !(rs > rt).
3208 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3209 (i1 (NOT_p (CMPGTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
3211 // Rss <= Rtt -> !(Rss > Rtt).
3212 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3213 (i1 (NOT_p (CMPGT64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
3215 // Map cmpne -> cmpeq.
3216 // Hexagon_TODO: We should improve on this.
3217 // rs != rt -> !(rs == rt).
3218 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
3219 (i1 (NOT_p(i1 (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2))))>;
3221 // Map cmpne(Rs) -> !cmpeqe(Rs).
3222 // rs != rt -> !(rs == rt).
3223 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3224 (i1 (NOT_p (i1 (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
3226 // Convert setne back to xor for hexagon since we compute w/ pred registers.
3227 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
3228 (i1 (XOR_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
3230 // Map cmpne(Rss) -> !cmpew(Rss).
3231 // rs != rt -> !(rs == rt).
3232 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3233 (i1 (NOT_p (i1 (CMPEHexagon4rr (i64 DoubleRegs:$src1),
3234 (i64 DoubleRegs:$src2)))))>;
3236 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
3237 // rs >= rt -> !(rt > rs).
3238 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3239 (i1 (NOT_p (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
3241 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ImmPred:$src2)),
3242 (i1 (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2))>;
3244 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
3245 // rss >= rtt -> !(rtt > rss).
3246 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3247 (i1 (NOT_p (i1 (CMPGT64rr (i64 DoubleRegs:$src2),
3248 (i64 DoubleRegs:$src1)))))>;
3250 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
3251 // rs < rt -> !(rs >= rt).
3252 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
3253 (i1 (NOT_p (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2)))>;
3255 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
3256 // rs < rt -> rt > rs.
3257 // We can let assembler map it, or we can do in the compiler itself.
3258 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3259 (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
3261 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
3262 // rss < rtt -> (rtt > rss).
3263 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3264 (i1 (CMPGT64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
3266 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
3267 // rs < rt -> rt > rs.
3268 // We can let assembler map it, or we can do in the compiler itself.
3269 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3270 (i1 (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
3272 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
3273 // rs < rt -> rt > rs.
3274 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3275 (i1 (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
3277 // Generate cmpgeu(Rs, #u8)
3278 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ImmPred:$src2)),
3279 (i1 (CMPGEUri (i32 IntRegs:$src1), u8ImmPred:$src2))>;
3281 // Generate cmpgtu(Rs, #u9)
3282 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ImmPred:$src2)),
3283 (i1 (CMPGTUri (i32 IntRegs:$src1), u9ImmPred:$src2))>;
3285 // Map from Rs >= Rt -> !(Rt > Rs).
3286 // rs >= rt -> !(rt > rs).
3287 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3288 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
3290 // Map from Rs >= Rt -> !(Rt > Rs).
3291 // rs >= rt -> !(rt > rs).
3292 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3293 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
3295 // Map from cmpleu(Rs, Rs) -> !cmpgtu(Rs, Rs).
3296 // Map from (Rs <= Rt) -> !(Rs > Rt).
3297 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3298 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
3300 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
3301 // Map from (Rs <= Rt) -> !(Rs > Rt).
3302 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3303 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
3307 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
3308 (i32 (MUX_ii (i1 PredRegs:$src1), -1, 0))>;
3311 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
3312 (i64 (COMBINE_rr (TFRI -1), (MUX_ii (i1 PredRegs:$src1), -1, 0)))>;
3314 // Convert sign-extended load back to load and sign extend.
3316 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
3317 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
3319 // Convert any-extended load back to load and sign extend.
3321 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
3322 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
3324 // Convert sign-extended load back to load and sign extend.
3326 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
3327 (i64 (SXTW (LDrih ADDRriS11_1:$src1)))>;
3329 // Convert sign-extended load back to load and sign extend.
3331 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
3332 (i64 (SXTW (LDriw ADDRriS11_2:$src1)))>;
3337 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
3338 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
3341 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
3342 (i64 (COMBINE_rr (TFRI 0), (MUX_ii (i1 PredRegs:$src1), 1, 0)))>;
3345 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
3346 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>;
3349 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
3350 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>;
3353 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
3354 (i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>;
3357 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
3358 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>;
3360 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
3361 (i32 (LDriw ADDRriS11_0:$src1))>;
3363 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
3364 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
3365 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
3367 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
3368 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
3369 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
3371 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
3372 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
3373 (i64 (SXTW (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))))>;
3376 // Any extended 64-bit load.
3377 // anyext i32 -> i64
3378 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
3379 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>;
3381 // anyext i16 -> i64.
3382 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
3383 (i64 (COMBINE_rr (TFRI 0), (LDrih ADDRriS11_2:$src1)))>;
3385 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
3386 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
3387 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>;
3389 // Multiply 64-bit unsigned and use upper result.
3390 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
3405 (COMBINE_rr (TFRI 0),
3411 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
3413 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
3414 subreg_loreg)))), 32)),
3416 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3417 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
3418 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
3419 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
3420 32)), subreg_loreg)))),
3421 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3422 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
3424 // Multiply 64-bit signed and use upper result.
3425 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
3429 (COMBINE_rr (TFRI 0),
3439 (COMBINE_rr (TFRI 0),
3445 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
3447 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
3448 subreg_loreg)))), 32)),
3450 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3451 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
3452 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
3453 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
3454 32)), subreg_loreg)))),
3455 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3456 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
3458 // Hexagon specific ISD nodes.
3459 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
3460 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
3461 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
3462 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
3463 SDTHexagonADJDYNALLOC>;
3464 // Needed to tag these instructions for stack layout.
3465 let usesCustomInserter = 1 in
3466 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
3468 "$dst = add($src1, #$src2)",
3469 [(set (i32 IntRegs:$dst),
3470 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
3471 s16ImmPred:$src2))]>;
3473 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
3474 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
3476 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
3478 [(set (i32 IntRegs:$dst),
3479 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
3481 let AddedComplexity = 100 in
3482 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
3483 (COPY (i32 IntRegs:$src1))>;
3485 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
3486 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
3488 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
3489 def BR_JT : JRInst<(outs), (ins IntRegs:$src),
3491 [(HexagonBR_JT (i32 IntRegs:$src))]>;
3493 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
3494 def HexagonWrapperCP: SDNode<"HexagonISD::WrapperCP", SDTIntUnaryOp>;
3496 def : Pat<(HexagonWrapperJT tjumptable:$dst),
3497 (i32 (CONST32_set_jt tjumptable:$dst))>;
3498 def : Pat<(HexagonWrapperCP tconstpool :$dst),
3499 (i32 (CONST32_set_jt tconstpool:$dst))>;
3503 // Multi-class for logical operators :
3504 // Shift by immediate/register and accumulate/logical
3505 multiclass xtype_imm<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
3506 def _ri : SInst_acc<(outs IntRegs:$dst),
3507 (ins IntRegs:$src1, IntRegs:$src2, u5Imm:$src3),
3508 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
3509 [(set (i32 IntRegs:$dst),
3510 (OpNode2 (i32 IntRegs:$src1),
3511 (OpNode1 (i32 IntRegs:$src2),
3512 u5ImmPred:$src3)))],
3515 def d_ri : SInst_acc<(outs DoubleRegs:$dst),
3516 (ins DoubleRegs:$src1, DoubleRegs:$src2, u6Imm:$src3),
3517 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
3518 [(set (i64 DoubleRegs:$dst), (OpNode2 (i64 DoubleRegs:$src1),
3519 (OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
3523 // Multi-class for logical operators :
3524 // Shift by register and accumulate/logical (32/64 bits)
3525 multiclass xtype_reg<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
3526 def _rr : SInst_acc<(outs IntRegs:$dst),
3527 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
3528 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
3529 [(set (i32 IntRegs:$dst),
3530 (OpNode2 (i32 IntRegs:$src1),
3531 (OpNode1 (i32 IntRegs:$src2),
3532 (i32 IntRegs:$src3))))],
3535 def d_rr : SInst_acc<(outs DoubleRegs:$dst),
3536 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3537 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
3538 [(set (i64 DoubleRegs:$dst),
3539 (OpNode2 (i64 DoubleRegs:$src1),
3540 (OpNode1 (i64 DoubleRegs:$src2),
3541 (i32 IntRegs:$src3))))],
3546 multiclass basic_xtype_imm<string OpcStr, SDNode OpNode> {
3547 let AddedComplexity = 100 in
3548 defm _ADD : xtype_imm< !strconcat("+= ", OpcStr), OpNode, add>;
3549 defm _SUB : xtype_imm< !strconcat("-= ", OpcStr), OpNode, sub>;
3550 defm _AND : xtype_imm< !strconcat("&= ", OpcStr), OpNode, and>;
3551 defm _OR : xtype_imm< !strconcat("|= ", OpcStr), OpNode, or>;
3554 multiclass basic_xtype_reg<string OpcStr, SDNode OpNode> {
3555 let AddedComplexity = 100 in
3556 defm _ADD : xtype_reg< !strconcat("+= ", OpcStr), OpNode, add>;
3557 defm _SUB : xtype_reg< !strconcat("-= ", OpcStr), OpNode, sub>;
3558 defm _AND : xtype_reg< !strconcat("&= ", OpcStr), OpNode, and>;
3559 defm _OR : xtype_reg< !strconcat("|= ", OpcStr), OpNode, or>;
3562 multiclass xtype_xor_imm<string OpcStr, SDNode OpNode> {
3563 let AddedComplexity = 100 in
3564 defm _XOR : xtype_imm< !strconcat("^= ", OpcStr), OpNode, xor>;
3567 defm ASL : basic_xtype_imm<"asl", shl>, basic_xtype_reg<"asl", shl>,
3568 xtype_xor_imm<"asl", shl>;
3570 defm LSR : basic_xtype_imm<"lsr", srl>, basic_xtype_reg<"lsr", srl>,
3571 xtype_xor_imm<"lsr", srl>;
3573 defm ASR : basic_xtype_imm<"asr", sra>, basic_xtype_reg<"asr", sra>;
3574 defm LSL : basic_xtype_reg<"lsl", shl>;
3576 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
3577 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
3578 (i32 (MPYI_rin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
3580 //===----------------------------------------------------------------------===//
3581 // V3 Instructions +
3582 //===----------------------------------------------------------------------===//
3584 include "HexagonInstrInfoV3.td"
3586 //===----------------------------------------------------------------------===//
3587 // V3 Instructions -
3588 //===----------------------------------------------------------------------===//
3590 //===----------------------------------------------------------------------===//
3591 // V4 Instructions +
3592 //===----------------------------------------------------------------------===//
3594 include "HexagonInstrInfoV4.td"
3596 //===----------------------------------------------------------------------===//
3597 // V4 Instructions -
3598 //===----------------------------------------------------------------------===//
3600 //===----------------------------------------------------------------------===//
3601 // V5 Instructions +
3602 //===----------------------------------------------------------------------===//
3604 include "HexagonInstrInfoV5.td"
3606 //===----------------------------------------------------------------------===//
3607 // V5 Instructions -
3608 //===----------------------------------------------------------------------===//