1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
17 // Pattern fragment that combines the value type and the register class
18 // into a single parameter.
19 // The pat frags in the definitions below need to have a named register,
20 // otherwise i32 will be assumed regardless of the register class. The
21 // name of the register does not matter.
22 def I1 : PatLeaf<(i1 PredRegs:$R)>;
23 def I32 : PatLeaf<(i32 IntRegs:$R)>;
24 def I64 : PatLeaf<(i64 DoubleRegs:$R)>;
25 def F32 : PatLeaf<(f32 IntRegs:$R)>;
26 def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
28 //===----------------------------------------------------------------------===//
30 //===----------------------------------------------------------------------===//
32 //===----------------------------------------------------------------------===//
33 let hasSideEffects = 0, isCompare = 1, InputType = "imm", isExtendable = 1,
35 class T_CMP <string mnemonic, bits<2> MajOp, bit isNot, Operand ImmOp>
36 : ALU32Inst <(outs PredRegs:$dst),
37 (ins IntRegs:$src1, ImmOp:$src2),
38 "$dst = "#!if(isNot, "!","")#mnemonic#"($src1, #$src2)",
39 [], "",ALU32_2op_tc_2early_SLOT0123 >, ImmRegRel {
43 let CextOpcode = mnemonic;
44 let opExtentBits = !if(!eq(mnemonic, "cmp.gtu"), 9, 10);
45 let isExtentSigned = !if(!eq(mnemonic, "cmp.gtu"), 0, 1);
49 let Inst{27-24} = 0b0101;
50 let Inst{23-22} = MajOp;
51 let Inst{21} = !if(!eq(mnemonic, "cmp.gtu"), 0, src2{9});
52 let Inst{20-16} = src1;
53 let Inst{13-5} = src2{8-0};
59 def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10Ext>;
60 def C2_cmpgti : T_CMP <"cmp.gt", 0b01, 0, s10Ext>;
61 def C2_cmpgtui : T_CMP <"cmp.gtu", 0b10, 0, u9Ext>;
63 class T_CMP_pat <InstHexagon MI, PatFrag OpNode, PatLeaf ImmPred>
64 : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)),
65 (MI IntRegs:$src1, ImmPred:$src2)>;
67 def : T_CMP_pat <C2_cmpeqi, seteq, s10ImmPred>;
68 def : T_CMP_pat <C2_cmpgti, setgt, s10ImmPred>;
69 def : T_CMP_pat <C2_cmpgtui, setugt, u9ImmPred>;
71 // Multi-class for logical operators.
72 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
73 def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
74 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
75 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),
77 def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
78 !strconcat("$dst = ", !strconcat(OpcStr, "(#$b, $c)")),
79 [(set (i32 IntRegs:$dst), (OpNode s10Imm:$b,
83 //===----------------------------------------------------------------------===//
85 //===----------------------------------------------------------------------===//
86 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
87 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
89 def HexagonCOMBINE : SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>;
91 def HexagonWrapperCombineII :
92 SDNode<"HexagonISD::WrapperCombineII", SDTHexagonI64I32I32>;
94 def HexagonWrapperCombineRR :
95 SDNode<"HexagonISD::WrapperCombineRR", SDTHexagonI64I32I32>;
97 let hasSideEffects = 0, hasNewValue = 1, InputType = "reg" in
98 class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev,
100 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
101 "$Rd = "#mnemonic#"($Rs, $Rt)",
102 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredRel {
103 let isCommutable = IsComm;
104 let BaseOpcode = mnemonic#_rr;
105 let CextOpcode = mnemonic;
113 let Inst{26-24} = MajOp;
114 let Inst{23-21} = MinOp;
115 let Inst{20-16} = !if(OpsRev,Rt,Rs);
116 let Inst{12-8} = !if(OpsRev,Rs,Rt);
120 let hasSideEffects = 0, hasNewValue = 1 in
121 class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp,
122 bit OpsRev, bit PredNot, bit PredNew>
123 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
124 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") "#
125 "$Rd = "#mnemonic#"($Rs, $Rt)",
126 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
127 let isPredicated = 1;
128 let isPredicatedFalse = PredNot;
129 let isPredicatedNew = PredNew;
130 let BaseOpcode = mnemonic#_rr;
131 let CextOpcode = mnemonic;
140 let Inst{26-24} = MajOp;
141 let Inst{23-21} = MinOp;
142 let Inst{20-16} = !if(OpsRev,Rt,Rs);
143 let Inst{13} = PredNew;
144 let Inst{12-8} = !if(OpsRev,Rs,Rt);
145 let Inst{7} = PredNot;
150 class T_ALU32_combineh<string Op1, string Op2, bits<3> MajOp, bits<3> MinOp,
152 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, 0> {
153 let AsmString = "$Rd = combine($Rs"#Op1#", $Rt"#Op2#")";
156 let isCodeGenOnly = 0 in {
157 def A2_combine_hh : T_ALU32_combineh<".h", ".h", 0b011, 0b100, 1>;
158 def A2_combine_hl : T_ALU32_combineh<".h", ".l", 0b011, 0b101, 1>;
159 def A2_combine_lh : T_ALU32_combineh<".l", ".h", 0b011, 0b110, 1>;
160 def A2_combine_ll : T_ALU32_combineh<".l", ".l", 0b011, 0b111, 1>;
163 class T_ALU32_3op_sfx<string mnemonic, string suffix, bits<3> MajOp,
164 bits<3> MinOp, bit OpsRev, bit IsComm>
165 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, IsComm> {
166 let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix;
169 let Defs = [USR_OVF], Itinerary = ALU32_3op_tc_2_SLOT0123,
170 isCodeGenOnly = 0 in {
171 def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>;
172 def A2_subsat : T_ALU32_3op_sfx<"sub", ":sat", 0b110, 0b110, 1, 0>;
175 multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,
177 def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>;
178 def f : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 0>;
179 def tnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 1>;
180 def fnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 1>;
183 multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp,
184 bit OpsRev, bit IsComm> {
185 let isPredicable = 1 in
186 def A2_#NAME : T_ALU32_3op <mnemonic, MajOp, MinOp, OpsRev, IsComm>;
187 defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>;
190 let isCodeGenOnly = 0 in {
191 defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
192 defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>;
193 defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>;
194 defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>;
195 defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>;
198 // Pats for instruction selection.
199 class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
200 : Pat<(ResT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
201 (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
203 def: BinOp32_pat<add, A2_add, i32>;
204 def: BinOp32_pat<and, A2_and, i32>;
205 def: BinOp32_pat<or, A2_or, i32>;
206 def: BinOp32_pat<sub, A2_sub, i32>;
207 def: BinOp32_pat<xor, A2_xor, i32>;
209 // A few special cases producing register pairs:
210 let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0,
211 isCodeGenOnly = 0 in {
212 def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>;
214 let isPredicable = 1 in
215 def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>;
217 // Conditional combinew uses "newt/f" instead of "t/fnew".
218 def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>;
219 def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>;
222 let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in
223 class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm>
224 : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
225 "$Pd = "#mnemonic#"($Rs, $Rt)",
226 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
227 let CextOpcode = mnemonic;
228 let isCommutable = IsComm;
234 let Inst{27-24} = 0b0010;
235 let Inst{22-21} = MinOp;
236 let Inst{20-16} = Rs;
239 let Inst{3-2} = 0b00;
243 let Itinerary = ALU32_3op_tc_2early_SLOT0123, isCodeGenOnly = 0 in {
244 def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>;
245 def C2_cmpgt : T_ALU32_3op_cmp< "cmp.gt", 0b10, 0, 0>;
246 def C2_cmpgtu : T_ALU32_3op_cmp< "cmp.gtu", 0b11, 0, 0>;
249 // Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones
250 // that reverse the order of the operands.
251 class RevCmp<PatFrag F> : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment>;
253 // Pats for compares. They use PatFrags as operands, not SDNodes,
254 // since seteq/setgt/etc. are defined as ParFrags.
255 class T_cmp32_rr_pat<InstHexagon MI, PatFrag Op, ValueType VT>
256 : Pat<(VT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
257 (VT (MI IntRegs:$Rs, IntRegs:$Rt))>;
259 def: T_cmp32_rr_pat<C2_cmpeq, seteq, i1>;
260 def: T_cmp32_rr_pat<C2_cmpgt, setgt, i1>;
261 def: T_cmp32_rr_pat<C2_cmpgtu, setugt, i1>;
263 def: T_cmp32_rr_pat<C2_cmpgt, RevCmp<setlt>, i1>;
264 def: T_cmp32_rr_pat<C2_cmpgtu, RevCmp<setult>, i1>;
266 let CextOpcode = "MUX", InputType = "reg", hasNewValue = 1,
268 def C2_mux: ALU32_rr<(outs IntRegs:$Rd),
269 (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
270 "$Rd = mux($Pu, $Rs, $Rt)", [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
276 let CextOpcode = "mux";
277 let InputType = "reg";
278 let hasSideEffects = 0;
281 let Inst{27-24} = 0b0100;
282 let Inst{20-16} = Rs;
288 def: Pat<(i32 (select (i1 PredRegs:$Pu), (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
289 (C2_mux PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt)>;
291 // Combines the two immediates into a double register.
292 // Increase complexity to make it greater than any complexity of a combine
293 // that involves a register.
295 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
296 isExtentSigned = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 1,
297 AddedComplexity = 75, isCodeGenOnly = 0 in
298 def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8),
299 "$Rdd = combine(#$s8, #$S8)",
300 [(set (i64 DoubleRegs:$Rdd),
301 (i64 (HexagonCOMBINE(i32 s8ExtPred:$s8), (i32 s8ImmPred:$S8))))]> {
307 let Inst{27-23} = 0b11000;
308 let Inst{22-16} = S8{7-1};
309 let Inst{13} = S8{0};
314 //===----------------------------------------------------------------------===//
315 // Template class for predicated ADD of a reg and an Immediate value.
316 //===----------------------------------------------------------------------===//
317 let hasNewValue = 1 in
318 class T_Addri_Pred <bit PredNot, bit PredNew>
319 : ALU32_ri <(outs IntRegs:$Rd),
320 (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
321 !if(PredNot, "if (!$Pu", "if ($Pu")#!if(PredNew,".new) $Rd = ",
322 ") $Rd = ")#"add($Rs, #$s8)"> {
328 let isPredicatedNew = PredNew;
331 let Inst{27-24} = 0b0100;
332 let Inst{23} = PredNot;
333 let Inst{22-21} = Pu;
334 let Inst{20-16} = Rs;
335 let Inst{13} = PredNew;
340 //===----------------------------------------------------------------------===//
341 // A2_addi: Add a signed immediate to a register.
342 //===----------------------------------------------------------------------===//
343 let hasNewValue = 1 in
344 class T_Addri <Operand immOp, list<dag> pattern = [] >
345 : ALU32_ri <(outs IntRegs:$Rd),
346 (ins IntRegs:$Rs, immOp:$s16),
347 "$Rd = add($Rs, #$s16)", pattern,
348 //[(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs), (s16ExtPred:$s16)))],
349 "", ALU32_ADDI_tc_1_SLOT0123> {
356 let Inst{27-21} = s16{15-9};
357 let Inst{20-16} = Rs;
358 let Inst{13-5} = s16{8-0};
362 //===----------------------------------------------------------------------===//
363 // Multiclass for ADD of a register and an immediate value.
364 //===----------------------------------------------------------------------===//
365 multiclass Addri_Pred<string mnemonic, bit PredNot> {
366 let isPredicatedFalse = PredNot in {
367 def _c#NAME : T_Addri_Pred<PredNot, 0>;
369 def _cdn#NAME : T_Addri_Pred<PredNot, 1>;
373 let isExtendable = 1, InputType = "imm" in
374 multiclass Addri_base<string mnemonic, SDNode OpNode> {
375 let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in {
376 let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
378 def NAME : T_Addri< s16Ext, // Rd=add(Rs,#s16)
379 [(set (i32 IntRegs:$Rd),
380 (add IntRegs:$Rs, s16ExtPred:$s16))]>;
382 let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
383 hasSideEffects = 0, isPredicated = 1 in {
384 defm Pt : Addri_Pred<mnemonic, 0>;
385 defm NotPt : Addri_Pred<mnemonic, 1>;
390 let isCodeGenOnly = 0 in
391 defm ADD_ri : Addri_base<"add", add>, ImmRegRel, PredNewRel;
393 //===----------------------------------------------------------------------===//
394 // Template class used for the following ALU32 instructions.
397 //===----------------------------------------------------------------------===//
398 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
399 InputType = "imm", hasNewValue = 1 in
400 class T_ALU32ri_logical <string mnemonic, SDNode OpNode, bits<2> MinOp>
401 : ALU32_ri <(outs IntRegs:$Rd),
402 (ins IntRegs:$Rs, s10Ext:$s10),
403 "$Rd = "#mnemonic#"($Rs, #$s10)" ,
404 [(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s10ExtPred:$s10))]> {
408 let CextOpcode = mnemonic;
412 let Inst{27-24} = 0b0110;
413 let Inst{23-22} = MinOp;
414 let Inst{21} = s10{9};
415 let Inst{20-16} = Rs;
416 let Inst{13-5} = s10{8-0};
420 let isCodeGenOnly = 0 in {
421 def OR_ri : T_ALU32ri_logical<"or", or, 0b10>, ImmRegRel;
422 def AND_ri : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel;
425 // Subtract register from immediate
426 // Rd32=sub(#s10,Rs32)
427 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
428 CextOpcode = "sub", InputType = "imm", hasNewValue = 1, isCodeGenOnly = 0 in
429 def SUB_ri: ALU32_ri <(outs IntRegs:$Rd), (ins s10Ext:$s10, IntRegs:$Rs),
430 "$Rd = sub(#$s10, $Rs)" ,
431 [(set IntRegs:$Rd, (sub s10ExtPred:$s10, IntRegs:$Rs))] > ,
439 let Inst{27-22} = 0b011001;
440 let Inst{21} = s10{9};
441 let Inst{20-16} = Rs;
442 let Inst{13-5} = s10{8-0};
447 let hasSideEffects = 0, isCodeGenOnly = 0 in
448 def A2_nop: ALU32Inst <(outs), (ins), "nop" > {
450 let Inst{27-24} = 0b1111;
452 // Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
453 def : Pat<(not (i32 IntRegs:$src1)),
454 (SUB_ri -1, (i32 IntRegs:$src1))>;
456 multiclass ALU32_Pbase<string mnemonic, RegisterClass RC, bit isNot,
458 let isPredicatedNew = isPredNew in
459 def NAME : ALU32_rr<(outs RC:$dst),
460 (ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
461 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
462 ") $dst = ")#mnemonic#"($src2, $src3)",
466 let hasSideEffects = 0, hasNewValue = 1 in
467 class T_tfr16<bit isHi>
468 : ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16Imm:$u16),
469 "$Rx"#!if(isHi, ".h", ".l")#" = #$u16",
470 [], "$src1 = $Rx" > {
475 let Inst{27-26} = 0b00;
476 let Inst{25-24} = !if(isHi, 0b10, 0b01);
477 let Inst{23-22} = u16{15-14};
479 let Inst{20-16} = Rx;
480 let Inst{13-0} = u16{13-0};
483 let isCodeGenOnly = 0 in {
484 def A2_tfril: T_tfr16<0>;
485 def A2_tfrih: T_tfr16<1>;
488 multiclass ALU32_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
489 let isPredicatedFalse = PredNot in {
490 defm _c#NAME : ALU32_Pbase<mnemonic, RC, PredNot, 0>;
492 defm _cdn#NAME : ALU32_Pbase<mnemonic, RC, PredNot, 1>;
496 // Combines the two integer registers SRC1 and SRC2 into a double register.
497 let isPredicable = 1 in
498 class T_Combine : ALU32_rr<(outs DoubleRegs:$dst),
499 (ins IntRegs:$src1, IntRegs:$src2),
500 "$dst = combine($src1, $src2)",
501 [(set (i64 DoubleRegs:$dst),
502 (i64 (HexagonWrapperCombineRR (i32 IntRegs:$src1),
503 (i32 IntRegs:$src2))))]>;
505 multiclass Combine_base {
506 let BaseOpcode = "combine" in {
507 def NAME : T_Combine;
508 let hasSideEffects = 0, isPredicated = 1 in {
509 defm Pt : ALU32_Pred<"combine", DoubleRegs, 0>;
510 defm NotPt : ALU32_Pred<"combine", DoubleRegs, 1>;
515 defm COMBINE_rr : Combine_base, PredNewRel;
517 // Combines the two immediates SRC1 and SRC2 into a double register.
518 class COMBINE_imm<Operand imm1, Operand imm2, PatLeaf pat1, PatLeaf pat2> :
519 ALU32_ii<(outs DoubleRegs:$dst), (ins imm1:$src1, imm2:$src2),
520 "$dst = combine(#$src1, #$src2)",
521 [(set (i64 DoubleRegs:$dst),
522 (i64 (HexagonWrapperCombineII (i32 pat1:$src1), (i32 pat2:$src2))))]>;
524 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8 in
525 def COMBINE_Ii : COMBINE_imm<s8Ext, s8Imm, s8ExtPred, s8ImmPred>;
527 // Rd = neg(Rs) gets mapped to Rd=sub(#0, Rs).
528 // Pattern definition for 'neg' was not necessary.
530 multiclass TFR_Pred<bit PredNot> {
531 let isPredicatedFalse = PredNot in {
532 def _c#NAME : ALU32_rr<(outs IntRegs:$dst),
533 (ins PredRegs:$src1, IntRegs:$src2),
534 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
537 let isPredicatedNew = 1 in
538 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
539 (ins PredRegs:$src1, IntRegs:$src2),
540 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
545 let InputType = "reg", hasSideEffects = 0 in
546 multiclass TFR_base<string CextOp> {
547 let CextOpcode = CextOp, BaseOpcode = CextOp in {
548 let isPredicable = 1 in
549 def NAME : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
553 let isPredicated = 1 in {
554 defm Pt : TFR_Pred<0>;
555 defm NotPt : TFR_Pred<1>;
560 class T_TFR64_Pred<bit PredNot, bit isPredNew>
561 : ALU32_rr<(outs DoubleRegs:$dst),
562 (ins PredRegs:$src1, DoubleRegs:$src2),
563 !if(PredNot, "if (!$src1", "if ($src1")#
564 !if(isPredNew, ".new) ", ") ")#"$dst = $src2", []>
571 let Inst{27-24} = 0b1101;
572 let Inst{13} = isPredNew;
573 let Inst{7} = PredNot;
575 let Inst{6-5} = src1;
576 let Inst{20-17} = src2{4-1};
578 let Inst{12-9} = src2{4-1};
582 multiclass TFR64_Pred<bit PredNot> {
583 let isPredicatedFalse = PredNot in {
584 def _c#NAME : T_TFR64_Pred<PredNot, 0>;
586 let isPredicatedNew = 1 in
587 def _cdn#NAME : T_TFR64_Pred<PredNot, 1>; // Predicate new
591 let hasSideEffects = 0 in
592 multiclass TFR64_base<string BaseName> {
593 let BaseOpcode = BaseName in {
594 let isPredicable = 1 in
595 def NAME : ALU32Inst <(outs DoubleRegs:$dst),
596 (ins DoubleRegs:$src1),
602 let Inst{27-23} = 0b01010;
604 let Inst{20-17} = src1{4-1};
606 let Inst{12-9} = src1{4-1};
610 let isPredicated = 1 in {
611 defm Pt : TFR64_Pred<0>;
612 defm NotPt : TFR64_Pred<1>;
617 multiclass TFRI_Pred<bit PredNot> {
618 let isMoveImm = 1, isPredicatedFalse = PredNot in {
619 def _c#NAME : ALU32_ri<(outs IntRegs:$dst),
620 (ins PredRegs:$src1, s12Ext:$src2),
621 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = #$src2",
625 let isPredicatedNew = 1 in
626 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
627 (ins PredRegs:$src1, s12Ext:$src2),
628 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = #$src2",
633 let InputType = "imm", isExtendable = 1, isExtentSigned = 1 in
634 multiclass TFRI_base<string CextOp> {
635 let CextOpcode = CextOp, BaseOpcode = CextOp#I in {
636 let isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16,
637 isMoveImm = 1, isPredicable = 1, isReMaterializable = 1 in
638 def NAME : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
640 [(set (i32 IntRegs:$dst), s16ExtPred:$src1)]>;
642 let opExtendable = 2, opExtentBits = 12, hasSideEffects = 0,
643 isPredicated = 1 in {
644 defm Pt : TFRI_Pred<0>;
645 defm NotPt : TFRI_Pred<1>;
650 defm TFRI : TFRI_base<"TFR">, ImmRegRel, PredNewRel;
651 defm TFR : TFR_base<"TFR">, ImmRegRel, PredNewRel;
652 defm TFR64 : TFR64_base<"TFR64">, PredNewRel;
654 // Transfer control register.
655 let hasSideEffects = 0 in
656 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
659 //===----------------------------------------------------------------------===//
661 //===----------------------------------------------------------------------===//
664 //===----------------------------------------------------------------------===//
666 //===----------------------------------------------------------------------===//
667 // Scalar mux register immediate.
668 let hasSideEffects = 0, isExtentSigned = 1, CextOpcode = "MUX",
669 InputType = "imm", hasNewValue = 1, isExtendable = 1, opExtentBits = 8 in
670 class T_MUX1 <bit MajOp, dag ins, string AsmStr>
671 : ALU32Inst <(outs IntRegs:$Rd), ins, AsmStr>, ImmRegRel {
678 let Inst{27-24} = 0b0011;
679 let Inst{23} = MajOp;
680 let Inst{22-21} = Pu;
681 let Inst{20-16} = Rs;
687 let opExtendable = 2, isCodeGenOnly = 0 in
688 def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8Ext:$s8, IntRegs:$Rs),
689 "$Rd = mux($Pu, #$s8, $Rs)">;
691 let opExtendable = 3, isCodeGenOnly = 0 in
692 def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
693 "$Rd = mux($Pu, $Rs, #$s8)">;
695 def : Pat<(i32 (select I1:$Pu, s8ExtPred:$s8, I32:$Rs)),
696 (C2_muxri I1:$Pu, s8ExtPred:$s8, I32:$Rs)>;
698 def : Pat<(i32 (select I1:$Pu, I32:$Rs, s8ExtPred:$s8)),
699 (C2_muxir I1:$Pu, I32:$Rs, s8ExtPred:$s8)>;
701 // C2_muxii: Scalar mux immediates.
702 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1,
703 opExtentBits = 8, opExtendable = 2, isCodeGenOnly = 0 in
704 def C2_muxii: ALU32Inst <(outs IntRegs:$Rd),
705 (ins PredRegs:$Pu, s8Ext:$s8, s8Imm:$S8),
706 "$Rd = mux($Pu, #$s8, #$S8)" ,
707 [(set (i32 IntRegs:$Rd),
708 (i32 (select I1:$Pu, s8ExtPred:$s8, s8ImmPred:$S8)))] > {
716 let Inst{27-25} = 0b101;
717 let Inst{24-23} = Pu;
718 let Inst{22-16} = S8{7-1};
719 let Inst{13} = S8{0};
724 //===----------------------------------------------------------------------===//
725 // template class for non-predicated alu32_2op instructions
726 // - aslh, asrh, sxtb, sxth, zxth
727 //===----------------------------------------------------------------------===//
728 let hasNewValue = 1, opNewValue = 0 in
729 class T_ALU32_2op <string mnemonic, bits<3> minOp> :
730 ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
731 "$Rd = "#mnemonic#"($Rs)", [] > {
737 let Inst{27-24} = 0b0000;
738 let Inst{23-21} = minOp;
741 let Inst{20-16} = Rs;
744 //===----------------------------------------------------------------------===//
745 // template class for predicated alu32_2op instructions
746 // - aslh, asrh, sxtb, sxth, zxtb, zxth
747 //===----------------------------------------------------------------------===//
748 let hasSideEffects = 0, validSubTargets = HasV4SubT,
749 hasNewValue = 1, opNewValue = 0 in
750 class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot,
752 ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
753 !if(isPredNot, "if (!$Pu", "if ($Pu")
754 #!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> {
761 let Inst{27-24} = 0b0000;
762 let Inst{23-21} = minOp;
764 let Inst{11} = isPredNot;
765 let Inst{10} = isPredNew;
768 let Inst{20-16} = Rs;
771 multiclass ALU32_2op_Pred<string mnemonic, bits<3> minOp, bit PredNot> {
772 let isPredicatedFalse = PredNot in {
773 def NAME : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 0>;
776 let isPredicatedNew = 1 in
777 def NAME#new : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 1>;
781 multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
782 let BaseOpcode = mnemonic in {
783 let isPredicable = 1, hasSideEffects = 0 in
784 def A2_#NAME : T_ALU32_2op<mnemonic, minOp>;
786 let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
787 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
788 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
793 let isCodeGenOnly = 0 in {
794 defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
795 defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel;
796 defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
797 defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
798 defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
801 // Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
802 // Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has
803 // predicated forms while 'and' doesn't. Since integrated assembler can't
804 // handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where
805 // immediate operand is set to '255'.
807 let hasNewValue = 1, opNewValue = 0 in
808 class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
809 "$Rd = zxtb($Rs)", [] > { // Rd = and(Rs,255)
816 let Inst{27-22} = 0b011000;
818 let Inst{20-16} = Rs;
819 let Inst{21} = s10{9};
820 let Inst{13-5} = s10{8-0};
823 //Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255)
824 multiclass ZXTB_base <string mnemonic, bits<3> minOp> {
825 let BaseOpcode = mnemonic in {
826 let isPredicable = 1, hasSideEffects = 0 in
827 def A2_#NAME : T_ZXTB;
829 let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
830 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
831 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
836 let isCodeGenOnly=0 in
837 defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
839 def: Pat<(shl I32:$src1, (i32 16)), (A2_aslh I32:$src1)>;
840 def: Pat<(sra I32:$src1, (i32 16)), (A2_asrh I32:$src1)>;
841 def: Pat<(sext_inreg I32:$src1, i8), (A2_sxtb I32:$src1)>;
842 def: Pat<(sext_inreg I32:$src1, i16), (A2_sxth I32:$src1)>;
845 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
848 "$dst = vmux($src1, $src2, $src3)",
852 //===----------------------------------------------------------------------===//
854 //===----------------------------------------------------------------------===//
857 //===----------------------------------------------------------------------===//
859 //===----------------------------------------------------------------------===//
861 // SDNode for converting immediate C to C-1.
862 def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
863 // Return the byte immediate const-1 as an SDNode.
864 int32_t imm = N->getSExtValue();
865 return XformSToSM1Imm(imm);
868 // SDNode for converting immediate C to C-1.
869 def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
870 // Return the byte immediate const-1 as an SDNode.
871 uint32_t imm = N->getZExtValue();
872 return XformUToUM1Imm(imm);
875 def CTLZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
877 [(set (i32 IntRegs:$dst), (ctlz (i32 IntRegs:$src1)))]>;
879 def CTTZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
881 [(set (i32 IntRegs:$dst), (cttz (i32 IntRegs:$src1)))]>;
883 def CTLZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
885 [(set (i32 IntRegs:$dst), (i32 (trunc (ctlz (i64 DoubleRegs:$src1)))))]>;
887 def CTTZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
889 [(set (i32 IntRegs:$dst), (i32 (trunc (cttz (i64 DoubleRegs:$src1)))))]>;
891 def TSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
892 "$dst = tstbit($src1, $src2)",
893 [(set (i1 PredRegs:$dst),
894 (setne (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>;
896 def TSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
897 "$dst = tstbit($src1, $src2)",
898 [(set (i1 PredRegs:$dst),
899 (setne (and (shl 1, (u5ImmPred:$src2)), (i32 IntRegs:$src1)), 0))]>;
901 //===----------------------------------------------------------------------===//
903 //===----------------------------------------------------------------------===//
906 //===----------------------------------------------------------------------===//
908 //===----------------------------------------------------------------------===//// Add.
909 //===----------------------------------------------------------------------===//
911 // Add/Subtract halfword
912 // Rd=add(Rt.L,Rs.[HL])[:sat]
913 // Rd=sub(Rt.L,Rs.[HL])[:sat]
914 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
915 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
916 //===----------------------------------------------------------------------===//
918 let hasNewValue = 1, opNewValue = 0 in
919 class T_XTYPE_ADD_SUB <bits<2> LHbits, bit isSat, bit hasShift, bit isSub>
920 : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
921 "$Rd = "#!if(isSub,"sub","add")#"($Rt."
922 #!if(hasShift, !if(LHbits{1},"h","l"),"l") #", $Rs."
923 #!if(hasShift, !if(LHbits{0},"h)","l)"), !if(LHbits{1},"h)","l)"))
924 #!if(isSat,":sat","")
925 #!if(hasShift,":<<16",""), [], "", ALU64_tc_1_SLOT23> {
931 let Inst{27-23} = 0b01010;
932 let Inst{22} = hasShift;
933 let Inst{21} = isSub;
935 let Inst{6-5} = LHbits;
938 let Inst{20-16} = Rs;
941 //Rd=sub(Rt.L,Rs.[LH])
942 let isCodeGenOnly = 0 in {
943 def A2_subh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 1>;
944 def A2_subh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 1>;
947 let isCodeGenOnly = 0 in {
948 //Rd=add(Rt.L,Rs.[LH])
949 def A2_addh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 0>;
950 def A2_addh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 0>;
953 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in {
954 //Rd=sub(Rt.L,Rs.[LH]):sat
955 def A2_subh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 1>;
956 def A2_subh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 1>;
958 //Rd=add(Rt.L,Rs.[LH]):sat
959 def A2_addh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 0>;
960 def A2_addh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 0>;
963 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
964 let isCodeGenOnly = 0 in {
965 def A2_subh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 1>;
966 def A2_subh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 1>;
967 def A2_subh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 1>;
968 def A2_subh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 1>;
971 //Rd=add(Rt.[LH],Rs.[LH]):<<16
972 let isCodeGenOnly = 0 in {
973 def A2_addh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 0>;
974 def A2_addh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 0>;
975 def A2_addh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 0>;
976 def A2_addh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 0>;
979 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in {
980 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
981 def A2_subh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 1>;
982 def A2_subh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 1>;
983 def A2_subh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 1>;
984 def A2_subh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 1>;
986 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
987 def A2_addh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 0>;
988 def A2_addh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 0>;
989 def A2_addh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 0>;
990 def A2_addh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 0>;
994 def: Pat<(sext_inreg (add I32:$src1, I32:$src2), i16),
995 (A2_addh_l16_ll I32:$src1, I32:$src2)>;
997 def: Pat<(sra (add (shl I32:$src1, (i32 16)), I32:$src2), (i32 16)),
998 (A2_addh_l16_hl I32:$src1, I32:$src2)>;
1000 def: Pat<(shl (add I32:$src1, I32:$src2), (i32 16)),
1001 (A2_addh_h16_ll I32:$src1, I32:$src2)>;
1003 // Subtract halfword.
1004 def: Pat<(sext_inreg (sub I32:$src1, I32:$src2), i16),
1005 (A2_subh_l16_ll I32:$src1, I32:$src2)>;
1007 def: Pat<(shl (sub I32:$src1, I32:$src2), (i32 16)),
1008 (A2_subh_h16_ll I32:$src1, I32:$src2)>;
1010 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
1011 def S2_parityp: ALU64Inst<(outs IntRegs:$Rd),
1012 (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1013 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1018 let IClass = 0b1101;
1019 let Inst{27-24} = 0b0000;
1020 let Inst{20-16} = Rs;
1021 let Inst{12-8} = Rt;
1025 let hasNewValue = 1, opNewValue = 0, hasSideEffects = 0 in
1026 class T_XTYPE_MIN_MAX < bit isMax, bit isUnsigned >
1027 : ALU64Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1028 "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
1029 #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
1034 let IClass = 0b1101;
1036 let Inst{27-23} = 0b01011;
1037 let Inst{22-21} = !if(isMax, 0b10, 0b01);
1038 let Inst{7} = isUnsigned;
1040 let Inst{12-8} = !if(isMax, Rs, Rt);
1041 let Inst{20-16} = !if(isMax, Rt, Rs);
1044 let isCodeGenOnly = 0 in {
1045 def A2_min : T_XTYPE_MIN_MAX < 0, 0 >;
1046 def A2_minu : T_XTYPE_MIN_MAX < 0, 1 >;
1047 def A2_max : T_XTYPE_MIN_MAX < 1, 0 >;
1048 def A2_maxu : T_XTYPE_MIN_MAX < 1, 1 >;
1051 // Here, depending on the operand being selected, we'll either generate a
1052 // min or max instruction.
1054 // (a>b)?a:b --> max(a,b) => Here check performed is '>' and the value selected
1055 // is the larger of two. So, the corresponding HexagonInst is passed in 'Inst'.
1056 // (a>b)?b:a --> min(a,b) => Here check performed is '>' but the smaller value
1057 // is selected and the corresponding HexagonInst is passed in 'SwapInst'.
1059 multiclass T_MinMax_pats <PatFrag Op, RegisterClass RC, ValueType VT,
1060 InstHexagon Inst, InstHexagon SwapInst> {
1061 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1062 (VT RC:$src1), (VT RC:$src2)),
1063 (Inst RC:$src1, RC:$src2)>;
1064 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1065 (VT RC:$src2), (VT RC:$src1)),
1066 (SwapInst RC:$src1, RC:$src2)>;
1070 multiclass MinMax_pats <PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
1071 defm: T_MinMax_pats<Op, IntRegs, i32, Inst, SwapInst>;
1073 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1074 (i32 PositiveHalfWord:$src2))),
1075 (i32 PositiveHalfWord:$src1),
1076 (i32 PositiveHalfWord:$src2))), i16),
1077 (Inst IntRegs:$src1, IntRegs:$src2)>;
1079 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1080 (i32 PositiveHalfWord:$src2))),
1081 (i32 PositiveHalfWord:$src2),
1082 (i32 PositiveHalfWord:$src1))), i16),
1083 (SwapInst IntRegs:$src1, IntRegs:$src2)>;
1086 let AddedComplexity = 200 in {
1087 defm: MinMax_pats<setge, A2_max, A2_min>;
1088 defm: MinMax_pats<setgt, A2_max, A2_min>;
1089 defm: MinMax_pats<setle, A2_min, A2_max>;
1090 defm: MinMax_pats<setlt, A2_min, A2_max>;
1091 defm: MinMax_pats<setuge, A2_maxu, A2_minu>;
1092 defm: MinMax_pats<setugt, A2_maxu, A2_minu>;
1093 defm: MinMax_pats<setule, A2_minu, A2_maxu>;
1094 defm: MinMax_pats<setult, A2_minu, A2_maxu>;
1097 class T_cmp64_rr<string mnemonic, bits<3> MinOp, bit IsComm>
1098 : ALU64_rr<(outs PredRegs:$Pd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1099 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", ALU64_tc_2early_SLOT23> {
1101 let isCommutable = IsComm;
1102 let hasSideEffects = 0;
1108 let IClass = 0b1101;
1109 let Inst{27-21} = 0b0010100;
1110 let Inst{20-16} = Rs;
1111 let Inst{12-8} = Rt;
1112 let Inst{7-5} = MinOp;
1116 let isCodeGenOnly = 0 in {
1117 def C2_cmpeqp : T_cmp64_rr<"cmp.eq", 0b000, 1>;
1118 def C2_cmpgtp : T_cmp64_rr<"cmp.gt", 0b010, 0>;
1119 def C2_cmpgtup : T_cmp64_rr<"cmp.gtu", 0b100, 0>;
1122 class T_cmp64_rr_pat<InstHexagon MI, PatFrag CmpOp>
1123 : Pat<(i1 (CmpOp (i64 DoubleRegs:$Rs), (i64 DoubleRegs:$Rt))),
1124 (i1 (MI DoubleRegs:$Rs, DoubleRegs:$Rt))>;
1126 def: T_cmp64_rr_pat<C2_cmpeqp, seteq>;
1127 def: T_cmp64_rr_pat<C2_cmpgtp, setgt>;
1128 def: T_cmp64_rr_pat<C2_cmpgtup, setugt>;
1129 def: T_cmp64_rr_pat<C2_cmpgtp, RevCmp<setlt>>;
1130 def: T_cmp64_rr_pat<C2_cmpgtup, RevCmp<setult>>;
1132 class T_ALU64_rr<string mnemonic, string suffix, bits<4> RegType,
1133 bits<3> MajOp, bits<3> MinOp, bit OpsRev, bit IsComm,
1135 : ALU64_rr<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1136 "$Rd = " #mnemonic# "($Rs, " #Op2Pfx# "$Rt)" #suffix, [],
1137 "", ALU64_tc_1_SLOT23> {
1138 let hasSideEffects = 0;
1139 let isCommutable = IsComm;
1145 let IClass = 0b1101;
1146 let Inst{27-24} = RegType;
1147 let Inst{23-21} = MajOp;
1148 let Inst{20-16} = !if (OpsRev,Rt,Rs);
1149 let Inst{12-8} = !if (OpsRev,Rs,Rt);
1150 let Inst{7-5} = MinOp;
1154 class T_ALU64_arith<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit IsSat,
1155 bit OpsRev, bit IsComm>
1156 : T_ALU64_rr<mnemonic, !if(IsSat,":sat",""), 0b0011, MajOp, MinOp, OpsRev,
1159 let isCodeGenOnly = 0 in {
1160 def A2_addp : T_ALU64_arith<"add", 0b000, 0b111, 0, 0, 1>;
1161 def A2_subp : T_ALU64_arith<"sub", 0b001, 0b111, 0, 1, 0>;
1164 def: Pat<(i64 (add I64:$Rs, I64:$Rt)), (A2_addp I64:$Rs, I64:$Rt)>;
1165 def: Pat<(i64 (sub I64:$Rs, I64:$Rt)), (A2_subp I64:$Rs, I64:$Rt)>;
1167 class T_ALU64_logical<string mnemonic, bits<3> MinOp, bit OpsRev, bit IsComm,
1169 : T_ALU64_rr<mnemonic, "", 0b0011, 0b111, MinOp, OpsRev, IsComm,
1172 let isCodeGenOnly = 0 in {
1173 def A2_andp : T_ALU64_logical<"and", 0b000, 0, 1, 0>;
1174 def A2_orp : T_ALU64_logical<"or", 0b010, 0, 1, 0>;
1175 def A2_xorp : T_ALU64_logical<"xor", 0b100, 0, 1, 0>;
1178 def: Pat<(i64 (and I64:$Rs, I64:$Rt)), (A2_andp I64:$Rs, I64:$Rt)>;
1179 def: Pat<(i64 (or I64:$Rs, I64:$Rt)), (A2_orp I64:$Rs, I64:$Rt)>;
1180 def: Pat<(i64 (xor I64:$Rs, I64:$Rt)), (A2_xorp I64:$Rs, I64:$Rt)>;
1182 def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1184 "$dst = add($src1, $src2)",
1185 [(set (i64 DoubleRegs:$dst), (add (i64 DoubleRegs:$src1),
1186 (i64 DoubleRegs:$src2)))]>;
1188 // Logical operations.
1189 def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1191 "$dst = and($src1, $src2)",
1192 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
1193 (i64 DoubleRegs:$src2)))]>;
1195 def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1197 "$dst = or($src1, $src2)",
1198 [(set (i64 DoubleRegs:$dst), (or (i64 DoubleRegs:$src1),
1199 (i64 DoubleRegs:$src2)))]>;
1201 def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1203 "$dst = xor($src1, $src2)",
1204 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
1205 (i64 DoubleRegs:$src2)))]>;
1208 def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1209 "$dst = max($src2, $src1)",
1210 [(set (i32 IntRegs:$dst),
1211 (i32 (select (i1 (setlt (i32 IntRegs:$src2),
1212 (i32 IntRegs:$src1))),
1213 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
1215 def MAXUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1216 "$dst = maxu($src2, $src1)",
1217 [(set (i32 IntRegs:$dst),
1218 (i32 (select (i1 (setult (i32 IntRegs:$src2),
1219 (i32 IntRegs:$src1))),
1220 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
1222 def MAXd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1224 "$dst = max($src2, $src1)",
1225 [(set (i64 DoubleRegs:$dst),
1226 (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
1227 (i64 DoubleRegs:$src1))),
1228 (i64 DoubleRegs:$src1),
1229 (i64 DoubleRegs:$src2))))]>;
1231 def MAXUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1233 "$dst = maxu($src2, $src1)",
1234 [(set (i64 DoubleRegs:$dst),
1235 (i64 (select (i1 (setult (i64 DoubleRegs:$src2),
1236 (i64 DoubleRegs:$src1))),
1237 (i64 DoubleRegs:$src1),
1238 (i64 DoubleRegs:$src2))))]>;
1241 def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1242 "$dst = min($src2, $src1)",
1243 [(set (i32 IntRegs:$dst),
1244 (i32 (select (i1 (setgt (i32 IntRegs:$src2),
1245 (i32 IntRegs:$src1))),
1246 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
1248 def MINUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1249 "$dst = minu($src2, $src1)",
1250 [(set (i32 IntRegs:$dst),
1251 (i32 (select (i1 (setugt (i32 IntRegs:$src2),
1252 (i32 IntRegs:$src1))),
1253 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
1255 def MINd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1257 "$dst = min($src2, $src1)",
1258 [(set (i64 DoubleRegs:$dst),
1259 (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
1260 (i64 DoubleRegs:$src1))),
1261 (i64 DoubleRegs:$src1),
1262 (i64 DoubleRegs:$src2))))]>;
1264 def MINUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1266 "$dst = minu($src2, $src1)",
1267 [(set (i64 DoubleRegs:$dst),
1268 (i64 (select (i1 (setugt (i64 DoubleRegs:$src2),
1269 (i64 DoubleRegs:$src1))),
1270 (i64 DoubleRegs:$src1),
1271 (i64 DoubleRegs:$src2))))]>;
1274 def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1276 "$dst = sub($src1, $src2)",
1277 [(set (i64 DoubleRegs:$dst), (sub (i64 DoubleRegs:$src1),
1278 (i64 DoubleRegs:$src2)))]>;
1280 // Subtract halfword.
1282 //===----------------------------------------------------------------------===//
1284 //===----------------------------------------------------------------------===//
1286 //===----------------------------------------------------------------------===//
1288 //===----------------------------------------------------------------------===//
1290 //===----------------------------------------------------------------------===//
1292 //===----------------------------------------------------------------------===//
1294 //===----------------------------------------------------------------------===//
1296 //===----------------------------------------------------------------------===//
1298 //===----------------------------------------------------------------------===//
1300 //===----------------------------------------------------------------------===//
1302 //===----------------------------------------------------------------------===//
1304 //===----------------------------------------------------------------------===//
1305 // Logical reductions on predicates.
1307 // Looping instructions.
1309 // Pipelined looping instructions.
1311 // Logical operations on predicates.
1312 def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
1313 "$dst = and($src1, $src2)",
1314 [(set (i1 PredRegs:$dst), (and (i1 PredRegs:$src1),
1315 (i1 PredRegs:$src2)))]>;
1317 let hasSideEffects = 0 in
1318 def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
1320 "$dst = and($src1, !$src2)",
1323 def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
1324 "$dst = any8($src1)",
1327 def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
1328 "$dst = all8($src1)",
1331 def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
1333 "$dst = vitpack($src1, $src2)",
1336 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1339 "$dst = valignb($src1, $src2, $src3)",
1342 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1345 "$dst = vspliceb($src1, $src2, $src3)",
1348 def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
1349 "$dst = mask($src1)",
1352 def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
1353 "$dst = not($src1)",
1354 [(set (i1 PredRegs:$dst), (not (i1 PredRegs:$src1)))]>;
1356 def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
1357 "$dst = or($src1, $src2)",
1358 [(set (i1 PredRegs:$dst), (or (i1 PredRegs:$src1),
1359 (i1 PredRegs:$src2)))]>;
1361 def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
1362 "$dst = xor($src1, $src2)",
1363 [(set (i1 PredRegs:$dst), (xor (i1 PredRegs:$src1),
1364 (i1 PredRegs:$src2)))]>;
1367 // User control register transfer.
1368 //===----------------------------------------------------------------------===//
1370 //===----------------------------------------------------------------------===//
1372 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
1373 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1374 def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone,
1377 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
1378 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
1380 let InputType = "imm", isBarrier = 1, isPredicable = 1,
1381 Defs = [PC], isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
1382 opExtentBits = 24, isCodeGenOnly = 0 in
1383 class T_JMP <dag InsDag, list<dag> JumpList = []>
1384 : JInst<(outs), InsDag,
1385 "jump $dst" , JumpList> {
1388 let IClass = 0b0101;
1390 let Inst{27-25} = 0b100;
1391 let Inst{24-16} = dst{23-15};
1392 let Inst{13-1} = dst{14-2};
1395 let InputType = "imm", isExtendable = 1, opExtendable = 1, isExtentSigned = 1,
1396 Defs = [PC], isPredicated = 1, opExtentBits = 17 in
1397 class T_JMP_c <bit PredNot, bit isPredNew, bit isTak>:
1398 JInst<(outs ), (ins PredRegs:$src, brtarget:$dst),
1399 !if(PredNot, "if (!$src", "if ($src")#
1400 !if(isPredNew, ".new) ", ") ")#"jump"#
1401 !if(isPredNew, !if(isTak, ":t ", ":nt "), " ")#"$dst"> {
1403 let isTaken = isTak;
1404 let isBrTaken = !if(isPredNew, !if(isTaken, "true", "false"), "");
1405 let isPredicatedFalse = PredNot;
1406 let isPredicatedNew = isPredNew;
1410 let IClass = 0b0101;
1412 let Inst{27-24} = 0b1100;
1413 let Inst{21} = PredNot;
1414 let Inst{12} = !if(isPredNew, isTak, zero);
1415 let Inst{11} = isPredNew;
1416 let Inst{9-8} = src;
1417 let Inst{23-22} = dst{16-15};
1418 let Inst{20-16} = dst{14-10};
1419 let Inst{13} = dst{9};
1420 let Inst{7-1} = dst{8-2};
1423 let isBarrier = 1, Defs = [PC], isPredicable = 1, InputType = "reg" in
1424 class T_JMPr<dag InsDag = (ins IntRegs:$dst)>
1425 : JRInst<(outs ), InsDag,
1430 let IClass = 0b0101;
1431 let Inst{27-21} = 0b0010100;
1432 let Inst{20-16} = dst;
1435 let Defs = [PC], isPredicated = 1, InputType = "reg" in
1436 class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>:
1437 JRInst <(outs ), (ins PredRegs:$src, IntRegs:$dst),
1438 !if(PredNot, "if (!$src", "if ($src")#
1439 !if(isPredNew, ".new) ", ") ")#"jumpr"#
1440 !if(isPredNew, !if(isTak, ":t ", ":nt "), " ")#"$dst"> {
1442 let isTaken = isTak;
1443 let isBrTaken = !if(isPredNew, !if(isTaken, "true", "false"), "");
1444 let isPredicatedFalse = PredNot;
1445 let isPredicatedNew = isPredNew;
1449 let IClass = 0b0101;
1451 let Inst{27-22} = 0b001101;
1452 let Inst{21} = PredNot;
1453 let Inst{20-16} = dst;
1454 let Inst{12} = !if(isPredNew, isTak, zero);
1455 let Inst{11} = isPredNew;
1456 let Inst{9-8} = src;
1457 let Predicates = !if(isPredNew, [HasV3T], [HasV2T]);
1458 let validSubTargets = !if(isPredNew, HasV3SubT, HasV2SubT);
1461 multiclass JMP_Pred<bit PredNot> {
1462 def _#NAME : T_JMP_c<PredNot, 0, 0>;
1464 def _#NAME#new_t : T_JMP_c<PredNot, 1, 1>; // taken
1465 def _#NAME#new_nt : T_JMP_c<PredNot, 1, 0>; // not taken
1468 multiclass JMP_base<string BaseOp> {
1469 let BaseOpcode = BaseOp in {
1470 def NAME : T_JMP<(ins brtarget:$dst), [(br bb:$dst)]>;
1471 defm t : JMP_Pred<0>;
1472 defm f : JMP_Pred<1>;
1476 multiclass JMPR_Pred<bit PredNot> {
1477 def NAME: T_JMPr_c<PredNot, 0, 0>;
1479 def NAME#new_tV3 : T_JMPr_c<PredNot, 1, 1>; // taken
1480 def NAME#new_ntV3 : T_JMPr_c<PredNot, 1, 0>; // not taken
1483 multiclass JMPR_base<string BaseOp> {
1484 let BaseOpcode = BaseOp in {
1486 defm _t : JMPR_Pred<0>;
1487 defm _f : JMPR_Pred<1>;
1491 let isTerminator = 1, hasSideEffects = 0 in {
1493 defm JMP : JMP_base<"JMP">, PredNewRel;
1495 let isBranch = 1, isIndirectBranch = 1 in
1496 defm JMPR : JMPR_base<"JMPr">, PredNewRel;
1498 let isReturn = 1, isCodeGenOnly = 1 in
1499 defm JMPret : JMPR_base<"JMPret">, PredNewRel;
1502 def : Pat<(retflag),
1503 (JMPret (i32 R31))>;
1505 def : Pat <(brcond (i1 PredRegs:$src1), bb:$offset),
1506 (JMP_t (i1 PredRegs:$src1), bb:$offset)>;
1508 // A return through builtin_eh_return.
1509 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
1510 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
1511 def EH_RETURN_JMPR : T_JMPr;
1513 def : Pat<(eh_return),
1514 (EH_RETURN_JMPR (i32 R31))>;
1516 def : Pat<(HexagonBR_JT (i32 IntRegs:$dst)),
1517 (JMPR (i32 IntRegs:$dst))>;
1519 def : Pat<(brind (i32 IntRegs:$dst)),
1520 (JMPR (i32 IntRegs:$dst))>;
1522 //===----------------------------------------------------------------------===//
1524 //===----------------------------------------------------------------------===//
1526 //===----------------------------------------------------------------------===//
1528 //===----------------------------------------------------------------------===//
1530 // Load -- MEMri operand
1531 multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
1532 bit isNot, bit isPredNew> {
1533 let isPredicatedNew = isPredNew in
1534 def NAME : LDInst2<(outs RC:$dst),
1535 (ins PredRegs:$src1, MEMri:$addr),
1536 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1537 ") ")#"$dst = "#mnemonic#"($addr)",
1541 multiclass LD_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1542 let isPredicatedFalse = PredNot in {
1543 defm _c#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
1545 defm _cdn#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
1549 let isExtendable = 1, hasSideEffects = 0 in
1550 multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
1551 bits<5> ImmBits, bits<5> PredImmBits> {
1553 let CextOpcode = CextOp, BaseOpcode = CextOp in {
1554 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
1556 def NAME : LDInst2<(outs RC:$dst), (ins MEMri:$addr),
1557 "$dst = "#mnemonic#"($addr)",
1560 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
1561 isPredicated = 1 in {
1562 defm Pt : LD_MEMri_Pred<mnemonic, RC, 0 >;
1563 defm NotPt : LD_MEMri_Pred<mnemonic, RC, 1 >;
1568 let addrMode = BaseImmOffset, isMEMri = "true" in {
1569 let accessSize = ByteAccess in {
1570 defm LDrib: LD_MEMri < "memb", "LDrib", IntRegs, 11, 6>, AddrModeRel;
1571 defm LDriub: LD_MEMri < "memub" , "LDriub", IntRegs, 11, 6>, AddrModeRel;
1574 let accessSize = HalfWordAccess in {
1575 defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
1576 defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel;
1579 let accessSize = WordAccess in
1580 defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;
1582 let accessSize = DoubleWordAccess in
1583 defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;
1586 def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
1587 (LDrib ADDRriS11_0:$addr) >;
1589 def : Pat < (i32 (zextloadi8 ADDRriS11_0:$addr)),
1590 (LDriub ADDRriS11_0:$addr) >;
1592 def : Pat < (i32 (sextloadi16 ADDRriS11_1:$addr)),
1593 (LDrih ADDRriS11_1:$addr) >;
1595 def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)),
1596 (LDriuh ADDRriS11_1:$addr) >;
1598 def : Pat < (i32 (load ADDRriS11_2:$addr)),
1599 (LDriw ADDRriS11_2:$addr) >;
1601 def : Pat < (i64 (load ADDRriS11_3:$addr)),
1602 (LDrid ADDRriS11_3:$addr) >;
1605 // Load - Base with Immediate offset addressing mode
1606 multiclass LD_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
1607 bit isNot, bit isPredNew> {
1608 let isPredicatedNew = isPredNew in
1609 def NAME : LDInst2<(outs RC:$dst),
1610 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
1611 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1612 ") ")#"$dst = "#mnemonic#"($src2+#$src3)",
1616 multiclass LD_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
1618 let isPredicatedFalse = PredNot in {
1619 defm _c#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
1621 defm _cdn#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
1625 let isExtendable = 1, hasSideEffects = 0 in
1626 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1627 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
1628 bits<5> PredImmBits> {
1630 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1631 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
1632 isPredicable = 1, AddedComplexity = 20 in
1633 def NAME : LDInst2<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1634 "$dst = "#mnemonic#"($src1+#$offset)",
1637 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
1638 isPredicated = 1 in {
1639 defm Pt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 0 >;
1640 defm NotPt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 1 >;
1645 let addrMode = BaseImmOffset in {
1646 let accessSize = ByteAccess in {
1647 defm LDrib_indexed: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext,
1648 11, 6>, AddrModeRel;
1649 defm LDriub_indexed: LD_Idxd <"memub" , "LDriub", IntRegs, s11_0Ext, u6_0Ext,
1650 11, 6>, AddrModeRel;
1652 let accessSize = HalfWordAccess in {
1653 defm LDrih_indexed: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
1654 12, 7>, AddrModeRel;
1655 defm LDriuh_indexed: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext,
1656 12, 7>, AddrModeRel;
1658 let accessSize = WordAccess in
1659 defm LDriw_indexed: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
1660 13, 8>, AddrModeRel;
1662 let accessSize = DoubleWordAccess in
1663 defm LDrid_indexed: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,
1664 14, 9>, AddrModeRel;
1667 let AddedComplexity = 20 in {
1668 def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
1669 (LDrib_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
1671 def : Pat < (i32 (zextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
1672 (LDriub_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
1674 def : Pat < (i32 (sextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
1675 (LDrih_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
1677 def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
1678 (LDriuh_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
1680 def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
1681 (LDriw_indexed IntRegs:$src1, s11_2ExtPred:$offset) >;
1683 def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
1684 (LDrid_indexed IntRegs:$src1, s11_3ExtPred:$offset) >;
1687 //===----------------------------------------------------------------------===//
1688 // Post increment load
1689 //===----------------------------------------------------------------------===//
1691 multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1692 bit isNot, bit isPredNew> {
1693 let isPredicatedNew = isPredNew in
1694 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1695 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1696 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1697 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1702 multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,
1703 Operand ImmOp, bit PredNot> {
1704 let isPredicatedFalse = PredNot in {
1705 defm _c#NAME : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1707 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1708 defm _cdn#NAME#_V4 : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1712 multiclass LD_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1715 let BaseOpcode = "POST_"#BaseOp in {
1716 let isPredicable = 1 in
1717 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1718 (ins IntRegs:$src1, ImmOp:$offset),
1719 "$dst = "#mnemonic#"($src1++#$offset)",
1723 let isPredicated = 1 in {
1724 defm Pt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1725 defm NotPt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1730 let hasCtrlDep = 1, hasSideEffects = 0, addrMode = PostInc in {
1731 defm POST_LDrib : LD_PostInc<"memb", "LDrib", IntRegs, s4_0Imm>,
1733 defm POST_LDriub : LD_PostInc<"memub", "LDriub", IntRegs, s4_0Imm>,
1735 defm POST_LDrih : LD_PostInc<"memh", "LDrih", IntRegs, s4_1Imm>,
1737 defm POST_LDriuh : LD_PostInc<"memuh", "LDriuh", IntRegs, s4_1Imm>,
1739 defm POST_LDriw : LD_PostInc<"memw", "LDriw", IntRegs, s4_2Imm>,
1741 defm POST_LDrid : LD_PostInc<"memd", "LDrid", DoubleRegs, s4_3Imm>,
1745 def : Pat< (i32 (extloadi1 ADDRriS11_0:$addr)),
1746 (i32 (LDrib ADDRriS11_0:$addr)) >;
1748 // Load byte any-extend.
1749 def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
1750 (i32 (LDrib ADDRriS11_0:$addr)) >;
1752 // Indexed load byte any-extend.
1753 let AddedComplexity = 20 in
1754 def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1755 (i32 (LDrib_indexed IntRegs:$src1, s11_0ImmPred:$offset)) >;
1757 def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
1758 (i32 (LDrih ADDRriS11_1:$addr))>;
1760 let AddedComplexity = 20 in
1761 def : Pat < (i32 (extloadi16 (add IntRegs:$src1, s11_1ImmPred:$offset))),
1762 (i32 (LDrih_indexed IntRegs:$src1, s11_1ImmPred:$offset)) >;
1764 let AddedComplexity = 10 in
1765 def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
1766 (i32 (LDriub ADDRriS11_0:$addr))>;
1768 let AddedComplexity = 20 in
1769 def : Pat < (i32 (zextloadi1 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1770 (i32 (LDriub_indexed IntRegs:$src1, s11_0ImmPred:$offset))>;
1773 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
1774 isPseudo = 1, Defs = [R10,R11,D5], hasSideEffects = 0 in
1775 def LDriw_pred : LDInst2<(outs PredRegs:$dst),
1777 "Error; should not emit",
1780 // Deallocate stack frame.
1781 let Defs = [R29, R30, R31], Uses = [R29], hasSideEffects = 0 in {
1782 def DEALLOCFRAME : LDInst2<(outs), (ins),
1787 // Load and unpack bytes to halfwords.
1788 //===----------------------------------------------------------------------===//
1790 //===----------------------------------------------------------------------===//
1792 //===----------------------------------------------------------------------===//
1794 //===----------------------------------------------------------------------===//
1795 //===----------------------------------------------------------------------===//
1797 //===----------------------------------------------------------------------===//
1799 //===----------------------------------------------------------------------===//
1801 //===----------------------------------------------------------------------===//
1802 //===----------------------------------------------------------------------===//
1804 //===----------------------------------------------------------------------===//
1806 //===----------------------------------------------------------------------===//
1808 //===----------------------------------------------------------------------===//
1809 // Multiply and use lower result.
1811 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in
1812 def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Ext:$src2),
1813 "$dst =+ mpyi($src1, #$src2)",
1814 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1815 u8ExtPred:$src2))]>;
1818 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1819 "$dst =- mpyi($src1, #$src2)",
1820 [(set (i32 IntRegs:$dst), (ineg (mul (i32 IntRegs:$src1),
1821 u8ImmPred:$src2)))]>;
1824 // s9 is NOT the same as m9 - but it works.. so far.
1825 // Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
1826 // depending on the value of m9. See Arch Spec.
1827 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
1828 CextOpcode = "MPYI", InputType = "imm" in
1829 def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
1830 "$dst = mpyi($src1, #$src2)",
1831 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1832 s9ExtPred:$src2))]>, ImmRegRel;
1835 let CextOpcode = "MPYI", InputType = "reg" in
1836 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1837 "$dst = mpyi($src1, $src2)",
1838 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1839 (i32 IntRegs:$src2)))]>, ImmRegRel;
1842 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8,
1843 CextOpcode = "MPYI_acc", InputType = "imm" in
1844 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
1845 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1846 "$dst += mpyi($src2, #$src3)",
1847 [(set (i32 IntRegs:$dst),
1848 (add (mul (i32 IntRegs:$src2), u8ExtPred:$src3),
1849 (i32 IntRegs:$src1)))],
1850 "$src1 = $dst">, ImmRegRel;
1853 let CextOpcode = "MPYI_acc", InputType = "reg" in
1854 def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
1855 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1856 "$dst += mpyi($src2, $src3)",
1857 [(set (i32 IntRegs:$dst),
1858 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1859 (i32 IntRegs:$src1)))],
1860 "$src1 = $dst">, ImmRegRel;
1863 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8 in
1864 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
1865 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1866 "$dst -= mpyi($src2, #$src3)",
1867 [(set (i32 IntRegs:$dst),
1868 (sub (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1869 u8ExtPred:$src3)))],
1872 // Multiply and use upper result.
1873 // Rd=mpy(Rs,Rt.H):<<1:rnd:sat
1874 // Rd=mpy(Rs,Rt.L):<<1:rnd:sat
1876 def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1877 "$dst = mpy($src1, $src2)",
1878 [(set (i32 IntRegs:$dst), (mulhs (i32 IntRegs:$src1),
1879 (i32 IntRegs:$src2)))]>;
1881 // Rd=mpy(Rs,Rt):rnd
1883 def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1884 "$dst = mpyu($src1, $src2)",
1885 [(set (i32 IntRegs:$dst), (mulhu (i32 IntRegs:$src1),
1886 (i32 IntRegs:$src2)))]>;
1888 // Multiply and use full result.
1890 def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1891 "$dst = mpyu($src1, $src2)",
1892 [(set (i64 DoubleRegs:$dst),
1893 (mul (i64 (anyext (i32 IntRegs:$src1))),
1894 (i64 (anyext (i32 IntRegs:$src2)))))]>;
1897 def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1898 "$dst = mpy($src1, $src2)",
1899 [(set (i64 DoubleRegs:$dst),
1900 (mul (i64 (sext (i32 IntRegs:$src1))),
1901 (i64 (sext (i32 IntRegs:$src2)))))]>;
1903 // Multiply and accumulate, use full result.
1904 // Rxx[+-]=mpy(Rs,Rt)
1906 def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
1907 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1908 "$dst += mpy($src2, $src3)",
1909 [(set (i64 DoubleRegs:$dst),
1910 (add (mul (i64 (sext (i32 IntRegs:$src2))),
1911 (i64 (sext (i32 IntRegs:$src3)))),
1912 (i64 DoubleRegs:$src1)))],
1916 def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
1917 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1918 "$dst -= mpy($src2, $src3)",
1919 [(set (i64 DoubleRegs:$dst),
1920 (sub (i64 DoubleRegs:$src1),
1921 (mul (i64 (sext (i32 IntRegs:$src2))),
1922 (i64 (sext (i32 IntRegs:$src3))))))],
1925 // Rxx[+-]=mpyu(Rs,Rt)
1927 def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1928 IntRegs:$src2, IntRegs:$src3),
1929 "$dst += mpyu($src2, $src3)",
1930 [(set (i64 DoubleRegs:$dst),
1931 (add (mul (i64 (anyext (i32 IntRegs:$src2))),
1932 (i64 (anyext (i32 IntRegs:$src3)))),
1933 (i64 DoubleRegs:$src1)))], "$src1 = $dst">;
1936 def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
1937 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1938 "$dst -= mpyu($src2, $src3)",
1939 [(set (i64 DoubleRegs:$dst),
1940 (sub (i64 DoubleRegs:$src1),
1941 (mul (i64 (anyext (i32 IntRegs:$src2))),
1942 (i64 (anyext (i32 IntRegs:$src3))))))],
1946 let InputType = "reg", CextOpcode = "ADD_acc" in
1947 def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1948 IntRegs:$src2, IntRegs:$src3),
1949 "$dst += add($src2, $src3)",
1950 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1951 (i32 IntRegs:$src3)),
1952 (i32 IntRegs:$src1)))],
1953 "$src1 = $dst">, ImmRegRel;
1955 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
1956 InputType = "imm", CextOpcode = "ADD_acc" in
1957 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1958 IntRegs:$src2, s8Ext:$src3),
1959 "$dst += add($src2, #$src3)",
1960 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1961 s8_16ExtPred:$src3),
1962 (i32 IntRegs:$src1)))],
1963 "$src1 = $dst">, ImmRegRel;
1965 let CextOpcode = "SUB_acc", InputType = "reg" in
1966 def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1967 IntRegs:$src2, IntRegs:$src3),
1968 "$dst -= add($src2, $src3)",
1969 [(set (i32 IntRegs:$dst),
1970 (sub (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1971 (i32 IntRegs:$src3))))],
1972 "$src1 = $dst">, ImmRegRel;
1974 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
1975 CextOpcode = "SUB_acc", InputType = "imm" in
1976 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1977 IntRegs:$src2, s8Ext:$src3),
1978 "$dst -= add($src2, #$src3)",
1979 [(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
1980 (add (i32 IntRegs:$src2),
1981 s8_16ExtPred:$src3)))],
1982 "$src1 = $dst">, ImmRegRel;
1984 //===----------------------------------------------------------------------===//
1986 //===----------------------------------------------------------------------===//
1988 //===----------------------------------------------------------------------===//
1990 //===----------------------------------------------------------------------===//
1991 //===----------------------------------------------------------------------===//
1993 //===----------------------------------------------------------------------===//
1995 //===----------------------------------------------------------------------===//
1997 //===----------------------------------------------------------------------===//
1998 //===----------------------------------------------------------------------===//
2000 //===----------------------------------------------------------------------===//
2002 //===----------------------------------------------------------------------===//
2004 //===----------------------------------------------------------------------===//
2005 //===----------------------------------------------------------------------===//
2007 //===----------------------------------------------------------------------===//
2009 //===----------------------------------------------------------------------===//
2011 //===----------------------------------------------------------------------===//
2013 // Store doubleword.
2015 //===----------------------------------------------------------------------===//
2016 // Post increment store
2017 //===----------------------------------------------------------------------===//
2019 multiclass ST_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
2020 bit isNot, bit isPredNew> {
2021 let isPredicatedNew = isPredNew in
2022 def NAME : STInst2PI<(outs IntRegs:$dst),
2023 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
2024 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2025 ") ")#mnemonic#"($src2++#$offset) = $src3",
2030 multiclass ST_PostInc_Pred<string mnemonic, RegisterClass RC,
2031 Operand ImmOp, bit PredNot> {
2032 let isPredicatedFalse = PredNot in {
2033 defm _c#NAME : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
2035 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
2036 defm _cdn#NAME#_V4 : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
2040 let hasCtrlDep = 1, isNVStorable = 1, hasSideEffects = 0 in
2041 multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
2044 let hasCtrlDep = 1, BaseOpcode = "POST_"#BaseOp in {
2045 let isPredicable = 1 in
2046 def NAME : STInst2PI<(outs IntRegs:$dst),
2047 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
2048 mnemonic#"($src1++#$offset) = $src2",
2052 let isPredicated = 1 in {
2053 defm Pt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
2054 defm NotPt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
2059 defm POST_STbri: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel;
2060 defm POST_SThri: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
2061 defm POST_STwri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
2063 let isNVStorable = 0 in
2064 defm POST_STdri: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm>, AddrModeRel;
2066 def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2,
2067 s4_3ImmPred:$offset),
2068 (POST_STbri IntRegs:$src2, s4_0ImmPred:$offset, IntRegs:$src1)>;
2070 def : Pat<(post_truncsti16 (i32 IntRegs:$src1), IntRegs:$src2,
2071 s4_3ImmPred:$offset),
2072 (POST_SThri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
2074 def : Pat<(post_store (i32 IntRegs:$src1), IntRegs:$src2, s4_2ImmPred:$offset),
2075 (POST_STwri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
2077 def : Pat<(post_store (i64 DoubleRegs:$src1), IntRegs:$src2,
2078 s4_3ImmPred:$offset),
2079 (POST_STdri IntRegs:$src2, s4_3ImmPred:$offset, DoubleRegs:$src1)>;
2081 //===----------------------------------------------------------------------===//
2082 // multiclass for the store instructions with MEMri operand.
2083 //===----------------------------------------------------------------------===//
2084 multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot,
2086 let isPredicatedNew = isPredNew in
2087 def NAME : STInst2<(outs),
2088 (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
2089 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2090 ") ")#mnemonic#"($addr) = $src2",
2094 multiclass ST_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
2095 let isPredicatedFalse = PredNot in {
2096 defm _c#NAME : ST_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
2099 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
2100 defm _cdn#NAME#_V4 : ST_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
2104 let isExtendable = 1, isNVStorable = 1, hasSideEffects = 0 in
2105 multiclass ST_MEMri<string mnemonic, string CextOp, RegisterClass RC,
2106 bits<5> ImmBits, bits<5> PredImmBits> {
2108 let CextOpcode = CextOp, BaseOpcode = CextOp in {
2109 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
2111 def NAME : STInst2<(outs),
2112 (ins MEMri:$addr, RC:$src),
2113 mnemonic#"($addr) = $src",
2116 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
2117 isPredicated = 1 in {
2118 defm Pt : ST_MEMri_Pred<mnemonic, RC, 0>;
2119 defm NotPt : ST_MEMri_Pred<mnemonic, RC, 1>;
2124 let addrMode = BaseImmOffset, isMEMri = "true" in {
2125 let accessSize = ByteAccess in
2126 defm STrib: ST_MEMri < "memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
2128 let accessSize = HalfWordAccess in
2129 defm STrih: ST_MEMri < "memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
2131 let accessSize = WordAccess in
2132 defm STriw: ST_MEMri < "memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
2134 let accessSize = DoubleWordAccess, isNVStorable = 0 in
2135 defm STrid: ST_MEMri < "memd", "STrid", DoubleRegs, 14, 9>, AddrModeRel;
2138 def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
2139 (STrib ADDRriS11_0:$addr, (i32 IntRegs:$src1))>;
2141 def : Pat<(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr),
2142 (STrih ADDRriS11_1:$addr, (i32 IntRegs:$src1))>;
2144 def : Pat<(store (i32 IntRegs:$src1), ADDRriS11_2:$addr),
2145 (STriw ADDRriS11_2:$addr, (i32 IntRegs:$src1))>;
2147 def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
2148 (STrid ADDRriS11_3:$addr, (i64 DoubleRegs:$src1))>;
2151 //===----------------------------------------------------------------------===//
2152 // multiclass for the store instructions with base+immediate offset
2154 //===----------------------------------------------------------------------===//
2155 multiclass ST_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
2156 bit isNot, bit isPredNew> {
2157 let isPredicatedNew = isPredNew in
2158 def NAME : STInst2<(outs),
2159 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
2160 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2161 ") ")#mnemonic#"($src2+#$src3) = $src4",
2165 multiclass ST_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
2167 let isPredicatedFalse = PredNot, isPredicated = 1 in {
2168 defm _c#NAME : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
2171 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
2172 defm _cdn#NAME#_V4 : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
2176 let isExtendable = 1, isNVStorable = 1, hasSideEffects = 0 in
2177 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
2178 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
2179 bits<5> PredImmBits> {
2181 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
2182 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
2184 def NAME : STInst2<(outs),
2185 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
2186 mnemonic#"($src1+#$src2) = $src3",
2189 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits in {
2190 defm Pt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 0>;
2191 defm NotPt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 1>;
2196 let addrMode = BaseImmOffset, InputType = "reg" in {
2197 let accessSize = ByteAccess in
2198 defm STrib_indexed: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext,
2199 u6_0Ext, 11, 6>, AddrModeRel, ImmRegRel;
2201 let accessSize = HalfWordAccess in
2202 defm STrih_indexed: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext,
2203 u6_1Ext, 12, 7>, AddrModeRel, ImmRegRel;
2205 let accessSize = WordAccess in
2206 defm STriw_indexed: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext,
2207 u6_2Ext, 13, 8>, AddrModeRel, ImmRegRel;
2209 let accessSize = DoubleWordAccess, isNVStorable = 0 in
2210 defm STrid_indexed: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
2211 u6_3Ext, 14, 9>, AddrModeRel;
2214 let AddedComplexity = 10 in {
2215 def : Pat<(truncstorei8 (i32 IntRegs:$src1), (add IntRegs:$src2,
2216 s11_0ExtPred:$offset)),
2217 (STrib_indexed IntRegs:$src2, s11_0ImmPred:$offset,
2218 (i32 IntRegs:$src1))>;
2220 def : Pat<(truncstorei16 (i32 IntRegs:$src1), (add IntRegs:$src2,
2221 s11_1ExtPred:$offset)),
2222 (STrih_indexed IntRegs:$src2, s11_1ImmPred:$offset,
2223 (i32 IntRegs:$src1))>;
2225 def : Pat<(store (i32 IntRegs:$src1), (add IntRegs:$src2,
2226 s11_2ExtPred:$offset)),
2227 (STriw_indexed IntRegs:$src2, s11_2ImmPred:$offset,
2228 (i32 IntRegs:$src1))>;
2230 def : Pat<(store (i64 DoubleRegs:$src1), (add IntRegs:$src2,
2231 s11_3ExtPred:$offset)),
2232 (STrid_indexed IntRegs:$src2, s11_3ImmPred:$offset,
2233 (i64 DoubleRegs:$src1))>;
2236 // memh(Rx++#s4:1)=Rt.H
2240 let Defs = [R10,R11,D5], hasSideEffects = 0 in
2241 def STriw_pred : STInst2<(outs),
2242 (ins MEMri:$addr, PredRegs:$src1),
2243 "Error; should not emit",
2246 // Allocate stack frame.
2247 let Defs = [R29, R30], Uses = [R31, R30], hasSideEffects = 0 in {
2248 def ALLOCFRAME : STInst2<(outs),
2250 "allocframe(#$amt)",
2253 //===----------------------------------------------------------------------===//
2255 //===----------------------------------------------------------------------===//
2257 //===----------------------------------------------------------------------===//
2259 //===----------------------------------------------------------------------===//
2261 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
2262 "$dst = not($src1)",
2263 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
2266 // Sign extend word to doubleword.
2267 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
2268 "$dst = sxtw($src1)",
2269 [(set (i64 DoubleRegs:$dst), (sext (i32 IntRegs:$src1)))]>;
2270 //===----------------------------------------------------------------------===//
2272 //===----------------------------------------------------------------------===//
2274 //===----------------------------------------------------------------------===//
2276 //===----------------------------------------------------------------------===//
2278 def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2279 "$dst = clrbit($src1, #$src2)",
2280 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
2282 (shl 1, u5ImmPred:$src2))))]>;
2284 def CLRBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2285 "$dst = clrbit($src1, #$src2)",
2288 // Map from r0 = and(r1, 2147483647) to r0 = clrbit(r1, #31).
2289 def : Pat <(and (i32 IntRegs:$src1), 2147483647),
2290 (CLRBIT_31 (i32 IntRegs:$src1), 31)>;
2293 def SETBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2294 "$dst = setbit($src1, #$src2)",
2295 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
2296 (shl 1, u5ImmPred:$src2)))]>;
2298 // Map from r0 = or(r1, -2147483648) to r0 = setbit(r1, #31).
2299 def SETBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2300 "$dst = setbit($src1, #$src2)",
2303 def : Pat <(or (i32 IntRegs:$src1), -2147483648),
2304 (SETBIT_31 (i32 IntRegs:$src1), 31)>;
2307 def TOGBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2308 "$dst = setbit($src1, #$src2)",
2309 [(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
2310 (shl 1, u5ImmPred:$src2)))]>;
2312 // Map from r0 = xor(r1, -2147483648) to r0 = togglebit(r1, #31).
2313 def TOGBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2314 "$dst = togglebit($src1, #$src2)",
2317 def : Pat <(xor (i32 IntRegs:$src1), -2147483648),
2318 (TOGBIT_31 (i32 IntRegs:$src1), 31)>;
2320 // Predicate transfer.
2321 let hasSideEffects = 0 in
2322 def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
2323 "$dst = $src1 /* Should almost never emit this. */",
2326 def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1),
2327 "$dst = $src1 /* Should almost never emit this. */",
2328 [(set (i1 PredRegs:$dst), (trunc (i32 IntRegs:$src1)))]>;
2329 //===----------------------------------------------------------------------===//
2331 //===----------------------------------------------------------------------===//
2333 //===----------------------------------------------------------------------===//
2335 //===----------------------------------------------------------------------===//
2336 // Shift by immediate.
2337 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2338 "$dst = asr($src1, #$src2)",
2339 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
2340 u5ImmPred:$src2))]>;
2342 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2343 "$dst = asr($src1, #$src2)",
2344 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
2345 u6ImmPred:$src2))]>;
2347 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2348 "$dst = asl($src1, #$src2)",
2349 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
2350 u5ImmPred:$src2))]>;
2352 def ASLd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2353 "$dst = asl($src1, #$src2)",
2354 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
2355 u6ImmPred:$src2))]>;
2357 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2358 "$dst = lsr($src1, #$src2)",
2359 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
2360 u5ImmPred:$src2))]>;
2362 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2363 "$dst = lsr($src1, #$src2)",
2364 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
2365 u6ImmPred:$src2))]>;
2367 // Shift by immediate and add.
2368 let AddedComplexity = 100 in
2369 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
2371 "$dst = addasl($src1, $src2, #$src3)",
2372 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
2373 (shl (i32 IntRegs:$src2),
2374 u3ImmPred:$src3)))]>;
2376 // Shift by register.
2377 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2378 "$dst = asl($src1, $src2)",
2379 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
2380 (i32 IntRegs:$src2)))]>;
2382 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2383 "$dst = asr($src1, $src2)",
2384 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
2385 (i32 IntRegs:$src2)))]>;
2387 def LSL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2388 "$dst = lsl($src1, $src2)",
2389 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
2390 (i32 IntRegs:$src2)))]>;
2392 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2393 "$dst = lsr($src1, $src2)",
2394 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
2395 (i32 IntRegs:$src2)))]>;
2397 def ASLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2398 "$dst = asl($src1, $src2)",
2399 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
2400 (i32 IntRegs:$src2)))]>;
2402 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2403 "$dst = lsl($src1, $src2)",
2404 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
2405 (i32 IntRegs:$src2)))]>;
2407 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2409 "$dst = asr($src1, $src2)",
2410 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
2411 (i32 IntRegs:$src2)))]>;
2413 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2415 "$dst = lsr($src1, $src2)",
2416 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
2417 (i32 IntRegs:$src2)))]>;
2419 //===----------------------------------------------------------------------===//
2421 //===----------------------------------------------------------------------===//
2423 //===----------------------------------------------------------------------===//
2425 //===----------------------------------------------------------------------===//
2426 //===----------------------------------------------------------------------===//
2428 //===----------------------------------------------------------------------===//
2430 //===----------------------------------------------------------------------===//
2432 //===----------------------------------------------------------------------===//
2433 //===----------------------------------------------------------------------===//
2435 //===----------------------------------------------------------------------===//
2437 //===----------------------------------------------------------------------===//
2439 //===----------------------------------------------------------------------===//
2441 //===----------------------------------------------------------------------===//
2443 //===----------------------------------------------------------------------===//
2444 def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
2445 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
2448 let hasSideEffects = 1, isSolo = 1 in
2449 def BARRIER : SYSInst<(outs), (ins),
2451 [(HexagonBARRIER)]>;
2453 //===----------------------------------------------------------------------===//
2455 //===----------------------------------------------------------------------===//
2457 // TFRI64 - assembly mapped.
2458 let isReMaterializable = 1 in
2459 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
2461 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
2463 let AddedComplexity = 100, isPredicated = 1 in
2464 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
2465 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
2466 "Error; should not emit",
2467 [(set (i32 IntRegs:$dst),
2468 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
2469 s12ImmPred:$src3)))]>;
2471 let AddedComplexity = 100, isPredicated = 1 in
2472 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
2473 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
2474 "Error; should not emit",
2475 [(set (i32 IntRegs:$dst),
2476 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
2477 (i32 IntRegs:$src3))))]>;
2479 let AddedComplexity = 100, isPredicated = 1 in
2480 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
2481 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
2482 "Error; should not emit",
2483 [(set (i32 IntRegs:$dst),
2484 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
2485 s12ImmPred:$src3)))]>;
2487 // Generate frameindex addresses.
2488 let isReMaterializable = 1 in
2489 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
2490 "$dst = add($src1)",
2491 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
2496 let hasSideEffects = 0, Defs = [SA0, LC0] in {
2497 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
2498 "loop0($offset, #$src2)",
2502 let hasSideEffects = 0, Defs = [SA0, LC0] in {
2503 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
2504 "loop0($offset, $src2)",
2508 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
2509 Defs = [PC, LC0], Uses = [SA0, LC0] in {
2510 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
2515 // Support for generating global address.
2516 // Taken from X86InstrInfo.td.
2517 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [
2521 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
2522 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
2524 // HI/LO Instructions
2525 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
2526 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
2527 "$dst.l = #LO($global)",
2530 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
2531 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
2532 "$dst.h = #HI($global)",
2535 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
2536 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2537 "$dst.l = #LO($imm_value)",
2541 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
2542 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2543 "$dst.h = #HI($imm_value)",
2546 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
2547 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2548 "$dst.l = #LO($jt)",
2551 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
2552 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2553 "$dst.h = #HI($jt)",
2557 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
2558 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2559 "$dst.l = #LO($label)",
2562 let isReMaterializable = 1, isMoveImm = 1 , hasSideEffects = 0 in
2563 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2564 "$dst.h = #HI($label)",
2567 // This pattern is incorrect. When we add small data, we should change
2568 // this pattern to use memw(#foo).
2569 // This is for sdata.
2570 let isMoveImm = 1 in
2571 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2572 "$dst = CONST32(#$global)",
2573 [(set (i32 IntRegs:$dst),
2574 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
2576 // This is for non-sdata.
2577 let isReMaterializable = 1, isMoveImm = 1 in
2578 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2579 "$dst = CONST32(#$global)",
2580 [(set (i32 IntRegs:$dst),
2581 (HexagonCONST32 tglobaladdr:$global))]>;
2583 let isReMaterializable = 1, isMoveImm = 1 in
2584 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2585 "$dst = CONST32(#$jt)",
2586 [(set (i32 IntRegs:$dst),
2587 (HexagonCONST32 tjumptable:$jt))]>;
2589 let isReMaterializable = 1, isMoveImm = 1 in
2590 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2591 "$dst = CONST32(#$global)",
2592 [(set (i32 IntRegs:$dst),
2593 (HexagonCONST32_GP tglobaladdr:$global))]>;
2595 let isReMaterializable = 1, isMoveImm = 1 in
2596 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
2597 "$dst = CONST32(#$global)",
2598 [(set (i32 IntRegs:$dst), imm:$global) ]>;
2600 // Map BlockAddress lowering to CONST32_Int_Real
2601 def : Pat<(HexagonCONST32_GP tblockaddress:$addr),
2602 (CONST32_Int_Real tblockaddress:$addr)>;
2604 let isReMaterializable = 1, isMoveImm = 1 in
2605 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
2606 "$dst = CONST32($label)",
2607 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
2609 let isReMaterializable = 1, isMoveImm = 1 in
2610 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
2611 "$dst = CONST64(#$global)",
2612 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
2614 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
2615 "$dst = xor($dst, $dst)",
2616 [(set (i1 PredRegs:$dst), 0)]>;
2618 def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2619 "$dst = mpy($src1, $src2)",
2620 [(set (i32 IntRegs:$dst),
2621 (trunc (i64 (srl (i64 (mul (i64 (sext (i32 IntRegs:$src1))),
2622 (i64 (sext (i32 IntRegs:$src2))))),
2625 // Pseudo instructions.
2626 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
2628 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
2629 SDTCisVT<1, i32> ]>;
2631 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
2632 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2634 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
2635 [SDNPHasChain, SDNPOutGlue]>;
2637 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2639 def call : SDNode<"HexagonISD::CALL", SDT_SPCall,
2640 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
2642 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
2643 // Optional Flag and Variable Arguments.
2644 // Its 1 Operand has pointer type.
2645 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
2646 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
2648 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
2649 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
2650 "Should never be emitted",
2651 [(callseq_start timm:$amt)]>;
2654 let Defs = [R29, R30, R31], Uses = [R29] in {
2655 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2656 "Should never be emitted",
2657 [(callseq_end timm:$amt1, timm:$amt2)]>;
2660 let isCall = 1, hasSideEffects = 0,
2661 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2662 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2663 def CALL : JInst<(outs), (ins calltarget:$dst),
2667 // Call subroutine from register.
2668 let isCall = 1, hasSideEffects = 0,
2669 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2670 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2671 def CALLR : JRInst<(outs), (ins IntRegs:$dst),
2677 // Indirect tail-call.
2678 let isCodeGenOnly = 1, isCall = 1, isReturn = 1 in
2679 def TCRETURNR : T_JMPr;
2681 // Direct tail-calls.
2682 let isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
2683 isTerminator = 1, isCodeGenOnly = 1 in {
2684 def TCRETURNtg : T_JMP<(ins calltarget:$dst)>;
2685 def TCRETURNtext : T_JMP<(ins calltarget:$dst)>;
2688 // Map call instruction.
2689 def : Pat<(call (i32 IntRegs:$dst)),
2690 (CALLR (i32 IntRegs:$dst))>, Requires<[HasV2TOnly]>;
2691 def : Pat<(call tglobaladdr:$dst),
2692 (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
2693 def : Pat<(call texternalsym:$dst),
2694 (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>;
2696 def : Pat<(HexagonTCRet tglobaladdr:$dst),
2697 (TCRETURNtg tglobaladdr:$dst)>;
2698 def : Pat<(HexagonTCRet texternalsym:$dst),
2699 (TCRETURNtext texternalsym:$dst)>;
2700 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
2701 (TCRETURNR (i32 IntRegs:$dst))>;
2703 // Atomic load and store support
2704 // 8 bit atomic load
2705 def : Pat<(atomic_load_8 ADDRriS11_0:$src1),
2706 (i32 (LDriub ADDRriS11_0:$src1))>;
2708 def : Pat<(atomic_load_8 (add (i32 IntRegs:$src1), s11_0ImmPred:$offset)),
2709 (i32 (LDriub_indexed (i32 IntRegs:$src1), s11_0ImmPred:$offset))>;
2711 // 16 bit atomic load
2712 def : Pat<(atomic_load_16 ADDRriS11_1:$src1),
2713 (i32 (LDriuh ADDRriS11_1:$src1))>;
2715 def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)),
2716 (i32 (LDriuh_indexed (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
2718 def : Pat<(atomic_load_32 ADDRriS11_2:$src1),
2719 (i32 (LDriw ADDRriS11_2:$src1))>;
2721 def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),
2722 (i32 (LDriw_indexed (i32 IntRegs:$src1), s11_2ImmPred:$offset))>;
2724 // 64 bit atomic load
2725 def : Pat<(atomic_load_64 ADDRriS11_3:$src1),
2726 (i64 (LDrid ADDRriS11_3:$src1))>;
2728 def : Pat<(atomic_load_64 (add (i32 IntRegs:$src1), s11_3ImmPred:$offset)),
2729 (i64 (LDrid_indexed (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
2732 def : Pat<(atomic_store_8 ADDRriS11_0:$src2, (i32 IntRegs:$src1)),
2733 (STrib ADDRriS11_0:$src2, (i32 IntRegs:$src1))>;
2735 def : Pat<(atomic_store_8 (add (i32 IntRegs:$src2), s11_0ImmPred:$offset),
2736 (i32 IntRegs:$src1)),
2737 (STrib_indexed (i32 IntRegs:$src2), s11_0ImmPred:$offset,
2738 (i32 IntRegs:$src1))>;
2741 def : Pat<(atomic_store_16 ADDRriS11_1:$src2, (i32 IntRegs:$src1)),
2742 (STrih ADDRriS11_1:$src2, (i32 IntRegs:$src1))>;
2744 def : Pat<(atomic_store_16 (i32 IntRegs:$src1),
2745 (add (i32 IntRegs:$src2), s11_1ImmPred:$offset)),
2746 (STrih_indexed (i32 IntRegs:$src2), s11_1ImmPred:$offset,
2747 (i32 IntRegs:$src1))>;
2749 def : Pat<(atomic_store_32 ADDRriS11_2:$src2, (i32 IntRegs:$src1)),
2750 (STriw ADDRriS11_2:$src2, (i32 IntRegs:$src1))>;
2752 def : Pat<(atomic_store_32 (add (i32 IntRegs:$src2), s11_2ImmPred:$offset),
2753 (i32 IntRegs:$src1)),
2754 (STriw_indexed (i32 IntRegs:$src2), s11_2ImmPred:$offset,
2755 (i32 IntRegs:$src1))>;
2760 def : Pat<(atomic_store_64 ADDRriS11_3:$src2, (i64 DoubleRegs:$src1)),
2761 (STrid ADDRriS11_3:$src2, (i64 DoubleRegs:$src1))>;
2763 def : Pat<(atomic_store_64 (add (i32 IntRegs:$src2), s11_3ImmPred:$offset),
2764 (i64 DoubleRegs:$src1)),
2765 (STrid_indexed (i32 IntRegs:$src2), s11_3ImmPred:$offset,
2766 (i64 DoubleRegs:$src1))>;
2768 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
2769 def : Pat <(and (i32 IntRegs:$src1), 65535),
2770 (A2_zxth (i32 IntRegs:$src1))>;
2772 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
2773 def : Pat <(and (i32 IntRegs:$src1), 255),
2774 (A2_zxtb (i32 IntRegs:$src1))>;
2776 // Map Add(p1, true) to p1 = not(p1).
2777 // Add(p1, false) should never be produced,
2778 // if it does, it got to be mapped to NOOP.
2779 def : Pat <(add (i1 PredRegs:$src1), -1),
2780 (NOT_p (i1 PredRegs:$src1))>;
2782 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
2783 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
2784 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
2787 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
2788 // => r0 = TFR_condset_ri(p0, r1, #i)
2789 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
2790 (i32 IntRegs:$src3)),
2791 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
2792 s12ImmPred:$src2))>;
2794 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
2795 // => r0 = TFR_condset_ir(p0, #i, r1)
2796 def : Pat <(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s12ImmPred:$src3),
2797 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
2798 (i32 IntRegs:$src2)))>;
2800 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
2801 def : Pat <(brcond (not (i1 PredRegs:$src1)), bb:$offset),
2802 (JMP_f (i1 PredRegs:$src1), bb:$offset)>;
2804 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
2805 def : Pat <(and (i1 PredRegs:$src1), (not (i1 PredRegs:$src2))),
2806 (i1 (AND_pnotp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2809 let AddedComplexity = 100 in
2810 def : Pat <(i64 (zextloadi1 (HexagonCONST32 tglobaladdr:$global))),
2811 (i64 (COMBINE_rr (TFRI 0),
2812 (LDriub_indexed (CONST32_set tglobaladdr:$global), 0)))>,
2815 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
2816 let AddedComplexity = 10 in
2817 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
2818 (i32 (A2_and (i32 (LDrib ADDRriS11_0:$addr)), (TFRI 0x1)))>;
2820 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
2821 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
2822 (i64 (SXTW (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
2824 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
2825 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
2826 (i64 (SXTW (i32 (A2_sxth (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2827 subreg_loreg))))))>;
2829 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
2830 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
2831 (i64 (SXTW (i32 (A2_sxtb (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2832 subreg_loreg))))))>;
2834 // We want to prevent emitting pnot's as much as possible.
2835 // Map brcond with an unsupported setcc to a JMP_f.
2836 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2838 (JMP_f (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2841 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
2843 (JMP_f (C2_cmpeqi (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
2845 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
2846 (JMP_f (i1 PredRegs:$src1), bb:$offset)>;
2848 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
2849 (JMP_t (i1 PredRegs:$src1), bb:$offset)>;
2851 // cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1)
2852 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
2854 (JMP_f (C2_cmpgti (i32 IntRegs:$src1),
2855 (DEC_CONST_SIGNED s8ImmPred:$src2)), bb:$offset)>;
2857 // cmp.lt(r0, r1) -> cmp.gt(r1, r0)
2858 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2860 (JMP_t (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)), bb:$offset)>;
2862 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2864 (JMP_f (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
2867 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2869 (JMP_f (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2872 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2874 (JMP_f (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2877 // Map from a 64-bit select to an emulated 64-bit mux.
2878 // Hexagon does not support 64-bit MUXes; so emulate with combines.
2879 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
2880 (i64 DoubleRegs:$src3)),
2881 (i64 (COMBINE_rr (i32 (C2_mux (i1 PredRegs:$src1),
2882 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2884 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2886 (i32 (C2_mux (i1 PredRegs:$src1),
2887 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2889 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2890 subreg_loreg))))))>;
2892 // Map from a 1-bit select to logical ops.
2893 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
2894 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
2895 (i1 PredRegs:$src3)),
2896 (OR_pp (AND_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
2897 (AND_pp (NOT_p (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
2899 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
2900 def : Pat<(i1 (load ADDRriS11_2:$addr)),
2901 (i1 (TFR_PdRs (i32 (LDrib ADDRriS11_2:$addr))))>;
2903 // Map for truncating from 64 immediates to 32 bit immediates.
2904 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
2905 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
2907 // Map for truncating from i64 immediates to i1 bit immediates.
2908 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
2909 (i1 (TFR_PdRs (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2912 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
2913 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2914 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2917 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
2918 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2919 (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2921 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
2922 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2923 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2926 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
2927 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2928 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2931 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
2932 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2933 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2936 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
2937 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2938 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2940 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
2941 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
2942 (STrib ADDRriS11_2:$addr, (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0)) )>;
2944 // Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs).
2945 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
2946 // Better way to do this?
2947 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
2948 (i64 (SXTW (i32 IntRegs:$src1)))>;
2950 // Map cmple -> cmpgt.
2951 // rs <= rt -> !(rs > rt).
2952 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
2953 (i1 (NOT_p (C2_cmpgti (i32 IntRegs:$src1), s10ExtPred:$src2)))>;
2955 // rs <= rt -> !(rs > rt).
2956 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2957 (i1 (NOT_p (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2959 // Rss <= Rtt -> !(Rss > Rtt).
2960 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2961 (i1 (NOT_p (C2_cmpgtp (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2963 // Map cmpne -> cmpeq.
2964 // Hexagon_TODO: We should improve on this.
2965 // rs != rt -> !(rs == rt).
2966 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
2967 (i1 (NOT_p(i1 (C2_cmpeqi (i32 IntRegs:$src1), s10ExtPred:$src2))))>;
2969 // Map cmpne(Rs) -> !cmpeqe(Rs).
2970 // rs != rt -> !(rs == rt).
2971 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2972 (i1 (NOT_p (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
2974 // Convert setne back to xor for hexagon since we compute w/ pred registers.
2975 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
2976 (i1 (XOR_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2978 // Map cmpne(Rss) -> !cmpew(Rss).
2979 // rs != rt -> !(rs == rt).
2980 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2981 (i1 (NOT_p (i1 (C2_cmpeqp (i64 DoubleRegs:$src1),
2982 (i64 DoubleRegs:$src2)))))>;
2984 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
2985 // rs >= rt -> !(rt > rs).
2986 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2987 (i1 (NOT_p (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
2989 // cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
2990 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)),
2991 (i1 (C2_cmpgti (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
2993 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
2994 // rss >= rtt -> !(rtt > rss).
2995 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2996 (i1 (NOT_p (i1 (C2_cmpgtp (i64 DoubleRegs:$src2),
2997 (i64 DoubleRegs:$src1)))))>;
2999 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
3000 // !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
3001 // rs < rt -> !(rs >= rt).
3002 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
3003 (i1 (NOT_p (C2_cmpgti (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2))))>;
3005 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
3006 // rs < rt -> rt > rs.
3007 // We can let assembler map it, or we can do in the compiler itself.
3008 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3009 (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
3011 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
3012 // rss < rtt -> (rtt > rss).
3013 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3014 (i1 (C2_cmpgtp (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
3016 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
3017 // rs < rt -> rt > rs.
3018 // We can let assembler map it, or we can do in the compiler itself.
3019 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3020 (i1 (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
3022 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
3023 // rs < rt -> rt > rs.
3024 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3025 (i1 (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
3027 // Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs)
3028 def : Pat <(i1 (setuge (i32 IntRegs:$src1), 0)),
3029 (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src1)))>;
3031 // Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1)
3032 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ExtPred:$src2)),
3033 (i1 (C2_cmpgtui (i32 IntRegs:$src1), (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
3035 // Generate cmpgtu(Rs, #u9)
3036 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)),
3037 (i1 (C2_cmpgtui (i32 IntRegs:$src1), u9ExtPred:$src2))>;
3039 // Map from Rs >= Rt -> !(Rt > Rs).
3040 // rs >= rt -> !(rt > rs).
3041 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3042 (i1 (NOT_p (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
3044 // Map from Rs >= Rt -> !(Rt > Rs).
3045 // rs >= rt -> !(rt > rs).
3046 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3047 (i1 (NOT_p (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
3049 // Map from cmpleu(Rs, Rt) -> !cmpgtu(Rs, Rt).
3050 // Map from (Rs <= Rt) -> !(Rs > Rt).
3051 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3052 (i1 (NOT_p (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
3054 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
3055 // Map from (Rs <= Rt) -> !(Rs > Rt).
3056 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3057 (i1 (NOT_p (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
3061 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
3062 (i32 (C2_muxii (i1 PredRegs:$src1), -1, 0))>;
3065 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
3066 (i64 (COMBINE_rr (TFRI -1), (C2_muxii (i1 PredRegs:$src1), -1, 0)))>;
3068 // Convert sign-extended load back to load and sign extend.
3070 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
3071 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
3073 // Convert any-extended load back to load and sign extend.
3075 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
3076 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
3078 // Convert sign-extended load back to load and sign extend.
3080 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
3081 (i64 (SXTW (LDrih ADDRriS11_1:$src1)))>;
3083 // Convert sign-extended load back to load and sign extend.
3085 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
3086 (i64 (SXTW (LDriw ADDRriS11_2:$src1)))>;
3091 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
3092 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
3095 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
3096 (i64 (COMBINE_rr (TFRI 0), (C2_muxii (i1 PredRegs:$src1), 1, 0)))>,
3100 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
3101 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>,
3105 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
3106 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>,
3109 let AddedComplexity = 20 in
3110 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
3111 s11_0ExtPred:$offset))),
3112 (i64 (COMBINE_rr (TFRI 0), (LDriub_indexed IntRegs:$src1,
3113 s11_0ExtPred:$offset)))>,
3117 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
3118 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>,
3121 let AddedComplexity = 20 in
3122 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
3123 s11_0ExtPred:$offset))),
3124 (i64 (COMBINE_rr (TFRI 0), (LDriub_indexed IntRegs:$src1,
3125 s11_0ExtPred:$offset)))>,
3129 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
3130 (i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>,
3133 let AddedComplexity = 20 in
3134 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
3135 s11_1ExtPred:$offset))),
3136 (i64 (COMBINE_rr (TFRI 0), (LDriuh_indexed IntRegs:$src1,
3137 s11_1ExtPred:$offset)))>,
3141 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
3142 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>,
3145 let AddedComplexity = 100 in
3146 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
3147 (i64 (COMBINE_rr (TFRI 0), (LDriw_indexed IntRegs:$src1,
3148 s11_2ExtPred:$offset)))>,
3151 let AddedComplexity = 10 in
3152 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
3153 (i32 (LDriw ADDRriS11_0:$src1))>;
3155 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
3156 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
3157 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
3159 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
3160 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
3161 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
3163 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
3164 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
3165 (i64 (SXTW (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))))>;
3168 let AddedComplexity = 100 in
3169 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
3171 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
3172 s11_2ExtPred:$offset2)))))),
3173 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
3174 (LDriw_indexed IntRegs:$src2,
3175 s11_2ExtPred:$offset2)))>;
3177 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
3179 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
3180 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
3181 (LDriw ADDRriS11_2:$srcLow)))>;
3183 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
3185 (i64 (zext (i32 IntRegs:$srcLow))))),
3186 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
3189 let AddedComplexity = 100 in
3190 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
3192 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
3193 s11_2ExtPred:$offset2)))))),
3194 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
3195 (LDriw_indexed IntRegs:$src2,
3196 s11_2ExtPred:$offset2)))>;
3198 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
3200 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
3201 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
3202 (LDriw ADDRriS11_2:$srcLow)))>;
3204 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
3206 (i64 (zext (i32 IntRegs:$srcLow))))),
3207 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
3210 // Any extended 64-bit load.
3211 // anyext i32 -> i64
3212 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
3213 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>,
3216 // When there is an offset we should prefer the pattern below over the pattern above.
3217 // The complexity of the above is 13 (gleaned from HexagonGenDAGIsel.inc)
3218 // So this complexity below is comfortably higher to allow for choosing the below.
3219 // If this is not done then we generate addresses such as
3220 // ********************************************
3221 // r1 = add (r0, #4)
3222 // r1 = memw(r1 + #0)
3224 // r1 = memw(r0 + #4)
3225 // ********************************************
3226 let AddedComplexity = 100 in
3227 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
3228 (i64 (COMBINE_rr (TFRI 0), (LDriw_indexed IntRegs:$src1,
3229 s11_2ExtPred:$offset)))>,
3232 // anyext i16 -> i64.
3233 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
3234 (i64 (COMBINE_rr (TFRI 0), (LDrih ADDRriS11_2:$src1)))>,
3237 let AddedComplexity = 20 in
3238 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
3239 s11_1ExtPred:$offset))),
3240 (i64 (COMBINE_rr (TFRI 0), (LDrih_indexed IntRegs:$src1,
3241 s11_1ExtPred:$offset)))>,
3244 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
3245 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
3246 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>,
3249 // Multiply 64-bit unsigned and use upper result.
3250 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
3265 (COMBINE_rr (TFRI 0),
3271 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
3273 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
3274 subreg_loreg)))), 32)),
3276 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3277 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
3278 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
3279 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
3280 32)), subreg_loreg)))),
3281 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3282 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
3284 // Multiply 64-bit signed and use upper result.
3285 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
3289 (COMBINE_rr (TFRI 0),
3299 (COMBINE_rr (TFRI 0),
3305 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
3307 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
3308 subreg_loreg)))), 32)),
3310 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3311 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
3312 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
3313 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
3314 32)), subreg_loreg)))),
3315 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3316 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
3318 // Hexagon specific ISD nodes.
3319 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
3320 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
3321 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
3322 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
3323 SDTHexagonADJDYNALLOC>;
3324 // Needed to tag these instructions for stack layout.
3325 let usesCustomInserter = 1 in
3326 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
3328 "$dst = add($src1, #$src2)",
3329 [(set (i32 IntRegs:$dst),
3330 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
3331 s16ImmPred:$src2))]>;
3333 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
3334 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
3335 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
3337 [(set (i32 IntRegs:$dst),
3338 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
3340 let AddedComplexity = 100 in
3341 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
3342 (COPY (i32 IntRegs:$src1))>;
3344 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
3346 def : Pat<(HexagonWrapperJT tjumptable:$dst),
3347 (i32 (CONST32_set_jt tjumptable:$dst))>;
3351 // Multi-class for logical operators :
3352 // Shift by immediate/register and accumulate/logical
3353 multiclass xtype_imm<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
3354 def _ri : SInst_acc<(outs IntRegs:$dst),
3355 (ins IntRegs:$src1, IntRegs:$src2, u5Imm:$src3),
3356 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
3357 [(set (i32 IntRegs:$dst),
3358 (OpNode2 (i32 IntRegs:$src1),
3359 (OpNode1 (i32 IntRegs:$src2),
3360 u5ImmPred:$src3)))],
3363 def d_ri : SInst_acc<(outs DoubleRegs:$dst),
3364 (ins DoubleRegs:$src1, DoubleRegs:$src2, u6Imm:$src3),
3365 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
3366 [(set (i64 DoubleRegs:$dst), (OpNode2 (i64 DoubleRegs:$src1),
3367 (OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
3371 // Multi-class for logical operators :
3372 // Shift by register and accumulate/logical (32/64 bits)
3373 multiclass xtype_reg<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
3374 def _rr : SInst_acc<(outs IntRegs:$dst),
3375 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
3376 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
3377 [(set (i32 IntRegs:$dst),
3378 (OpNode2 (i32 IntRegs:$src1),
3379 (OpNode1 (i32 IntRegs:$src2),
3380 (i32 IntRegs:$src3))))],
3383 def d_rr : SInst_acc<(outs DoubleRegs:$dst),
3384 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3385 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
3386 [(set (i64 DoubleRegs:$dst),
3387 (OpNode2 (i64 DoubleRegs:$src1),
3388 (OpNode1 (i64 DoubleRegs:$src2),
3389 (i32 IntRegs:$src3))))],
3394 multiclass basic_xtype_imm<string OpcStr, SDNode OpNode> {
3395 let AddedComplexity = 100 in
3396 defm _ADD : xtype_imm< !strconcat("+= ", OpcStr), OpNode, add>;
3397 defm _SUB : xtype_imm< !strconcat("-= ", OpcStr), OpNode, sub>;
3398 defm _AND : xtype_imm< !strconcat("&= ", OpcStr), OpNode, and>;
3399 defm _OR : xtype_imm< !strconcat("|= ", OpcStr), OpNode, or>;
3402 multiclass basic_xtype_reg<string OpcStr, SDNode OpNode> {
3403 let AddedComplexity = 100 in
3404 defm _ADD : xtype_reg< !strconcat("+= ", OpcStr), OpNode, add>;
3405 defm _SUB : xtype_reg< !strconcat("-= ", OpcStr), OpNode, sub>;
3406 defm _AND : xtype_reg< !strconcat("&= ", OpcStr), OpNode, and>;
3407 defm _OR : xtype_reg< !strconcat("|= ", OpcStr), OpNode, or>;
3410 multiclass xtype_xor_imm<string OpcStr, SDNode OpNode> {
3411 let AddedComplexity = 100 in
3412 defm _XOR : xtype_imm< !strconcat("^= ", OpcStr), OpNode, xor>;
3415 defm ASL : basic_xtype_imm<"asl", shl>, basic_xtype_reg<"asl", shl>,
3416 xtype_xor_imm<"asl", shl>;
3418 defm LSR : basic_xtype_imm<"lsr", srl>, basic_xtype_reg<"lsr", srl>,
3419 xtype_xor_imm<"lsr", srl>;
3421 defm ASR : basic_xtype_imm<"asr", sra>, basic_xtype_reg<"asr", sra>;
3422 defm LSL : basic_xtype_reg<"lsl", shl>;
3424 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
3425 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
3426 (i32 (MPYI_rin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
3428 //===----------------------------------------------------------------------===//
3429 // V3 Instructions +
3430 //===----------------------------------------------------------------------===//
3432 include "HexagonInstrInfoV3.td"
3434 //===----------------------------------------------------------------------===//
3435 // V3 Instructions -
3436 //===----------------------------------------------------------------------===//
3438 //===----------------------------------------------------------------------===//
3439 // V4 Instructions +
3440 //===----------------------------------------------------------------------===//
3442 include "HexagonInstrInfoV4.td"
3444 //===----------------------------------------------------------------------===//
3445 // V4 Instructions -
3446 //===----------------------------------------------------------------------===//
3448 //===----------------------------------------------------------------------===//
3449 // V5 Instructions +
3450 //===----------------------------------------------------------------------===//
3452 include "HexagonInstrInfoV5.td"
3454 //===----------------------------------------------------------------------===//
3455 // V5 Instructions -
3456 //===----------------------------------------------------------------------===//