1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
17 // Multi-class for logical operators.
18 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
19 def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
20 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
21 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),
23 def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
24 !strconcat("$dst = ", !strconcat(OpcStr, "(#$b, $c)")),
25 [(set (i32 IntRegs:$dst), (OpNode s10Imm:$b,
29 // Multi-class for compare ops.
30 let isCompare = 1 in {
31 multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
32 def rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
33 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
34 [(set (i1 PredRegs:$dst),
35 (OpNode (i64 DoubleRegs:$b), (i64 DoubleRegs:$c)))]>;
37 multiclass CMP32_rr<string OpcStr, PatFrag OpNode> {
38 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
39 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
40 [(set (i1 PredRegs:$dst),
41 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
44 multiclass CMP32_rr_ri_s10<string OpcStr, string CextOp, PatFrag OpNode> {
45 let CextOpcode = CextOp in {
46 let InputType = "reg" in
47 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
48 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
49 [(set (i1 PredRegs:$dst),
50 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
52 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1,
53 opExtentBits = 10, InputType = "imm" in
54 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Ext:$c),
55 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
56 [(set (i1 PredRegs:$dst),
57 (OpNode (i32 IntRegs:$b), s10ExtPred:$c))]>;
61 multiclass CMP32_rr_ri_u9<string OpcStr, string CextOp, PatFrag OpNode> {
62 let CextOpcode = CextOp in {
63 let InputType = "reg" in
64 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
65 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
66 [(set (i1 PredRegs:$dst),
67 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
69 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0,
70 opExtentBits = 9, InputType = "imm" in
71 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Ext:$c),
72 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
73 [(set (i1 PredRegs:$dst),
74 (OpNode (i32 IntRegs:$b), u9ExtPred:$c))]>;
78 multiclass CMP32_ri_u8<string OpcStr, PatFrag OpNode> {
79 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in
80 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u8Ext:$c),
81 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
82 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
86 multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
87 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
88 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Ext:$c),
89 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
90 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
95 //===----------------------------------------------------------------------===//
96 // ALU32/ALU (Instructions with register-register form)
97 //===----------------------------------------------------------------------===//
98 multiclass ALU32_Pbase<string mnemonic, bit isNot,
101 let PNewValue = !if(isPredNew, "new", "") in
102 def NAME : ALU32_rr<(outs IntRegs:$dst),
103 (ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
104 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
105 ") $dst = ")#mnemonic#"($src2, $src3)",
109 multiclass ALU32_Pred<string mnemonic, bit PredNot> {
110 let PredSense = !if(PredNot, "false", "true") in {
111 defm _c#NAME : ALU32_Pbase<mnemonic, PredNot, 0>;
113 defm _cdn#NAME : ALU32_Pbase<mnemonic, PredNot, 1>;
117 let InputType = "reg" in
118 multiclass ALU32_base<string mnemonic, string CextOp, SDNode OpNode> {
119 let CextOpcode = CextOp, BaseOpcode = CextOp#_rr in {
120 let isPredicable = 1 in
121 def NAME : ALU32_rr<(outs IntRegs:$dst),
122 (ins IntRegs:$src1, IntRegs:$src2),
123 "$dst = "#mnemonic#"($src1, $src2)",
124 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
125 (i32 IntRegs:$src2)))]>;
127 let neverHasSideEffects = 1, isPredicated = 1 in {
128 defm Pt : ALU32_Pred<mnemonic, 0>;
129 defm NotPt : ALU32_Pred<mnemonic, 1>;
134 let isCommutable = 1 in {
135 defm ADD_rr : ALU32_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
136 defm AND_rr : ALU32_base<"and", "AND", and>, ImmRegRel, PredNewRel;
137 defm XOR_rr : ALU32_base<"xor", "XOR", xor>, ImmRegRel, PredNewRel;
138 defm OR_rr : ALU32_base<"or", "OR", or>, ImmRegRel, PredNewRel;
141 defm SUB_rr : ALU32_base<"sub", "SUB", sub>, ImmRegRel, PredNewRel;
143 //===----------------------------------------------------------------------===//
144 // ALU32/ALU (ADD with register-immediate form)
145 //===----------------------------------------------------------------------===//
146 multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
147 let PNewValue = !if(isPredNew, "new", "") in
148 def NAME : ALU32_ri<(outs IntRegs:$dst),
149 (ins PredRegs:$src1, IntRegs:$src2, s8Ext: $src3),
150 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
151 ") $dst = ")#mnemonic#"($src2, #$src3)",
155 multiclass ALU32ri_Pred<string mnemonic, bit PredNot> {
156 let PredSense = !if(PredNot, "false", "true") in {
157 defm _c#NAME : ALU32ri_Pbase<mnemonic, PredNot, 0>;
159 defm _cdn#NAME : ALU32ri_Pbase<mnemonic, PredNot, 1>;
163 let isExtendable = 1, InputType = "imm" in
164 multiclass ALU32ri_base<string mnemonic, string CextOp, SDNode OpNode> {
165 let CextOpcode = CextOp, BaseOpcode = CextOp#_ri in {
166 let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
168 def NAME : ALU32_ri<(outs IntRegs:$dst),
169 (ins IntRegs:$src1, s16Ext:$src2),
170 "$dst = "#mnemonic#"($src1, #$src2)",
171 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
172 (s16ExtPred:$src2)))]>;
174 let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
175 neverHasSideEffects = 1, isPredicated = 1 in {
176 defm Pt : ALU32ri_Pred<mnemonic, 0>;
177 defm NotPt : ALU32ri_Pred<mnemonic, 1>;
182 defm ADD_ri : ALU32ri_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
184 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
185 CextOpcode = "OR", InputType = "imm" in
186 def OR_ri : ALU32_ri<(outs IntRegs:$dst),
187 (ins IntRegs:$src1, s10Ext:$src2),
188 "$dst = or($src1, #$src2)",
189 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
190 s10ExtPred:$src2))]>, ImmRegRel;
192 def NOT_rr : ALU32_rr<(outs IntRegs:$dst),
195 [(set (i32 IntRegs:$dst), (not (i32 IntRegs:$src1)))]>;
197 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
198 InputType = "imm", CextOpcode = "AND" in
199 def AND_ri : ALU32_ri<(outs IntRegs:$dst),
200 (ins IntRegs:$src1, s10Ext:$src2),
201 "$dst = and($src1, #$src2)",
202 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
203 s10ExtPred:$src2))]>, ImmRegRel;
205 def NEG : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
207 [(set (i32 IntRegs:$dst), (ineg (i32 IntRegs:$src1)))]>;
209 let neverHasSideEffects = 1 in
210 def NOP : ALU32_rr<(outs), (ins),
214 // Rd32=sub(#s10,Rs32)
215 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
216 CextOpcode = "SUB", InputType = "imm" in
217 def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
218 (ins s10Ext:$src1, IntRegs:$src2),
219 "$dst = sub(#$src1, $src2)",
220 [(set IntRegs:$dst, (sub s10ExtPred:$src1, IntRegs:$src2))]>,
224 multiclass TFR_Pred<bit PredNot> {
225 let PredSense = !if(PredNot, "false", "true") in {
226 def _c#NAME : ALU32_rr<(outs IntRegs:$dst),
227 (ins PredRegs:$src1, IntRegs:$src2),
228 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
231 let PNewValue = "new" in
232 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
233 (ins PredRegs:$src1, IntRegs:$src2),
234 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
239 let InputType = "reg", neverHasSideEffects = 1 in
240 multiclass TFR_base<string CextOp> {
241 let CextOpcode = CextOp, BaseOpcode = CextOp in {
242 let isPredicable = 1 in
243 def NAME : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
247 let isPredicated = 1 in {
248 defm Pt : TFR_Pred<0>;
249 defm NotPt : TFR_Pred<1>;
254 multiclass TFR64_Pred<bit PredNot> {
255 let PredSense = !if(PredNot, "false", "true") in {
256 def _c#NAME : ALU32_rr<(outs DoubleRegs:$dst),
257 (ins PredRegs:$src1, DoubleRegs:$src2),
258 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
261 let PNewValue = "new" in
262 def _cdn#NAME : ALU32_rr<(outs DoubleRegs:$dst),
263 (ins PredRegs:$src1, DoubleRegs:$src2),
264 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
269 let InputType = "reg", neverHasSideEffects = 1 in
270 multiclass TFR64_base<string CextOp> {
271 let CextOpcode = CextOp, BaseOpcode = CextOp in {
272 let isPredicable = 1 in
273 def NAME : ALU32_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
277 let isPredicated = 1 in {
278 defm Pt : TFR64_Pred<0>;
279 defm NotPt : TFR64_Pred<1>;
285 multiclass TFRI_Pred<bit PredNot> {
286 let PredSense = !if(PredNot, "false", "true") in {
287 def _c#NAME : ALU32_ri<(outs IntRegs:$dst),
288 (ins PredRegs:$src1, s12Ext:$src2),
289 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = #$src2",
293 let PNewValue = "new" in
294 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
295 (ins PredRegs:$src1, s12Ext:$src2),
296 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = #$src2",
301 let InputType = "imm", isExtendable = 1, isExtentSigned = 1 in
302 multiclass TFRI_base<string CextOp> {
303 let CextOpcode = CextOp, BaseOpcode = CextOp#I in {
304 let opExtendable = 1, opExtentBits = 16, isMoveImm = 1, isPredicable = 1,
305 isReMaterializable = 1 in
306 def NAME : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
308 [(set (i32 IntRegs:$dst), s16ExtPred:$src1)]>;
310 let opExtendable = 2, opExtentBits = 12, neverHasSideEffects = 1,
311 isPredicated = 1 in {
312 defm Pt : TFRI_Pred<0>;
313 defm NotPt : TFRI_Pred<1>;
318 defm TFRI : TFRI_base<"TFR">, ImmRegRel, PredNewRel;
319 defm TFR : TFR_base<"TFR">, ImmRegRel, PredNewRel;
320 defm TFR64 : TFR64_base<"TFR64">, ImmRegRel, PredNewRel;
322 // Transfer control register.
323 let neverHasSideEffects = 1 in
324 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
327 //===----------------------------------------------------------------------===//
329 //===----------------------------------------------------------------------===//
332 //===----------------------------------------------------------------------===//
334 //===----------------------------------------------------------------------===//
338 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
339 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
341 def HexagonWrapperCombineII :
342 SDNode<"HexagonISD::WrapperCombineII", SDTHexagonI64I32I32>;
343 def HexagonWrapperCombineRR :
344 SDNode<"HexagonISD::WrapperCombineRR", SDTHexagonI64I32I32>;
346 // Combines the two integer registers SRC1 and SRC2 into a double register.
347 let isPredicable = 1 in
348 def COMBINE_rr : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1,
350 "$dst = combine($src1, $src2)",
351 [(set (i64 DoubleRegs:$dst),
352 (i64 (HexagonWrapperCombineRR (i32 IntRegs:$src1),
353 (i32 IntRegs:$src2))))]>;
355 // Rd=combine(Rt.[HL], Rs.[HL])
356 class COMBINE_halves<string A, string B>: ALU32_rr<(outs IntRegs:$dst),
359 "$dst = combine($src1."# A #", $src2."# B #")", []>;
361 let isPredicable = 1 in {
362 def COMBINE_hh : COMBINE_halves<"H", "H">;
363 def COMBINE_hl : COMBINE_halves<"H", "L">;
364 def COMBINE_lh : COMBINE_halves<"L", "H">;
365 def COMBINE_ll : COMBINE_halves<"L", "L">;
368 def : Pat<(i32 (trunc (i64 (srl (i64 DoubleRegs:$a), (i32 16))))),
369 (COMBINE_lh (EXTRACT_SUBREG (i64 DoubleRegs:$a), subreg_hireg),
370 (EXTRACT_SUBREG (i64 DoubleRegs:$a), subreg_loreg))>;
372 // Combines the two immediates SRC1 and SRC2 into a double register.
373 class COMBINE_imm<Operand imm1, Operand imm2, PatLeaf pat1, PatLeaf pat2> :
374 ALU32_ii<(outs DoubleRegs:$dst), (ins imm1:$src1, imm2:$src2),
375 "$dst = combine(#$src1, #$src2)",
376 [(set (i64 DoubleRegs:$dst),
377 (i64 (HexagonWrapperCombineII (i32 pat1:$src1), (i32 pat2:$src2))))]>;
379 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8 in
380 def COMBINE_Ii : COMBINE_imm<s8Ext, s8Imm, s8ExtPred, s8ImmPred>;
383 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
386 "$dst = vmux($src1, $src2, $src3)",
389 let CextOpcode = "MUX", InputType = "reg" in
390 def MUX_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
391 IntRegs:$src2, IntRegs:$src3),
392 "$dst = mux($src1, $src2, $src3)",
393 [(set (i32 IntRegs:$dst),
394 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
395 (i32 IntRegs:$src3))))]>, ImmRegRel;
397 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
398 CextOpcode = "MUX", InputType = "imm" in
399 def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
401 "$dst = mux($src1, #$src2, $src3)",
402 [(set (i32 IntRegs:$dst),
403 (i32 (select (i1 PredRegs:$src1), s8ExtPred:$src2,
404 (i32 IntRegs:$src3))))]>, ImmRegRel;
406 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
407 CextOpcode = "MUX", InputType = "imm" in
408 def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
410 "$dst = mux($src1, $src2, #$src3)",
411 [(set (i32 IntRegs:$dst),
412 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
413 s8ExtPred:$src3)))]>, ImmRegRel;
415 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
416 def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
418 "$dst = mux($src1, #$src2, #$src3)",
419 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
421 s8ImmPred:$src3)))]>;
424 let isPredicable = 1 in
425 def ASLH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
426 "$dst = aslh($src1)",
427 [(set (i32 IntRegs:$dst), (shl 16, (i32 IntRegs:$src1)))]>;
429 let isPredicable = 1 in
430 def ASRH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
431 "$dst = asrh($src1)",
432 [(set (i32 IntRegs:$dst), (sra 16, (i32 IntRegs:$src1)))]>;
435 let isPredicable = 1 in
436 def SXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
437 "$dst = sxtb($src1)",
438 [(set (i32 IntRegs:$dst), (sext_inreg (i32 IntRegs:$src1), i8))]>;
440 let isPredicable = 1 in
441 def SXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
442 "$dst = sxth($src1)",
443 [(set (i32 IntRegs:$dst), (sext_inreg (i32 IntRegs:$src1), i16))]>;
446 let isPredicable = 1, neverHasSideEffects = 1 in
447 def ZXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
448 "$dst = zxtb($src1)",
451 let isPredicable = 1, neverHasSideEffects = 1 in
452 def ZXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
453 "$dst = zxth($src1)",
455 //===----------------------------------------------------------------------===//
457 //===----------------------------------------------------------------------===//
460 //===----------------------------------------------------------------------===//
462 //===----------------------------------------------------------------------===//
464 // Conditional combine.
465 let neverHasSideEffects = 1, isPredicated = 1 in
466 def COMBINE_rr_cPt : ALU32_rr<(outs DoubleRegs:$dst),
467 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
468 "if ($src1) $dst = combine($src2, $src3)",
471 let neverHasSideEffects = 1, isPredicated = 1 in
472 def COMBINE_rr_cNotPt : ALU32_rr<(outs DoubleRegs:$dst),
473 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
474 "if (!$src1) $dst = combine($src2, $src3)",
477 let neverHasSideEffects = 1, isPredicated = 1 in
478 def COMBINE_rr_cdnPt : ALU32_rr<(outs DoubleRegs:$dst),
479 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
480 "if ($src1.new) $dst = combine($src2, $src3)",
483 let neverHasSideEffects = 1, isPredicated = 1 in
484 def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst),
485 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
486 "if (!$src1.new) $dst = combine($src2, $src3)",
490 defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", "CMPGTU", setugt>, ImmRegRel;
491 defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", "CMPGT", setgt>, ImmRegRel;
492 defm CMPLT : CMP32_rr<"cmp.lt", setlt>;
493 defm CMPLTU : CMP32_rr<"cmp.ltu", setult>;
494 defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", "CMPEQ", seteq>, ImmRegRel;
495 defm CMPGE : CMP32_ri_s8<"cmp.ge", setge>;
496 defm CMPGEU : CMP32_ri_u8<"cmp.geu", setuge>;
498 def CTLZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
500 [(set (i32 IntRegs:$dst), (ctlz (i32 IntRegs:$src1)))]>;
502 def CTTZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
504 [(set (i32 IntRegs:$dst), (cttz (i32 IntRegs:$src1)))]>;
506 def CTLZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
508 [(set (i32 IntRegs:$dst), (i32 (trunc (ctlz (i64 DoubleRegs:$src1)))))]>;
510 def CTTZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
512 [(set (i32 IntRegs:$dst), (i32 (trunc (cttz (i64 DoubleRegs:$src1)))))]>;
514 def TSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
515 "$dst = tstbit($src1, $src2)",
516 [(set (i1 PredRegs:$dst),
517 (setne (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>;
519 def TSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
520 "$dst = tstbit($src1, $src2)",
521 [(set (i1 PredRegs:$dst),
522 (setne (and (shl 1, (u5ImmPred:$src2)), (i32 IntRegs:$src1)), 0))]>;
524 //===----------------------------------------------------------------------===//
526 //===----------------------------------------------------------------------===//
529 //===----------------------------------------------------------------------===//
531 //===----------------------------------------------------------------------===//
533 def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
535 "$dst = add($src1, $src2)",
536 [(set (i64 DoubleRegs:$dst), (add (i64 DoubleRegs:$src1),
537 (i64 DoubleRegs:$src2)))]>;
542 defm CMPEHexagon4 : CMP64_rr<"cmp.eq", seteq>;
543 defm CMPGT64 : CMP64_rr<"cmp.gt", setgt>;
544 defm CMPGTU64 : CMP64_rr<"cmp.gtu", setugt>;
546 // Logical operations.
547 def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
549 "$dst = and($src1, $src2)",
550 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
551 (i64 DoubleRegs:$src2)))]>;
553 def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
555 "$dst = or($src1, $src2)",
556 [(set (i64 DoubleRegs:$dst), (or (i64 DoubleRegs:$src1),
557 (i64 DoubleRegs:$src2)))]>;
559 def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
561 "$dst = xor($src1, $src2)",
562 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
563 (i64 DoubleRegs:$src2)))]>;
566 def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
567 "$dst = max($src2, $src1)",
568 [(set (i32 IntRegs:$dst),
569 (i32 (select (i1 (setlt (i32 IntRegs:$src2),
570 (i32 IntRegs:$src1))),
571 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
573 def MAXUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
574 "$dst = maxu($src2, $src1)",
575 [(set (i32 IntRegs:$dst),
576 (i32 (select (i1 (setult (i32 IntRegs:$src2),
577 (i32 IntRegs:$src1))),
578 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
580 def MAXd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
582 "$dst = max($src2, $src1)",
583 [(set (i64 DoubleRegs:$dst),
584 (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
585 (i64 DoubleRegs:$src1))),
586 (i64 DoubleRegs:$src1),
587 (i64 DoubleRegs:$src2))))]>;
589 def MAXUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
591 "$dst = maxu($src2, $src1)",
592 [(set (i64 DoubleRegs:$dst),
593 (i64 (select (i1 (setult (i64 DoubleRegs:$src2),
594 (i64 DoubleRegs:$src1))),
595 (i64 DoubleRegs:$src1),
596 (i64 DoubleRegs:$src2))))]>;
599 def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
600 "$dst = min($src2, $src1)",
601 [(set (i32 IntRegs:$dst),
602 (i32 (select (i1 (setgt (i32 IntRegs:$src2),
603 (i32 IntRegs:$src1))),
604 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
606 def MINUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
607 "$dst = minu($src2, $src1)",
608 [(set (i32 IntRegs:$dst),
609 (i32 (select (i1 (setugt (i32 IntRegs:$src2),
610 (i32 IntRegs:$src1))),
611 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
613 def MINd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
615 "$dst = min($src2, $src1)",
616 [(set (i64 DoubleRegs:$dst),
617 (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
618 (i64 DoubleRegs:$src1))),
619 (i64 DoubleRegs:$src1),
620 (i64 DoubleRegs:$src2))))]>;
622 def MINUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
624 "$dst = minu($src2, $src1)",
625 [(set (i64 DoubleRegs:$dst),
626 (i64 (select (i1 (setugt (i64 DoubleRegs:$src2),
627 (i64 DoubleRegs:$src1))),
628 (i64 DoubleRegs:$src1),
629 (i64 DoubleRegs:$src2))))]>;
632 def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
634 "$dst = sub($src1, $src2)",
635 [(set (i64 DoubleRegs:$dst), (sub (i64 DoubleRegs:$src1),
636 (i64 DoubleRegs:$src2)))]>;
638 // Subtract halfword.
640 //===----------------------------------------------------------------------===//
642 //===----------------------------------------------------------------------===//
644 //===----------------------------------------------------------------------===//
646 //===----------------------------------------------------------------------===//
648 //===----------------------------------------------------------------------===//
650 //===----------------------------------------------------------------------===//
652 //===----------------------------------------------------------------------===//
654 //===----------------------------------------------------------------------===//
656 //===----------------------------------------------------------------------===//
658 //===----------------------------------------------------------------------===//
660 //===----------------------------------------------------------------------===//
662 //===----------------------------------------------------------------------===//
663 // Logical reductions on predicates.
665 // Looping instructions.
667 // Pipelined looping instructions.
669 // Logical operations on predicates.
670 def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
671 "$dst = and($src1, $src2)",
672 [(set (i1 PredRegs:$dst), (and (i1 PredRegs:$src1),
673 (i1 PredRegs:$src2)))]>;
675 let neverHasSideEffects = 1 in
676 def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
678 "$dst = and($src1, !$src2)",
681 def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
682 "$dst = any8($src1)",
685 def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
686 "$dst = all8($src1)",
689 def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
691 "$dst = vitpack($src1, $src2)",
694 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
697 "$dst = valignb($src1, $src2, $src3)",
700 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
703 "$dst = vspliceb($src1, $src2, $src3)",
706 def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
707 "$dst = mask($src1)",
710 def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
712 [(set (i1 PredRegs:$dst), (not (i1 PredRegs:$src1)))]>;
714 def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
715 "$dst = or($src1, $src2)",
716 [(set (i1 PredRegs:$dst), (or (i1 PredRegs:$src1),
717 (i1 PredRegs:$src2)))]>;
719 def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
720 "$dst = xor($src1, $src2)",
721 [(set (i1 PredRegs:$dst), (xor (i1 PredRegs:$src1),
722 (i1 PredRegs:$src2)))]>;
725 // User control register transfer.
726 //===----------------------------------------------------------------------===//
728 //===----------------------------------------------------------------------===//
731 //===----------------------------------------------------------------------===//
733 //===----------------------------------------------------------------------===//
735 let isBranch = 1, isTerminator=1, isBarrier = 1, isPredicable = 1 in {
736 def JMP : JInst< (outs),
737 (ins brtarget:$offset),
743 let isBranch = 1, isTerminator=1, Defs = [PC],
744 isPredicated = 1 in {
745 def JMP_c : JInst< (outs),
746 (ins PredRegs:$src, brtarget:$offset),
747 "if ($src) jump $offset",
748 [(brcond (i1 PredRegs:$src), bb:$offset)]>;
752 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
753 isPredicated = 1 in {
754 def JMP_cNot : JInst< (outs),
755 (ins PredRegs:$src, brtarget:$offset),
756 "if (!$src) jump $offset",
760 let isTerminator = 1, isBranch = 1, neverHasSideEffects = 1, Defs = [PC],
761 isPredicated = 1 in {
762 def BRCOND : JInst < (outs), (ins PredRegs:$pred, brtarget:$dst),
763 "if ($pred) jump $dst",
767 // Jump to address conditioned on new predicate.
769 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
770 isPredicated = 1 in {
771 def JMP_cdnPt : JInst< (outs),
772 (ins PredRegs:$src, brtarget:$offset),
773 "if ($src.new) jump:t $offset",
778 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
779 isPredicated = 1 in {
780 def JMP_cdnNotPt : JInst< (outs),
781 (ins PredRegs:$src, brtarget:$offset),
782 "if (!$src.new) jump:t $offset",
787 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
788 isPredicated = 1 in {
789 def JMP_cdnPnt : JInst< (outs),
790 (ins PredRegs:$src, brtarget:$offset),
791 "if ($src.new) jump:nt $offset",
796 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
797 isPredicated = 1 in {
798 def JMP_cdnNotPnt : JInst< (outs),
799 (ins PredRegs:$src, brtarget:$offset),
800 "if (!$src.new) jump:nt $offset",
803 //===----------------------------------------------------------------------===//
805 //===----------------------------------------------------------------------===//
807 //===----------------------------------------------------------------------===//
809 //===----------------------------------------------------------------------===//
810 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
811 [SDNPHasChain, SDNPOptInGlue]>;
813 // Jump to address from register.
814 let isPredicable =1, isReturn = 1, isTerminator = 1, isBarrier = 1,
815 Defs = [PC], Uses = [R31] in {
816 def JMPR: JRInst<(outs), (ins),
821 // Jump to address from register.
822 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
823 Defs = [PC], Uses = [R31] in {
824 def JMPR_cPt: JRInst<(outs), (ins PredRegs:$src1),
825 "if ($src1) jumpr r31",
829 // Jump to address from register.
830 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
831 Defs = [PC], Uses = [R31] in {
832 def JMPR_cNotPt: JRInst<(outs), (ins PredRegs:$src1),
833 "if (!$src1) jumpr r31",
837 //===----------------------------------------------------------------------===//
839 //===----------------------------------------------------------------------===//
841 //===----------------------------------------------------------------------===//
843 //===----------------------------------------------------------------------===//
845 // Load -- MEMri operand
846 multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
847 bit isNot, bit isPredNew> {
848 let PNewValue = !if(isPredNew, "new", "") in
849 def NAME : LDInst2<(outs RC:$dst),
850 (ins PredRegs:$src1, MEMri:$addr),
851 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
852 ") ")#"$dst = "#mnemonic#"($addr)",
856 multiclass LD_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
857 let PredSense = !if(PredNot, "false", "true") in {
858 defm _c#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
860 defm _cdn#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
864 let isExtendable = 1, neverHasSideEffects = 1 in
865 multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
866 bits<5> ImmBits, bits<5> PredImmBits> {
868 let CextOpcode = CextOp, BaseOpcode = CextOp in {
869 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
871 def NAME : LDInst2<(outs RC:$dst), (ins MEMri:$addr),
872 "$dst = "#mnemonic#"($addr)",
875 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
876 isPredicated = 1 in {
877 defm Pt : LD_MEMri_Pred<mnemonic, RC, 0 >;
878 defm NotPt : LD_MEMri_Pred<mnemonic, RC, 1 >;
883 let addrMode = BaseImmOffset, isMEMri = "true" in {
884 defm LDrib: LD_MEMri < "memb", "LDrib", IntRegs, 11, 6>, AddrModeRel;
885 defm LDriub: LD_MEMri < "memub" , "LDriub", IntRegs, 11, 6>, AddrModeRel;
886 defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
887 defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel;
888 defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;
889 defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;
892 def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
893 (LDrib ADDRriS11_0:$addr) >;
895 def : Pat < (i32 (zextloadi8 ADDRriS11_0:$addr)),
896 (LDriub ADDRriS11_0:$addr) >;
898 def : Pat < (i32 (sextloadi16 ADDRriS11_1:$addr)),
899 (LDrih ADDRriS11_1:$addr) >;
901 def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)),
902 (LDriuh ADDRriS11_1:$addr) >;
904 def : Pat < (i32 (load ADDRriS11_2:$addr)),
905 (LDriw ADDRriS11_2:$addr) >;
907 def : Pat < (i64 (load ADDRriS11_3:$addr)),
908 (LDrid ADDRriS11_3:$addr) >;
911 // Load - Base with Immediate offset addressing mode
912 multiclass LD_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
913 bit isNot, bit isPredNew> {
914 let PNewValue = !if(isPredNew, "new", "") in
915 def NAME : LDInst2<(outs RC:$dst),
916 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
917 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
918 ") ")#"$dst = "#mnemonic#"($src2+#$src3)",
922 multiclass LD_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
924 let PredSense = !if(PredNot, "false", "true") in {
925 defm _c#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
927 defm _cdn#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
931 let isExtendable = 1, neverHasSideEffects = 1 in
932 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
933 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
934 bits<5> PredImmBits> {
936 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
937 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
938 isPredicable = 1, AddedComplexity = 20 in
939 def NAME : LDInst2<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
940 "$dst = "#mnemonic#"($src1+#$offset)",
943 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
944 isPredicated = 1 in {
945 defm Pt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 0 >;
946 defm NotPt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 1 >;
951 let addrMode = BaseImmOffset in {
952 defm LDrib_indexed: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext,
954 defm LDriub_indexed: LD_Idxd <"memub" , "LDriub", IntRegs, s11_0Ext, u6_0Ext,
956 defm LDrih_indexed: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
958 defm LDriuh_indexed: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext,
960 defm LDriw_indexed: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
962 defm LDrid_indexed: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,
966 let AddedComplexity = 20 in {
967 def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
968 (LDrib_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
970 def : Pat < (i32 (zextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
971 (LDriub_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
973 def : Pat < (i32 (sextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
974 (LDrih_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
976 def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
977 (LDriuh_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
979 def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
980 (LDriw_indexed IntRegs:$src1, s11_2ExtPred:$offset) >;
982 def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
983 (LDrid_indexed IntRegs:$src1, s11_3ExtPred:$offset) >;
986 let neverHasSideEffects = 1 in
987 def LDrid_GP : LDInst2<(outs DoubleRegs:$dst),
988 (ins globaladdress:$global, u16Imm:$offset),
989 "$dst = memd(#$global+$offset)",
993 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
994 def LDd_GP : LDInst2<(outs DoubleRegs:$dst),
995 (ins globaladdress:$global),
996 "$dst = memd(#$global)",
1000 //===----------------------------------------------------------------------===//
1001 // Post increment load
1002 // Make sure that in post increment load, the first operand is always the post
1003 // increment operand.
1004 //===----------------------------------------------------------------------===//
1006 multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1007 bit isNot, bit isPredNew> {
1008 let PNewValue = !if(isPredNew, "new", "") in
1009 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1010 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1011 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1012 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1017 multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,
1018 Operand ImmOp, bit PredNot> {
1019 let PredSense = !if(PredNot, "false", "true") in {
1020 defm _c#NAME : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1022 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1023 defm _cdn#NAME#_V4 : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1027 multiclass LD_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1030 let BaseOpcode = "POST_"#BaseOp in {
1031 let isPredicable = 1 in
1032 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1033 (ins IntRegs:$src1, ImmOp:$offset),
1034 "$dst = "#mnemonic#"($src1++#$offset)",
1038 let isPredicated = 1 in {
1039 defm Pt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1040 defm NotPt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1045 let hasCtrlDep = 1, neverHasSideEffects = 1 in {
1046 defm POST_LDrib : LD_PostInc<"memb", "LDrib", IntRegs, s4_0Imm>,
1048 defm POST_LDriub : LD_PostInc<"memub", "LDriub", IntRegs, s4_0Imm>,
1050 defm POST_LDrih : LD_PostInc<"memh", "LDrih", IntRegs, s4_1Imm>,
1052 defm POST_LDriuh : LD_PostInc<"memuh", "LDriuh", IntRegs, s4_1Imm>,
1054 defm POST_LDriw : LD_PostInc<"memw", "LDriw", IntRegs, s4_2Imm>,
1056 defm POST_LDrid : LD_PostInc<"memd", "LDrid", DoubleRegs, s4_3Imm>,
1060 def : Pat< (i32 (extloadi1 ADDRriS11_0:$addr)),
1061 (i32 (LDrib ADDRriS11_0:$addr)) >;
1063 // Load byte any-extend.
1064 def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
1065 (i32 (LDrib ADDRriS11_0:$addr)) >;
1067 // Indexed load byte any-extend.
1068 let AddedComplexity = 20 in
1069 def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1070 (i32 (LDrib_indexed IntRegs:$src1, s11_0ImmPred:$offset)) >;
1072 let neverHasSideEffects = 1 in
1073 def LDrib_GP : LDInst2<(outs IntRegs:$dst),
1074 (ins globaladdress:$global, u16Imm:$offset),
1075 "$dst = memb(#$global+$offset)",
1079 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1080 def LDb_GP : LDInst2<(outs IntRegs:$dst),
1081 (ins globaladdress:$global),
1082 "$dst = memb(#$global)",
1086 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1087 def LDub_GP : LDInst2<(outs IntRegs:$dst),
1088 (ins globaladdress:$global),
1089 "$dst = memub(#$global)",
1093 def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
1094 (i32 (LDrih ADDRriS11_1:$addr))>;
1096 let AddedComplexity = 20 in
1097 def : Pat < (i32 (extloadi16 (add IntRegs:$src1, s11_1ImmPred:$offset))),
1098 (i32 (LDrih_indexed IntRegs:$src1, s11_1ImmPred:$offset)) >;
1100 let neverHasSideEffects = 1 in
1101 def LDrih_GP : LDInst2<(outs IntRegs:$dst),
1102 (ins globaladdress:$global, u16Imm:$offset),
1103 "$dst = memh(#$global+$offset)",
1107 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1108 def LDh_GP : LDInst2<(outs IntRegs:$dst),
1109 (ins globaladdress:$global),
1110 "$dst = memh(#$global)",
1114 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1115 def LDuh_GP : LDInst2<(outs IntRegs:$dst),
1116 (ins globaladdress:$global),
1117 "$dst = memuh(#$global)",
1121 let AddedComplexity = 10 in
1122 def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
1123 (i32 (LDriub ADDRriS11_0:$addr))>;
1125 let AddedComplexity = 20 in
1126 def : Pat < (i32 (zextloadi1 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1127 (i32 (LDriub_indexed IntRegs:$src1, s11_0ImmPred:$offset))>;
1129 let neverHasSideEffects = 1 in
1130 def LDriub_GP : LDInst2<(outs IntRegs:$dst),
1131 (ins globaladdress:$global, u16Imm:$offset),
1132 "$dst = memub(#$global+$offset)",
1136 // Load unsigned halfword.
1137 let neverHasSideEffects = 1 in
1138 def LDriuh_GP : LDInst2<(outs IntRegs:$dst),
1139 (ins globaladdress:$global, u16Imm:$offset),
1140 "$dst = memuh(#$global+$offset)",
1145 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
1146 isPseudo = 1, Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1147 def LDriw_pred : LDInst2<(outs PredRegs:$dst),
1149 "Error; should not emit",
1153 let neverHasSideEffects = 1 in
1154 def LDriw_GP : LDInst2<(outs IntRegs:$dst),
1155 (ins globaladdress:$global, u16Imm:$offset),
1156 "$dst = memw(#$global+$offset)",
1160 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1161 def LDw_GP : LDInst2<(outs IntRegs:$dst),
1162 (ins globaladdress:$global),
1163 "$dst = memw(#$global)",
1167 // Deallocate stack frame.
1168 let Defs = [R29, R30, R31], Uses = [R29], neverHasSideEffects = 1 in {
1169 def DEALLOCFRAME : LDInst2<(outs), (ins),
1174 // Load and unpack bytes to halfwords.
1175 //===----------------------------------------------------------------------===//
1177 //===----------------------------------------------------------------------===//
1179 //===----------------------------------------------------------------------===//
1181 //===----------------------------------------------------------------------===//
1182 //===----------------------------------------------------------------------===//
1184 //===----------------------------------------------------------------------===//
1186 //===----------------------------------------------------------------------===//
1188 //===----------------------------------------------------------------------===//
1189 //===----------------------------------------------------------------------===//
1191 //===----------------------------------------------------------------------===//
1193 //===----------------------------------------------------------------------===//
1195 //===----------------------------------------------------------------------===//
1196 // Multiply and use lower result.
1198 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in
1199 def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Ext:$src2),
1200 "$dst =+ mpyi($src1, #$src2)",
1201 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1202 u8ExtPred:$src2))]>;
1205 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1206 "$dst =- mpyi($src1, #$src2)",
1207 [(set (i32 IntRegs:$dst), (ineg (mul (i32 IntRegs:$src1),
1208 u8ImmPred:$src2)))]>;
1211 // s9 is NOT the same as m9 - but it works.. so far.
1212 // Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
1213 // depending on the value of m9. See Arch Spec.
1214 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
1215 CextOpcode = "MPYI", InputType = "imm" in
1216 def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
1217 "$dst = mpyi($src1, #$src2)",
1218 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1219 s9ExtPred:$src2))]>, ImmRegRel;
1222 let CextOpcode = "MPYI", InputType = "reg" in
1223 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1224 "$dst = mpyi($src1, $src2)",
1225 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1226 (i32 IntRegs:$src2)))]>, ImmRegRel;
1229 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8,
1230 CextOpcode = "MPYI_acc", InputType = "imm" in
1231 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
1232 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1233 "$dst += mpyi($src2, #$src3)",
1234 [(set (i32 IntRegs:$dst),
1235 (add (mul (i32 IntRegs:$src2), u8ExtPred:$src3),
1236 (i32 IntRegs:$src1)))],
1237 "$src1 = $dst">, ImmRegRel;
1240 let CextOpcode = "MPYI_acc", InputType = "reg" in
1241 def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
1242 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1243 "$dst += mpyi($src2, $src3)",
1244 [(set (i32 IntRegs:$dst),
1245 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1246 (i32 IntRegs:$src1)))],
1247 "$src1 = $dst">, ImmRegRel;
1250 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8 in
1251 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
1252 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1253 "$dst -= mpyi($src2, #$src3)",
1254 [(set (i32 IntRegs:$dst),
1255 (sub (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1256 u8ExtPred:$src3)))],
1259 // Multiply and use upper result.
1260 // Rd=mpy(Rs,Rt.H):<<1:rnd:sat
1261 // Rd=mpy(Rs,Rt.L):<<1:rnd:sat
1263 def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1264 "$dst = mpy($src1, $src2)",
1265 [(set (i32 IntRegs:$dst), (mulhs (i32 IntRegs:$src1),
1266 (i32 IntRegs:$src2)))]>;
1268 // Rd=mpy(Rs,Rt):rnd
1270 def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1271 "$dst = mpyu($src1, $src2)",
1272 [(set (i32 IntRegs:$dst), (mulhu (i32 IntRegs:$src1),
1273 (i32 IntRegs:$src2)))]>;
1275 // Multiply and use full result.
1277 def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1278 "$dst = mpyu($src1, $src2)",
1279 [(set (i64 DoubleRegs:$dst),
1280 (mul (i64 (anyext (i32 IntRegs:$src1))),
1281 (i64 (anyext (i32 IntRegs:$src2)))))]>;
1284 def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1285 "$dst = mpy($src1, $src2)",
1286 [(set (i64 DoubleRegs:$dst),
1287 (mul (i64 (sext (i32 IntRegs:$src1))),
1288 (i64 (sext (i32 IntRegs:$src2)))))]>;
1290 // Multiply and accumulate, use full result.
1291 // Rxx[+-]=mpy(Rs,Rt)
1293 def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
1294 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1295 "$dst += mpy($src2, $src3)",
1296 [(set (i64 DoubleRegs:$dst),
1297 (add (mul (i64 (sext (i32 IntRegs:$src2))),
1298 (i64 (sext (i32 IntRegs:$src3)))),
1299 (i64 DoubleRegs:$src1)))],
1303 def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
1304 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1305 "$dst -= mpy($src2, $src3)",
1306 [(set (i64 DoubleRegs:$dst),
1307 (sub (i64 DoubleRegs:$src1),
1308 (mul (i64 (sext (i32 IntRegs:$src2))),
1309 (i64 (sext (i32 IntRegs:$src3))))))],
1312 // Rxx[+-]=mpyu(Rs,Rt)
1314 def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1315 IntRegs:$src2, IntRegs:$src3),
1316 "$dst += mpyu($src2, $src3)",
1317 [(set (i64 DoubleRegs:$dst),
1318 (add (mul (i64 (anyext (i32 IntRegs:$src2))),
1319 (i64 (anyext (i32 IntRegs:$src3)))),
1320 (i64 DoubleRegs:$src1)))], "$src1 = $dst">;
1323 def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
1324 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1325 "$dst -= mpyu($src2, $src3)",
1326 [(set (i64 DoubleRegs:$dst),
1327 (sub (i64 DoubleRegs:$src1),
1328 (mul (i64 (anyext (i32 IntRegs:$src2))),
1329 (i64 (anyext (i32 IntRegs:$src3))))))],
1333 let InputType = "reg", CextOpcode = "ADD_acc" in
1334 def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1335 IntRegs:$src2, IntRegs:$src3),
1336 "$dst += add($src2, $src3)",
1337 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1338 (i32 IntRegs:$src3)),
1339 (i32 IntRegs:$src1)))],
1340 "$src1 = $dst">, ImmRegRel;
1342 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
1343 InputType = "imm", CextOpcode = "ADD_acc" in
1344 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1345 IntRegs:$src2, s8Ext:$src3),
1346 "$dst += add($src2, #$src3)",
1347 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1348 s8_16ExtPred:$src3),
1349 (i32 IntRegs:$src1)))],
1350 "$src1 = $dst">, ImmRegRel;
1352 let CextOpcode = "SUB_acc", InputType = "reg" in
1353 def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1354 IntRegs:$src2, IntRegs:$src3),
1355 "$dst -= add($src2, $src3)",
1356 [(set (i32 IntRegs:$dst),
1357 (sub (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1358 (i32 IntRegs:$src3))))],
1359 "$src1 = $dst">, ImmRegRel;
1361 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
1362 CextOpcode = "SUB_acc", InputType = "imm" in
1363 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1364 IntRegs:$src2, s8Ext:$src3),
1365 "$dst -= add($src2, #$src3)",
1366 [(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
1367 (add (i32 IntRegs:$src2),
1368 s8_16ExtPred:$src3)))],
1369 "$src1 = $dst">, ImmRegRel;
1371 //===----------------------------------------------------------------------===//
1373 //===----------------------------------------------------------------------===//
1375 //===----------------------------------------------------------------------===//
1377 //===----------------------------------------------------------------------===//
1378 //===----------------------------------------------------------------------===//
1380 //===----------------------------------------------------------------------===//
1382 //===----------------------------------------------------------------------===//
1384 //===----------------------------------------------------------------------===//
1385 //===----------------------------------------------------------------------===//
1387 //===----------------------------------------------------------------------===//
1389 //===----------------------------------------------------------------------===//
1391 //===----------------------------------------------------------------------===//
1392 //===----------------------------------------------------------------------===//
1394 //===----------------------------------------------------------------------===//
1396 //===----------------------------------------------------------------------===//
1398 //===----------------------------------------------------------------------===//
1400 /// Assumptions::: ****** DO NOT IGNORE ********
1401 /// 1. Make sure that in post increment store, the zero'th operand is always the
1402 /// post increment operand.
1403 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
1406 // Store doubleword.
1408 let neverHasSideEffects = 1 in
1409 def STrid_GP : STInst2<(outs),
1410 (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),
1411 "memd(#$global+$offset) = $src",
1415 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1416 def STd_GP : STInst2<(outs),
1417 (ins globaladdress:$global, DoubleRegs:$src),
1418 "memd(#$global) = $src",
1422 let hasCtrlDep = 1, isPredicable = 1 in
1423 def POST_STdri : STInstPI<(outs IntRegs:$dst),
1424 (ins DoubleRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1425 "memd($src2++#$offset) = $src1",
1427 (post_store (i64 DoubleRegs:$src1), (i32 IntRegs:$src2),
1428 s4_3ImmPred:$offset))],
1431 // if ([!]Pv) memd(Rx++#s4:3)=Rtt
1432 // if (Pv) memd(Rx++#s4:3)=Rtt
1433 let AddedComplexity = 10, neverHasSideEffects = 1,
1435 def POST_STdri_cPt : STInst2PI<(outs IntRegs:$dst),
1436 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1438 "if ($src1) memd($src3++#$offset) = $src2",
1442 // if (!Pv) memd(Rx++#s4:3)=Rtt
1443 let AddedComplexity = 10, neverHasSideEffects = 1, isPredicated = 1,
1445 def POST_STdri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1446 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1448 "if (!$src1) memd($src3++#$offset) = $src2",
1452 //===----------------------------------------------------------------------===//
1453 // multiclass for the store instructions with MEMri operand.
1454 //===----------------------------------------------------------------------===//
1455 multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot,
1457 let PNewValue = !if(isPredNew, "new", "") in
1458 def NAME : STInst2<(outs),
1459 (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
1460 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1461 ") ")#mnemonic#"($addr) = $src2",
1465 multiclass ST_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1466 let PredSense = !if(PredNot, "false", "true") in {
1467 defm _c#NAME : ST_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
1470 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1471 defm _cdn#NAME#_V4 : ST_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
1475 let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1476 multiclass ST_MEMri<string mnemonic, string CextOp, RegisterClass RC,
1477 bits<5> ImmBits, bits<5> PredImmBits> {
1479 let CextOpcode = CextOp, BaseOpcode = CextOp in {
1480 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1482 def NAME : STInst2<(outs),
1483 (ins MEMri:$addr, RC:$src),
1484 mnemonic#"($addr) = $src",
1487 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
1488 isPredicated = 1 in {
1489 defm Pt : ST_MEMri_Pred<mnemonic, RC, 0>;
1490 defm NotPt : ST_MEMri_Pred<mnemonic, RC, 1>;
1495 let addrMode = BaseImmOffset, isMEMri = "true" in {
1496 defm STrib: ST_MEMri < "memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
1497 defm STrih: ST_MEMri < "memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
1498 defm STriw: ST_MEMri < "memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
1500 let isNVStorable = 0 in
1501 defm STrid: ST_MEMri < "memd", "STrid", DoubleRegs, 14, 9>, AddrModeRel;
1504 def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
1505 (STrib ADDRriS11_0:$addr, (i32 IntRegs:$src1))>;
1507 def : Pat<(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr),
1508 (STrih ADDRriS11_1:$addr, (i32 IntRegs:$src1))>;
1510 def : Pat<(store (i32 IntRegs:$src1), ADDRriS11_2:$addr),
1511 (STriw ADDRriS11_2:$addr, (i32 IntRegs:$src1))>;
1513 def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
1514 (STrid ADDRriS11_3:$addr, (i64 DoubleRegs:$src1))>;
1517 //===----------------------------------------------------------------------===//
1518 // multiclass for the store instructions with base+immediate offset
1520 //===----------------------------------------------------------------------===//
1521 multiclass ST_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
1522 bit isNot, bit isPredNew> {
1523 let PNewValue = !if(isPredNew, "new", "") in
1524 def NAME : STInst2<(outs),
1525 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
1526 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1527 ") ")#mnemonic#"($src2+#$src3) = $src4",
1531 multiclass ST_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
1533 let PredSense = !if(PredNot, "false", "true"), isPredicated = 1 in {
1534 defm _c#NAME : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
1537 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1538 defm _cdn#NAME#_V4 : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
1542 let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1543 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1544 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
1545 bits<5> PredImmBits> {
1547 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1548 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1550 def NAME : STInst2<(outs),
1551 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1552 mnemonic#"($src1+#$src2) = $src3",
1555 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits in {
1556 defm Pt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 0>;
1557 defm NotPt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 1>;
1562 let addrMode = BaseImmOffset, InputType = "reg" in {
1563 defm STrib_indexed: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext,
1564 u6_0Ext, 11, 6>, AddrModeRel, ImmRegRel;
1565 defm STrih_indexed: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext,
1566 u6_1Ext, 12, 7>, AddrModeRel, ImmRegRel;
1567 defm STriw_indexed: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext,
1568 u6_2Ext, 13, 8>, AddrModeRel, ImmRegRel;
1569 let isNVStorable = 0 in
1570 defm STrid_indexed: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
1571 u6_3Ext, 14, 9>, AddrModeRel;
1574 let AddedComplexity = 10 in {
1575 def : Pat<(truncstorei8 (i32 IntRegs:$src1), (add IntRegs:$src2,
1576 s11_0ExtPred:$offset)),
1577 (STrib_indexed IntRegs:$src2, s11_0ImmPred:$offset,
1578 (i32 IntRegs:$src1))>;
1580 def : Pat<(truncstorei16 (i32 IntRegs:$src1), (add IntRegs:$src2,
1581 s11_1ExtPred:$offset)),
1582 (STrih_indexed IntRegs:$src2, s11_1ImmPred:$offset,
1583 (i32 IntRegs:$src1))>;
1585 def : Pat<(store (i32 IntRegs:$src1), (add IntRegs:$src2,
1586 s11_2ExtPred:$offset)),
1587 (STriw_indexed IntRegs:$src2, s11_2ImmPred:$offset,
1588 (i32 IntRegs:$src1))>;
1590 def : Pat<(store (i64 DoubleRegs:$src1), (add IntRegs:$src2,
1591 s11_3ExtPred:$offset)),
1592 (STrid_indexed IntRegs:$src2, s11_3ImmPred:$offset,
1593 (i64 DoubleRegs:$src1))>;
1596 // memb(gp+#u16:0)=Rt
1597 let neverHasSideEffects = 1 in
1598 def STrib_GP : STInst2<(outs),
1599 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1600 "memb(#$global+$offset) = $src",
1605 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1606 def STb_GP : STInst2<(outs),
1607 (ins globaladdress:$global, IntRegs:$src),
1608 "memb(#$global) = $src",
1612 // memb(Rx++#s4:0)=Rt
1613 let hasCtrlDep = 1, isPredicable = 1 in
1614 def POST_STbri : STInstPI<(outs IntRegs:$dst), (ins IntRegs:$src1,
1617 "memb($src2++#$offset) = $src1",
1619 (post_truncsti8 (i32 IntRegs:$src1), (i32 IntRegs:$src2),
1620 s4_0ImmPred:$offset))],
1623 // if ([!]Pv) memb(Rx++#s4:0)=Rt
1624 // if (Pv) memb(Rx++#s4:0)=Rt
1625 let hasCtrlDep = 1, isPredicated = 1 in
1626 def POST_STbri_cPt : STInst2PI<(outs IntRegs:$dst),
1627 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1628 "if ($src1) memb($src3++#$offset) = $src2",
1631 // if (!Pv) memb(Rx++#s4:0)=Rt
1632 let hasCtrlDep = 1, isPredicated = 1 in
1633 def POST_STbri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1634 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1635 "if (!$src1) memb($src3++#$offset) = $src2",
1638 let neverHasSideEffects = 1 in
1639 def STrih_GP : STInst2<(outs),
1640 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1641 "memh(#$global+$offset) = $src",
1645 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1646 def STh_GP : STInst2<(outs),
1647 (ins globaladdress:$global, IntRegs:$src),
1648 "memh(#$global) = $src",
1652 // memh(Rx++#s4:1)=Rt.H
1653 // memh(Rx++#s4:1)=Rt
1654 let hasCtrlDep = 1, isPredicable = 1 in
1655 def POST_SThri : STInstPI<(outs IntRegs:$dst),
1656 (ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1657 "memh($src2++#$offset) = $src1",
1659 (post_truncsti16 (i32 IntRegs:$src1), (i32 IntRegs:$src2),
1660 s4_1ImmPred:$offset))],
1663 // if ([!]Pv) memh(Rx++#s4:1)=Rt
1664 // if (Pv) memh(Rx++#s4:1)=Rt
1665 let hasCtrlDep = 1, isPredicated = 1 in
1666 def POST_SThri_cPt : STInst2PI<(outs IntRegs:$dst),
1667 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1668 "if ($src1) memh($src3++#$offset) = $src2",
1671 // if (!Pv) memh(Rx++#s4:1)=Rt
1672 let hasCtrlDep = 1, isPredicated = 1 in
1673 def POST_SThri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1674 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1675 "if (!$src1) memh($src3++#$offset) = $src2",
1681 let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1682 def STriw_pred : STInst2<(outs),
1683 (ins MEMri:$addr, PredRegs:$src1),
1684 "Error; should not emit",
1687 let neverHasSideEffects = 1 in
1688 def STriw_GP : STInst2<(outs),
1689 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1690 "memw(#$global+$offset) = $src",
1694 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1695 def STw_GP : STInst2<(outs),
1696 (ins globaladdress:$global, IntRegs:$src),
1697 "memw(#$global) = $src",
1701 let hasCtrlDep = 1, isPredicable = 1 in
1702 def POST_STwri : STInstPI<(outs IntRegs:$dst),
1703 (ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1704 "memw($src2++#$offset) = $src1",
1706 (post_store (i32 IntRegs:$src1), (i32 IntRegs:$src2),
1707 s4_2ImmPred:$offset))],
1710 // if ([!]Pv) memw(Rx++#s4:2)=Rt
1711 // if (Pv) memw(Rx++#s4:2)=Rt
1712 let hasCtrlDep = 1, isPredicated = 1 in
1713 def POST_STwri_cPt : STInst2PI<(outs IntRegs:$dst),
1714 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
1715 "if ($src1) memw($src3++#$offset) = $src2",
1718 // if (!Pv) memw(Rx++#s4:2)=Rt
1719 let hasCtrlDep = 1, isPredicated = 1 in
1720 def POST_STwri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1721 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
1722 "if (!$src1) memw($src3++#$offset) = $src2",
1727 // Allocate stack frame.
1728 let Defs = [R29, R30], Uses = [R31, R30], neverHasSideEffects = 1 in {
1729 def ALLOCFRAME : STInst2<(outs),
1731 "allocframe(#$amt)",
1734 //===----------------------------------------------------------------------===//
1736 //===----------------------------------------------------------------------===//
1738 //===----------------------------------------------------------------------===//
1740 //===----------------------------------------------------------------------===//
1742 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
1743 "$dst = not($src1)",
1744 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
1747 // Sign extend word to doubleword.
1748 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
1749 "$dst = sxtw($src1)",
1750 [(set (i64 DoubleRegs:$dst), (sext (i32 IntRegs:$src1)))]>;
1751 //===----------------------------------------------------------------------===//
1753 //===----------------------------------------------------------------------===//
1755 //===----------------------------------------------------------------------===//
1757 //===----------------------------------------------------------------------===//
1759 def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1760 "$dst = clrbit($src1, #$src2)",
1761 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
1763 (shl 1, u5ImmPred:$src2))))]>;
1765 def CLRBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1766 "$dst = clrbit($src1, #$src2)",
1769 // Map from r0 = and(r1, 2147483647) to r0 = clrbit(r1, #31).
1770 def : Pat <(and (i32 IntRegs:$src1), 2147483647),
1771 (CLRBIT_31 (i32 IntRegs:$src1), 31)>;
1774 def SETBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1775 "$dst = setbit($src1, #$src2)",
1776 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
1777 (shl 1, u5ImmPred:$src2)))]>;
1779 // Map from r0 = or(r1, -2147483648) to r0 = setbit(r1, #31).
1780 def SETBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1781 "$dst = setbit($src1, #$src2)",
1784 def : Pat <(or (i32 IntRegs:$src1), -2147483648),
1785 (SETBIT_31 (i32 IntRegs:$src1), 31)>;
1788 def TOGBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1789 "$dst = setbit($src1, #$src2)",
1790 [(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
1791 (shl 1, u5ImmPred:$src2)))]>;
1793 // Map from r0 = xor(r1, -2147483648) to r0 = togglebit(r1, #31).
1794 def TOGBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1795 "$dst = togglebit($src1, #$src2)",
1798 def : Pat <(xor (i32 IntRegs:$src1), -2147483648),
1799 (TOGBIT_31 (i32 IntRegs:$src1), 31)>;
1801 // Predicate transfer.
1802 let neverHasSideEffects = 1 in
1803 def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
1804 "$dst = $src1 /* Should almost never emit this. */",
1807 def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1),
1808 "$dst = $src1 /* Should almost never emit this. */",
1809 [(set (i1 PredRegs:$dst), (trunc (i32 IntRegs:$src1)))]>;
1810 //===----------------------------------------------------------------------===//
1812 //===----------------------------------------------------------------------===//
1814 //===----------------------------------------------------------------------===//
1816 //===----------------------------------------------------------------------===//
1817 // Shift by immediate.
1818 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1819 "$dst = asr($src1, #$src2)",
1820 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1821 u5ImmPred:$src2))]>;
1823 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1824 "$dst = asr($src1, #$src2)",
1825 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1826 u6ImmPred:$src2))]>;
1828 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1829 "$dst = asl($src1, #$src2)",
1830 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1831 u5ImmPred:$src2))]>;
1833 def ASLd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1834 "$dst = asl($src1, #$src2)",
1835 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1836 u6ImmPred:$src2))]>;
1838 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1839 "$dst = lsr($src1, #$src2)",
1840 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1841 u5ImmPred:$src2))]>;
1843 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1844 "$dst = lsr($src1, #$src2)",
1845 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1846 u6ImmPred:$src2))]>;
1848 // Shift by immediate and add.
1849 let AddedComplexity = 100 in
1850 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
1852 "$dst = addasl($src1, $src2, #$src3)",
1853 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
1854 (shl (i32 IntRegs:$src2),
1855 u3ImmPred:$src3)))]>;
1857 // Shift by register.
1858 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1859 "$dst = asl($src1, $src2)",
1860 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1861 (i32 IntRegs:$src2)))]>;
1863 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1864 "$dst = asr($src1, $src2)",
1865 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1866 (i32 IntRegs:$src2)))]>;
1868 def LSL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1869 "$dst = lsl($src1, $src2)",
1870 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1871 (i32 IntRegs:$src2)))]>;
1873 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1874 "$dst = lsr($src1, $src2)",
1875 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1876 (i32 IntRegs:$src2)))]>;
1878 def ASLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1879 "$dst = asl($src1, $src2)",
1880 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1881 (i32 IntRegs:$src2)))]>;
1883 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1884 "$dst = lsl($src1, $src2)",
1885 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1886 (i32 IntRegs:$src2)))]>;
1888 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1890 "$dst = asr($src1, $src2)",
1891 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1892 (i32 IntRegs:$src2)))]>;
1894 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1896 "$dst = lsr($src1, $src2)",
1897 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1898 (i32 IntRegs:$src2)))]>;
1900 //===----------------------------------------------------------------------===//
1902 //===----------------------------------------------------------------------===//
1904 //===----------------------------------------------------------------------===//
1906 //===----------------------------------------------------------------------===//
1907 //===----------------------------------------------------------------------===//
1909 //===----------------------------------------------------------------------===//
1911 //===----------------------------------------------------------------------===//
1913 //===----------------------------------------------------------------------===//
1914 //===----------------------------------------------------------------------===//
1916 //===----------------------------------------------------------------------===//
1918 //===----------------------------------------------------------------------===//
1920 //===----------------------------------------------------------------------===//
1922 //===----------------------------------------------------------------------===//
1924 //===----------------------------------------------------------------------===//
1925 def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
1926 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
1929 let hasSideEffects = 1, isHexagonSolo = 1 in
1930 def BARRIER : SYSInst<(outs), (ins),
1932 [(HexagonBARRIER)]>;
1934 //===----------------------------------------------------------------------===//
1936 //===----------------------------------------------------------------------===//
1938 // TFRI64 - assembly mapped.
1939 let isReMaterializable = 1 in
1940 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
1942 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
1944 // Pseudo instruction to encode a set of conditional transfers.
1945 // This instruction is used instead of a mux and trades-off codesize
1946 // for performance. We conduct this transformation optimistically in
1947 // the hope that these instructions get promoted to dot-new transfers.
1948 let AddedComplexity = 100, isPredicated = 1 in
1949 def TFR_condset_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
1952 "Error; should not emit",
1953 [(set (i32 IntRegs:$dst),
1954 (i32 (select (i1 PredRegs:$src1),
1955 (i32 IntRegs:$src2),
1956 (i32 IntRegs:$src3))))]>;
1957 let AddedComplexity = 100, isPredicated = 1 in
1958 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
1959 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
1960 "Error; should not emit",
1961 [(set (i32 IntRegs:$dst),
1962 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
1963 s12ImmPred:$src3)))]>;
1965 let AddedComplexity = 100, isPredicated = 1 in
1966 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
1967 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
1968 "Error; should not emit",
1969 [(set (i32 IntRegs:$dst),
1970 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
1971 (i32 IntRegs:$src3))))]>;
1973 let AddedComplexity = 100, isPredicated = 1 in
1974 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
1975 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
1976 "Error; should not emit",
1977 [(set (i32 IntRegs:$dst),
1978 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
1979 s12ImmPred:$src3)))]>;
1981 // Generate frameindex addresses.
1982 let isReMaterializable = 1 in
1983 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
1984 "$dst = add($src1)",
1985 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
1990 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
1991 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
1992 "loop0($offset, #$src2)",
1996 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
1997 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
1998 "loop0($offset, $src2)",
2002 let isBranch = 1, isTerminator = 1, neverHasSideEffects = 1,
2003 Defs = [PC, LC0], Uses = [SA0, LC0] in {
2004 def ENDLOOP0 : Marker<(outs), (ins brtarget:$offset),
2009 // Support for generating global address.
2010 // Taken from X86InstrInfo.td.
2011 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [
2015 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
2016 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
2018 // HI/LO Instructions
2019 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2020 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
2021 "$dst.l = #LO($global)",
2024 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2025 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
2026 "$dst.h = #HI($global)",
2029 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2030 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2031 "$dst.l = #LO($imm_value)",
2035 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2036 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2037 "$dst.h = #HI($imm_value)",
2040 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2041 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2042 "$dst.l = #LO($jt)",
2045 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2046 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2047 "$dst.h = #HI($jt)",
2051 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2052 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2053 "$dst.l = #LO($label)",
2056 let isReMaterializable = 1, isMoveImm = 1 , neverHasSideEffects = 1 in
2057 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2058 "$dst.h = #HI($label)",
2061 // This pattern is incorrect. When we add small data, we should change
2062 // this pattern to use memw(#foo).
2063 // This is for sdata.
2064 let isMoveImm = 1 in
2065 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2066 "$dst = CONST32(#$global)",
2067 [(set (i32 IntRegs:$dst),
2068 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
2070 // This is for non-sdata.
2071 let isReMaterializable = 1, isMoveImm = 1 in
2072 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2073 "$dst = CONST32(#$global)",
2074 [(set (i32 IntRegs:$dst),
2075 (HexagonCONST32 tglobaladdr:$global))]>;
2077 let isReMaterializable = 1, isMoveImm = 1 in
2078 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2079 "$dst = CONST32(#$jt)",
2080 [(set (i32 IntRegs:$dst),
2081 (HexagonCONST32 tjumptable:$jt))]>;
2083 let isReMaterializable = 1, isMoveImm = 1 in
2084 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2085 "$dst = CONST32(#$global)",
2086 [(set (i32 IntRegs:$dst),
2087 (HexagonCONST32_GP tglobaladdr:$global))]>;
2089 let isReMaterializable = 1, isMoveImm = 1 in
2090 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
2091 "$dst = CONST32(#$global)",
2092 [(set (i32 IntRegs:$dst), imm:$global) ]>;
2094 let isReMaterializable = 1, isMoveImm = 1 in
2095 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
2096 "$dst = CONST32($label)",
2097 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
2099 let isReMaterializable = 1, isMoveImm = 1 in
2100 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
2101 "$dst = CONST64(#$global)",
2102 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
2104 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
2105 "$dst = xor($dst, $dst)",
2106 [(set (i1 PredRegs:$dst), 0)]>;
2108 def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2109 "$dst = mpy($src1, $src2)",
2110 [(set (i32 IntRegs:$dst),
2111 (trunc (i64 (srl (i64 (mul (i64 (sext (i32 IntRegs:$src1))),
2112 (i64 (sext (i32 IntRegs:$src2))))),
2115 // Pseudo instructions.
2116 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
2118 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
2119 SDTCisVT<1, i32> ]>;
2121 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
2122 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2124 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
2125 [SDNPHasChain, SDNPOutGlue]>;
2127 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2129 def call : SDNode<"HexagonISD::CALL", SDT_SPCall,
2130 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
2132 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
2133 // Optional Flag and Variable Arguments.
2134 // Its 1 Operand has pointer type.
2135 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
2136 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
2138 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
2139 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
2140 "Should never be emitted",
2141 [(callseq_start timm:$amt)]>;
2144 let Defs = [R29, R30, R31], Uses = [R29] in {
2145 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2146 "Should never be emitted",
2147 [(callseq_end timm:$amt1, timm:$amt2)]>;
2150 let isCall = 1, neverHasSideEffects = 1,
2151 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2152 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2153 def CALL : JInst<(outs), (ins calltarget:$dst),
2157 // Call subroutine from register.
2158 let isCall = 1, neverHasSideEffects = 1,
2159 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2160 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2161 def CALLR : JRInst<(outs), (ins IntRegs:$dst),
2167 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2168 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst),
2169 "jump $dst // TAILCALL", []>;
2171 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2172 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst),
2173 "jump $dst // TAILCALL", []>;
2176 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2177 def TCRETURNR : JInst<(outs), (ins IntRegs:$dst),
2178 "jumpr $dst // TAILCALL", []>;
2180 // Map call instruction.
2181 def : Pat<(call (i32 IntRegs:$dst)),
2182 (CALLR (i32 IntRegs:$dst))>, Requires<[HasV2TOnly]>;
2183 def : Pat<(call tglobaladdr:$dst),
2184 (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
2185 def : Pat<(call texternalsym:$dst),
2186 (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>;
2188 def : Pat<(HexagonTCRet tglobaladdr:$dst),
2189 (TCRETURNtg tglobaladdr:$dst)>;
2190 def : Pat<(HexagonTCRet texternalsym:$dst),
2191 (TCRETURNtext texternalsym:$dst)>;
2192 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
2193 (TCRETURNR (i32 IntRegs:$dst))>;
2195 // Atomic load and store support
2196 // 8 bit atomic load
2197 def : Pat<(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
2198 (i32 (LDub_GP tglobaladdr:$global))>,
2201 def : Pat<(atomic_load_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2202 u16ImmPred:$offset)),
2203 (i32 (LDriub_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2206 def : Pat<(atomic_load_8 ADDRriS11_0:$src1),
2207 (i32 (LDriub ADDRriS11_0:$src1))>;
2209 def : Pat<(atomic_load_8 (add (i32 IntRegs:$src1), s11_0ImmPred:$offset)),
2210 (i32 (LDriub_indexed (i32 IntRegs:$src1), s11_0ImmPred:$offset))>;
2214 // 16 bit atomic load
2215 def : Pat<(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
2216 (i32 (LDuh_GP tglobaladdr:$global))>,
2219 def : Pat<(atomic_load_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2220 u16ImmPred:$offset)),
2221 (i32 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2224 def : Pat<(atomic_load_16 ADDRriS11_1:$src1),
2225 (i32 (LDriuh ADDRriS11_1:$src1))>;
2227 def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)),
2228 (i32 (LDriuh_indexed (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
2232 // 32 bit atomic load
2233 def : Pat<(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
2234 (i32 (LDw_GP tglobaladdr:$global))>,
2237 def : Pat<(atomic_load_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2238 u16ImmPred:$offset)),
2239 (i32 (LDriw_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2242 def : Pat<(atomic_load_32 ADDRriS11_2:$src1),
2243 (i32 (LDriw ADDRriS11_2:$src1))>;
2245 def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),
2246 (i32 (LDriw_indexed (i32 IntRegs:$src1), s11_2ImmPred:$offset))>;
2249 // 64 bit atomic load
2250 def : Pat<(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
2251 (i64 (LDd_GP tglobaladdr:$global))>,
2254 def : Pat<(atomic_load_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2255 u16ImmPred:$offset)),
2256 (i64 (LDrid_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2259 def : Pat<(atomic_load_64 ADDRriS11_3:$src1),
2260 (i64 (LDrid ADDRriS11_3:$src1))>;
2262 def : Pat<(atomic_load_64 (add (i32 IntRegs:$src1), s11_3ImmPred:$offset)),
2263 (i64 (LDrid_indexed (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
2266 // 64 bit atomic store
2267 def : Pat<(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
2268 (i64 DoubleRegs:$src1)),
2269 (STd_GP tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2272 def : Pat<(atomic_store_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2273 u16ImmPred:$offset),
2274 (i64 DoubleRegs:$src1)),
2275 (STrid_GP tglobaladdr:$global, u16ImmPred:$offset,
2276 (i64 DoubleRegs:$src1))>, Requires<[NoV4T]>;
2278 // 8 bit atomic store
2279 def : Pat<(atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
2280 (i32 IntRegs:$src1)),
2281 (STb_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2284 def : Pat<(atomic_store_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2285 u16ImmPred:$offset),
2286 (i32 IntRegs:$src1)),
2287 (STrib_GP tglobaladdr:$global, u16ImmPred:$offset,
2288 (i32 IntRegs:$src1))>, Requires<[NoV4T]>;
2290 def : Pat<(atomic_store_8 ADDRriS11_0:$src2, (i32 IntRegs:$src1)),
2291 (STrib ADDRriS11_0:$src2, (i32 IntRegs:$src1))>;
2293 def : Pat<(atomic_store_8 (add (i32 IntRegs:$src2), s11_0ImmPred:$offset),
2294 (i32 IntRegs:$src1)),
2295 (STrib_indexed (i32 IntRegs:$src2), s11_0ImmPred:$offset,
2296 (i32 IntRegs:$src1))>;
2299 // 16 bit atomic store
2300 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
2301 (i32 IntRegs:$src1)),
2302 (STh_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2305 def : Pat<(atomic_store_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2306 u16ImmPred:$offset),
2307 (i32 IntRegs:$src1)),
2308 (STrih_GP tglobaladdr:$global, u16ImmPred:$offset,
2309 (i32 IntRegs:$src1))>, Requires<[NoV4T]>;
2311 def : Pat<(atomic_store_16 ADDRriS11_1:$src2, (i32 IntRegs:$src1)),
2312 (STrih ADDRriS11_1:$src2, (i32 IntRegs:$src1))>;
2314 def : Pat<(atomic_store_16 (i32 IntRegs:$src1),
2315 (add (i32 IntRegs:$src2), s11_1ImmPred:$offset)),
2316 (STrih_indexed (i32 IntRegs:$src2), s11_1ImmPred:$offset,
2317 (i32 IntRegs:$src1))>;
2320 // 32 bit atomic store
2321 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
2322 (i32 IntRegs:$src1)),
2323 (STw_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2326 def : Pat<(atomic_store_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2327 u16ImmPred:$offset),
2328 (i32 IntRegs:$src1)),
2329 (STriw_GP tglobaladdr:$global, u16ImmPred:$offset,
2330 (i32 IntRegs:$src1))>,
2333 def : Pat<(atomic_store_32 ADDRriS11_2:$src2, (i32 IntRegs:$src1)),
2334 (STriw ADDRriS11_2:$src2, (i32 IntRegs:$src1))>;
2336 def : Pat<(atomic_store_32 (add (i32 IntRegs:$src2), s11_2ImmPred:$offset),
2337 (i32 IntRegs:$src1)),
2338 (STriw_indexed (i32 IntRegs:$src2), s11_2ImmPred:$offset,
2339 (i32 IntRegs:$src1))>;
2344 def : Pat<(atomic_store_64 ADDRriS11_3:$src2, (i64 DoubleRegs:$src1)),
2345 (STrid ADDRriS11_3:$src2, (i64 DoubleRegs:$src1))>;
2347 def : Pat<(atomic_store_64 (add (i32 IntRegs:$src2), s11_3ImmPred:$offset),
2348 (i64 DoubleRegs:$src1)),
2349 (STrid_indexed (i32 IntRegs:$src2), s11_3ImmPred:$offset,
2350 (i64 DoubleRegs:$src1))>;
2352 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
2353 def : Pat <(and (i32 IntRegs:$src1), 65535),
2354 (ZXTH (i32 IntRegs:$src1))>;
2356 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
2357 def : Pat <(and (i32 IntRegs:$src1), 255),
2358 (ZXTB (i32 IntRegs:$src1))>;
2360 // Map Add(p1, true) to p1 = not(p1).
2361 // Add(p1, false) should never be produced,
2362 // if it does, it got to be mapped to NOOP.
2363 def : Pat <(add (i1 PredRegs:$src1), -1),
2364 (NOT_p (i1 PredRegs:$src1))>;
2366 // Map from p0 = setlt(r0, r1) r2 = mux(p0, r3, r4) =>
2367 // p0 = cmp.lt(r0, r1), r0 = mux(p0, r2, r1).
2368 def : Pat <(select (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2369 (i32 IntRegs:$src3),
2370 (i32 IntRegs:$src4)),
2371 (i32 (TFR_condset_rr (CMPLTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2372 (i32 IntRegs:$src4), (i32 IntRegs:$src3)))>,
2373 Requires<[HasV2TOnly]>;
2375 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
2376 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
2377 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
2380 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
2381 // => r0 = TFR_condset_ri(p0, r1, #i)
2382 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
2383 (i32 IntRegs:$src3)),
2384 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
2385 s12ImmPred:$src2))>;
2387 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
2388 // => r0 = TFR_condset_ir(p0, #i, r1)
2389 def : Pat <(select (not PredRegs:$src1), IntRegs:$src2, s12ImmPred:$src3),
2390 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
2391 (i32 IntRegs:$src2)))>;
2393 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
2394 def : Pat <(brcond (not PredRegs:$src1), bb:$offset),
2395 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
2397 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
2398 def : Pat <(and PredRegs:$src1, (not PredRegs:$src2)),
2399 (i1 (AND_pnotp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2401 // Map from store(globaladdress + x) -> memd(#foo + x).
2402 let AddedComplexity = 100 in
2403 def : Pat <(store (i64 DoubleRegs:$src1),
2404 (add (HexagonCONST32_GP tglobaladdr:$global),
2405 u16ImmPred:$offset)),
2406 (STrid_GP tglobaladdr:$global, u16ImmPred:$offset,
2407 (i64 DoubleRegs:$src1))>, Requires<[NoV4T]>;
2409 // Map from store(globaladdress) -> memd(#foo).
2410 let AddedComplexity = 100 in
2411 def : Pat <(store (i64 DoubleRegs:$src1),
2412 (HexagonCONST32_GP tglobaladdr:$global)),
2413 (STd_GP tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2416 // Map from store(globaladdress + x) -> memw(#foo + x).
2417 let AddedComplexity = 100 in
2418 def : Pat <(store (i32 IntRegs:$src1),
2419 (add (HexagonCONST32_GP tglobaladdr:$global),
2420 u16ImmPred:$offset)),
2421 (STriw_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2424 // Map from store(globaladdress) -> memw(#foo + 0).
2425 let AddedComplexity = 100 in
2426 def : Pat <(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2427 (STriw_GP tglobaladdr:$global, 0, (i32 IntRegs:$src1))>;
2429 // Map from store(globaladdress) -> memw(#foo).
2430 let AddedComplexity = 100 in
2431 def : Pat <(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2432 (STriw_GP tglobaladdr:$global, 0, (i32 IntRegs:$src1))>,
2435 // Map from store(globaladdress + x) -> memh(#foo + x).
2436 let AddedComplexity = 100 in
2437 def : Pat <(truncstorei16 (i32 IntRegs:$src1),
2438 (add (HexagonCONST32_GP tglobaladdr:$global),
2439 u16ImmPred:$offset)),
2440 (STrih_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2443 // Map from store(globaladdress) -> memh(#foo).
2444 let AddedComplexity = 100 in
2445 def : Pat <(truncstorei16 (i32 IntRegs:$src1),
2446 (HexagonCONST32_GP tglobaladdr:$global)),
2447 (STh_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2450 // Map from store(globaladdress + x) -> memb(#foo + x).
2451 let AddedComplexity = 100 in
2452 def : Pat <(truncstorei8 (i32 IntRegs:$src1),
2453 (add (HexagonCONST32_GP tglobaladdr:$global),
2454 u16ImmPred:$offset)),
2455 (STrib_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2458 // Map from store(globaladdress) -> memb(#foo).
2459 let AddedComplexity = 100 in
2460 def : Pat <(truncstorei8 (i32 IntRegs:$src1),
2461 (HexagonCONST32_GP tglobaladdr:$global)),
2462 (STb_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2465 // Map from load(globaladdress + x) -> memw(#foo + x).
2466 let AddedComplexity = 100 in
2467 def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global),
2468 u16ImmPred:$offset))),
2469 (i32 (LDriw_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2472 // Map from load(globaladdress) -> memw(#foo).
2473 let AddedComplexity = 100 in
2474 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
2475 (i32 (LDw_GP tglobaladdr:$global))>,
2478 // Map from load(globaladdress + x) -> memd(#foo + x).
2479 let AddedComplexity = 100 in
2480 def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),
2481 u16ImmPred:$offset))),
2482 (i64 (LDrid_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2485 // Map from load(globaladdress) -> memw(#foo + 0).
2486 let AddedComplexity = 100 in
2487 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
2488 (i64 (LDd_GP tglobaladdr:$global))>,
2491 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd.
2492 let AddedComplexity = 100 in
2493 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
2494 (i1 (TFR_PdRs (i32 (LDb_GP tglobaladdr:$global))))>,
2497 // Map from load(globaladdress + x) -> memh(#foo + x).
2498 let AddedComplexity = 100 in
2499 def : Pat <(i32 (extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2500 u16ImmPred:$offset))),
2501 (i32 (LDrih_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2504 // Map from load(globaladdress + x) -> memh(#foo + x).
2505 let AddedComplexity = 100 in
2506 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2507 (i32 (LDrih_GP tglobaladdr:$global, 0))>,
2510 // Map from load(globaladdress + x) -> memuh(#foo + x).
2511 let AddedComplexity = 100 in
2512 def : Pat <(i32 (zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2513 u16ImmPred:$offset))),
2514 (i32 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2517 // Map from load(globaladdress) -> memuh(#foo).
2518 let AddedComplexity = 100 in
2519 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2520 (i32 (LDriuh_GP tglobaladdr:$global, 0))>,
2523 // Map from load(globaladdress) -> memh(#foo).
2524 let AddedComplexity = 100 in
2525 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2526 (i32 (LDh_GP tglobaladdr:$global))>,
2529 // Map from load(globaladdress) -> memuh(#foo).
2530 let AddedComplexity = 100 in
2531 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2532 (i32 (LDuh_GP tglobaladdr:$global))>,
2535 // Map from load(globaladdress + x) -> memb(#foo + x).
2536 let AddedComplexity = 100 in
2537 def : Pat <(i32 (extloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2538 u16ImmPred:$offset))),
2539 (i32 (LDrib_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2542 // Map from load(globaladdress + x) -> memb(#foo + x).
2543 let AddedComplexity = 100 in
2544 def : Pat <(i32 (sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2545 u16ImmPred:$offset))),
2546 (i32 (LDrib_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2549 // Map from load(globaladdress + x) -> memub(#foo + x).
2550 let AddedComplexity = 100 in
2551 def : Pat <(i32 (zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2552 u16ImmPred:$offset))),
2553 (i32 (LDriub_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2556 // Map from load(globaladdress) -> memb(#foo).
2557 let AddedComplexity = 100 in
2558 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2559 (i32 (LDb_GP tglobaladdr:$global))>,
2562 // Map from load(globaladdress) -> memb(#foo).
2563 let AddedComplexity = 100 in
2564 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2565 (i32 (LDb_GP tglobaladdr:$global))>,
2568 // Map from load(globaladdress) -> memub(#foo).
2569 let AddedComplexity = 100 in
2570 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2571 (i32 (LDub_GP tglobaladdr:$global))>,
2574 // When the Interprocedural Global Variable optimizer realizes that a
2575 // certain global variable takes only two constant values, it shrinks the
2576 // global to a boolean. Catch those loads here in the following 3 patterns.
2577 let AddedComplexity = 100 in
2578 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2579 (i32 (LDb_GP tglobaladdr:$global))>,
2582 let AddedComplexity = 100 in
2583 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2584 (i32 (LDb_GP tglobaladdr:$global))>,
2587 let AddedComplexity = 100 in
2588 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2589 (i32 (LDub_GP tglobaladdr:$global))>,
2592 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
2593 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
2594 (i32 (AND_rr (i32 (LDrib ADDRriS11_0:$addr)), (TFRI 0x1)))>;
2596 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
2597 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
2598 (i64 (SXTW (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
2600 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
2601 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
2602 (i64 (SXTW (i32 (SXTH (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2603 subreg_loreg))))))>;
2605 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
2606 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
2607 (i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2608 subreg_loreg))))))>;
2610 // We want to prevent emitting pnot's as much as possible.
2611 // Map brcond with an unsupported setcc to a JMP_cNot.
2612 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2614 (JMP_cNot (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2617 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
2619 (JMP_cNot (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
2621 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
2622 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
2624 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
2625 (JMP_c (i1 PredRegs:$src1), bb:$offset)>;
2627 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
2629 (JMP_cNot (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2), bb:$offset)>;
2631 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2633 (JMP_c (CMPLTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)), bb:$offset)>;
2635 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2637 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
2640 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2642 (JMP_cNot (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2645 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2647 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2650 // Map from a 64-bit select to an emulated 64-bit mux.
2651 // Hexagon does not support 64-bit MUXes; so emulate with combines.
2652 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
2653 (i64 DoubleRegs:$src3)),
2654 (i64 (COMBINE_rr (i32 (MUX_rr (i1 PredRegs:$src1),
2655 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2657 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2659 (i32 (MUX_rr (i1 PredRegs:$src1),
2660 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2662 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2663 subreg_loreg))))))>;
2665 // Map from a 1-bit select to logical ops.
2666 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
2667 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
2668 (i1 PredRegs:$src3)),
2669 (OR_pp (AND_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
2670 (AND_pp (NOT_p (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
2672 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
2673 def : Pat<(i1 (load ADDRriS11_2:$addr)),
2674 (i1 (TFR_PdRs (i32 (LDrib ADDRriS11_2:$addr))))>;
2676 // Map for truncating from 64 immediates to 32 bit immediates.
2677 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
2678 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
2680 // Map for truncating from i64 immediates to i1 bit immediates.
2681 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
2682 (i1 (TFR_PdRs (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2685 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
2686 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2687 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2690 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
2691 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2692 (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2694 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
2695 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2696 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2699 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
2700 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2701 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2704 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
2705 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2706 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2708 let AddedComplexity = 100 in
2709 // Map from i1 = constant<-1>; memw(CONST32(#foo)) = i1 -> r0 = 1;
2711 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
2712 (STb_GP tglobaladdr:$global, (TFRI 1))>,
2715 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
2716 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2717 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2719 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
2720 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
2721 (STrib ADDRriS11_2:$addr, (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0)) )>;
2723 // Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs).
2724 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
2725 // Better way to do this?
2726 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
2727 (i64 (SXTW (i32 IntRegs:$src1)))>;
2729 // Map cmple -> cmpgt.
2730 // rs <= rt -> !(rs > rt).
2731 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ImmPred:$src2)),
2732 (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), s10ImmPred:$src2)))>;
2734 // rs <= rt -> !(rs > rt).
2735 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2736 (i1 (NOT_p (CMPGTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2738 // Rss <= Rtt -> !(Rss > Rtt).
2739 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2740 (i1 (NOT_p (CMPGT64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2742 // Map cmpne -> cmpeq.
2743 // Hexagon_TODO: We should improve on this.
2744 // rs != rt -> !(rs == rt).
2745 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
2746 (i1 (NOT_p(i1 (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2))))>;
2748 // Map cmpne(Rs) -> !cmpeqe(Rs).
2749 // rs != rt -> !(rs == rt).
2750 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2751 (i1 (NOT_p (i1 (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
2753 // Convert setne back to xor for hexagon since we compute w/ pred registers.
2754 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
2755 (i1 (XOR_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2757 // Map cmpne(Rss) -> !cmpew(Rss).
2758 // rs != rt -> !(rs == rt).
2759 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2760 (i1 (NOT_p (i1 (CMPEHexagon4rr (i64 DoubleRegs:$src1),
2761 (i64 DoubleRegs:$src2)))))>;
2763 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
2764 // rs >= rt -> !(rt > rs).
2765 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2766 (i1 (NOT_p (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
2768 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ImmPred:$src2)),
2769 (i1 (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2))>;
2771 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
2772 // rss >= rtt -> !(rtt > rss).
2773 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2774 (i1 (NOT_p (i1 (CMPGT64rr (i64 DoubleRegs:$src2),
2775 (i64 DoubleRegs:$src1)))))>;
2777 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
2778 // rs < rt -> !(rs >= rt).
2779 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
2780 (i1 (NOT_p (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2)))>;
2782 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
2783 // rs < rt -> rt > rs.
2784 // We can let assembler map it, or we can do in the compiler itself.
2785 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2786 (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2788 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
2789 // rss < rtt -> (rtt > rss).
2790 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2791 (i1 (CMPGT64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2793 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
2794 // rs < rt -> rt > rs.
2795 // We can let assembler map it, or we can do in the compiler itself.
2796 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2797 (i1 (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2799 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
2800 // rs < rt -> rt > rs.
2801 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2802 (i1 (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2804 // Generate cmpgeu(Rs, #u8)
2805 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ImmPred:$src2)),
2806 (i1 (CMPGEUri (i32 IntRegs:$src1), u8ImmPred:$src2))>;
2808 // Generate cmpgtu(Rs, #u9)
2809 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ImmPred:$src2)),
2810 (i1 (CMPGTUri (i32 IntRegs:$src1), u9ImmPred:$src2))>;
2812 // Map from Rs >= Rt -> !(Rt > Rs).
2813 // rs >= rt -> !(rt > rs).
2814 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2815 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
2817 // Map from Rs >= Rt -> !(Rt > Rs).
2818 // rs >= rt -> !(rt > rs).
2819 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2820 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
2822 // Map from cmpleu(Rs, Rs) -> !cmpgtu(Rs, Rs).
2823 // Map from (Rs <= Rt) -> !(Rs > Rt).
2824 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2825 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2827 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
2828 // Map from (Rs <= Rt) -> !(Rs > Rt).
2829 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2830 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2834 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
2835 (i32 (MUX_ii (i1 PredRegs:$src1), -1, 0))>;
2838 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
2839 (i64 (COMBINE_rr (TFRI -1), (MUX_ii (i1 PredRegs:$src1), -1, 0)))>;
2841 // Convert sign-extended load back to load and sign extend.
2843 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
2844 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2846 // Convert any-extended load back to load and sign extend.
2848 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
2849 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2851 // Convert sign-extended load back to load and sign extend.
2853 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
2854 (i64 (SXTW (LDrih ADDRriS11_1:$src1)))>;
2856 // Convert sign-extended load back to load and sign extend.
2858 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
2859 (i64 (SXTW (LDriw ADDRriS11_2:$src1)))>;
2864 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2865 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2868 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
2869 (i64 (COMBINE_rr (TFRI 0), (MUX_ii (i1 PredRegs:$src1), 1, 0)))>;
2872 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
2873 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>;
2876 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
2877 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>;
2880 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
2881 (i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>;
2884 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
2885 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>;
2887 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
2888 (i32 (LDriw ADDRriS11_0:$src1))>;
2890 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2891 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2892 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2894 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2895 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
2896 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2898 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
2899 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
2900 (i64 (SXTW (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))))>;
2903 // Any extended 64-bit load.
2904 // anyext i32 -> i64
2905 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
2906 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>;
2908 // anyext i16 -> i64.
2909 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
2910 (i64 (COMBINE_rr (TFRI 0), (LDrih ADDRriS11_2:$src1)))>;
2912 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
2913 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
2914 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>;
2916 // Multiply 64-bit unsigned and use upper result.
2917 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2932 (COMBINE_rr (TFRI 0),
2938 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2940 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2941 subreg_loreg)))), 32)),
2943 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2944 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2945 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2946 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2947 32)), subreg_loreg)))),
2948 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2949 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2951 // Multiply 64-bit signed and use upper result.
2952 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2956 (COMBINE_rr (TFRI 0),
2966 (COMBINE_rr (TFRI 0),
2972 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2974 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2975 subreg_loreg)))), 32)),
2977 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2978 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2979 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2980 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2981 32)), subreg_loreg)))),
2982 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2983 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2985 // Hexagon specific ISD nodes.
2986 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
2987 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
2988 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
2989 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
2990 SDTHexagonADJDYNALLOC>;
2991 // Needed to tag these instructions for stack layout.
2992 let usesCustomInserter = 1 in
2993 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
2995 "$dst = add($src1, #$src2)",
2996 [(set (i32 IntRegs:$dst),
2997 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
2998 s16ImmPred:$src2))]>;
3000 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
3001 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
3002 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
3004 [(set (i32 IntRegs:$dst),
3005 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
3007 let AddedComplexity = 100 in
3008 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
3009 (COPY (i32 IntRegs:$src1))>;
3011 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
3012 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
3014 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
3015 def BR_JT : JRInst<(outs), (ins IntRegs:$src),
3017 [(HexagonBR_JT (i32 IntRegs:$src))]>;
3019 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
3021 def : Pat<(HexagonWrapperJT tjumptable:$dst),
3022 (i32 (CONST32_set_jt tjumptable:$dst))>;
3026 // Multi-class for logical operators :
3027 // Shift by immediate/register and accumulate/logical
3028 multiclass xtype_imm<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
3029 def _ri : SInst_acc<(outs IntRegs:$dst),
3030 (ins IntRegs:$src1, IntRegs:$src2, u5Imm:$src3),
3031 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
3032 [(set (i32 IntRegs:$dst),
3033 (OpNode2 (i32 IntRegs:$src1),
3034 (OpNode1 (i32 IntRegs:$src2),
3035 u5ImmPred:$src3)))],
3038 def d_ri : SInst_acc<(outs DoubleRegs:$dst),
3039 (ins DoubleRegs:$src1, DoubleRegs:$src2, u6Imm:$src3),
3040 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
3041 [(set (i64 DoubleRegs:$dst), (OpNode2 (i64 DoubleRegs:$src1),
3042 (OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
3046 // Multi-class for logical operators :
3047 // Shift by register and accumulate/logical (32/64 bits)
3048 multiclass xtype_reg<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
3049 def _rr : SInst_acc<(outs IntRegs:$dst),
3050 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
3051 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
3052 [(set (i32 IntRegs:$dst),
3053 (OpNode2 (i32 IntRegs:$src1),
3054 (OpNode1 (i32 IntRegs:$src2),
3055 (i32 IntRegs:$src3))))],
3058 def d_rr : SInst_acc<(outs DoubleRegs:$dst),
3059 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3060 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
3061 [(set (i64 DoubleRegs:$dst),
3062 (OpNode2 (i64 DoubleRegs:$src1),
3063 (OpNode1 (i64 DoubleRegs:$src2),
3064 (i32 IntRegs:$src3))))],
3069 multiclass basic_xtype_imm<string OpcStr, SDNode OpNode> {
3070 let AddedComplexity = 100 in
3071 defm _ADD : xtype_imm< !strconcat("+= ", OpcStr), OpNode, add>;
3072 defm _SUB : xtype_imm< !strconcat("-= ", OpcStr), OpNode, sub>;
3073 defm _AND : xtype_imm< !strconcat("&= ", OpcStr), OpNode, and>;
3074 defm _OR : xtype_imm< !strconcat("|= ", OpcStr), OpNode, or>;
3077 multiclass basic_xtype_reg<string OpcStr, SDNode OpNode> {
3078 let AddedComplexity = 100 in
3079 defm _ADD : xtype_reg< !strconcat("+= ", OpcStr), OpNode, add>;
3080 defm _SUB : xtype_reg< !strconcat("-= ", OpcStr), OpNode, sub>;
3081 defm _AND : xtype_reg< !strconcat("&= ", OpcStr), OpNode, and>;
3082 defm _OR : xtype_reg< !strconcat("|= ", OpcStr), OpNode, or>;
3085 multiclass xtype_xor_imm<string OpcStr, SDNode OpNode> {
3086 let AddedComplexity = 100 in
3087 defm _XOR : xtype_imm< !strconcat("^= ", OpcStr), OpNode, xor>;
3090 defm ASL : basic_xtype_imm<"asl", shl>, basic_xtype_reg<"asl", shl>,
3091 xtype_xor_imm<"asl", shl>;
3093 defm LSR : basic_xtype_imm<"lsr", srl>, basic_xtype_reg<"lsr", srl>,
3094 xtype_xor_imm<"lsr", srl>;
3096 defm ASR : basic_xtype_imm<"asr", sra>, basic_xtype_reg<"asr", sra>;
3097 defm LSL : basic_xtype_reg<"lsl", shl>;
3099 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
3100 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
3101 (i32 (MPYI_rin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
3103 //===----------------------------------------------------------------------===//
3104 // V3 Instructions +
3105 //===----------------------------------------------------------------------===//
3107 include "HexagonInstrInfoV3.td"
3109 //===----------------------------------------------------------------------===//
3110 // V3 Instructions -
3111 //===----------------------------------------------------------------------===//
3113 //===----------------------------------------------------------------------===//
3114 // V4 Instructions +
3115 //===----------------------------------------------------------------------===//
3117 include "HexagonInstrInfoV4.td"
3119 //===----------------------------------------------------------------------===//
3120 // V4 Instructions -
3121 //===----------------------------------------------------------------------===//
3123 //===----------------------------------------------------------------------===//
3124 // V5 Instructions +
3125 //===----------------------------------------------------------------------===//
3127 include "HexagonInstrInfoV5.td"
3129 //===----------------------------------------------------------------------===//
3130 // V5 Instructions -
3131 //===----------------------------------------------------------------------===//