1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
18 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
19 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>;
20 def ADDRriS11_0 : ComplexPattern<i32, 2, "SelectADDRriS11_0", [frameindex], []>;
21 def ADDRriS11_1 : ComplexPattern<i32, 2, "SelectADDRriS11_1", [frameindex], []>;
22 def ADDRriS11_2 : ComplexPattern<i32, 2, "SelectADDRriS11_2", [frameindex], []>;
23 def ADDRriS11_3 : ComplexPattern<i32, 2, "SelectADDRriS11_3", [frameindex], []>;
24 def ADDRriU6_0 : ComplexPattern<i32, 2, "SelectADDRriU6_0", [frameindex], []>;
25 def ADDRriU6_1 : ComplexPattern<i32, 2, "SelectADDRriU6_1", [frameindex], []>;
26 def ADDRriU6_2 : ComplexPattern<i32, 2, "SelectADDRriU6_2", [frameindex], []>;
29 def MEMrr : Operand<i32> {
30 let PrintMethod = "printMEMrrOperand";
31 let MIOperandInfo = (ops IntRegs, IntRegs);
35 def MEMri : Operand<i32> {
36 let PrintMethod = "printMEMriOperand";
37 let MIOperandInfo = (ops IntRegs, IntRegs);
40 def MEMri_s11_2 : Operand<i32>,
41 ComplexPattern<i32, 2, "SelectMEMriS11_2", []> {
42 let PrintMethod = "printMEMriOperand";
43 let MIOperandInfo = (ops IntRegs, s11Imm);
46 def FrameIndex : Operand<i32> {
47 let PrintMethod = "printFrameIndexOperand";
48 let MIOperandInfo = (ops IntRegs, s11Imm);
51 let PrintMethod = "printGlobalOperand" in
52 def globaladdress : Operand<i32>;
54 let PrintMethod = "printJumpTable" in
55 def jumptablebase : Operand<i32>;
57 def brtarget : Operand<OtherVT>;
58 def calltarget : Operand<i32>;
60 def bblabel : Operand<i32>;
61 def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf , [], "BasicBlockSDNode">;
63 def symbolHi32 : Operand<i32> {
64 let PrintMethod = "printSymbolHi";
66 def symbolLo32 : Operand<i32> {
67 let PrintMethod = "printSymbolLo";
70 // Multi-class for logical operators.
71 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
72 def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
73 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
74 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),
76 def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
77 !strconcat("$dst = ", !strconcat(OpcStr, "(#$b, $c)")),
78 [(set (i32 IntRegs:$dst), (OpNode s10Imm:$b,
82 // Multi-class for compare ops.
83 let isCompare = 1 in {
84 multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
85 def rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
86 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
87 [(set (i1 PredRegs:$dst),
88 (OpNode (i64 DoubleRegs:$b), (i64 DoubleRegs:$c)))]>;
90 multiclass CMP32_rr<string OpcStr, PatFrag OpNode> {
91 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
92 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
93 [(set (i1 PredRegs:$dst),
94 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
97 multiclass CMP32_rr_ri_s10<string OpcStr, PatFrag OpNode> {
98 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
99 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
100 [(set (i1 PredRegs:$dst),
101 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
102 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Imm:$c),
103 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
104 [(set (i1 PredRegs:$dst),
105 (OpNode (i32 IntRegs:$b), s10ImmPred:$c))]>;
108 multiclass CMP32_rr_ri_u9<string OpcStr, PatFrag OpNode> {
109 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
110 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
111 [(set (i1 PredRegs:$dst),
112 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
113 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Imm:$c),
114 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
115 [(set (i1 PredRegs:$dst),
116 (OpNode (i32 IntRegs:$b), u9ImmPred:$c))]>;
119 multiclass CMP32_ri_u8<string OpcStr, PatFrag OpNode> {
120 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u8Imm:$c),
121 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
122 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
126 multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
127 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Imm:$c),
128 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
129 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
134 //===----------------------------------------------------------------------===//
135 // ALU32/ALU (Instructions with register-register form)
136 //===----------------------------------------------------------------------===//
137 multiclass ALU32_Pbase<string mnemonic, bit isNot,
140 let PNewValue = #!if(isPredNew, "new", "") in
141 def #NAME# : ALU32_rr<(outs IntRegs:$dst),
142 (ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
143 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
144 ") $dst = ")#mnemonic#"($src2, $src3)",
148 multiclass ALU32_Pred<string mnemonic, bit PredNot> {
149 let PredSense = #!if(PredNot, "false", "true") in {
150 defm _c#NAME# : ALU32_Pbase<mnemonic, PredNot, 0>;
152 defm _cdn#NAME# : ALU32_Pbase<mnemonic, PredNot, 1>;
156 let InputType = "reg" in
157 multiclass ALU32_base<string mnemonic, string CextOp, SDNode OpNode> {
158 let CextOpcode = CextOp, BaseOpcode = CextOp#_rr in {
159 let isPredicable = 1 in
160 def #NAME# : ALU32_rr<(outs IntRegs:$dst),
161 (ins IntRegs:$src1, IntRegs:$src2),
162 "$dst = "#mnemonic#"($src1, $src2)",
163 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
164 (i32 IntRegs:$src2)))]>;
166 let neverHasSideEffects = 1, isPredicated = 1 in {
167 defm Pt : ALU32_Pred<mnemonic, 0>;
168 defm NotPt : ALU32_Pred<mnemonic, 1>;
173 let isCommutable = 1 in {
174 defm ADD_rr : ALU32_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
175 defm AND_rr : ALU32_base<"and", "AND", and>, ImmRegRel, PredNewRel;
176 defm XOR_rr : ALU32_base<"xor", "XOR", xor>, ImmRegRel, PredNewRel;
177 defm OR_rr : ALU32_base<"or", "OR", or>, ImmRegRel, PredNewRel;
180 defm SUB_rr : ALU32_base<"sub", "SUB", sub>, ImmRegRel, PredNewRel;
182 //===----------------------------------------------------------------------===//
183 // ALU32/ALU (ADD with register-immediate form)
184 //===----------------------------------------------------------------------===//
185 multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
186 let PNewValue = #!if(isPredNew, "new", "") in
187 def #NAME# : ALU32_ri<(outs IntRegs:$dst),
188 (ins PredRegs:$src1, IntRegs:$src2, s8Imm: $src3),
189 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
190 ") $dst = ")#mnemonic#"($src2, #$src3)",
194 multiclass ALU32ri_Pred<string mnemonic, bit PredNot> {
195 let PredSense = #!if(PredNot, "false", "true") in {
196 defm _c#NAME# : ALU32ri_Pbase<mnemonic, PredNot, 0>;
198 defm _cdn#NAME# : ALU32ri_Pbase<mnemonic, PredNot, 1>;
202 let InputType = "imm" in
203 multiclass ALU32ri_base<string mnemonic, string CextOp, SDNode OpNode> {
204 let CextOpcode = CextOp, BaseOpcode = CextOp#_ri in {
205 let isPredicable = 1 in
206 def #NAME# : ALU32_ri<(outs IntRegs:$dst),
207 (ins IntRegs:$src1, s16Imm:$src2),
208 "$dst = "#mnemonic#"($src1, #$src2)",
209 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
210 (s16ImmPred:$src2)))]>;
212 let neverHasSideEffects = 1, isPredicated = 1 in {
213 defm Pt : ALU32ri_Pred<mnemonic, 0>;
214 defm NotPt : ALU32ri_Pred<mnemonic, 1>;
219 defm ADD_ri : ALU32ri_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
221 def OR_ri : ALU32_ri<(outs IntRegs:$dst),
222 (ins IntRegs:$src1, s10Imm:$src2),
223 "$dst = or($src1, #$src2)",
224 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
225 s10ImmPred:$src2))]>;
227 def NOT_rr : ALU32_rr<(outs IntRegs:$dst),
230 [(set (i32 IntRegs:$dst), (not (i32 IntRegs:$src1)))]>;
232 def AND_ri : ALU32_ri<(outs IntRegs:$dst),
233 (ins IntRegs:$src1, s10Imm:$src2),
234 "$dst = and($src1, #$src2)",
235 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
236 s10ImmPred:$src2))]>;
239 def NEG : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
241 [(set (i32 IntRegs:$dst), (ineg (i32 IntRegs:$src1)))]>;
243 let neverHasSideEffects = 1 in
244 def NOP : ALU32_rr<(outs), (ins),
248 // Rd32=sub(#s10,Rs32)
249 def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
250 (ins s10Imm:$src1, IntRegs:$src2),
251 "$dst = sub(#$src1, $src2)",
252 [(set IntRegs:$dst, (sub s10ImmPred:$src1, IntRegs:$src2))]>;
255 multiclass TFR_Pred<bit PredNot> {
256 let PredSense = #!if(PredNot, "false", "true") in {
257 def _c#NAME# : ALU32_rr<(outs IntRegs:$dst),
258 (ins PredRegs:$src1, IntRegs:$src2),
259 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
262 let PNewValue = "new" in
263 def _cdn#NAME# : ALU32_rr<(outs IntRegs:$dst),
264 (ins PredRegs:$src1, IntRegs:$src2),
265 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
270 let InputType = "reg", neverHasSideEffects = 1 in
271 multiclass TFR_base<string CextOp> {
272 let CextOpcode = CextOp, BaseOpcode = CextOp in {
273 let isPredicable = 1 in
274 def #NAME# : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
278 let isPredicated = 1 in {
279 defm Pt : TFR_Pred<0>;
280 defm NotPt : TFR_Pred<1>;
285 multiclass TFR64_Pred<bit PredNot> {
286 let PredSense = #!if(PredNot, "false", "true") in {
287 def _c#NAME# : ALU32_rr<(outs DoubleRegs:$dst),
288 (ins PredRegs:$src1, DoubleRegs:$src2),
289 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
292 let PNewValue = "new" in
293 def _cdn#NAME# : ALU32_rr<(outs DoubleRegs:$dst),
294 (ins PredRegs:$src1, DoubleRegs:$src2),
295 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
300 let InputType = "reg", neverHasSideEffects = 1 in
301 multiclass TFR64_base<string CextOp> {
302 let CextOpcode = CextOp, BaseOpcode = CextOp in {
303 let isPredicable = 1 in
304 def #NAME# : ALU32_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
308 let isPredicated = 1 in {
309 defm Pt : TFR64_Pred<0>;
310 defm NotPt : TFR64_Pred<1>;
316 multiclass TFRI_Pred<bit PredNot> {
317 let PredSense = #!if(PredNot, "false", "true") in {
318 def _c#NAME# : ALU32_ri<(outs IntRegs:$dst),
319 (ins PredRegs:$src1, s12Ext:$src2),
320 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = #$src2",
324 let PNewValue = "new" in
325 def _cdn#NAME# : ALU32_rr<(outs IntRegs:$dst),
326 (ins PredRegs:$src1, s12Ext:$src2),
327 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = #$src2",
332 let InputType = "imm", isExtendable = 1, isExtentSigned = 1 in
333 multiclass TFRI_base<string CextOp> {
334 let CextOpcode = CextOp, BaseOpcode = CextOp#I in {
335 let opExtendable = 1, opExtentBits = 16, isMoveImm = 1, isPredicable = 1,
336 isReMaterializable = 1 in
337 def #NAME# : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
339 [(set (i32 IntRegs:$dst), s16ExtPred:$src1)]>;
341 let opExtendable = 2, opExtentBits = 12, neverHasSideEffects = 1,
342 isPredicated = 1 in {
343 defm Pt : TFRI_Pred<0>;
344 defm NotPt : TFRI_Pred<1>;
349 defm TFRI : TFRI_base<"TFR">, ImmRegRel, PredNewRel;
350 defm TFR : TFR_base<"TFR">, ImmRegRel, PredNewRel;
351 defm TFR64 : TFR64_base<"TFR64">, ImmRegRel, PredNewRel;
353 // Transfer control register.
354 let neverHasSideEffects = 1 in
355 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
358 //===----------------------------------------------------------------------===//
360 //===----------------------------------------------------------------------===//
363 //===----------------------------------------------------------------------===//
365 //===----------------------------------------------------------------------===//
368 let isPredicable = 1, neverHasSideEffects = 1 in
369 def COMBINE_rr : ALU32_rr<(outs DoubleRegs:$dst),
370 (ins IntRegs:$src1, IntRegs:$src2),
371 "$dst = combine($src1, $src2)",
374 let neverHasSideEffects = 1 in
375 def COMBINE_ii : ALU32_ii<(outs DoubleRegs:$dst),
376 (ins s8Imm:$src1, s8Imm:$src2),
377 "$dst = combine(#$src1, #$src2)",
381 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
384 "$dst = vmux($src1, $src2, $src3)",
387 def MUX_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
388 IntRegs:$src2, IntRegs:$src3),
389 "$dst = mux($src1, $src2, $src3)",
390 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
392 (i32 IntRegs:$src3))))]>;
394 def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Imm:$src2,
396 "$dst = mux($src1, #$src2, $src3)",
397 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
399 (i32 IntRegs:$src3))))]>;
401 def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
403 "$dst = mux($src1, $src2, #$src3)",
404 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
406 s8ImmPred:$src3)))]>;
408 def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Imm:$src2,
410 "$dst = mux($src1, #$src2, #$src3)",
411 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
413 s8ImmPred:$src3)))]>;
416 let isPredicable = 1 in
417 def ASLH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
418 "$dst = aslh($src1)",
419 [(set (i32 IntRegs:$dst), (shl 16, (i32 IntRegs:$src1)))]>;
421 let isPredicable = 1 in
422 def ASRH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
423 "$dst = asrh($src1)",
424 [(set (i32 IntRegs:$dst), (sra 16, (i32 IntRegs:$src1)))]>;
427 let isPredicable = 1 in
428 def SXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
429 "$dst = sxtb($src1)",
430 [(set (i32 IntRegs:$dst), (sext_inreg (i32 IntRegs:$src1), i8))]>;
432 let isPredicable = 1 in
433 def SXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
434 "$dst = sxth($src1)",
435 [(set (i32 IntRegs:$dst), (sext_inreg (i32 IntRegs:$src1), i16))]>;
438 let isPredicable = 1, neverHasSideEffects = 1 in
439 def ZXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
440 "$dst = zxtb($src1)",
443 let isPredicable = 1, neverHasSideEffects = 1 in
444 def ZXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
445 "$dst = zxth($src1)",
447 //===----------------------------------------------------------------------===//
449 //===----------------------------------------------------------------------===//
452 //===----------------------------------------------------------------------===//
454 //===----------------------------------------------------------------------===//
456 // Conditional combine.
458 let neverHasSideEffects = 1, isPredicated = 1 in
459 def COMBINE_rr_cPt : ALU32_rr<(outs DoubleRegs:$dst),
460 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
461 "if ($src1) $dst = combine($src2, $src3)",
464 let neverHasSideEffects = 1, isPredicated = 1 in
465 def COMBINE_rr_cNotPt : ALU32_rr<(outs DoubleRegs:$dst),
466 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
467 "if (!$src1) $dst = combine($src2, $src3)",
470 let neverHasSideEffects = 1, isPredicated = 1 in
471 def COMBINE_rr_cdnPt : ALU32_rr<(outs DoubleRegs:$dst),
472 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
473 "if ($src1.new) $dst = combine($src2, $src3)",
476 let neverHasSideEffects = 1, isPredicated = 1 in
477 def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst),
478 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
479 "if (!$src1.new) $dst = combine($src2, $src3)",
483 defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", setugt>;
484 defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", setgt>;
485 defm CMPLT : CMP32_rr<"cmp.lt", setlt>;
486 defm CMPLTU : CMP32_rr<"cmp.ltu", setult>;
487 defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", seteq>;
488 defm CMPGE : CMP32_ri_s8<"cmp.ge", setge>;
489 defm CMPGEU : CMP32_ri_u8<"cmp.geu", setuge>;
490 //===----------------------------------------------------------------------===//
492 //===----------------------------------------------------------------------===//
495 //===----------------------------------------------------------------------===//
497 //===----------------------------------------------------------------------===//
499 def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
501 "$dst = add($src1, $src2)",
502 [(set (i64 DoubleRegs:$dst), (add (i64 DoubleRegs:$src1),
503 (i64 DoubleRegs:$src2)))]>;
508 defm CMPEHexagon4 : CMP64_rr<"cmp.eq", seteq>;
509 defm CMPGT64 : CMP64_rr<"cmp.gt", setgt>;
510 defm CMPGTU64 : CMP64_rr<"cmp.gtu", setugt>;
512 // Logical operations.
513 def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
515 "$dst = and($src1, $src2)",
516 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
517 (i64 DoubleRegs:$src2)))]>;
519 def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
521 "$dst = or($src1, $src2)",
522 [(set (i64 DoubleRegs:$dst), (or (i64 DoubleRegs:$src1),
523 (i64 DoubleRegs:$src2)))]>;
525 def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
527 "$dst = xor($src1, $src2)",
528 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
529 (i64 DoubleRegs:$src2)))]>;
532 def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
533 "$dst = max($src2, $src1)",
534 [(set (i32 IntRegs:$dst),
535 (i32 (select (i1 (setlt (i32 IntRegs:$src2),
536 (i32 IntRegs:$src1))),
537 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
539 def MAXUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
540 "$dst = maxu($src2, $src1)",
541 [(set (i32 IntRegs:$dst),
542 (i32 (select (i1 (setult (i32 IntRegs:$src2),
543 (i32 IntRegs:$src1))),
544 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
546 def MAXd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
548 "$dst = max($src2, $src1)",
549 [(set (i64 DoubleRegs:$dst),
550 (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
551 (i64 DoubleRegs:$src1))),
552 (i64 DoubleRegs:$src1),
553 (i64 DoubleRegs:$src2))))]>;
555 def MAXUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
557 "$dst = maxu($src2, $src1)",
558 [(set (i64 DoubleRegs:$dst),
559 (i64 (select (i1 (setult (i64 DoubleRegs:$src2),
560 (i64 DoubleRegs:$src1))),
561 (i64 DoubleRegs:$src1),
562 (i64 DoubleRegs:$src2))))]>;
565 def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
566 "$dst = min($src2, $src1)",
567 [(set (i32 IntRegs:$dst),
568 (i32 (select (i1 (setgt (i32 IntRegs:$src2),
569 (i32 IntRegs:$src1))),
570 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
572 def MINUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
573 "$dst = minu($src2, $src1)",
574 [(set (i32 IntRegs:$dst),
575 (i32 (select (i1 (setugt (i32 IntRegs:$src2),
576 (i32 IntRegs:$src1))),
577 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
579 def MINd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
581 "$dst = min($src2, $src1)",
582 [(set (i64 DoubleRegs:$dst),
583 (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
584 (i64 DoubleRegs:$src1))),
585 (i64 DoubleRegs:$src1),
586 (i64 DoubleRegs:$src2))))]>;
588 def MINUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
590 "$dst = minu($src2, $src1)",
591 [(set (i64 DoubleRegs:$dst),
592 (i64 (select (i1 (setugt (i64 DoubleRegs:$src2),
593 (i64 DoubleRegs:$src1))),
594 (i64 DoubleRegs:$src1),
595 (i64 DoubleRegs:$src2))))]>;
598 def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
600 "$dst = sub($src1, $src2)",
601 [(set (i64 DoubleRegs:$dst), (sub (i64 DoubleRegs:$src1),
602 (i64 DoubleRegs:$src2)))]>;
604 // Subtract halfword.
606 //===----------------------------------------------------------------------===//
608 //===----------------------------------------------------------------------===//
610 //===----------------------------------------------------------------------===//
612 //===----------------------------------------------------------------------===//
614 //===----------------------------------------------------------------------===//
616 //===----------------------------------------------------------------------===//
618 //===----------------------------------------------------------------------===//
620 //===----------------------------------------------------------------------===//
622 //===----------------------------------------------------------------------===//
624 //===----------------------------------------------------------------------===//
626 //===----------------------------------------------------------------------===//
628 //===----------------------------------------------------------------------===//
629 // Logical reductions on predicates.
631 // Looping instructions.
633 // Pipelined looping instructions.
635 // Logical operations on predicates.
636 def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
637 "$dst = and($src1, $src2)",
638 [(set (i1 PredRegs:$dst), (and (i1 PredRegs:$src1),
639 (i1 PredRegs:$src2)))]>;
641 let neverHasSideEffects = 1 in
642 def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
644 "$dst = and($src1, !$src2)",
647 def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
648 "$dst = any8($src1)",
651 def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
652 "$dst = all8($src1)",
655 def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
657 "$dst = vitpack($src1, $src2)",
660 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
663 "$dst = valignb($src1, $src2, $src3)",
666 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
669 "$dst = vspliceb($src1, $src2, $src3)",
672 def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
673 "$dst = mask($src1)",
676 def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
678 [(set (i1 PredRegs:$dst), (not (i1 PredRegs:$src1)))]>;
680 def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
681 "$dst = or($src1, $src2)",
682 [(set (i1 PredRegs:$dst), (or (i1 PredRegs:$src1),
683 (i1 PredRegs:$src2)))]>;
685 def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
686 "$dst = xor($src1, $src2)",
687 [(set (i1 PredRegs:$dst), (xor (i1 PredRegs:$src1),
688 (i1 PredRegs:$src2)))]>;
691 // User control register transfer.
692 //===----------------------------------------------------------------------===//
694 //===----------------------------------------------------------------------===//
697 //===----------------------------------------------------------------------===//
699 //===----------------------------------------------------------------------===//
701 let isBranch = 1, isTerminator=1, isBarrier = 1, isPredicable = 1 in {
702 def JMP : JInst< (outs),
703 (ins brtarget:$offset),
709 let isBranch = 1, isTerminator=1, Defs = [PC],
710 isPredicated = 1 in {
711 def JMP_c : JInst< (outs),
712 (ins PredRegs:$src, brtarget:$offset),
713 "if ($src) jump $offset",
714 [(brcond (i1 PredRegs:$src), bb:$offset)]>;
718 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
719 isPredicated = 1 in {
720 def JMP_cNot : JInst< (outs),
721 (ins PredRegs:$src, brtarget:$offset),
722 "if (!$src) jump $offset",
726 let isTerminator = 1, isBranch = 1, neverHasSideEffects = 1, Defs = [PC],
727 isPredicated = 1 in {
728 def BRCOND : JInst < (outs), (ins PredRegs:$pred, brtarget:$dst),
729 "if ($pred) jump $dst",
733 // Jump to address conditioned on new predicate.
735 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
736 isPredicated = 1 in {
737 def JMP_cdnPt : JInst< (outs),
738 (ins PredRegs:$src, brtarget:$offset),
739 "if ($src.new) jump:t $offset",
744 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
745 isPredicated = 1 in {
746 def JMP_cdnNotPt : JInst< (outs),
747 (ins PredRegs:$src, brtarget:$offset),
748 "if (!$src.new) jump:t $offset",
753 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
754 isPredicated = 1 in {
755 def JMP_cdnPnt : JInst< (outs),
756 (ins PredRegs:$src, brtarget:$offset),
757 "if ($src.new) jump:nt $offset",
762 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
763 isPredicated = 1 in {
764 def JMP_cdnNotPnt : JInst< (outs),
765 (ins PredRegs:$src, brtarget:$offset),
766 "if (!$src.new) jump:nt $offset",
769 //===----------------------------------------------------------------------===//
771 //===----------------------------------------------------------------------===//
773 //===----------------------------------------------------------------------===//
775 //===----------------------------------------------------------------------===//
776 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
777 [SDNPHasChain, SDNPOptInGlue]>;
779 // Jump to address from register.
780 let isPredicable =1, isReturn = 1, isTerminator = 1, isBarrier = 1,
781 Defs = [PC], Uses = [R31] in {
782 def JMPR: JRInst<(outs), (ins),
787 // Jump to address from register.
788 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
789 Defs = [PC], Uses = [R31] in {
790 def JMPR_cPt: JRInst<(outs), (ins PredRegs:$src1),
791 "if ($src1) jumpr r31",
795 // Jump to address from register.
796 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
797 Defs = [PC], Uses = [R31] in {
798 def JMPR_cNotPt: JRInst<(outs), (ins PredRegs:$src1),
799 "if (!$src1) jumpr r31",
803 //===----------------------------------------------------------------------===//
805 //===----------------------------------------------------------------------===//
807 //===----------------------------------------------------------------------===//
809 //===----------------------------------------------------------------------===//
811 // Load -- MEMri operand
812 multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
813 bit isNot, bit isPredNew> {
814 let PNewValue = #!if(isPredNew, "new", "") in
815 def #NAME# : LDInst2<(outs RC:$dst),
816 (ins PredRegs:$src1, MEMri:$addr),
817 #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
818 ") ")#"$dst = "#mnemonic#"($addr)",
822 multiclass LD_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
823 let PredSense = #!if(PredNot, "false", "true") in {
824 defm _c#NAME# : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
826 defm _cdn#NAME# : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
830 let isExtendable = 1, neverHasSideEffects = 1 in
831 multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
832 bits<5> ImmBits, bits<5> PredImmBits> {
834 let CextOpcode = CextOp, BaseOpcode = CextOp in {
835 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
837 def #NAME# : LDInst2<(outs RC:$dst), (ins MEMri:$addr),
838 "$dst = "#mnemonic#"($addr)",
841 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
842 isPredicated = 1 in {
843 defm Pt : LD_MEMri_Pred<mnemonic, RC, 0 >;
844 defm NotPt : LD_MEMri_Pred<mnemonic, RC, 1 >;
849 let addrMode = BaseImmOffset, isMEMri = "true" in {
850 defm LDrib: LD_MEMri < "memb", "LDrib", IntRegs, 11, 6>, AddrModeRel;
851 defm LDriub: LD_MEMri < "memub" , "LDriub", IntRegs, 11, 6>, AddrModeRel;
852 defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
853 defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel;
854 defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;
855 defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;
858 def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
859 (LDrib ADDRriS11_0:$addr) >;
861 def : Pat < (i32 (zextloadi8 ADDRriS11_0:$addr)),
862 (LDriub ADDRriS11_0:$addr) >;
864 def : Pat < (i32 (sextloadi16 ADDRriS11_1:$addr)),
865 (LDrih ADDRriS11_1:$addr) >;
867 def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)),
868 (LDriuh ADDRriS11_1:$addr) >;
870 def : Pat < (i32 (load ADDRriS11_2:$addr)),
871 (LDriw ADDRriS11_2:$addr) >;
873 def : Pat < (i64 (load ADDRriS11_3:$addr)),
874 (LDrid ADDRriS11_3:$addr) >;
877 // Load - Base with Immediate offset addressing mode
878 multiclass LD_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
879 bit isNot, bit isPredNew> {
880 let PNewValue = #!if(isPredNew, "new", "") in
881 def #NAME# : LDInst2<(outs RC:$dst),
882 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
883 #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
884 ") ")#"$dst = "#mnemonic#"($src2+#$src3)",
888 multiclass LD_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
890 let PredSense = #!if(PredNot, "false", "true") in {
891 defm _c#NAME# : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
893 defm _cdn#NAME# : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
897 let isExtendable = 1, neverHasSideEffects = 1 in
898 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
899 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
900 bits<5> PredImmBits> {
902 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
903 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
904 isPredicable = 1, AddedComplexity = 20 in
905 def #NAME# : LDInst2<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
906 "$dst = "#mnemonic#"($src1+#$offset)",
909 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
910 isPredicated = 1 in {
911 defm Pt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 0 >;
912 defm NotPt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 1 >;
917 let addrMode = BaseImmOffset in {
918 defm LDrib_indexed: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext,
920 defm LDriub_indexed: LD_Idxd <"memub" , "LDriub", IntRegs, s11_0Ext, u6_0Ext,
922 defm LDrih_indexed: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
924 defm LDriuh_indexed: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext,
926 defm LDriw_indexed: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
928 defm LDrid_indexed: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,
932 let AddedComplexity = 20 in {
933 def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
934 (LDrib_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
936 def : Pat < (i32 (zextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
937 (LDriub_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
939 def : Pat < (i32 (sextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
940 (LDrih_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
942 def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
943 (LDriuh_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
945 def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
946 (LDriw_indexed IntRegs:$src1, s11_2ExtPred:$offset) >;
948 def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
949 (LDrid_indexed IntRegs:$src1, s11_3ExtPred:$offset) >;
952 let neverHasSideEffects = 1 in
953 def LDrid_GP : LDInst2<(outs DoubleRegs:$dst),
954 (ins globaladdress:$global, u16Imm:$offset),
955 "$dst = memd(#$global+$offset)",
959 let neverHasSideEffects = 1 in
960 def LDd_GP : LDInst2<(outs DoubleRegs:$dst),
961 (ins globaladdress:$global),
962 "$dst = memd(#$global)",
966 //===----------------------------------------------------------------------===//
967 // Post increment load
968 // Make sure that in post increment load, the first operand is always the post
969 // increment operand.
970 //===----------------------------------------------------------------------===//
972 multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
973 bit isNot, bit isPredNew> {
974 let PNewValue = #!if(isPredNew, "new", "") in
975 def #NAME# : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
976 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
977 #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
978 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
983 multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,
984 Operand ImmOp, bit PredNot> {
985 let PredSense = #!if(PredNot, "false", "true") in {
986 defm _c#NAME# : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
988 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
989 defm _cdn#NAME#_V4 : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
993 multiclass LD_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
996 let BaseOpcode = "POST_"#BaseOp in {
997 let isPredicable = 1 in
998 def #NAME# : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
999 (ins IntRegs:$src1, ImmOp:$offset),
1000 "$dst = "#mnemonic#"($src1++#$offset)",
1004 let isPredicated = 1 in {
1005 defm Pt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1006 defm NotPt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1011 let hasCtrlDep = 1, neverHasSideEffects = 1 in {
1012 defm POST_LDrib : LD_PostInc<"memb", "LDrib", IntRegs, s4_0Imm>,
1014 defm POST_LDriub : LD_PostInc<"memub", "LDriub", IntRegs, s4_0Imm>,
1016 defm POST_LDrih : LD_PostInc<"memh", "LDrih", IntRegs, s4_1Imm>,
1018 defm POST_LDriuh : LD_PostInc<"memuh", "LDriuh", IntRegs, s4_1Imm>,
1020 defm POST_LDriw : LD_PostInc<"memw", "LDriw", IntRegs, s4_2Imm>,
1022 defm POST_LDrid : LD_PostInc<"memd", "LDrid", DoubleRegs, s4_3Imm>,
1026 // Load byte any-extend.
1027 def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
1028 (i32 (LDrib ADDRriS11_0:$addr)) >;
1030 // Indexed load byte any-extend.
1031 let AddedComplexity = 20 in
1032 def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1033 (i32 (LDrib_indexed IntRegs:$src1, s11_0ImmPred:$offset)) >;
1035 let neverHasSideEffects = 1 in
1036 def LDrib_GP : LDInst2<(outs IntRegs:$dst),
1037 (ins globaladdress:$global, u16Imm:$offset),
1038 "$dst = memb(#$global+$offset)",
1042 let neverHasSideEffects = 1 in
1043 def LDb_GP : LDInst2<(outs IntRegs:$dst),
1044 (ins globaladdress:$global),
1045 "$dst = memb(#$global)",
1049 let neverHasSideEffects = 1 in
1050 def LDub_GP : LDInst2<(outs IntRegs:$dst),
1051 (ins globaladdress:$global),
1052 "$dst = memub(#$global)",
1056 def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
1057 (i32 (LDrih ADDRriS11_1:$addr))>;
1059 let AddedComplexity = 20 in
1060 def : Pat < (i32 (extloadi16 (add IntRegs:$src1, s11_1ImmPred:$offset))),
1061 (i32 (LDrih_indexed IntRegs:$src1, s11_1ImmPred:$offset)) >;
1063 let neverHasSideEffects = 1 in
1064 def LDrih_GP : LDInst2<(outs IntRegs:$dst),
1065 (ins globaladdress:$global, u16Imm:$offset),
1066 "$dst = memh(#$global+$offset)",
1070 let neverHasSideEffects = 1 in
1071 def LDh_GP : LDInst2<(outs IntRegs:$dst),
1072 (ins globaladdress:$global),
1073 "$dst = memh(#$global)",
1077 let neverHasSideEffects = 1 in
1078 def LDuh_GP : LDInst2<(outs IntRegs:$dst),
1079 (ins globaladdress:$global),
1080 "$dst = memuh(#$global)",
1084 def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
1085 (i32 (LDriub ADDRriS11_0:$addr))>;
1087 let AddedComplexity = 20 in
1088 def : Pat < (i32 (zextloadi1 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1089 (i32 (LDriub_indexed IntRegs:$src1, s11_0ImmPred:$offset))>;
1091 let neverHasSideEffects = 1 in
1092 def LDriub_GP : LDInst2<(outs IntRegs:$dst),
1093 (ins globaladdress:$global, u16Imm:$offset),
1094 "$dst = memub(#$global+$offset)",
1098 // Load unsigned halfword.
1099 let neverHasSideEffects = 1 in
1100 def LDriuh_GP : LDInst2<(outs IntRegs:$dst),
1101 (ins globaladdress:$global, u16Imm:$offset),
1102 "$dst = memuh(#$global+$offset)",
1107 let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1108 def LDriw_pred : LDInst<(outs PredRegs:$dst),
1110 "Error; should not emit",
1114 let neverHasSideEffects = 1 in
1115 def LDriw_GP : LDInst2<(outs IntRegs:$dst),
1116 (ins globaladdress:$global, u16Imm:$offset),
1117 "$dst = memw(#$global+$offset)",
1121 let neverHasSideEffects = 1 in
1122 def LDw_GP : LDInst2<(outs IntRegs:$dst),
1123 (ins globaladdress:$global),
1124 "$dst = memw(#$global)",
1128 // Deallocate stack frame.
1129 let Defs = [R29, R30, R31], Uses = [R29], neverHasSideEffects = 1 in {
1130 def DEALLOCFRAME : LDInst2<(outs), (ins i32imm:$amt1),
1135 // Load and unpack bytes to halfwords.
1136 //===----------------------------------------------------------------------===//
1138 //===----------------------------------------------------------------------===//
1140 //===----------------------------------------------------------------------===//
1142 //===----------------------------------------------------------------------===//
1143 //===----------------------------------------------------------------------===//
1145 //===----------------------------------------------------------------------===//
1147 //===----------------------------------------------------------------------===//
1149 //===----------------------------------------------------------------------===//
1150 //===----------------------------------------------------------------------===//
1152 //===----------------------------------------------------------------------===//
1154 //===----------------------------------------------------------------------===//
1156 //===----------------------------------------------------------------------===//
1157 // Multiply and use lower result.
1159 def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1160 "$dst =+ mpyi($src1, #$src2)",
1161 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1162 u8ImmPred:$src2))]>;
1165 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, n8Imm:$src2),
1166 "$dst =- mpyi($src1, #$src2)",
1167 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1168 n8ImmPred:$src2))]>;
1171 // s9 is NOT the same as m9 - but it works.. so far.
1172 // Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
1173 // depending on the value of m9. See Arch Spec.
1174 def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Imm:$src2),
1175 "$dst = mpyi($src1, #$src2)",
1176 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1177 s9ImmPred:$src2))]>;
1180 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1181 "$dst = mpyi($src1, $src2)",
1182 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1183 (i32 IntRegs:$src2)))]>;
1186 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
1187 (ins IntRegs:$src1, IntRegs:$src2, u8Imm:$src3),
1188 "$dst += mpyi($src2, #$src3)",
1189 [(set (i32 IntRegs:$dst),
1190 (add (mul (i32 IntRegs:$src2), u8ImmPred:$src3),
1191 (i32 IntRegs:$src1)))],
1195 def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
1196 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1197 "$dst += mpyi($src2, $src3)",
1198 [(set (i32 IntRegs:$dst),
1199 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1200 (i32 IntRegs:$src1)))],
1204 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
1205 (ins IntRegs:$src1, IntRegs:$src2, u8Imm:$src3),
1206 "$dst -= mpyi($src2, #$src3)",
1207 [(set (i32 IntRegs:$dst),
1208 (sub (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1209 u8ImmPred:$src3)))],
1212 // Multiply and use upper result.
1213 // Rd=mpy(Rs,Rt.H):<<1:rnd:sat
1214 // Rd=mpy(Rs,Rt.L):<<1:rnd:sat
1216 def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1217 "$dst = mpy($src1, $src2)",
1218 [(set (i32 IntRegs:$dst), (mulhs (i32 IntRegs:$src1),
1219 (i32 IntRegs:$src2)))]>;
1221 // Rd=mpy(Rs,Rt):rnd
1223 def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1224 "$dst = mpyu($src1, $src2)",
1225 [(set (i32 IntRegs:$dst), (mulhu (i32 IntRegs:$src1),
1226 (i32 IntRegs:$src2)))]>;
1228 // Multiply and use full result.
1230 def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1231 "$dst = mpyu($src1, $src2)",
1232 [(set (i64 DoubleRegs:$dst),
1233 (mul (i64 (anyext (i32 IntRegs:$src1))),
1234 (i64 (anyext (i32 IntRegs:$src2)))))]>;
1237 def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1238 "$dst = mpy($src1, $src2)",
1239 [(set (i64 DoubleRegs:$dst),
1240 (mul (i64 (sext (i32 IntRegs:$src1))),
1241 (i64 (sext (i32 IntRegs:$src2)))))]>;
1243 // Multiply and accumulate, use full result.
1244 // Rxx[+-]=mpy(Rs,Rt)
1246 def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
1247 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1248 "$dst += mpy($src2, $src3)",
1249 [(set (i64 DoubleRegs:$dst),
1250 (add (mul (i64 (sext (i32 IntRegs:$src2))),
1251 (i64 (sext (i32 IntRegs:$src3)))),
1252 (i64 DoubleRegs:$src1)))],
1256 def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
1257 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1258 "$dst -= mpy($src2, $src3)",
1259 [(set (i64 DoubleRegs:$dst),
1260 (sub (i64 DoubleRegs:$src1),
1261 (mul (i64 (sext (i32 IntRegs:$src2))),
1262 (i64 (sext (i32 IntRegs:$src3))))))],
1265 // Rxx[+-]=mpyu(Rs,Rt)
1267 def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1268 IntRegs:$src2, IntRegs:$src3),
1269 "$dst += mpyu($src2, $src3)",
1270 [(set (i64 DoubleRegs:$dst),
1271 (add (mul (i64 (anyext (i32 IntRegs:$src2))),
1272 (i64 (anyext (i32 IntRegs:$src3)))),
1273 (i64 DoubleRegs:$src1)))], "$src1 = $dst">;
1276 def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
1277 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1278 "$dst += mpyu($src2, $src3)",
1279 [(set (i64 DoubleRegs:$dst),
1280 (sub (i64 DoubleRegs:$src1),
1281 (mul (i64 (anyext (i32 IntRegs:$src2))),
1282 (i64 (anyext (i32 IntRegs:$src3))))))],
1286 def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1287 IntRegs:$src2, IntRegs:$src3),
1288 "$dst += add($src2, $src3)",
1289 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1290 (i32 IntRegs:$src3)),
1291 (i32 IntRegs:$src1)))],
1294 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1295 IntRegs:$src2, s8Imm:$src3),
1296 "$dst += add($src2, #$src3)",
1297 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1299 (i32 IntRegs:$src1)))],
1302 def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1303 IntRegs:$src2, IntRegs:$src3),
1304 "$dst -= add($src2, $src3)",
1305 [(set (i32 IntRegs:$dst),
1306 (sub (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1307 (i32 IntRegs:$src3))))],
1310 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1311 IntRegs:$src2, s8Imm:$src3),
1312 "$dst -= add($src2, #$src3)",
1313 [(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
1314 (add (i32 IntRegs:$src2),
1315 s8ImmPred:$src3)))],
1318 //===----------------------------------------------------------------------===//
1320 //===----------------------------------------------------------------------===//
1322 //===----------------------------------------------------------------------===//
1324 //===----------------------------------------------------------------------===//
1325 //===----------------------------------------------------------------------===//
1327 //===----------------------------------------------------------------------===//
1329 //===----------------------------------------------------------------------===//
1331 //===----------------------------------------------------------------------===//
1332 //===----------------------------------------------------------------------===//
1334 //===----------------------------------------------------------------------===//
1336 //===----------------------------------------------------------------------===//
1338 //===----------------------------------------------------------------------===//
1339 //===----------------------------------------------------------------------===//
1341 //===----------------------------------------------------------------------===//
1343 //===----------------------------------------------------------------------===//
1345 //===----------------------------------------------------------------------===//
1347 /// Assumptions::: ****** DO NOT IGNORE ********
1348 /// 1. Make sure that in post increment store, the zero'th operand is always the
1349 /// post increment operand.
1350 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
1353 // Store doubleword.
1355 let neverHasSideEffects = 1 in
1356 def STrid_GP : STInst2<(outs),
1357 (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),
1358 "memd(#$global+$offset) = $src",
1362 let neverHasSideEffects = 1 in
1363 def STd_GP : STInst2<(outs),
1364 (ins globaladdress:$global, DoubleRegs:$src),
1365 "memd(#$global) = $src",
1369 let hasCtrlDep = 1, isPredicable = 1 in
1370 def POST_STdri : STInstPI<(outs IntRegs:$dst),
1371 (ins DoubleRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1372 "memd($src2++#$offset) = $src1",
1374 (post_store (i64 DoubleRegs:$src1), (i32 IntRegs:$src2),
1375 s4_3ImmPred:$offset))],
1378 // if ([!]Pv) memd(Rx++#s4:3)=Rtt
1379 // if (Pv) memd(Rx++#s4:3)=Rtt
1380 let AddedComplexity = 10, neverHasSideEffects = 1,
1382 def POST_STdri_cPt : STInst2PI<(outs IntRegs:$dst),
1383 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1385 "if ($src1) memd($src3++#$offset) = $src2",
1389 // if (!Pv) memd(Rx++#s4:3)=Rtt
1390 let AddedComplexity = 10, neverHasSideEffects = 1, isPredicated = 1,
1392 def POST_STdri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1393 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1395 "if (!$src1) memd($src3++#$offset) = $src2",
1399 //===----------------------------------------------------------------------===//
1400 // multiclass for the store instructions with MEMri operand.
1401 //===----------------------------------------------------------------------===//
1402 multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot,
1404 let PNewValue = #!if(isPredNew, "new", "") in
1405 def #NAME# : STInst2<(outs),
1406 (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
1407 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1408 ") ")#mnemonic#"($addr) = $src2",
1412 multiclass ST_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1413 let PredSense = #!if(PredNot, "false", "true") in {
1414 defm _c#NAME# : ST_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
1417 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1418 defm _cdn#NAME#_V4 : ST_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
1422 let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1423 multiclass ST_MEMri<string mnemonic, string CextOp, RegisterClass RC,
1424 bits<5> ImmBits, bits<5> PredImmBits> {
1426 let CextOpcode = CextOp, BaseOpcode = CextOp in {
1427 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1429 def #NAME# : STInst2<(outs),
1430 (ins MEMri:$addr, RC:$src),
1431 #mnemonic#"($addr) = $src",
1434 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
1435 isPredicated = 1 in {
1436 defm Pt : ST_MEMri_Pred<mnemonic, RC, 0>;
1437 defm NotPt : ST_MEMri_Pred<mnemonic, RC, 1>;
1442 let addrMode = BaseImmOffset, isMEMri = "true" in {
1443 defm STrib: ST_MEMri < "memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
1444 defm STrih: ST_MEMri < "memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
1445 defm STriw: ST_MEMri < "memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
1447 let isNVStorable = 0 in
1448 defm STrid: ST_MEMri < "memd", "STrid", DoubleRegs, 14, 9>, AddrModeRel;
1451 def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
1452 (STrib ADDRriS11_0:$addr, (i32 IntRegs:$src1))>;
1454 def : Pat<(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr),
1455 (STrih ADDRriS11_1:$addr, (i32 IntRegs:$src1))>;
1457 def : Pat<(store (i32 IntRegs:$src1), ADDRriS11_2:$addr),
1458 (STriw ADDRriS11_2:$addr, (i32 IntRegs:$src1))>;
1460 def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
1461 (STrid ADDRriS11_3:$addr, (i64 DoubleRegs:$src1))>;
1464 //===----------------------------------------------------------------------===//
1465 // multiclass for the store instructions with base+immediate offset
1467 //===----------------------------------------------------------------------===//
1468 multiclass ST_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
1469 bit isNot, bit isPredNew> {
1470 let PNewValue = #!if(isPredNew, "new", "") in
1471 def #NAME# : STInst2<(outs),
1472 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
1473 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1474 ") ")#mnemonic#"($src2+#$src3) = $src4",
1478 multiclass ST_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
1480 let PredSense = #!if(PredNot, "false", "true"), isPredicated = 1 in {
1481 defm _c#NAME# : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
1484 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1485 defm _cdn#NAME#_V4 : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
1489 let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1490 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1491 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
1492 bits<5> PredImmBits> {
1494 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1495 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1497 def #NAME# : STInst2<(outs),
1498 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1499 #mnemonic#"($src1+#$src2) = $src3",
1502 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits in {
1503 defm Pt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 0>;
1504 defm NotPt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 1>;
1509 let addrMode = BaseImmOffset, InputType = "reg" in {
1510 defm STrib_indexed: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext,
1511 u6_0Ext, 11, 6>, AddrModeRel, ImmRegRel;
1512 defm STrih_indexed: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext,
1513 u6_1Ext, 12, 7>, AddrModeRel, ImmRegRel;
1514 defm STriw_indexed: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext,
1515 u6_2Ext, 13, 8>, AddrModeRel, ImmRegRel;
1516 let isNVStorable = 0 in
1517 defm STrid_indexed: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
1518 u6_3Ext, 14, 9>, AddrModeRel;
1521 let AddedComplexity = 10 in {
1522 def : Pat<(truncstorei8 (i32 IntRegs:$src1), (add IntRegs:$src2,
1523 s11_0ExtPred:$offset)),
1524 (STrib_indexed IntRegs:$src2, s11_0ImmPred:$offset,
1525 (i32 IntRegs:$src1))>;
1527 def : Pat<(truncstorei16 (i32 IntRegs:$src1), (add IntRegs:$src2,
1528 s11_1ExtPred:$offset)),
1529 (STrih_indexed IntRegs:$src2, s11_1ImmPred:$offset,
1530 (i32 IntRegs:$src1))>;
1532 def : Pat<(store (i32 IntRegs:$src1), (add IntRegs:$src2,
1533 s11_2ExtPred:$offset)),
1534 (STriw_indexed IntRegs:$src2, s11_2ImmPred:$offset,
1535 (i32 IntRegs:$src1))>;
1537 def : Pat<(store (i64 DoubleRegs:$src1), (add IntRegs:$src2,
1538 s11_3ExtPred:$offset)),
1539 (STrid_indexed IntRegs:$src2, s11_3ImmPred:$offset,
1540 (i64 DoubleRegs:$src1))>;
1543 // memb(gp+#u16:0)=Rt
1544 let neverHasSideEffects = 1 in
1545 def STrib_GP : STInst2<(outs),
1546 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1547 "memb(#$global+$offset) = $src",
1552 let neverHasSideEffects = 1 in
1553 def STb_GP : STInst2<(outs),
1554 (ins globaladdress:$global, IntRegs:$src),
1555 "memb(#$global) = $src",
1559 // memb(Rx++#s4:0)=Rt
1560 let hasCtrlDep = 1, isPredicable = 1 in
1561 def POST_STbri : STInstPI<(outs IntRegs:$dst), (ins IntRegs:$src1,
1564 "memb($src2++#$offset) = $src1",
1566 (post_truncsti8 (i32 IntRegs:$src1), (i32 IntRegs:$src2),
1567 s4_0ImmPred:$offset))],
1570 // if ([!]Pv) memb(Rx++#s4:0)=Rt
1571 // if (Pv) memb(Rx++#s4:0)=Rt
1572 let hasCtrlDep = 1, isPredicated = 1 in
1573 def POST_STbri_cPt : STInst2PI<(outs IntRegs:$dst),
1574 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1575 "if ($src1) memb($src3++#$offset) = $src2",
1578 // if (!Pv) memb(Rx++#s4:0)=Rt
1579 let hasCtrlDep = 1, isPredicated = 1 in
1580 def POST_STbri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1581 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1582 "if (!$src1) memb($src3++#$offset) = $src2",
1585 let neverHasSideEffects = 1 in
1586 def STrih_GP : STInst2<(outs),
1587 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1588 "memh(#$global+$offset) = $src",
1592 let neverHasSideEffects = 1 in
1593 def STh_GP : STInst2<(outs),
1594 (ins globaladdress:$global, IntRegs:$src),
1595 "memh(#$global) = $src",
1599 // memh(Rx++#s4:1)=Rt.H
1600 // memh(Rx++#s4:1)=Rt
1601 let hasCtrlDep = 1, isPredicable = 1 in
1602 def POST_SThri : STInstPI<(outs IntRegs:$dst),
1603 (ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1604 "memh($src2++#$offset) = $src1",
1606 (post_truncsti16 (i32 IntRegs:$src1), (i32 IntRegs:$src2),
1607 s4_1ImmPred:$offset))],
1610 // if ([!]Pv) memh(Rx++#s4:1)=Rt
1611 // if (Pv) memh(Rx++#s4:1)=Rt
1612 let hasCtrlDep = 1, isPredicated = 1 in
1613 def POST_SThri_cPt : STInst2PI<(outs IntRegs:$dst),
1614 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1615 "if ($src1) memh($src3++#$offset) = $src2",
1618 // if (!Pv) memh(Rx++#s4:1)=Rt
1619 let hasCtrlDep = 1, isPredicated = 1 in
1620 def POST_SThri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1621 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1622 "if (!$src1) memh($src3++#$offset) = $src2",
1628 let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1629 def STriw_pred : STInst2<(outs),
1630 (ins MEMri:$addr, PredRegs:$src1),
1631 "Error; should not emit",
1634 let neverHasSideEffects = 1 in
1635 def STriw_GP : STInst2<(outs),
1636 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1637 "memw(#$global+$offset) = $src",
1641 let neverHasSideEffects = 1 in
1642 def STw_GP : STInst2<(outs),
1643 (ins globaladdress:$global, IntRegs:$src),
1644 "memw(#$global) = $src",
1648 let hasCtrlDep = 1, isPredicable = 1 in
1649 def POST_STwri : STInstPI<(outs IntRegs:$dst),
1650 (ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1651 "memw($src2++#$offset) = $src1",
1653 (post_store (i32 IntRegs:$src1), (i32 IntRegs:$src2),
1654 s4_2ImmPred:$offset))],
1657 // if ([!]Pv) memw(Rx++#s4:2)=Rt
1658 // if (Pv) memw(Rx++#s4:2)=Rt
1659 let hasCtrlDep = 1, isPredicated = 1 in
1660 def POST_STwri_cPt : STInst2PI<(outs IntRegs:$dst),
1661 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
1662 "if ($src1) memw($src3++#$offset) = $src2",
1665 // if (!Pv) memw(Rx++#s4:2)=Rt
1666 let hasCtrlDep = 1, isPredicated = 1 in
1667 def POST_STwri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1668 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
1669 "if (!$src1) memw($src3++#$offset) = $src2",
1674 // Allocate stack frame.
1675 let Defs = [R29, R30], Uses = [R31, R30], neverHasSideEffects = 1 in {
1676 def ALLOCFRAME : STInst2<(outs),
1678 "allocframe(#$amt)",
1681 //===----------------------------------------------------------------------===//
1683 //===----------------------------------------------------------------------===//
1685 //===----------------------------------------------------------------------===//
1687 //===----------------------------------------------------------------------===//
1689 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
1690 "$dst = not($src1)",
1691 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
1694 // Sign extend word to doubleword.
1695 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
1696 "$dst = sxtw($src1)",
1697 [(set (i64 DoubleRegs:$dst), (sext (i32 IntRegs:$src1)))]>;
1698 //===----------------------------------------------------------------------===//
1700 //===----------------------------------------------------------------------===//
1702 //===----------------------------------------------------------------------===//
1704 //===----------------------------------------------------------------------===//
1706 def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1707 "$dst = clrbit($src1, #$src2)",
1708 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
1710 (shl 1, u5ImmPred:$src2))))]>;
1712 def CLRBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1713 "$dst = clrbit($src1, #$src2)",
1716 // Map from r0 = and(r1, 2147483647) to r0 = clrbit(r1, #31).
1717 def : Pat <(and (i32 IntRegs:$src1), 2147483647),
1718 (CLRBIT_31 (i32 IntRegs:$src1), 31)>;
1721 def SETBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1722 "$dst = setbit($src1, #$src2)",
1723 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
1724 (shl 1, u5ImmPred:$src2)))]>;
1726 // Map from r0 = or(r1, -2147483648) to r0 = setbit(r1, #31).
1727 def SETBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1728 "$dst = setbit($src1, #$src2)",
1731 def : Pat <(or (i32 IntRegs:$src1), -2147483648),
1732 (SETBIT_31 (i32 IntRegs:$src1), 31)>;
1735 def TOGBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1736 "$dst = setbit($src1, #$src2)",
1737 [(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
1738 (shl 1, u5ImmPred:$src2)))]>;
1740 // Map from r0 = xor(r1, -2147483648) to r0 = togglebit(r1, #31).
1741 def TOGBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1742 "$dst = togglebit($src1, #$src2)",
1745 def : Pat <(xor (i32 IntRegs:$src1), -2147483648),
1746 (TOGBIT_31 (i32 IntRegs:$src1), 31)>;
1748 // Predicate transfer.
1749 let neverHasSideEffects = 1 in
1750 def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
1751 "$dst = $src1 /* Should almost never emit this. */",
1754 def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1),
1755 "$dst = $src1 /* Should almost never emit this. */",
1756 [(set (i1 PredRegs:$dst), (trunc (i32 IntRegs:$src1)))]>;
1757 //===----------------------------------------------------------------------===//
1759 //===----------------------------------------------------------------------===//
1761 //===----------------------------------------------------------------------===//
1763 //===----------------------------------------------------------------------===//
1764 // Shift by immediate.
1765 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1766 "$dst = asr($src1, #$src2)",
1767 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1768 u5ImmPred:$src2))]>;
1770 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1771 "$dst = asr($src1, #$src2)",
1772 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1773 u6ImmPred:$src2))]>;
1775 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1776 "$dst = asl($src1, #$src2)",
1777 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1778 u5ImmPred:$src2))]>;
1780 def ASLd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1781 "$dst = asl($src1, #$src2)",
1782 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1783 u6ImmPred:$src2))]>;
1785 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1786 "$dst = lsr($src1, #$src2)",
1787 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1788 u5ImmPred:$src2))]>;
1790 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1791 "$dst = lsr($src1, #$src2)",
1792 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1793 u6ImmPred:$src2))]>;
1795 // Shift by immediate and add.
1796 let AddedComplexity = 100 in
1797 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
1799 "$dst = addasl($src1, $src2, #$src3)",
1800 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
1801 (shl (i32 IntRegs:$src2),
1802 u3ImmPred:$src3)))]>;
1804 // Shift by register.
1805 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1806 "$dst = asl($src1, $src2)",
1807 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1808 (i32 IntRegs:$src2)))]>;
1810 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1811 "$dst = asr($src1, $src2)",
1812 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1813 (i32 IntRegs:$src2)))]>;
1815 def LSL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1816 "$dst = lsl($src1, $src2)",
1817 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1818 (i32 IntRegs:$src2)))]>;
1820 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1821 "$dst = lsr($src1, $src2)",
1822 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1823 (i32 IntRegs:$src2)))]>;
1825 def ASLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1826 "$dst = asl($src1, $src2)",
1827 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1828 (i32 IntRegs:$src2)))]>;
1830 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1831 "$dst = lsl($src1, $src2)",
1832 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1833 (i32 IntRegs:$src2)))]>;
1835 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1837 "$dst = asr($src1, $src2)",
1838 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1839 (i32 IntRegs:$src2)))]>;
1841 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1843 "$dst = lsr($src1, $src2)",
1844 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1845 (i32 IntRegs:$src2)))]>;
1847 //===----------------------------------------------------------------------===//
1849 //===----------------------------------------------------------------------===//
1851 //===----------------------------------------------------------------------===//
1853 //===----------------------------------------------------------------------===//
1854 //===----------------------------------------------------------------------===//
1856 //===----------------------------------------------------------------------===//
1858 //===----------------------------------------------------------------------===//
1860 //===----------------------------------------------------------------------===//
1861 //===----------------------------------------------------------------------===//
1863 //===----------------------------------------------------------------------===//
1865 //===----------------------------------------------------------------------===//
1867 //===----------------------------------------------------------------------===//
1869 //===----------------------------------------------------------------------===//
1871 //===----------------------------------------------------------------------===//
1872 def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
1873 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
1876 let hasSideEffects = 1, isHexagonSolo = 1 in
1877 def BARRIER : SYSInst<(outs), (ins),
1879 [(HexagonBARRIER)]>;
1881 //===----------------------------------------------------------------------===//
1883 //===----------------------------------------------------------------------===//
1885 // TFRI64 - assembly mapped.
1886 let isReMaterializable = 1 in
1887 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
1889 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
1891 // Pseudo instruction to encode a set of conditional transfers.
1892 // This instruction is used instead of a mux and trades-off codesize
1893 // for performance. We conduct this transformation optimistically in
1894 // the hope that these instructions get promoted to dot-new transfers.
1895 let AddedComplexity = 100, isPredicated = 1 in
1896 def TFR_condset_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
1899 "Error; should not emit",
1900 [(set (i32 IntRegs:$dst),
1901 (i32 (select (i1 PredRegs:$src1),
1902 (i32 IntRegs:$src2),
1903 (i32 IntRegs:$src3))))]>;
1904 let AddedComplexity = 100, isPredicated = 1 in
1905 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
1906 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
1907 "Error; should not emit",
1908 [(set (i32 IntRegs:$dst),
1909 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
1910 s12ImmPred:$src3)))]>;
1912 let AddedComplexity = 100, isPredicated = 1 in
1913 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
1914 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
1915 "Error; should not emit",
1916 [(set (i32 IntRegs:$dst),
1917 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
1918 (i32 IntRegs:$src3))))]>;
1920 let AddedComplexity = 100, isPredicated = 1 in
1921 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
1922 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
1923 "Error; should not emit",
1924 [(set (i32 IntRegs:$dst),
1925 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
1926 s12ImmPred:$src3)))]>;
1928 // Generate frameindex addresses.
1929 let isReMaterializable = 1 in
1930 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
1931 "$dst = add($src1)",
1932 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
1937 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
1938 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
1939 "loop0($offset, #$src2)",
1943 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
1944 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
1945 "loop0($offset, $src2)",
1949 let isBranch = 1, isTerminator = 1, neverHasSideEffects = 1,
1950 Defs = [PC, LC0], Uses = [SA0, LC0] in {
1951 def ENDLOOP0 : Marker<(outs), (ins brtarget:$offset),
1956 // Support for generating global address.
1957 // Taken from X86InstrInfo.td.
1958 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [
1962 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
1963 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
1965 // HI/LO Instructions
1966 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1967 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
1968 "$dst.l = #LO($global)",
1971 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1972 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
1973 "$dst.h = #HI($global)",
1976 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1977 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
1978 "$dst.l = #LO($imm_value)",
1982 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1983 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
1984 "$dst.h = #HI($imm_value)",
1987 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1988 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
1989 "$dst.l = #LO($jt)",
1992 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1993 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
1994 "$dst.h = #HI($jt)",
1998 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1999 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2000 "$dst.l = #LO($label)",
2003 let isReMaterializable = 1, isMoveImm = 1 , neverHasSideEffects = 1 in
2004 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2005 "$dst.h = #HI($label)",
2008 // This pattern is incorrect. When we add small data, we should change
2009 // this pattern to use memw(#foo).
2010 // This is for sdata.
2011 let isMoveImm = 1 in
2012 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2013 "$dst = CONST32(#$global)",
2014 [(set (i32 IntRegs:$dst),
2015 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
2017 // This is for non-sdata.
2018 let isReMaterializable = 1, isMoveImm = 1 in
2019 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2020 "$dst = CONST32(#$global)",
2021 [(set (i32 IntRegs:$dst),
2022 (HexagonCONST32 tglobaladdr:$global))]>;
2024 let isReMaterializable = 1, isMoveImm = 1 in
2025 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2026 "$dst = CONST32(#$jt)",
2027 [(set (i32 IntRegs:$dst),
2028 (HexagonCONST32 tjumptable:$jt))]>;
2030 let isReMaterializable = 1, isMoveImm = 1 in
2031 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2032 "$dst = CONST32(#$global)",
2033 [(set (i32 IntRegs:$dst),
2034 (HexagonCONST32_GP tglobaladdr:$global))]>;
2036 let isReMaterializable = 1, isMoveImm = 1 in
2037 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
2038 "$dst = CONST32(#$global)",
2039 [(set (i32 IntRegs:$dst), imm:$global) ]>;
2041 let isReMaterializable = 1, isMoveImm = 1 in
2042 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
2043 "$dst = CONST32($label)",
2044 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
2046 let isReMaterializable = 1, isMoveImm = 1 in
2047 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
2048 "$dst = CONST64(#$global)",
2049 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
2051 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
2052 "$dst = xor($dst, $dst)",
2053 [(set (i1 PredRegs:$dst), 0)]>;
2055 def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2056 "$dst = mpy($src1, $src2)",
2057 [(set (i32 IntRegs:$dst),
2058 (trunc (i64 (srl (i64 (mul (i64 (sext (i32 IntRegs:$src1))),
2059 (i64 (sext (i32 IntRegs:$src2))))),
2062 // Pseudo instructions.
2063 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
2065 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
2066 SDTCisVT<1, i32> ]>;
2068 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
2069 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2071 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
2072 [SDNPHasChain, SDNPOutGlue]>;
2074 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2076 def call : SDNode<"HexagonISD::CALL", SDT_SPCall,
2077 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
2079 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
2080 // Optional Flag and Variable Arguments.
2081 // Its 1 Operand has pointer type.
2082 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
2083 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
2085 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
2086 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
2087 "Should never be emitted",
2088 [(callseq_start timm:$amt)]>;
2091 let Defs = [R29, R30, R31], Uses = [R29] in {
2092 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2093 "Should never be emitted",
2094 [(callseq_end timm:$amt1, timm:$amt2)]>;
2097 let isCall = 1, neverHasSideEffects = 1,
2098 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2099 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2100 def CALL : JInst<(outs), (ins calltarget:$dst),
2104 // Call subroutine from register.
2105 let isCall = 1, neverHasSideEffects = 1,
2106 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2107 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2108 def CALLR : JRInst<(outs), (ins IntRegs:$dst),
2114 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2115 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst),
2116 "jump $dst // TAILCALL", []>;
2118 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2119 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst),
2120 "jump $dst // TAILCALL", []>;
2123 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2124 def TCRETURNR : JInst<(outs), (ins IntRegs:$dst),
2125 "jumpr $dst // TAILCALL", []>;
2127 // Map call instruction.
2128 def : Pat<(call (i32 IntRegs:$dst)),
2129 (CALLR (i32 IntRegs:$dst))>, Requires<[HasV2TOnly]>;
2130 def : Pat<(call tglobaladdr:$dst),
2131 (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
2132 def : Pat<(call texternalsym:$dst),
2133 (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>;
2135 def : Pat<(HexagonTCRet tglobaladdr:$dst),
2136 (TCRETURNtg tglobaladdr:$dst)>;
2137 def : Pat<(HexagonTCRet texternalsym:$dst),
2138 (TCRETURNtext texternalsym:$dst)>;
2139 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
2140 (TCRETURNR (i32 IntRegs:$dst))>;
2142 // Atomic load and store support
2143 // 8 bit atomic load
2144 def : Pat<(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
2145 (i32 (LDub_GP tglobaladdr:$global))>,
2148 def : Pat<(atomic_load_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2149 u16ImmPred:$offset)),
2150 (i32 (LDriub_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2153 def : Pat<(atomic_load_8 ADDRriS11_0:$src1),
2154 (i32 (LDriub ADDRriS11_0:$src1))>;
2156 def : Pat<(atomic_load_8 (add (i32 IntRegs:$src1), s11_0ImmPred:$offset)),
2157 (i32 (LDriub_indexed (i32 IntRegs:$src1), s11_0ImmPred:$offset))>;
2161 // 16 bit atomic load
2162 def : Pat<(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
2163 (i32 (LDuh_GP tglobaladdr:$global))>,
2166 def : Pat<(atomic_load_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2167 u16ImmPred:$offset)),
2168 (i32 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2171 def : Pat<(atomic_load_16 ADDRriS11_1:$src1),
2172 (i32 (LDriuh ADDRriS11_1:$src1))>;
2174 def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)),
2175 (i32 (LDriuh_indexed (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
2179 // 32 bit atomic load
2180 def : Pat<(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
2181 (i32 (LDw_GP tglobaladdr:$global))>,
2184 def : Pat<(atomic_load_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2185 u16ImmPred:$offset)),
2186 (i32 (LDriw_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2189 def : Pat<(atomic_load_32 ADDRriS11_2:$src1),
2190 (i32 (LDriw ADDRriS11_2:$src1))>;
2192 def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),
2193 (i32 (LDriw_indexed (i32 IntRegs:$src1), s11_2ImmPred:$offset))>;
2196 // 64 bit atomic load
2197 def : Pat<(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
2198 (i64 (LDd_GP tglobaladdr:$global))>,
2201 def : Pat<(atomic_load_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2202 u16ImmPred:$offset)),
2203 (i64 (LDrid_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2206 def : Pat<(atomic_load_64 ADDRriS11_3:$src1),
2207 (i64 (LDrid ADDRriS11_3:$src1))>;
2209 def : Pat<(atomic_load_64 (add (i32 IntRegs:$src1), s11_3ImmPred:$offset)),
2210 (i64 (LDrid_indexed (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
2213 // 64 bit atomic store
2214 def : Pat<(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
2215 (i64 DoubleRegs:$src1)),
2216 (STd_GP tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2219 def : Pat<(atomic_store_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2220 u16ImmPred:$offset),
2221 (i64 DoubleRegs:$src1)),
2222 (STrid_GP tglobaladdr:$global, u16ImmPred:$offset,
2223 (i64 DoubleRegs:$src1))>, Requires<[NoV4T]>;
2225 // 8 bit atomic store
2226 def : Pat<(atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
2227 (i32 IntRegs:$src1)),
2228 (STb_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2231 def : Pat<(atomic_store_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2232 u16ImmPred:$offset),
2233 (i32 IntRegs:$src1)),
2234 (STrib_GP tglobaladdr:$global, u16ImmPred:$offset,
2235 (i32 IntRegs:$src1))>, Requires<[NoV4T]>;
2237 def : Pat<(atomic_store_8 ADDRriS11_0:$src2, (i32 IntRegs:$src1)),
2238 (STrib ADDRriS11_0:$src2, (i32 IntRegs:$src1))>;
2240 def : Pat<(atomic_store_8 (add (i32 IntRegs:$src2), s11_0ImmPred:$offset),
2241 (i32 IntRegs:$src1)),
2242 (STrib_indexed (i32 IntRegs:$src2), s11_0ImmPred:$offset,
2243 (i32 IntRegs:$src1))>;
2246 // 16 bit atomic store
2247 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
2248 (i32 IntRegs:$src1)),
2249 (STh_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2252 def : Pat<(atomic_store_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2253 u16ImmPred:$offset),
2254 (i32 IntRegs:$src1)),
2255 (STrih_GP tglobaladdr:$global, u16ImmPred:$offset,
2256 (i32 IntRegs:$src1))>, Requires<[NoV4T]>;
2258 def : Pat<(atomic_store_16 ADDRriS11_1:$src2, (i32 IntRegs:$src1)),
2259 (STrih ADDRriS11_1:$src2, (i32 IntRegs:$src1))>;
2261 def : Pat<(atomic_store_16 (i32 IntRegs:$src1),
2262 (add (i32 IntRegs:$src2), s11_1ImmPred:$offset)),
2263 (STrih_indexed (i32 IntRegs:$src2), s11_1ImmPred:$offset,
2264 (i32 IntRegs:$src1))>;
2267 // 32 bit atomic store
2268 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
2269 (i32 IntRegs:$src1)),
2270 (STw_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2273 def : Pat<(atomic_store_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2274 u16ImmPred:$offset),
2275 (i32 IntRegs:$src1)),
2276 (STriw_GP tglobaladdr:$global, u16ImmPred:$offset,
2277 (i32 IntRegs:$src1))>,
2280 def : Pat<(atomic_store_32 ADDRriS11_2:$src2, (i32 IntRegs:$src1)),
2281 (STriw ADDRriS11_2:$src2, (i32 IntRegs:$src1))>;
2283 def : Pat<(atomic_store_32 (add (i32 IntRegs:$src2), s11_2ImmPred:$offset),
2284 (i32 IntRegs:$src1)),
2285 (STriw_indexed (i32 IntRegs:$src2), s11_2ImmPred:$offset,
2286 (i32 IntRegs:$src1))>;
2291 def : Pat<(atomic_store_64 ADDRriS11_3:$src2, (i64 DoubleRegs:$src1)),
2292 (STrid ADDRriS11_3:$src2, (i64 DoubleRegs:$src1))>;
2294 def : Pat<(atomic_store_64 (add (i32 IntRegs:$src2), s11_3ImmPred:$offset),
2295 (i64 DoubleRegs:$src1)),
2296 (STrid_indexed (i32 IntRegs:$src2), s11_3ImmPred:$offset,
2297 (i64 DoubleRegs:$src1))>;
2299 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
2300 def : Pat <(and (i32 IntRegs:$src1), 65535),
2301 (ZXTH (i32 IntRegs:$src1))>;
2303 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
2304 def : Pat <(and (i32 IntRegs:$src1), 255),
2305 (ZXTB (i32 IntRegs:$src1))>;
2307 // Map Add(p1, true) to p1 = not(p1).
2308 // Add(p1, false) should never be produced,
2309 // if it does, it got to be mapped to NOOP.
2310 def : Pat <(add (i1 PredRegs:$src1), -1),
2311 (NOT_p (i1 PredRegs:$src1))>;
2313 // Map from p0 = setlt(r0, r1) r2 = mux(p0, r3, r4) =>
2314 // p0 = cmp.lt(r0, r1), r0 = mux(p0, r2, r1).
2315 def : Pat <(select (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2316 (i32 IntRegs:$src3),
2317 (i32 IntRegs:$src4)),
2318 (i32 (TFR_condset_rr (CMPLTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2319 (i32 IntRegs:$src4), (i32 IntRegs:$src3)))>,
2320 Requires<[HasV2TOnly]>;
2322 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
2323 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
2324 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
2327 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
2328 // => r0 = TFR_condset_ri(p0, r1, #i)
2329 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
2330 (i32 IntRegs:$src3)),
2331 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
2332 s12ImmPred:$src2))>;
2334 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
2335 // => r0 = TFR_condset_ir(p0, #i, r1)
2336 def : Pat <(select (not PredRegs:$src1), IntRegs:$src2, s12ImmPred:$src3),
2337 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
2338 (i32 IntRegs:$src2)))>;
2340 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
2341 def : Pat <(brcond (not PredRegs:$src1), bb:$offset),
2342 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
2344 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
2345 def : Pat <(and PredRegs:$src1, (not PredRegs:$src2)),
2346 (i1 (AND_pnotp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2348 // Map from store(globaladdress + x) -> memd(#foo + x).
2349 let AddedComplexity = 100 in
2350 def : Pat <(store (i64 DoubleRegs:$src1),
2351 (add (HexagonCONST32_GP tglobaladdr:$global),
2352 u16ImmPred:$offset)),
2353 (STrid_GP tglobaladdr:$global, u16ImmPred:$offset,
2354 (i64 DoubleRegs:$src1))>, Requires<[NoV4T]>;
2356 // Map from store(globaladdress) -> memd(#foo).
2357 let AddedComplexity = 100 in
2358 def : Pat <(store (i64 DoubleRegs:$src1),
2359 (HexagonCONST32_GP tglobaladdr:$global)),
2360 (STd_GP tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2363 // Map from store(globaladdress + x) -> memw(#foo + x).
2364 let AddedComplexity = 100 in
2365 def : Pat <(store (i32 IntRegs:$src1),
2366 (add (HexagonCONST32_GP tglobaladdr:$global),
2367 u16ImmPred:$offset)),
2368 (STriw_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2371 // Map from store(globaladdress) -> memw(#foo + 0).
2372 let AddedComplexity = 100 in
2373 def : Pat <(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2374 (STriw_GP tglobaladdr:$global, 0, (i32 IntRegs:$src1))>;
2376 // Map from store(globaladdress) -> memw(#foo).
2377 let AddedComplexity = 100 in
2378 def : Pat <(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2379 (STriw_GP tglobaladdr:$global, 0, (i32 IntRegs:$src1))>,
2382 // Map from store(globaladdress + x) -> memh(#foo + x).
2383 let AddedComplexity = 100 in
2384 def : Pat <(truncstorei16 (i32 IntRegs:$src1),
2385 (add (HexagonCONST32_GP tglobaladdr:$global),
2386 u16ImmPred:$offset)),
2387 (STrih_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2390 // Map from store(globaladdress) -> memh(#foo).
2391 let AddedComplexity = 100 in
2392 def : Pat <(truncstorei16 (i32 IntRegs:$src1),
2393 (HexagonCONST32_GP tglobaladdr:$global)),
2394 (STh_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2397 // Map from store(globaladdress + x) -> memb(#foo + x).
2398 let AddedComplexity = 100 in
2399 def : Pat <(truncstorei8 (i32 IntRegs:$src1),
2400 (add (HexagonCONST32_GP tglobaladdr:$global),
2401 u16ImmPred:$offset)),
2402 (STrib_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2405 // Map from store(globaladdress) -> memb(#foo).
2406 let AddedComplexity = 100 in
2407 def : Pat <(truncstorei8 (i32 IntRegs:$src1),
2408 (HexagonCONST32_GP tglobaladdr:$global)),
2409 (STb_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2412 // Map from load(globaladdress + x) -> memw(#foo + x).
2413 let AddedComplexity = 100 in
2414 def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global),
2415 u16ImmPred:$offset))),
2416 (i32 (LDriw_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2419 // Map from load(globaladdress) -> memw(#foo).
2420 let AddedComplexity = 100 in
2421 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
2422 (i32 (LDw_GP tglobaladdr:$global))>,
2425 // Map from load(globaladdress + x) -> memd(#foo + x).
2426 let AddedComplexity = 100 in
2427 def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),
2428 u16ImmPred:$offset))),
2429 (i64 (LDrid_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2432 // Map from load(globaladdress) -> memw(#foo + 0).
2433 let AddedComplexity = 100 in
2434 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
2435 (i64 (LDd_GP tglobaladdr:$global))>,
2438 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd.
2439 let AddedComplexity = 100 in
2440 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
2441 (i1 (TFR_PdRs (i32 (LDb_GP tglobaladdr:$global))))>,
2444 // Map from load(globaladdress + x) -> memh(#foo + x).
2445 let AddedComplexity = 100 in
2446 def : Pat <(i32 (extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2447 u16ImmPred:$offset))),
2448 (i32 (LDrih_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2451 // Map from load(globaladdress + x) -> memh(#foo + x).
2452 let AddedComplexity = 100 in
2453 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2454 (i32 (LDrih_GP tglobaladdr:$global, 0))>,
2457 // Map from load(globaladdress + x) -> memuh(#foo + x).
2458 let AddedComplexity = 100 in
2459 def : Pat <(i32 (zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2460 u16ImmPred:$offset))),
2461 (i32 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2464 // Map from load(globaladdress) -> memuh(#foo).
2465 let AddedComplexity = 100 in
2466 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2467 (i32 (LDriuh_GP tglobaladdr:$global, 0))>,
2470 // Map from load(globaladdress) -> memh(#foo).
2471 let AddedComplexity = 100 in
2472 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2473 (i32 (LDh_GP tglobaladdr:$global))>,
2476 // Map from load(globaladdress) -> memuh(#foo).
2477 let AddedComplexity = 100 in
2478 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2479 (i32 (LDuh_GP tglobaladdr:$global))>,
2482 // Map from load(globaladdress + x) -> memb(#foo + x).
2483 let AddedComplexity = 100 in
2484 def : Pat <(i32 (extloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2485 u16ImmPred:$offset))),
2486 (i32 (LDrib_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2489 // Map from load(globaladdress + x) -> memb(#foo + x).
2490 let AddedComplexity = 100 in
2491 def : Pat <(i32 (sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2492 u16ImmPred:$offset))),
2493 (i32 (LDrib_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2496 // Map from load(globaladdress + x) -> memub(#foo + x).
2497 let AddedComplexity = 100 in
2498 def : Pat <(i32 (zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2499 u16ImmPred:$offset))),
2500 (i32 (LDriub_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2503 // Map from load(globaladdress) -> memb(#foo).
2504 let AddedComplexity = 100 in
2505 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2506 (i32 (LDb_GP tglobaladdr:$global))>,
2509 // Map from load(globaladdress) -> memb(#foo).
2510 let AddedComplexity = 100 in
2511 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2512 (i32 (LDb_GP tglobaladdr:$global))>,
2515 // Map from load(globaladdress) -> memub(#foo).
2516 let AddedComplexity = 100 in
2517 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2518 (i32 (LDub_GP tglobaladdr:$global))>,
2521 // When the Interprocedural Global Variable optimizer realizes that a
2522 // certain global variable takes only two constant values, it shrinks the
2523 // global to a boolean. Catch those loads here in the following 3 patterns.
2524 let AddedComplexity = 100 in
2525 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2526 (i32 (LDb_GP tglobaladdr:$global))>,
2529 let AddedComplexity = 100 in
2530 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2531 (i32 (LDb_GP tglobaladdr:$global))>,
2534 let AddedComplexity = 100 in
2535 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2536 (i32 (LDub_GP tglobaladdr:$global))>,
2539 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
2540 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
2541 (i32 (AND_rr (i32 (LDrib ADDRriS11_0:$addr)), (TFRI 0x1)))>;
2543 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
2544 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
2545 (i64 (SXTW (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
2547 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
2548 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
2549 (i64 (SXTW (i32 (SXTH (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2550 subreg_loreg))))))>;
2552 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
2553 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
2554 (i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2555 subreg_loreg))))))>;
2557 // We want to prevent emitting pnot's as much as possible.
2558 // Map brcond with an unsupported setcc to a JMP_cNot.
2559 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2561 (JMP_cNot (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2564 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
2566 (JMP_cNot (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
2568 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
2569 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
2571 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
2572 (JMP_c (i1 PredRegs:$src1), bb:$offset)>;
2574 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
2576 (JMP_cNot (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2), bb:$offset)>;
2578 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2580 (JMP_c (CMPLTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)), bb:$offset)>;
2582 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2584 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
2587 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2589 (JMP_cNot (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2592 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2594 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2597 // Map from a 64-bit select to an emulated 64-bit mux.
2598 // Hexagon does not support 64-bit MUXes; so emulate with combines.
2599 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
2600 (i64 DoubleRegs:$src3)),
2601 (i64 (COMBINE_rr (i32 (MUX_rr (i1 PredRegs:$src1),
2602 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2604 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2606 (i32 (MUX_rr (i1 PredRegs:$src1),
2607 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2609 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2610 subreg_loreg))))))>;
2612 // Map from a 1-bit select to logical ops.
2613 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
2614 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
2615 (i1 PredRegs:$src3)),
2616 (OR_pp (AND_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
2617 (AND_pp (NOT_p (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
2619 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
2620 def : Pat<(i1 (load ADDRriS11_2:$addr)),
2621 (i1 (TFR_PdRs (i32 (LDrib ADDRriS11_2:$addr))))>;
2623 // Map for truncating from 64 immediates to 32 bit immediates.
2624 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
2625 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
2627 // Map for truncating from i64 immediates to i1 bit immediates.
2628 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
2629 (i1 (TFR_PdRs (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2632 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
2633 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2634 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2637 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
2638 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2639 (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2641 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
2642 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2643 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2646 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
2647 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2648 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2651 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
2652 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2653 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2655 let AddedComplexity = 100 in
2656 // Map from i1 = constant<-1>; memw(CONST32(#foo)) = i1 -> r0 = 1;
2658 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
2659 (STb_GP tglobaladdr:$global, (TFRI 1))>,
2662 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
2663 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2664 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2666 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
2667 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
2668 (STrib ADDRriS11_2:$addr, (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0)) )>;
2670 // Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs).
2671 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
2672 // Better way to do this?
2673 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
2674 (i64 (SXTW (i32 IntRegs:$src1)))>;
2676 // Map cmple -> cmpgt.
2677 // rs <= rt -> !(rs > rt).
2678 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ImmPred:$src2)),
2679 (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), s10ImmPred:$src2)))>;
2681 // rs <= rt -> !(rs > rt).
2682 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2683 (i1 (NOT_p (CMPGTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2685 // Rss <= Rtt -> !(Rss > Rtt).
2686 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2687 (i1 (NOT_p (CMPGT64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2689 // Map cmpne -> cmpeq.
2690 // Hexagon_TODO: We should improve on this.
2691 // rs != rt -> !(rs == rt).
2692 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
2693 (i1 (NOT_p(i1 (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2))))>;
2695 // Map cmpne(Rs) -> !cmpeqe(Rs).
2696 // rs != rt -> !(rs == rt).
2697 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2698 (i1 (NOT_p (i1 (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
2700 // Convert setne back to xor for hexagon since we compute w/ pred registers.
2701 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
2702 (i1 (XOR_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2704 // Map cmpne(Rss) -> !cmpew(Rss).
2705 // rs != rt -> !(rs == rt).
2706 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2707 (i1 (NOT_p (i1 (CMPEHexagon4rr (i64 DoubleRegs:$src1),
2708 (i64 DoubleRegs:$src2)))))>;
2710 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
2711 // rs >= rt -> !(rt > rs).
2712 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2713 (i1 (NOT_p (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
2715 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ImmPred:$src2)),
2716 (i1 (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2))>;
2718 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
2719 // rss >= rtt -> !(rtt > rss).
2720 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2721 (i1 (NOT_p (i1 (CMPGT64rr (i64 DoubleRegs:$src2),
2722 (i64 DoubleRegs:$src1)))))>;
2724 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
2725 // rs < rt -> !(rs >= rt).
2726 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
2727 (i1 (NOT_p (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2)))>;
2729 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
2730 // rs < rt -> rt > rs.
2731 // We can let assembler map it, or we can do in the compiler itself.
2732 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2733 (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2735 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
2736 // rss < rtt -> (rtt > rss).
2737 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2738 (i1 (CMPGT64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2740 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
2741 // rs < rt -> rt > rs.
2742 // We can let assembler map it, or we can do in the compiler itself.
2743 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2744 (i1 (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2746 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
2747 // rs < rt -> rt > rs.
2748 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2749 (i1 (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2751 // Generate cmpgeu(Rs, #u8)
2752 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ImmPred:$src2)),
2753 (i1 (CMPGEUri (i32 IntRegs:$src1), u8ImmPred:$src2))>;
2755 // Generate cmpgtu(Rs, #u9)
2756 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ImmPred:$src2)),
2757 (i1 (CMPGTUri (i32 IntRegs:$src1), u9ImmPred:$src2))>;
2759 // Map from Rs >= Rt -> !(Rt > Rs).
2760 // rs >= rt -> !(rt > rs).
2761 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2762 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
2764 // Map from Rs >= Rt -> !(Rt > Rs).
2765 // rs >= rt -> !(rt > rs).
2766 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2767 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
2769 // Map from cmpleu(Rs, Rs) -> !cmpgtu(Rs, Rs).
2770 // Map from (Rs <= Rt) -> !(Rs > Rt).
2771 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2772 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2774 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
2775 // Map from (Rs <= Rt) -> !(Rs > Rt).
2776 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2777 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2781 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
2782 (i32 (MUX_ii (i1 PredRegs:$src1), -1, 0))>;
2785 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
2786 (i64 (COMBINE_rr (TFRI -1), (MUX_ii (i1 PredRegs:$src1), -1, 0)))>;
2788 // Convert sign-extended load back to load and sign extend.
2790 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
2791 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2793 // Convert any-extended load back to load and sign extend.
2795 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
2796 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2798 // Convert sign-extended load back to load and sign extend.
2800 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
2801 (i64 (SXTW (LDrih ADDRriS11_1:$src1)))>;
2803 // Convert sign-extended load back to load and sign extend.
2805 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
2806 (i64 (SXTW (LDriw ADDRriS11_2:$src1)))>;
2811 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2812 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2815 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
2816 (i64 (COMBINE_rr (TFRI 0), (MUX_ii (i1 PredRegs:$src1), 1, 0)))>;
2819 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
2820 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>;
2823 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
2824 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>;
2827 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
2828 (i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>;
2831 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
2832 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>;
2834 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
2835 (i32 (LDriw ADDRriS11_0:$src1))>;
2837 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2838 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2839 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2841 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2842 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
2843 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2845 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
2846 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
2847 (i64 (SXTW (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))))>;
2850 // Any extended 64-bit load.
2851 // anyext i32 -> i64
2852 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
2853 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>;
2855 // anyext i16 -> i64.
2856 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
2857 (i64 (COMBINE_rr (TFRI 0), (LDrih ADDRriS11_2:$src1)))>;
2859 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
2860 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
2861 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>;
2863 // Multiply 64-bit unsigned and use upper result.
2864 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2879 (COMBINE_rr (TFRI 0),
2885 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2887 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2888 subreg_loreg)))), 32)),
2890 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2891 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2892 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2893 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2894 32)), subreg_loreg)))),
2895 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2896 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2898 // Multiply 64-bit signed and use upper result.
2899 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2903 (COMBINE_rr (TFRI 0),
2913 (COMBINE_rr (TFRI 0),
2919 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2921 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2922 subreg_loreg)))), 32)),
2924 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2925 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2926 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2927 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2928 32)), subreg_loreg)))),
2929 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2930 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2932 // Hexagon specific ISD nodes.
2933 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
2934 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
2935 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
2936 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
2937 SDTHexagonADJDYNALLOC>;
2938 // Needed to tag these instructions for stack layout.
2939 let usesCustomInserter = 1 in
2940 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
2942 "$dst = add($src1, #$src2)",
2943 [(set (i32 IntRegs:$dst),
2944 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
2945 s16ImmPred:$src2))]>;
2947 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
2948 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
2949 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
2951 [(set (i32 IntRegs:$dst),
2952 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
2954 let AddedComplexity = 100 in
2955 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
2956 (COPY (i32 IntRegs:$src1))>;
2958 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2959 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
2961 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
2962 def BR_JT : JRInst<(outs), (ins IntRegs:$src),
2964 [(HexagonBR_JT (i32 IntRegs:$src))]>;
2966 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
2968 def : Pat<(HexagonWrapperJT tjumptable:$dst),
2969 (i32 (CONST32_set_jt tjumptable:$dst))>;
2973 // Multi-class for logical operators :
2974 // Shift by immediate/register and accumulate/logical
2975 multiclass xtype_imm<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
2976 def _ri : SInst_acc<(outs IntRegs:$dst),
2977 (ins IntRegs:$src1, IntRegs:$src2, u5Imm:$src3),
2978 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
2979 [(set (i32 IntRegs:$dst),
2980 (OpNode2 (i32 IntRegs:$src1),
2981 (OpNode1 (i32 IntRegs:$src2),
2982 u5ImmPred:$src3)))],
2985 def d_ri : SInst_acc<(outs DoubleRegs:$dst),
2986 (ins DoubleRegs:$src1, DoubleRegs:$src2, u6Imm:$src3),
2987 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
2988 [(set (i64 DoubleRegs:$dst), (OpNode2 (i64 DoubleRegs:$src1),
2989 (OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
2993 // Multi-class for logical operators :
2994 // Shift by register and accumulate/logical (32/64 bits)
2995 multiclass xtype_reg<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
2996 def _rr : SInst_acc<(outs IntRegs:$dst),
2997 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2998 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
2999 [(set (i32 IntRegs:$dst),
3000 (OpNode2 (i32 IntRegs:$src1),
3001 (OpNode1 (i32 IntRegs:$src2),
3002 (i32 IntRegs:$src3))))],
3005 def d_rr : SInst_acc<(outs DoubleRegs:$dst),
3006 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3007 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
3008 [(set (i64 DoubleRegs:$dst),
3009 (OpNode2 (i64 DoubleRegs:$src1),
3010 (OpNode1 (i64 DoubleRegs:$src2),
3011 (i32 IntRegs:$src3))))],
3016 multiclass basic_xtype_imm<string OpcStr, SDNode OpNode> {
3017 let AddedComplexity = 100 in
3018 defm _ADD : xtype_imm< !strconcat("+= ", OpcStr), OpNode, add>;
3019 defm _SUB : xtype_imm< !strconcat("-= ", OpcStr), OpNode, sub>;
3020 defm _AND : xtype_imm< !strconcat("&= ", OpcStr), OpNode, and>;
3021 defm _OR : xtype_imm< !strconcat("|= ", OpcStr), OpNode, or>;
3024 multiclass basic_xtype_reg<string OpcStr, SDNode OpNode> {
3025 let AddedComplexity = 100 in
3026 defm _ADD : xtype_reg< !strconcat("+= ", OpcStr), OpNode, add>;
3027 defm _SUB : xtype_reg< !strconcat("-= ", OpcStr), OpNode, sub>;
3028 defm _AND : xtype_reg< !strconcat("&= ", OpcStr), OpNode, and>;
3029 defm _OR : xtype_reg< !strconcat("|= ", OpcStr), OpNode, or>;
3032 multiclass xtype_xor_imm<string OpcStr, SDNode OpNode> {
3033 let AddedComplexity = 100 in
3034 defm _XOR : xtype_imm< !strconcat("^= ", OpcStr), OpNode, xor>;
3037 defm ASL : basic_xtype_imm<"asl", shl>, basic_xtype_reg<"asl", shl>,
3038 xtype_xor_imm<"asl", shl>;
3040 defm LSR : basic_xtype_imm<"lsr", srl>, basic_xtype_reg<"lsr", srl>,
3041 xtype_xor_imm<"lsr", srl>;
3043 defm ASR : basic_xtype_imm<"asr", sra>, basic_xtype_reg<"asr", sra>;
3044 defm LSL : basic_xtype_reg<"lsl", shl>;
3046 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
3047 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
3048 (i32 (MPYI_rin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
3050 //===----------------------------------------------------------------------===//
3051 // V3 Instructions +
3052 //===----------------------------------------------------------------------===//
3054 include "HexagonInstrInfoV3.td"
3056 //===----------------------------------------------------------------------===//
3057 // V3 Instructions -
3058 //===----------------------------------------------------------------------===//
3060 //===----------------------------------------------------------------------===//
3061 // V4 Instructions +
3062 //===----------------------------------------------------------------------===//
3064 include "HexagonInstrInfoV4.td"
3066 //===----------------------------------------------------------------------===//
3067 // V4 Instructions -
3068 //===----------------------------------------------------------------------===//
3070 //===----------------------------------------------------------------------===//
3071 // V5 Instructions +
3072 //===----------------------------------------------------------------------===//
3074 include "HexagonInstrInfoV5.td"
3076 //===----------------------------------------------------------------------===//
3077 // V5 Instructions -
3078 //===----------------------------------------------------------------------===//