1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
17 // Pattern fragment that combines the value type and the register class
18 // into a single parameter.
19 // The pat frags in the definitions below need to have a named register,
20 // otherwise i32 will be assumed regardless of the register class. The
21 // name of the register does not matter.
22 def I1 : PatLeaf<(i1 PredRegs:$R)>;
23 def I32 : PatLeaf<(i32 IntRegs:$R)>;
24 def I64 : PatLeaf<(i64 DoubleRegs:$R)>;
25 def F32 : PatLeaf<(f32 IntRegs:$R)>;
26 def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
28 // Pattern fragments to extract the low and high subregisters from a
30 def LoReg: OutPatFrag<(ops node:$Rs),
31 (EXTRACT_SUBREG (i64 $Rs), subreg_loreg)>;
32 def HiReg: OutPatFrag<(ops node:$Rs),
33 (EXTRACT_SUBREG (i64 $Rs), subreg_hireg)>;
35 // SDNode for converting immediate C to C-1.
36 def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
37 // Return the byte immediate const-1 as an SDNode.
38 int32_t imm = N->getSExtValue();
39 return XformSToSM1Imm(imm);
42 // SDNode for converting immediate C to C-2.
43 def DEC2_CONST_SIGNED : SDNodeXForm<imm, [{
44 // Return the byte immediate const-2 as an SDNode.
45 int32_t imm = N->getSExtValue();
46 return XformSToSM2Imm(imm);
49 // SDNode for converting immediate C to C-3.
50 def DEC3_CONST_SIGNED : SDNodeXForm<imm, [{
51 // Return the byte immediate const-3 as an SDNode.
52 int32_t imm = N->getSExtValue();
53 return XformSToSM3Imm(imm);
56 // SDNode for converting immediate C to C-1.
57 def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
58 // Return the byte immediate const-1 as an SDNode.
59 uint32_t imm = N->getZExtValue();
60 return XformUToUM1Imm(imm);
63 //===----------------------------------------------------------------------===//
65 //===----------------------------------------------------------------------===//
67 //===----------------------------------------------------------------------===//
68 let hasSideEffects = 0, isCompare = 1, InputType = "imm", isExtendable = 1,
70 class T_CMP <string mnemonic, bits<2> MajOp, bit isNot, Operand ImmOp>
71 : ALU32Inst <(outs PredRegs:$dst),
72 (ins IntRegs:$src1, ImmOp:$src2),
73 "$dst = "#!if(isNot, "!","")#mnemonic#"($src1, #$src2)",
74 [], "",ALU32_2op_tc_2early_SLOT0123 >, ImmRegRel {
78 let CextOpcode = mnemonic;
79 let opExtentBits = !if(!eq(mnemonic, "cmp.gtu"), 9, 10);
80 let isExtentSigned = !if(!eq(mnemonic, "cmp.gtu"), 0, 1);
84 let Inst{27-24} = 0b0101;
85 let Inst{23-22} = MajOp;
86 let Inst{21} = !if(!eq(mnemonic, "cmp.gtu"), 0, src2{9});
87 let Inst{20-16} = src1;
88 let Inst{13-5} = src2{8-0};
94 def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10Ext>;
95 def C2_cmpgti : T_CMP <"cmp.gt", 0b01, 0, s10Ext>;
96 def C2_cmpgtui : T_CMP <"cmp.gtu", 0b10, 0, u9Ext>;
98 class T_CMP_pat <InstHexagon MI, PatFrag OpNode, PatLeaf ImmPred>
99 : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)),
100 (MI IntRegs:$src1, ImmPred:$src2)>;
102 def : T_CMP_pat <C2_cmpeqi, seteq, s10ImmPred>;
103 def : T_CMP_pat <C2_cmpgti, setgt, s10ImmPred>;
104 def : T_CMP_pat <C2_cmpgtui, setugt, u9ImmPred>;
106 //===----------------------------------------------------------------------===//
108 //===----------------------------------------------------------------------===//
109 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
110 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
112 def HexagonCOMBINE : SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>;
114 let hasSideEffects = 0, hasNewValue = 1, InputType = "reg" in
115 class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev,
117 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
118 "$Rd = "#mnemonic#"($Rs, $Rt)",
119 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredRel {
120 let isCommutable = IsComm;
121 let BaseOpcode = mnemonic#_rr;
122 let CextOpcode = mnemonic;
130 let Inst{26-24} = MajOp;
131 let Inst{23-21} = MinOp;
132 let Inst{20-16} = !if(OpsRev,Rt,Rs);
133 let Inst{12-8} = !if(OpsRev,Rs,Rt);
137 let hasSideEffects = 0, hasNewValue = 1 in
138 class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp,
139 bit OpsRev, bit PredNot, bit PredNew>
140 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
141 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") "#
142 "$Rd = "#mnemonic#"($Rs, $Rt)",
143 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
144 let isPredicated = 1;
145 let isPredicatedFalse = PredNot;
146 let isPredicatedNew = PredNew;
147 let BaseOpcode = mnemonic#_rr;
148 let CextOpcode = mnemonic;
157 let Inst{26-24} = MajOp;
158 let Inst{23-21} = MinOp;
159 let Inst{20-16} = !if(OpsRev,Rt,Rs);
160 let Inst{13} = PredNew;
161 let Inst{12-8} = !if(OpsRev,Rs,Rt);
162 let Inst{7} = PredNot;
167 class T_ALU32_combineh<string Op1, string Op2, bits<3> MajOp, bits<3> MinOp,
169 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, 0> {
170 let AsmString = "$Rd = combine($Rs"#Op1#", $Rt"#Op2#")";
173 let isCodeGenOnly = 0 in {
174 def A2_combine_hh : T_ALU32_combineh<".h", ".h", 0b011, 0b100, 1>;
175 def A2_combine_hl : T_ALU32_combineh<".h", ".l", 0b011, 0b101, 1>;
176 def A2_combine_lh : T_ALU32_combineh<".l", ".h", 0b011, 0b110, 1>;
177 def A2_combine_ll : T_ALU32_combineh<".l", ".l", 0b011, 0b111, 1>;
180 class T_ALU32_3op_sfx<string mnemonic, string suffix, bits<3> MajOp,
181 bits<3> MinOp, bit OpsRev, bit IsComm>
182 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, IsComm> {
183 let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix;
186 let Defs = [USR_OVF], Itinerary = ALU32_3op_tc_2_SLOT0123,
187 isCodeGenOnly = 0 in {
188 def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>;
189 def A2_subsat : T_ALU32_3op_sfx<"sub", ":sat", 0b110, 0b110, 1, 0>;
192 multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,
194 def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>;
195 def f : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 0>;
196 def tnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 1>;
197 def fnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 1>;
200 multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp,
201 bit OpsRev, bit IsComm> {
202 let isPredicable = 1 in
203 def A2_#NAME : T_ALU32_3op <mnemonic, MajOp, MinOp, OpsRev, IsComm>;
204 defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>;
207 let isCodeGenOnly = 0 in {
208 defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
209 defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>;
210 defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>;
211 defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>;
212 defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>;
215 // Pats for instruction selection.
216 class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
217 : Pat<(ResT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
218 (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
220 def: BinOp32_pat<add, A2_add, i32>;
221 def: BinOp32_pat<and, A2_and, i32>;
222 def: BinOp32_pat<or, A2_or, i32>;
223 def: BinOp32_pat<sub, A2_sub, i32>;
224 def: BinOp32_pat<xor, A2_xor, i32>;
226 // A few special cases producing register pairs:
227 let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0,
228 isCodeGenOnly = 0 in {
229 def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>;
231 let isPredicable = 1 in
232 def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>;
234 // Conditional combinew uses "newt/f" instead of "t/fnew".
235 def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>;
236 def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>;
237 def C2_ccombinewnewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 1>;
238 def C2_ccombinewnewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 1>;
241 let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in
242 class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm>
243 : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
244 "$Pd = "#mnemonic#"($Rs, $Rt)",
245 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
246 let CextOpcode = mnemonic;
247 let isCommutable = IsComm;
253 let Inst{27-24} = 0b0010;
254 let Inst{22-21} = MinOp;
255 let Inst{20-16} = Rs;
258 let Inst{3-2} = 0b00;
262 let Itinerary = ALU32_3op_tc_2early_SLOT0123, isCodeGenOnly = 0 in {
263 def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>;
264 def C2_cmpgt : T_ALU32_3op_cmp< "cmp.gt", 0b10, 0, 0>;
265 def C2_cmpgtu : T_ALU32_3op_cmp< "cmp.gtu", 0b11, 0, 0>;
268 // Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones
269 // that reverse the order of the operands.
270 class RevCmp<PatFrag F> : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment>;
272 // Pats for compares. They use PatFrags as operands, not SDNodes,
273 // since seteq/setgt/etc. are defined as ParFrags.
274 class T_cmp32_rr_pat<InstHexagon MI, PatFrag Op, ValueType VT>
275 : Pat<(VT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
276 (VT (MI IntRegs:$Rs, IntRegs:$Rt))>;
278 def: T_cmp32_rr_pat<C2_cmpeq, seteq, i1>;
279 def: T_cmp32_rr_pat<C2_cmpgt, setgt, i1>;
280 def: T_cmp32_rr_pat<C2_cmpgtu, setugt, i1>;
282 def: T_cmp32_rr_pat<C2_cmpgt, RevCmp<setlt>, i1>;
283 def: T_cmp32_rr_pat<C2_cmpgtu, RevCmp<setult>, i1>;
285 let CextOpcode = "MUX", InputType = "reg", hasNewValue = 1,
287 def C2_mux: ALU32_rr<(outs IntRegs:$Rd),
288 (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
289 "$Rd = mux($Pu, $Rs, $Rt)", [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
295 let CextOpcode = "mux";
296 let InputType = "reg";
297 let hasSideEffects = 0;
300 let Inst{27-24} = 0b0100;
301 let Inst{20-16} = Rs;
307 def: Pat<(i32 (select (i1 PredRegs:$Pu), (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
308 (C2_mux PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt)>;
310 // Combines the two immediates into a double register.
311 // Increase complexity to make it greater than any complexity of a combine
312 // that involves a register.
314 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
315 isExtentSigned = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 1,
316 AddedComplexity = 75, isCodeGenOnly = 0 in
317 def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8),
318 "$Rdd = combine(#$s8, #$S8)",
319 [(set (i64 DoubleRegs:$Rdd),
320 (i64 (HexagonCOMBINE(i32 s8ExtPred:$s8), (i32 s8ImmPred:$S8))))]> {
326 let Inst{27-23} = 0b11000;
327 let Inst{22-16} = S8{7-1};
328 let Inst{13} = S8{0};
333 //===----------------------------------------------------------------------===//
334 // Template class for predicated ADD of a reg and an Immediate value.
335 //===----------------------------------------------------------------------===//
336 let hasNewValue = 1 in
337 class T_Addri_Pred <bit PredNot, bit PredNew>
338 : ALU32_ri <(outs IntRegs:$Rd),
339 (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
340 !if(PredNot, "if (!$Pu", "if ($Pu")#!if(PredNew,".new) $Rd = ",
341 ") $Rd = ")#"add($Rs, #$s8)"> {
347 let isPredicatedNew = PredNew;
350 let Inst{27-24} = 0b0100;
351 let Inst{23} = PredNot;
352 let Inst{22-21} = Pu;
353 let Inst{20-16} = Rs;
354 let Inst{13} = PredNew;
359 //===----------------------------------------------------------------------===//
360 // A2_addi: Add a signed immediate to a register.
361 //===----------------------------------------------------------------------===//
362 let hasNewValue = 1 in
363 class T_Addri <Operand immOp, list<dag> pattern = [] >
364 : ALU32_ri <(outs IntRegs:$Rd),
365 (ins IntRegs:$Rs, immOp:$s16),
366 "$Rd = add($Rs, #$s16)", pattern,
367 //[(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs), (s16ExtPred:$s16)))],
368 "", ALU32_ADDI_tc_1_SLOT0123> {
375 let Inst{27-21} = s16{15-9};
376 let Inst{20-16} = Rs;
377 let Inst{13-5} = s16{8-0};
381 //===----------------------------------------------------------------------===//
382 // Multiclass for ADD of a register and an immediate value.
383 //===----------------------------------------------------------------------===//
384 multiclass Addri_Pred<string mnemonic, bit PredNot> {
385 let isPredicatedFalse = PredNot in {
386 def _c#NAME : T_Addri_Pred<PredNot, 0>;
388 def _cdn#NAME : T_Addri_Pred<PredNot, 1>;
392 let isExtendable = 1, InputType = "imm" in
393 multiclass Addri_base<string mnemonic, SDNode OpNode> {
394 let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in {
395 let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
397 def NAME : T_Addri< s16Ext, // Rd=add(Rs,#s16)
398 [(set (i32 IntRegs:$Rd),
399 (add IntRegs:$Rs, s16ExtPred:$s16))]>;
401 let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
402 hasSideEffects = 0, isPredicated = 1 in {
403 defm Pt : Addri_Pred<mnemonic, 0>;
404 defm NotPt : Addri_Pred<mnemonic, 1>;
409 let isCodeGenOnly = 0 in
410 defm ADD_ri : Addri_base<"add", add>, ImmRegRel, PredNewRel;
412 //===----------------------------------------------------------------------===//
413 // Template class used for the following ALU32 instructions.
416 //===----------------------------------------------------------------------===//
417 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
418 InputType = "imm", hasNewValue = 1 in
419 class T_ALU32ri_logical <string mnemonic, SDNode OpNode, bits<2> MinOp>
420 : ALU32_ri <(outs IntRegs:$Rd),
421 (ins IntRegs:$Rs, s10Ext:$s10),
422 "$Rd = "#mnemonic#"($Rs, #$s10)" ,
423 [(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s10ExtPred:$s10))]> {
427 let CextOpcode = mnemonic;
431 let Inst{27-24} = 0b0110;
432 let Inst{23-22} = MinOp;
433 let Inst{21} = s10{9};
434 let Inst{20-16} = Rs;
435 let Inst{13-5} = s10{8-0};
439 let isCodeGenOnly = 0 in {
440 def OR_ri : T_ALU32ri_logical<"or", or, 0b10>, ImmRegRel;
441 def AND_ri : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel;
444 // Subtract register from immediate
445 // Rd32=sub(#s10,Rs32)
446 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
447 CextOpcode = "sub", InputType = "imm", hasNewValue = 1, isCodeGenOnly = 0 in
448 def SUB_ri: ALU32_ri <(outs IntRegs:$Rd), (ins s10Ext:$s10, IntRegs:$Rs),
449 "$Rd = sub(#$s10, $Rs)" ,
450 [(set IntRegs:$Rd, (sub s10ExtPred:$s10, IntRegs:$Rs))] > ,
458 let Inst{27-22} = 0b011001;
459 let Inst{21} = s10{9};
460 let Inst{20-16} = Rs;
461 let Inst{13-5} = s10{8-0};
466 let hasSideEffects = 0, isCodeGenOnly = 0 in
467 def A2_nop: ALU32Inst <(outs), (ins), "nop" > {
469 let Inst{27-24} = 0b1111;
471 // Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
472 def : Pat<(not (i32 IntRegs:$src1)),
473 (SUB_ri -1, (i32 IntRegs:$src1))>;
475 let hasSideEffects = 0, hasNewValue = 1 in
476 class T_tfr16<bit isHi>
477 : ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16Imm:$u16),
478 "$Rx"#!if(isHi, ".h", ".l")#" = #$u16",
479 [], "$src1 = $Rx" > {
484 let Inst{27-26} = 0b00;
485 let Inst{25-24} = !if(isHi, 0b10, 0b01);
486 let Inst{23-22} = u16{15-14};
488 let Inst{20-16} = Rx;
489 let Inst{13-0} = u16{13-0};
492 let isCodeGenOnly = 0 in {
493 def A2_tfril: T_tfr16<0>;
494 def A2_tfrih: T_tfr16<1>;
497 // Conditional transfer is an alias to conditional "Rd = add(Rs, #0)".
498 let isPredicated = 1, hasNewValue = 1, opNewValue = 0 in
499 class T_tfr_pred<bit isPredNot, bit isPredNew>
500 : ALU32Inst<(outs IntRegs:$dst),
501 (ins PredRegs:$src1, IntRegs:$src2),
502 "if ("#!if(isPredNot, "!", "")#
503 "$src1"#!if(isPredNew, ".new", "")#
509 let isPredicatedFalse = isPredNot;
510 let isPredicatedNew = isPredNew;
513 let Inst{27-24} = 0b0100;
514 let Inst{23} = isPredNot;
515 let Inst{13} = isPredNew;
518 let Inst{22-21} = src1;
519 let Inst{20-16} = src2;
522 let isPredicable = 1 in
523 class T_tfr : ALU32Inst<(outs IntRegs:$dst), (ins IntRegs:$src),
530 let Inst{27-21} = 0b0000011;
531 let Inst{20-16} = src;
536 let InputType = "reg", hasNewValue = 1, hasSideEffects = 0 in
537 multiclass tfr_base<string CextOp> {
538 let CextOpcode = CextOp, BaseOpcode = CextOp in {
542 def t : T_tfr_pred<0, 0>;
543 def f : T_tfr_pred<1, 0>;
545 def tnew : T_tfr_pred<0, 1>;
546 def fnew : T_tfr_pred<1, 1>;
550 // Assembler mapped to C2_ccombinew[t|f|newt|newf].
551 // Please don't add bits to this instruction as it'll be converted into
552 // 'combine' before object code emission.
553 let isPredicated = 1 in
554 class T_tfrp_pred<bit PredNot, bit PredNew>
555 : ALU32_rr <(outs DoubleRegs:$dst),
556 (ins PredRegs:$src1, DoubleRegs:$src2),
557 "if ("#!if(PredNot, "!", "")#"$src1"
558 #!if(PredNew, ".new", "")#") $dst = $src2" > {
559 let isPredicatedFalse = PredNot;
560 let isPredicatedNew = PredNew;
563 // Assembler mapped to A2_combinew.
564 // Please don't add bits to this instruction as it'll be converted into
565 // 'combine' before object code emission.
566 class T_tfrp : ALU32Inst <(outs DoubleRegs:$dst),
567 (ins DoubleRegs:$src),
570 let hasSideEffects = 0 in
571 multiclass TFR64_base<string BaseName> {
572 let BaseOpcode = BaseName in {
573 let isPredicable = 1 in
576 def t : T_tfrp_pred <0, 0>;
577 def f : T_tfrp_pred <1, 0>;
579 def tnew : T_tfrp_pred <0, 1>;
580 def fnew : T_tfrp_pred <1, 1>;
584 let InputType = "imm", isExtendable = 1, isExtentSigned = 1, opExtentBits = 12,
585 isMoveImm = 1, opExtendable = 2, BaseOpcode = "TFRI", CextOpcode = "TFR",
586 hasSideEffects = 0, isPredicated = 1, hasNewValue = 1 in
587 class T_TFRI_Pred<bit PredNot, bit PredNew>
588 : ALU32_ri<(outs IntRegs:$Rd), (ins PredRegs:$Pu, s12Ext:$s12),
589 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") $Rd = #$s12",
590 [], "", ALU32_2op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
591 let isPredicatedFalse = PredNot;
592 let isPredicatedNew = PredNew;
599 let Inst{27-24} = 0b1110;
600 let Inst{23} = PredNot;
601 let Inst{22-21} = Pu;
603 let Inst{19-16,12-5} = s12;
604 let Inst{13} = PredNew;
608 let isCodeGenOnly = 0 in {
609 def C2_cmoveit : T_TFRI_Pred<0, 0>;
610 def C2_cmoveif : T_TFRI_Pred<1, 0>;
611 def C2_cmovenewit : T_TFRI_Pred<0, 1>;
612 def C2_cmovenewif : T_TFRI_Pred<1, 1>;
615 let InputType = "imm", isExtendable = 1, isExtentSigned = 1,
616 CextOpcode = "TFR", BaseOpcode = "TFRI", hasNewValue = 1, opNewValue = 0,
617 isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16, isMoveImm = 1,
618 isPredicated = 0, isPredicable = 1, isReMaterializable = 1,
620 def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16Ext:$s16), "$Rd = #$s16",
621 [(set (i32 IntRegs:$Rd), s16ExtPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>,
627 let Inst{27-24} = 0b1000;
628 let Inst{23-22,20-16,13-5} = s16;
632 let isCodeGenOnly = 0 in
633 defm A2_tfr : tfr_base<"TFR">, ImmRegRel, PredNewRel;
634 defm A2_tfrp : TFR64_base<"TFR64">, PredNewRel;
637 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1 in
638 def A2_tfrpi : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
640 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
642 // TODO: see if this instruction can be deleted..
643 let isExtendable = 1, opExtendable = 1, opExtentBits = 6 in
644 def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u6Ext:$src1),
647 //===----------------------------------------------------------------------===//
649 //===----------------------------------------------------------------------===//
652 //===----------------------------------------------------------------------===//
654 //===----------------------------------------------------------------------===//
655 // Scalar mux register immediate.
656 let hasSideEffects = 0, isExtentSigned = 1, CextOpcode = "MUX",
657 InputType = "imm", hasNewValue = 1, isExtendable = 1, opExtentBits = 8 in
658 class T_MUX1 <bit MajOp, dag ins, string AsmStr>
659 : ALU32Inst <(outs IntRegs:$Rd), ins, AsmStr>, ImmRegRel {
666 let Inst{27-24} = 0b0011;
667 let Inst{23} = MajOp;
668 let Inst{22-21} = Pu;
669 let Inst{20-16} = Rs;
675 let opExtendable = 2, isCodeGenOnly = 0 in
676 def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8Ext:$s8, IntRegs:$Rs),
677 "$Rd = mux($Pu, #$s8, $Rs)">;
679 let opExtendable = 3, isCodeGenOnly = 0 in
680 def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
681 "$Rd = mux($Pu, $Rs, #$s8)">;
683 def : Pat<(i32 (select I1:$Pu, s8ExtPred:$s8, I32:$Rs)),
684 (C2_muxri I1:$Pu, s8ExtPred:$s8, I32:$Rs)>;
686 def : Pat<(i32 (select I1:$Pu, I32:$Rs, s8ExtPred:$s8)),
687 (C2_muxir I1:$Pu, I32:$Rs, s8ExtPred:$s8)>;
689 // C2_muxii: Scalar mux immediates.
690 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1,
691 opExtentBits = 8, opExtendable = 2, isCodeGenOnly = 0 in
692 def C2_muxii: ALU32Inst <(outs IntRegs:$Rd),
693 (ins PredRegs:$Pu, s8Ext:$s8, s8Imm:$S8),
694 "$Rd = mux($Pu, #$s8, #$S8)" ,
695 [(set (i32 IntRegs:$Rd),
696 (i32 (select I1:$Pu, s8ExtPred:$s8, s8ImmPred:$S8)))] > {
704 let Inst{27-25} = 0b101;
705 let Inst{24-23} = Pu;
706 let Inst{22-16} = S8{7-1};
707 let Inst{13} = S8{0};
712 //===----------------------------------------------------------------------===//
713 // template class for non-predicated alu32_2op instructions
714 // - aslh, asrh, sxtb, sxth, zxth
715 //===----------------------------------------------------------------------===//
716 let hasNewValue = 1, opNewValue = 0 in
717 class T_ALU32_2op <string mnemonic, bits<3> minOp> :
718 ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
719 "$Rd = "#mnemonic#"($Rs)", [] > {
725 let Inst{27-24} = 0b0000;
726 let Inst{23-21} = minOp;
729 let Inst{20-16} = Rs;
732 //===----------------------------------------------------------------------===//
733 // template class for predicated alu32_2op instructions
734 // - aslh, asrh, sxtb, sxth, zxtb, zxth
735 //===----------------------------------------------------------------------===//
736 let hasSideEffects = 0, validSubTargets = HasV4SubT,
737 hasNewValue = 1, opNewValue = 0 in
738 class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot,
740 ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
741 !if(isPredNot, "if (!$Pu", "if ($Pu")
742 #!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> {
749 let Inst{27-24} = 0b0000;
750 let Inst{23-21} = minOp;
752 let Inst{11} = isPredNot;
753 let Inst{10} = isPredNew;
756 let Inst{20-16} = Rs;
759 multiclass ALU32_2op_Pred<string mnemonic, bits<3> minOp, bit PredNot> {
760 let isPredicatedFalse = PredNot in {
761 def NAME : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 0>;
764 let isPredicatedNew = 1 in
765 def NAME#new : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 1>;
769 multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
770 let BaseOpcode = mnemonic in {
771 let isPredicable = 1, hasSideEffects = 0 in
772 def A2_#NAME : T_ALU32_2op<mnemonic, minOp>;
774 let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
775 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
776 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
781 let isCodeGenOnly = 0 in {
782 defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
783 defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel;
784 defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
785 defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
786 defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
789 // Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
790 // Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has
791 // predicated forms while 'and' doesn't. Since integrated assembler can't
792 // handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where
793 // immediate operand is set to '255'.
795 let hasNewValue = 1, opNewValue = 0 in
796 class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
797 "$Rd = zxtb($Rs)", [] > { // Rd = and(Rs,255)
804 let Inst{27-22} = 0b011000;
806 let Inst{20-16} = Rs;
807 let Inst{21} = s10{9};
808 let Inst{13-5} = s10{8-0};
811 //Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255)
812 multiclass ZXTB_base <string mnemonic, bits<3> minOp> {
813 let BaseOpcode = mnemonic in {
814 let isPredicable = 1, hasSideEffects = 0 in
815 def A2_#NAME : T_ZXTB;
817 let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
818 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
819 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
824 let isCodeGenOnly=0 in
825 defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
827 def: Pat<(shl I32:$src1, (i32 16)), (A2_aslh I32:$src1)>;
828 def: Pat<(sra I32:$src1, (i32 16)), (A2_asrh I32:$src1)>;
829 def: Pat<(sext_inreg I32:$src1, i8), (A2_sxtb I32:$src1)>;
830 def: Pat<(sext_inreg I32:$src1, i16), (A2_sxth I32:$src1)>;
832 //===----------------------------------------------------------------------===//
834 //===----------------------------------------------------------------------===//
837 //===----------------------------------------------------------------------===//
839 //===----------------------------------------------------------------------===//
841 //===----------------------------------------------------------------------===//
843 //===----------------------------------------------------------------------===//
846 //===----------------------------------------------------------------------===//
848 //===----------------------------------------------------------------------===//// Add.
849 //===----------------------------------------------------------------------===//
851 // Add/Subtract halfword
852 // Rd=add(Rt.L,Rs.[HL])[:sat]
853 // Rd=sub(Rt.L,Rs.[HL])[:sat]
854 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
855 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
856 //===----------------------------------------------------------------------===//
858 let hasNewValue = 1, opNewValue = 0 in
859 class T_XTYPE_ADD_SUB <bits<2> LHbits, bit isSat, bit hasShift, bit isSub>
860 : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
861 "$Rd = "#!if(isSub,"sub","add")#"($Rt."
862 #!if(hasShift, !if(LHbits{1},"h","l"),"l") #", $Rs."
863 #!if(hasShift, !if(LHbits{0},"h)","l)"), !if(LHbits{1},"h)","l)"))
864 #!if(isSat,":sat","")
865 #!if(hasShift,":<<16",""), [], "", ALU64_tc_1_SLOT23> {
871 let Inst{27-23} = 0b01010;
872 let Inst{22} = hasShift;
873 let Inst{21} = isSub;
875 let Inst{6-5} = LHbits;
878 let Inst{20-16} = Rs;
881 //Rd=sub(Rt.L,Rs.[LH])
882 let isCodeGenOnly = 0 in {
883 def A2_subh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 1>;
884 def A2_subh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 1>;
887 let isCodeGenOnly = 0 in {
888 //Rd=add(Rt.L,Rs.[LH])
889 def A2_addh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 0>;
890 def A2_addh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 0>;
893 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in {
894 //Rd=sub(Rt.L,Rs.[LH]):sat
895 def A2_subh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 1>;
896 def A2_subh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 1>;
898 //Rd=add(Rt.L,Rs.[LH]):sat
899 def A2_addh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 0>;
900 def A2_addh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 0>;
903 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
904 let isCodeGenOnly = 0 in {
905 def A2_subh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 1>;
906 def A2_subh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 1>;
907 def A2_subh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 1>;
908 def A2_subh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 1>;
911 //Rd=add(Rt.[LH],Rs.[LH]):<<16
912 let isCodeGenOnly = 0 in {
913 def A2_addh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 0>;
914 def A2_addh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 0>;
915 def A2_addh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 0>;
916 def A2_addh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 0>;
919 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in {
920 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
921 def A2_subh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 1>;
922 def A2_subh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 1>;
923 def A2_subh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 1>;
924 def A2_subh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 1>;
926 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
927 def A2_addh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 0>;
928 def A2_addh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 0>;
929 def A2_addh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 0>;
930 def A2_addh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 0>;
934 def: Pat<(sext_inreg (add I32:$src1, I32:$src2), i16),
935 (A2_addh_l16_ll I32:$src1, I32:$src2)>;
937 def: Pat<(sra (add (shl I32:$src1, (i32 16)), I32:$src2), (i32 16)),
938 (A2_addh_l16_hl I32:$src1, I32:$src2)>;
940 def: Pat<(shl (add I32:$src1, I32:$src2), (i32 16)),
941 (A2_addh_h16_ll I32:$src1, I32:$src2)>;
943 // Subtract halfword.
944 def: Pat<(sext_inreg (sub I32:$src1, I32:$src2), i16),
945 (A2_subh_l16_ll I32:$src1, I32:$src2)>;
947 def: Pat<(shl (sub I32:$src1, I32:$src2), (i32 16)),
948 (A2_subh_h16_ll I32:$src1, I32:$src2)>;
950 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
951 def S2_parityp: ALU64Inst<(outs IntRegs:$Rd),
952 (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
953 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
959 let Inst{27-24} = 0b0000;
960 let Inst{20-16} = Rs;
965 let hasNewValue = 1, opNewValue = 0, hasSideEffects = 0 in
966 class T_XTYPE_MIN_MAX < bit isMax, bit isUnsigned >
967 : ALU64Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
968 "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
969 #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
976 let Inst{27-23} = 0b01011;
977 let Inst{22-21} = !if(isMax, 0b10, 0b01);
978 let Inst{7} = isUnsigned;
980 let Inst{12-8} = !if(isMax, Rs, Rt);
981 let Inst{20-16} = !if(isMax, Rt, Rs);
984 let isCodeGenOnly = 0 in {
985 def A2_min : T_XTYPE_MIN_MAX < 0, 0 >;
986 def A2_minu : T_XTYPE_MIN_MAX < 0, 1 >;
987 def A2_max : T_XTYPE_MIN_MAX < 1, 0 >;
988 def A2_maxu : T_XTYPE_MIN_MAX < 1, 1 >;
991 // Here, depending on the operand being selected, we'll either generate a
992 // min or max instruction.
994 // (a>b)?a:b --> max(a,b) => Here check performed is '>' and the value selected
995 // is the larger of two. So, the corresponding HexagonInst is passed in 'Inst'.
996 // (a>b)?b:a --> min(a,b) => Here check performed is '>' but the smaller value
997 // is selected and the corresponding HexagonInst is passed in 'SwapInst'.
999 multiclass T_MinMax_pats <PatFrag Op, RegisterClass RC, ValueType VT,
1000 InstHexagon Inst, InstHexagon SwapInst> {
1001 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1002 (VT RC:$src1), (VT RC:$src2)),
1003 (Inst RC:$src1, RC:$src2)>;
1004 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1005 (VT RC:$src2), (VT RC:$src1)),
1006 (SwapInst RC:$src1, RC:$src2)>;
1010 multiclass MinMax_pats <PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
1011 defm: T_MinMax_pats<Op, IntRegs, i32, Inst, SwapInst>;
1013 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1014 (i32 PositiveHalfWord:$src2))),
1015 (i32 PositiveHalfWord:$src1),
1016 (i32 PositiveHalfWord:$src2))), i16),
1017 (Inst IntRegs:$src1, IntRegs:$src2)>;
1019 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1020 (i32 PositiveHalfWord:$src2))),
1021 (i32 PositiveHalfWord:$src2),
1022 (i32 PositiveHalfWord:$src1))), i16),
1023 (SwapInst IntRegs:$src1, IntRegs:$src2)>;
1026 let AddedComplexity = 200 in {
1027 defm: MinMax_pats<setge, A2_max, A2_min>;
1028 defm: MinMax_pats<setgt, A2_max, A2_min>;
1029 defm: MinMax_pats<setle, A2_min, A2_max>;
1030 defm: MinMax_pats<setlt, A2_min, A2_max>;
1031 defm: MinMax_pats<setuge, A2_maxu, A2_minu>;
1032 defm: MinMax_pats<setugt, A2_maxu, A2_minu>;
1033 defm: MinMax_pats<setule, A2_minu, A2_maxu>;
1034 defm: MinMax_pats<setult, A2_minu, A2_maxu>;
1037 class T_cmp64_rr<string mnemonic, bits<3> MinOp, bit IsComm>
1038 : ALU64_rr<(outs PredRegs:$Pd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1039 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", ALU64_tc_2early_SLOT23> {
1041 let isCommutable = IsComm;
1042 let hasSideEffects = 0;
1048 let IClass = 0b1101;
1049 let Inst{27-21} = 0b0010100;
1050 let Inst{20-16} = Rs;
1051 let Inst{12-8} = Rt;
1052 let Inst{7-5} = MinOp;
1056 let isCodeGenOnly = 0 in {
1057 def C2_cmpeqp : T_cmp64_rr<"cmp.eq", 0b000, 1>;
1058 def C2_cmpgtp : T_cmp64_rr<"cmp.gt", 0b010, 0>;
1059 def C2_cmpgtup : T_cmp64_rr<"cmp.gtu", 0b100, 0>;
1062 class T_cmp64_rr_pat<InstHexagon MI, PatFrag CmpOp>
1063 : Pat<(i1 (CmpOp (i64 DoubleRegs:$Rs), (i64 DoubleRegs:$Rt))),
1064 (i1 (MI DoubleRegs:$Rs, DoubleRegs:$Rt))>;
1066 def: T_cmp64_rr_pat<C2_cmpeqp, seteq>;
1067 def: T_cmp64_rr_pat<C2_cmpgtp, setgt>;
1068 def: T_cmp64_rr_pat<C2_cmpgtup, setugt>;
1069 def: T_cmp64_rr_pat<C2_cmpgtp, RevCmp<setlt>>;
1070 def: T_cmp64_rr_pat<C2_cmpgtup, RevCmp<setult>>;
1072 let isCodeGenOnly = 0 in
1073 def C2_vmux : ALU64_rr<(outs DoubleRegs:$Rd),
1074 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
1075 "$Rd = vmux($Pu, $Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
1076 let hasSideEffects = 0;
1083 let IClass = 0b1101;
1084 let Inst{27-24} = 0b0001;
1085 let Inst{20-16} = Rs;
1086 let Inst{12-8} = Rt;
1091 class T_ALU64_rr<string mnemonic, string suffix, bits<4> RegType,
1092 bits<3> MajOp, bits<3> MinOp, bit OpsRev, bit IsComm,
1094 : ALU64_rr<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1095 "$Rd = " #mnemonic# "($Rs, " #Op2Pfx# "$Rt)" #suffix, [],
1096 "", ALU64_tc_1_SLOT23> {
1097 let hasSideEffects = 0;
1098 let isCommutable = IsComm;
1104 let IClass = 0b1101;
1105 let Inst{27-24} = RegType;
1106 let Inst{23-21} = MajOp;
1107 let Inst{20-16} = !if (OpsRev,Rt,Rs);
1108 let Inst{12-8} = !if (OpsRev,Rs,Rt);
1109 let Inst{7-5} = MinOp;
1113 class T_ALU64_arith<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit IsSat,
1114 bit OpsRev, bit IsComm>
1115 : T_ALU64_rr<mnemonic, !if(IsSat,":sat",""), 0b0011, MajOp, MinOp, OpsRev,
1118 let isCodeGenOnly = 0 in {
1119 def A2_addp : T_ALU64_arith<"add", 0b000, 0b111, 0, 0, 1>;
1120 def A2_subp : T_ALU64_arith<"sub", 0b001, 0b111, 0, 1, 0>;
1123 def: Pat<(i64 (add I64:$Rs, I64:$Rt)), (A2_addp I64:$Rs, I64:$Rt)>;
1124 def: Pat<(i64 (sub I64:$Rs, I64:$Rt)), (A2_subp I64:$Rs, I64:$Rt)>;
1126 class T_ALU64_logical<string mnemonic, bits<3> MinOp, bit OpsRev, bit IsComm,
1128 : T_ALU64_rr<mnemonic, "", 0b0011, 0b111, MinOp, OpsRev, IsComm,
1131 let isCodeGenOnly = 0 in {
1132 def A2_andp : T_ALU64_logical<"and", 0b000, 0, 1, 0>;
1133 def A2_orp : T_ALU64_logical<"or", 0b010, 0, 1, 0>;
1134 def A2_xorp : T_ALU64_logical<"xor", 0b100, 0, 1, 0>;
1137 def: Pat<(i64 (and I64:$Rs, I64:$Rt)), (A2_andp I64:$Rs, I64:$Rt)>;
1138 def: Pat<(i64 (or I64:$Rs, I64:$Rt)), (A2_orp I64:$Rs, I64:$Rt)>;
1139 def: Pat<(i64 (xor I64:$Rs, I64:$Rt)), (A2_xorp I64:$Rs, I64:$Rt)>;
1141 //===----------------------------------------------------------------------===//
1143 //===----------------------------------------------------------------------===//
1145 //===----------------------------------------------------------------------===//
1147 //===----------------------------------------------------------------------===//
1149 //===----------------------------------------------------------------------===//
1151 //===----------------------------------------------------------------------===//
1153 //===----------------------------------------------------------------------===//
1155 //===----------------------------------------------------------------------===//
1157 //===----------------------------------------------------------------------===//
1159 //===----------------------------------------------------------------------===//
1161 //===----------------------------------------------------------------------===//
1163 //===----------------------------------------------------------------------===//
1164 // Logical reductions on predicates.
1166 // Looping instructions.
1168 // Pipelined looping instructions.
1170 // Logical operations on predicates.
1171 let hasSideEffects = 0 in
1172 class T_LOGICAL_1OP<string MnOp, bits<2> OpBits>
1173 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps),
1174 "$Pd = " # MnOp # "($Ps)", [], "", CR_tc_2early_SLOT23> {
1178 let IClass = 0b0110;
1179 let Inst{27-23} = 0b10111;
1180 let Inst{22-21} = OpBits;
1182 let Inst{17-16} = Ps;
1187 let isCodeGenOnly = 0 in {
1188 def C2_any8 : T_LOGICAL_1OP<"any8", 0b00>;
1189 def C2_all8 : T_LOGICAL_1OP<"all8", 0b01>;
1190 def C2_not : T_LOGICAL_1OP<"not", 0b10>;
1193 def: Pat<(i1 (not (i1 PredRegs:$Ps))),
1194 (C2_not PredRegs:$Ps)>;
1196 let hasSideEffects = 0 in
1197 class T_LOGICAL_2OP<string MnOp, bits<3> OpBits, bit IsNeg, bit Rev>
1198 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps, PredRegs:$Pt),
1199 "$Pd = " # MnOp # "($Ps, " # !if (IsNeg,"!","") # "$Pt)",
1200 [], "", CR_tc_2early_SLOT23> {
1205 let IClass = 0b0110;
1206 let Inst{27-24} = 0b1011;
1207 let Inst{23-21} = OpBits;
1209 let Inst{17-16} = !if(Rev,Pt,Ps); // Rs and Rt are reversed for some
1210 let Inst{13} = 0b0; // instructions.
1211 let Inst{9-8} = !if(Rev,Ps,Pt);
1215 let isCodeGenOnly = 0 in {
1216 def C2_and : T_LOGICAL_2OP<"and", 0b000, 0, 1>;
1217 def C2_or : T_LOGICAL_2OP<"or", 0b001, 0, 1>;
1218 def C2_xor : T_LOGICAL_2OP<"xor", 0b010, 0, 0>;
1219 def C2_andn : T_LOGICAL_2OP<"and", 0b011, 1, 1>;
1220 def C2_orn : T_LOGICAL_2OP<"or", 0b111, 1, 1>;
1223 def: Pat<(i1 (and I1:$Ps, I1:$Pt)), (C2_and I1:$Ps, I1:$Pt)>;
1224 def: Pat<(i1 (or I1:$Ps, I1:$Pt)), (C2_or I1:$Ps, I1:$Pt)>;
1225 def: Pat<(i1 (xor I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>;
1226 def: Pat<(i1 (and I1:$Ps, (not I1:$Pt))), (C2_andn I1:$Ps, I1:$Pt)>;
1227 def: Pat<(i1 (or I1:$Ps, (not I1:$Pt))), (C2_orn I1:$Ps, I1:$Pt)>;
1229 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
1230 def C2_vitpack : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps, PredRegs:$Pt),
1231 "$Rd = vitpack($Ps, $Pt)", [], "", S_2op_tc_1_SLOT23> {
1236 let IClass = 0b1000;
1237 let Inst{27-24} = 0b1001;
1238 let Inst{22-21} = 0b00;
1239 let Inst{17-16} = Ps;
1244 let hasSideEffects = 0, isCodeGenOnly = 0 in
1245 def C2_mask : SInst<(outs DoubleRegs:$Rd), (ins PredRegs:$Pt),
1246 "$Rd = mask($Pt)", [], "", S_2op_tc_1_SLOT23> {
1250 let IClass = 0b1000;
1251 let Inst{27-24} = 0b0110;
1256 // User control register transfer.
1257 //===----------------------------------------------------------------------===//
1259 //===----------------------------------------------------------------------===//
1261 //===----------------------------------------------------------------------===//
1263 //===----------------------------------------------------------------------===//
1265 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
1266 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1267 def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>;
1269 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
1270 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
1272 class CondStr<string CReg, bit True, bit New> {
1273 string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") ";
1275 class JumpOpcStr<string Mnemonic, bit New, bit Taken> {
1276 string S = Mnemonic # !if(New, !if(Taken,":t",":nt"), "");
1279 let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0,
1281 isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
1282 opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in
1283 class T_JMP<string ExtStr>
1284 : JInst<(outs), (ins brtarget:$dst),
1285 "jump " # ExtStr # "$dst",
1286 [], "", J_tc_2early_SLOT23> {
1288 let IClass = 0b0101;
1290 let Inst{27-25} = 0b100;
1291 let Inst{24-16} = dst{23-15};
1292 let Inst{13-1} = dst{14-2};
1295 let isBranch = 1, Defs = [PC], hasSideEffects = 0, isPredicated = 1,
1296 isExtendable = 1, opExtendable = 1, isExtentSigned = 1,
1297 opExtentBits = 17, opExtentAlign = 2, InputType = "imm" in
1298 class T_JMP_c<bit PredNot, bit isPredNew, bit isTak, string ExtStr>
1299 : JInst<(outs), (ins PredRegs:$src, brtarget:$dst),
1300 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
1301 JumpOpcStr<"jump", isPredNew, isTak>.S # " " #
1303 [], "", J_tc_2early_SLOT23>, ImmRegRel {
1304 let isTaken = isTak;
1305 let isPredicatedFalse = PredNot;
1306 let isPredicatedNew = isPredNew;
1310 let IClass = 0b0101;
1312 let Inst{27-24} = 0b1100;
1313 let Inst{21} = PredNot;
1314 let Inst{12} = !if(isPredNew, isTak, zero);
1315 let Inst{11} = isPredNew;
1316 let Inst{9-8} = src;
1317 let Inst{23-22} = dst{16-15};
1318 let Inst{20-16} = dst{14-10};
1319 let Inst{13} = dst{9};
1320 let Inst{7-1} = dst{8-2};
1323 multiclass JMP_Pred<bit PredNot, string ExtStr> {
1324 def NAME : T_JMP_c<PredNot, 0, 0, ExtStr>;
1326 def NAME#newpt : T_JMP_c<PredNot, 1, 1, ExtStr>; // taken
1327 def NAME#new : T_JMP_c<PredNot, 1, 0, ExtStr>; // not taken
1330 multiclass JMP_base<string BaseOp, string ExtStr> {
1331 let BaseOpcode = BaseOp in {
1332 def NAME : T_JMP<ExtStr>;
1333 defm t : JMP_Pred<0, ExtStr>;
1334 defm f : JMP_Pred<1, ExtStr>;
1338 // Jumps to address stored in a register, JUMPR_MISC
1339 // if ([[!]P[.new]]) jumpr[:t/nt] Rs
1340 let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC],
1341 isPredicable = 1, hasSideEffects = 0, InputType = "reg" in
1343 : JRInst<(outs), (ins IntRegs:$dst),
1344 "jumpr $dst", [], "", J_tc_2early_SLOT2> {
1347 let IClass = 0b0101;
1348 let Inst{27-21} = 0b0010100;
1349 let Inst{20-16} = dst;
1352 let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1,
1353 hasSideEffects = 0, InputType = "reg" in
1354 class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>
1355 : JRInst <(outs), (ins PredRegs:$src, IntRegs:$dst),
1356 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
1357 JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst", [],
1358 "", J_tc_2early_SLOT2> {
1360 let isTaken = isTak;
1361 let isPredicatedFalse = PredNot;
1362 let isPredicatedNew = isPredNew;
1366 let IClass = 0b0101;
1368 let Inst{27-22} = 0b001101;
1369 let Inst{21} = PredNot;
1370 let Inst{20-16} = dst;
1371 let Inst{12} = !if(isPredNew, isTak, zero);
1372 let Inst{11} = isPredNew;
1373 let Inst{9-8} = src;
1376 multiclass JMPR_Pred<bit PredNot> {
1377 def NAME: T_JMPr_c<PredNot, 0, 0>;
1379 def NAME#newpt : T_JMPr_c<PredNot, 1, 1>; // taken
1380 def NAME#new : T_JMPr_c<PredNot, 1, 0>; // not taken
1383 multiclass JMPR_base<string BaseOp> {
1384 let BaseOpcode = BaseOp in {
1386 defm t : JMPR_Pred<0>;
1387 defm f : JMPR_Pred<1>;
1391 let isCall = 1, hasSideEffects = 1 in
1392 class JUMPR_MISC_CALLR<bit isPred, bit isPredNot,
1393 dag InputDag = (ins IntRegs:$Rs)>
1394 : JRInst<(outs), InputDag,
1395 !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs",
1396 "if ($Pu) callr $Rs"),
1398 [], "", J_tc_2early_SLOT2> {
1401 let isPredicated = isPred;
1402 let isPredicatedFalse = isPredNot;
1404 let IClass = 0b0101;
1405 let Inst{27-25} = 0b000;
1406 let Inst{24-23} = !if (isPred, 0b10, 0b01);
1408 let Inst{21} = isPredNot;
1409 let Inst{9-8} = !if (isPred, Pu, 0b00);
1410 let Inst{20-16} = Rs;
1414 let Defs = VolatileV3.Regs, isCodeGenOnly = 0 in {
1415 def J2_callrt : JUMPR_MISC_CALLR<1, 0, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1416 def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1419 let isTerminator = 1, hasSideEffects = 0, isCodeGenOnly = 0 in {
1420 defm J2_jump : JMP_base<"JMP", "">, PredNewRel;
1422 // Deal with explicit assembly
1423 // - never extened a jump #, always extend a jump ##
1424 let isAsmParserOnly = 1 in {
1425 defm J2_jump_ext : JMP_base<"JMP", "##">;
1426 defm J2_jump_noext : JMP_base<"JMP", "#">;
1429 defm J2_jumpr : JMPR_base<"JMPr">, PredNewRel;
1431 let isReturn = 1, isCodeGenOnly = 1 in
1432 defm JMPret : JMPR_base<"JMPret">, PredNewRel;
1435 def: Pat<(br bb:$dst),
1436 (J2_jump brtarget:$dst)>;
1438 (JMPret (i32 R31))>;
1439 def: Pat<(brcond (i1 PredRegs:$src1), bb:$offset),
1440 (J2_jumpt PredRegs:$src1, bb:$offset)>;
1442 // A return through builtin_eh_return.
1443 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
1444 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
1445 def EH_RETURN_JMPR : T_JMPr;
1447 def: Pat<(eh_return),
1448 (EH_RETURN_JMPR (i32 R31))>;
1449 def: Pat<(HexagonBR_JT (i32 IntRegs:$dst)),
1450 (J2_jumpr IntRegs:$dst)>;
1451 def: Pat<(brind (i32 IntRegs:$dst)),
1452 (J2_jumpr IntRegs:$dst)>;
1454 //===----------------------------------------------------------------------===//
1456 //===----------------------------------------------------------------------===//
1458 //===----------------------------------------------------------------------===//
1460 //===----------------------------------------------------------------------===//
1461 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, AddedComplexity = 20 in
1462 class T_load_io <string mnemonic, RegisterClass RC, bits<4> MajOp,
1464 : LDInst<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1465 "$dst = "#mnemonic#"($src1 + #$offset)", []>, AddrModeRel {
1470 bits<11> offsetBits;
1472 string ImmOpStr = !cast<string>(ImmOp);
1473 let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), offset{13-3},
1474 !if (!eq(ImmOpStr, "s11_2Ext"), offset{12-2},
1475 !if (!eq(ImmOpStr, "s11_1Ext"), offset{11-1},
1476 /* s11_0Ext */ offset{10-0})));
1477 let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14,
1478 !if (!eq(ImmOpStr, "s11_2Ext"), 13,
1479 !if (!eq(ImmOpStr, "s11_1Ext"), 12,
1480 /* s11_0Ext */ 11)));
1481 let hasNewValue = !if (!eq(ImmOpStr, "s11_3Ext"), 0, 1);
1483 let IClass = 0b1001;
1486 let Inst{26-25} = offsetBits{10-9};
1487 let Inst{24-21} = MajOp;
1488 let Inst{20-16} = src1;
1489 let Inst{13-5} = offsetBits{8-0};
1490 let Inst{4-0} = dst;
1493 let opExtendable = 3, isExtentSigned = 0, isPredicated = 1 in
1494 class T_pload_io <string mnemonic, RegisterClass RC, bits<4>MajOp,
1495 Operand ImmOp, bit isNot, bit isPredNew>
1496 : LDInst<(outs RC:$dst),
1497 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1498 "if ("#!if(isNot, "!$src1", "$src1")
1499 #!if(isPredNew, ".new", "")
1500 #") $dst = "#mnemonic#"($src2 + #$offset)",
1501 [],"", V2LDST_tc_ld_SLOT01> , AddrModeRel {
1507 string ImmOpStr = !cast<string>(ImmOp);
1509 let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), offset{8-3},
1510 !if (!eq(ImmOpStr, "u6_2Ext"), offset{7-2},
1511 !if (!eq(ImmOpStr, "u6_1Ext"), offset{6-1},
1512 /* u6_0Ext */ offset{5-0})));
1513 let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9,
1514 !if (!eq(ImmOpStr, "u6_2Ext"), 8,
1515 !if (!eq(ImmOpStr, "u6_1Ext"), 7,
1517 let hasNewValue = !if (!eq(ImmOpStr, "u6_3Ext"), 0, 1);
1518 let isPredicatedNew = isPredNew;
1519 let isPredicatedFalse = isNot;
1521 let IClass = 0b0100;
1525 let Inst{26} = isNot;
1526 let Inst{25} = isPredNew;
1527 let Inst{24-21} = MajOp;
1528 let Inst{20-16} = src2;
1530 let Inst{12-11} = src1;
1531 let Inst{10-5} = offsetBits;
1532 let Inst{4-0} = dst;
1535 let isExtendable = 1, hasSideEffects = 0, addrMode = BaseImmOffset in
1536 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1537 Operand ImmOp, Operand predImmOp, bits<4>MajOp> {
1538 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1539 let isPredicable = 1 in
1540 def L2_#NAME#_io : T_load_io <mnemonic, RC, MajOp, ImmOp>;
1543 def L2_p#NAME#t_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 0>;
1544 def L2_p#NAME#f_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 0>;
1547 def L2_p#NAME#tnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 1>;
1548 def L2_p#NAME#fnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 1>;
1552 let accessSize = ByteAccess, isCodeGenOnly = 0 in {
1553 defm loadrb: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext, 0b1000>;
1554 defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>;
1557 let accessSize = HalfWordAccess, opExtentAlign = 1, isCodeGenOnly = 0 in {
1558 defm loadrh: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, 0b1010>;
1559 defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>;
1562 let accessSize = WordAccess, opExtentAlign = 2, isCodeGenOnly = 0 in
1563 defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>;
1565 let accessSize = DoubleWordAccess, opExtentAlign = 3, isCodeGenOnly = 0 in
1566 defm loadrd: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, 0b1110>;
1568 // Patterns to select load-indexed (i.e. load from base+offset).
1569 multiclass Loadx_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
1571 def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>;
1572 def: Pat<(VT (Load (add (i32 IntRegs:$Rs), ImmPred:$Off))),
1573 (VT (MI IntRegs:$Rs, imm:$Off))>;
1574 def: Pat<(VT (Load (i32 IntRegs:$Rs))), (VT (MI IntRegs:$Rs, 0))>;
1577 let AddedComplexity = 20 in {
1578 defm: Loadx_pat<load, i32, s11_2ExtPred, L2_loadri_io>;
1579 defm: Loadx_pat<load, i64, s11_3ExtPred, L2_loadrd_io>;
1580 defm: Loadx_pat<atomic_load_8 , i32, s11_0ExtPred, L2_loadrub_io>;
1581 defm: Loadx_pat<atomic_load_16, i32, s11_1ExtPred, L2_loadruh_io>;
1582 defm: Loadx_pat<atomic_load_32, i32, s11_2ExtPred, L2_loadri_io>;
1583 defm: Loadx_pat<atomic_load_64, i64, s11_3ExtPred, L2_loadrd_io>;
1585 defm: Loadx_pat<extloadi1, i32, s11_0ExtPred, L2_loadrub_io>;
1586 defm: Loadx_pat<extloadi8, i32, s11_0ExtPred, L2_loadrub_io>;
1587 defm: Loadx_pat<extloadi16, i32, s11_1ExtPred, L2_loadruh_io>;
1588 defm: Loadx_pat<sextloadi8, i32, s11_0ExtPred, L2_loadrb_io>;
1589 defm: Loadx_pat<sextloadi16, i32, s11_1ExtPred, L2_loadrh_io>;
1590 defm: Loadx_pat<zextloadi1, i32, s11_0ExtPred, L2_loadrub_io>;
1591 defm: Loadx_pat<zextloadi8, i32, s11_0ExtPred, L2_loadrub_io>;
1592 defm: Loadx_pat<zextloadi16, i32, s11_1ExtPred, L2_loadruh_io>;
1596 // Sign-extending loads of i1 need to replicate the lowest bit throughout
1597 // the 32-bit value. Since the loaded value can only be 0 or 1, 0-v should
1599 let AddedComplexity = 20 in
1600 def: Pat<(i32 (sextloadi1 (i32 IntRegs:$Rs))),
1601 (SUB_ri 0, (L2_loadrub_io IntRegs:$Rs, 0))>;
1603 //===----------------------------------------------------------------------===//
1604 // Post increment load
1605 //===----------------------------------------------------------------------===//
1606 //===----------------------------------------------------------------------===//
1607 // Template class for non-predicated post increment loads with immediate offset.
1608 //===----------------------------------------------------------------------===//
1609 let hasSideEffects = 0, addrMode = PostInc in
1610 class T_load_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
1612 : LDInstPI <(outs RC:$dst, IntRegs:$dst2),
1613 (ins IntRegs:$src1, ImmOp:$offset),
1614 "$dst = "#mnemonic#"($src1++#$offset)" ,
1623 string ImmOpStr = !cast<string>(ImmOp);
1624 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
1625 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1626 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1627 /* s4_0Imm */ offset{3-0})));
1628 let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
1630 let IClass = 0b1001;
1632 let Inst{27-25} = 0b101;
1633 let Inst{24-21} = MajOp;
1634 let Inst{20-16} = src1;
1635 let Inst{13-12} = 0b00;
1636 let Inst{8-5} = offsetBits;
1637 let Inst{4-0} = dst;
1640 //===----------------------------------------------------------------------===//
1641 // Template class for predicated post increment loads with immediate offset.
1642 //===----------------------------------------------------------------------===//
1643 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
1644 class T_pload_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
1645 bits<4> MajOp, bit isPredNot, bit isPredNew >
1646 : LDInst <(outs RC:$dst, IntRegs:$dst2),
1647 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1648 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1649 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1659 let isPredicatedNew = isPredNew;
1660 let isPredicatedFalse = isPredNot;
1662 string ImmOpStr = !cast<string>(ImmOp);
1663 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
1664 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1665 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1666 /* s4_0Imm */ offset{3-0})));
1667 let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
1669 let IClass = 0b1001;
1671 let Inst{27-25} = 0b101;
1672 let Inst{24-21} = MajOp;
1673 let Inst{20-16} = src2;
1675 let Inst{12} = isPredNew;
1676 let Inst{11} = isPredNot;
1677 let Inst{10-9} = src1;
1678 let Inst{8-5} = offsetBits;
1679 let Inst{4-0} = dst;
1682 //===----------------------------------------------------------------------===//
1683 // Multiclass for post increment loads with immediate offset.
1684 //===----------------------------------------------------------------------===//
1686 multiclass LD_PostInc <string mnemonic, string BaseOp, RegisterClass RC,
1687 Operand ImmOp, bits<4> MajOp> {
1688 let BaseOpcode = "POST_"#BaseOp in {
1689 let isPredicable = 1 in
1690 def L2_#NAME#_pi : T_load_pi < mnemonic, RC, ImmOp, MajOp>;
1693 def L2_p#NAME#t_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 0>;
1694 def L2_p#NAME#f_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 0>;
1697 def L2_p#NAME#tnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 1>;
1698 def L2_p#NAME#fnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 1>;
1702 // post increment byte loads with immediate offset
1703 let accessSize = ByteAccess, isCodeGenOnly = 0 in {
1704 defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>;
1705 defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>;
1708 // post increment halfword loads with immediate offset
1709 let accessSize = HalfWordAccess, opExtentAlign = 1, isCodeGenOnly = 0 in {
1710 defm loadrh : LD_PostInc <"memh", "LDrih", IntRegs, s4_1Imm, 0b1010>;
1711 defm loadruh : LD_PostInc <"memuh", "LDriuh", IntRegs, s4_1Imm, 0b1011>;
1714 // post increment word loads with immediate offset
1715 let accessSize = WordAccess, opExtentAlign = 2, isCodeGenOnly = 0 in
1716 defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>;
1718 // post increment doubleword loads with immediate offset
1719 let accessSize = DoubleWordAccess, opExtentAlign = 3, isCodeGenOnly = 0 in
1720 defm loadrd : LD_PostInc <"memd", "LDrid", DoubleRegs, s4_3Imm, 0b1110>;
1722 //===----------------------------------------------------------------------===//
1723 // Template class for post increment loads with register offset.
1724 //===----------------------------------------------------------------------===//
1725 let hasSideEffects = 0, addrMode = PostInc in
1726 class T_load_pr <string mnemonic, RegisterClass RC, bits<4> MajOp,
1727 MemAccessSize AccessSz>
1728 : LDInstPI <(outs RC:$dst, IntRegs:$_dst_),
1729 (ins IntRegs:$src1, ModRegs:$src2),
1730 "$dst = "#mnemonic#"($src1++$src2)" ,
1731 [], "$src1 = $_dst_" > {
1736 let accessSize = AccessSz;
1737 let IClass = 0b1001;
1739 let Inst{27-25} = 0b110;
1740 let Inst{24-21} = MajOp;
1741 let Inst{20-16} = src1;
1742 let Inst{13} = src2;
1745 let Inst{4-0} = dst;
1748 let hasNewValue = 1, isCodeGenOnly = 0 in {
1749 def L2_loadrb_pr : T_load_pr <"memb", IntRegs, 0b1000, ByteAccess>;
1750 def L2_loadrub_pr : T_load_pr <"memub", IntRegs, 0b1001, ByteAccess>;
1751 def L2_loadrh_pr : T_load_pr <"memh", IntRegs, 0b1010, HalfWordAccess>;
1752 def L2_loadruh_pr : T_load_pr <"memuh", IntRegs, 0b1011, HalfWordAccess>;
1753 def L2_loadri_pr : T_load_pr <"memw", IntRegs, 0b1100, WordAccess>;
1756 let isCodeGenOnly = 0 in
1757 def L2_loadrd_pr : T_load_pr <"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
1760 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
1761 isPseudo = 1, Defs = [R10,R11,D5], hasSideEffects = 0 in
1762 def LDriw_pred : LDInst2<(outs PredRegs:$dst),
1764 "Error; should not emit",
1767 let Defs = [R29, R30, R31], Uses = [R30], hasSideEffects = 0, isCodeGenOnly = 0 in
1768 def L2_deallocframe : LDInst<(outs), (ins),
1771 let IClass = 0b1001;
1773 let Inst{27-16} = 0b000000011110;
1775 let Inst{4-0} = 0b11110;
1778 // Load / Post increment circular addressing mode.
1779 let Uses = [CS], hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
1780 class T_load_pcr<string mnemonic, RegisterClass RC, bits<4> MajOp>
1781 : LDInst <(outs RC:$dst, IntRegs:$_dst_),
1782 (ins IntRegs:$Rz, ModRegs:$Mu),
1783 "$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [],
1789 let IClass = 0b1001;
1791 let Inst{27-25} = 0b100;
1792 let Inst{24-21} = MajOp;
1793 let Inst{20-16} = Rz;
1798 let Inst{4-0} = dst;
1801 let accessSize = ByteAccess, isCodeGenOnly = 0 in {
1802 def L2_loadrb_pcr : T_load_pcr <"memb", IntRegs, 0b1000>;
1803 def L2_loadrub_pcr : T_load_pcr <"memub", IntRegs, 0b1001>;
1806 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in {
1807 def L2_loadrh_pcr : T_load_pcr <"memh", IntRegs, 0b1010>;
1808 def L2_loadruh_pcr : T_load_pcr <"memuh", IntRegs, 0b1011>;
1811 let accessSize = WordAccess, isCodeGenOnly = 0 in {
1812 def L2_loadri_pcr : T_load_pcr <"memw", IntRegs, 0b1100>;
1815 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
1816 def L2_loadrd_pcr : T_load_pcr <"memd", DoubleRegs, 0b1110>;
1818 //===----------------------------------------------------------------------===//
1819 // Circular loads with immediate offset.
1820 //===----------------------------------------------------------------------===//
1821 let Uses = [CS], mayLoad = 1, hasSideEffects = 0, hasNewValue = 1 in
1822 class T_load_pci <string mnemonic, RegisterClass RC,
1823 Operand ImmOp, bits<4> MajOp>
1824 : LDInstPI<(outs RC:$dst, IntRegs:$_dst_),
1825 (ins IntRegs:$Rz, ImmOp:$offset, ModRegs:$Mu),
1826 "$dst = "#mnemonic#"($Rz ++ #$offset:circ($Mu))", [],
1834 string ImmOpStr = !cast<string>(ImmOp);
1835 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
1836 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1837 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1838 /* s4_0Imm */ offset{3-0})));
1839 let IClass = 0b1001;
1840 let Inst{27-25} = 0b100;
1841 let Inst{24-21} = MajOp;
1842 let Inst{20-16} = Rz;
1846 let Inst{8-5} = offsetBits;
1847 let Inst{4-0} = dst;
1850 // Byte variants of circ load
1851 let accessSize = ByteAccess, isCodeGenOnly = 0 in {
1852 def L2_loadrb_pci : T_load_pci <"memb", IntRegs, s4_0Imm, 0b1000>;
1853 def L2_loadrub_pci : T_load_pci <"memub", IntRegs, s4_0Imm, 0b1001>;
1856 // Half word variants of circ load
1857 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in {
1858 def L2_loadrh_pci : T_load_pci <"memh", IntRegs, s4_1Imm, 0b1010>;
1859 def L2_loadruh_pci : T_load_pci <"memuh", IntRegs, s4_1Imm, 0b1011>;
1862 // Word variants of circ load
1863 let accessSize = WordAccess, isCodeGenOnly = 0 in
1864 def L2_loadri_pci : T_load_pci <"memw", IntRegs, s4_2Imm, 0b1100>;
1866 let accessSize = DoubleWordAccess, hasNewValue = 0, isCodeGenOnly = 0 in
1867 def L2_loadrd_pci : T_load_pci <"memd", DoubleRegs, s4_3Imm, 0b1110>;
1869 // L[24]_load[wd]_locked: Load word/double with lock.
1871 class T_load_locked <string mnemonic, RegisterClass RC>
1872 : LD0Inst <(outs RC:$dst),
1874 "$dst = "#mnemonic#"($src)"> {
1877 let IClass = 0b1001;
1878 let Inst{27-21} = 0b0010000;
1879 let Inst{20-16} = src;
1880 let Inst{13-12} = !if (!eq(mnemonic, "memd_locked"), 0b01, 0b00);
1881 let Inst{4-0} = dst;
1883 let hasNewValue = 1, accessSize = WordAccess, opNewValue = 0, isCodeGenOnly = 0 in
1884 def L2_loadw_locked : T_load_locked <"memw_locked", IntRegs>;
1885 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
1886 def L4_loadd_locked : T_load_locked <"memd_locked", DoubleRegs>;
1887 //===----------------------------------------------------------------------===//
1888 // Bit-reversed loads with auto-increment register
1889 //===----------------------------------------------------------------------===//
1890 let hasSideEffects = 0 in
1891 class T_load_pbr<string mnemonic, RegisterClass RC,
1892 MemAccessSize addrSize, bits<4> majOp>
1894 <(outs RC:$dst, IntRegs:$_dst_),
1895 (ins IntRegs:$Rz, ModRegs:$Mu),
1896 "$dst = "#mnemonic#"($Rz ++ $Mu:brev)" ,
1897 [] , "$Rz = $_dst_" > {
1899 let accessSize = addrSize;
1905 let IClass = 0b1001;
1907 let Inst{27-25} = 0b111;
1908 let Inst{24-21} = majOp;
1909 let Inst{20-16} = Rz;
1913 let Inst{4-0} = dst;
1916 let hasNewValue =1, opNewValue = 0, isCodeGenOnly = 0 in {
1917 def L2_loadrb_pbr : T_load_pbr <"memb", IntRegs, ByteAccess, 0b1000>;
1918 def L2_loadrub_pbr : T_load_pbr <"memub", IntRegs, ByteAccess, 0b1001>;
1919 def L2_loadrh_pbr : T_load_pbr <"memh", IntRegs, HalfWordAccess, 0b1010>;
1920 def L2_loadruh_pbr : T_load_pbr <"memuh", IntRegs, HalfWordAccess, 0b1011>;
1921 def L2_loadri_pbr : T_load_pbr <"memw", IntRegs, WordAccess, 0b1100>;
1924 let isCodeGenOnly = 0 in
1925 def L2_loadrd_pbr : T_load_pbr <"memd", DoubleRegs, DoubleWordAccess, 0b1110>;
1927 //===----------------------------------------------------------------------===//
1929 //===----------------------------------------------------------------------===//
1931 //===----------------------------------------------------------------------===//
1933 //===----------------------------------------------------------------------===//
1934 //===----------------------------------------------------------------------===//
1936 //===----------------------------------------------------------------------===//
1938 //===----------------------------------------------------------------------===//
1940 //===----------------------------------------------------------------------===//
1941 //===----------------------------------------------------------------------===//
1943 //===----------------------------------------------------------------------===//
1945 //===----------------------------------------------------------------------===//
1947 //===----------------------------------------------------------------------===//
1949 //===----------------------------------------------------------------------===//
1951 // MPYS / Multipy signed/unsigned halfwords
1952 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
1953 //===----------------------------------------------------------------------===//
1955 let hasNewValue = 1, opNewValue = 0 in
1956 class T_M2_mpy < bits<2> LHbits, bit isSat, bit isRnd,
1957 bit hasShift, bit isUnsigned>
1958 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
1959 "$Rd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
1960 #", $Rt."#!if(LHbits{0},"h)","l)")
1961 #!if(hasShift,":<<1","")
1962 #!if(isRnd,":rnd","")
1963 #!if(isSat,":sat",""),
1964 [], "", M_tc_3x_SLOT23 > {
1969 let IClass = 0b1110;
1971 let Inst{27-24} = 0b1100;
1972 let Inst{23} = hasShift;
1973 let Inst{22} = isUnsigned;
1974 let Inst{21} = isRnd;
1975 let Inst{7} = isSat;
1976 let Inst{6-5} = LHbits;
1978 let Inst{20-16} = Rs;
1979 let Inst{12-8} = Rt;
1982 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]
1983 let isCodeGenOnly = 0 in {
1984 def M2_mpy_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 0>;
1985 def M2_mpy_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 0>;
1986 def M2_mpy_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 0>;
1987 def M2_mpy_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 0>;
1988 def M2_mpy_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 0>;
1989 def M2_mpy_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 0>;
1990 def M2_mpy_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 0>;
1991 def M2_mpy_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 0>;
1994 //Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
1995 let isCodeGenOnly = 0 in {
1996 def M2_mpyu_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 1>;
1997 def M2_mpyu_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 1>;
1998 def M2_mpyu_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 1>;
1999 def M2_mpyu_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 1>;
2000 def M2_mpyu_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 1>;
2001 def M2_mpyu_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 1>;
2002 def M2_mpyu_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 1>;
2003 def M2_mpyu_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 1>;
2006 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]:rnd
2007 let isCodeGenOnly = 0 in {
2008 def M2_mpy_rnd_ll_s1: T_M2_mpy <0b00, 0, 1, 1, 0>;
2009 def M2_mpy_rnd_ll_s0: T_M2_mpy <0b00, 0, 1, 0, 0>;
2010 def M2_mpy_rnd_lh_s1: T_M2_mpy <0b01, 0, 1, 1, 0>;
2011 def M2_mpy_rnd_lh_s0: T_M2_mpy <0b01, 0, 1, 0, 0>;
2012 def M2_mpy_rnd_hl_s1: T_M2_mpy <0b10, 0, 1, 1, 0>;
2013 def M2_mpy_rnd_hl_s0: T_M2_mpy <0b10, 0, 1, 0, 0>;
2014 def M2_mpy_rnd_hh_s1: T_M2_mpy <0b11, 0, 1, 1, 0>;
2015 def M2_mpy_rnd_hh_s0: T_M2_mpy <0b11, 0, 1, 0, 0>;
2018 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2019 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
2020 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
2021 def M2_mpy_sat_ll_s1: T_M2_mpy <0b00, 1, 0, 1, 0>;
2022 def M2_mpy_sat_ll_s0: T_M2_mpy <0b00, 1, 0, 0, 0>;
2023 def M2_mpy_sat_lh_s1: T_M2_mpy <0b01, 1, 0, 1, 0>;
2024 def M2_mpy_sat_lh_s0: T_M2_mpy <0b01, 1, 0, 0, 0>;
2025 def M2_mpy_sat_hl_s1: T_M2_mpy <0b10, 1, 0, 1, 0>;
2026 def M2_mpy_sat_hl_s0: T_M2_mpy <0b10, 1, 0, 0, 0>;
2027 def M2_mpy_sat_hh_s1: T_M2_mpy <0b11, 1, 0, 1, 0>;
2028 def M2_mpy_sat_hh_s0: T_M2_mpy <0b11, 1, 0, 0, 0>;
2030 def M2_mpy_sat_rnd_ll_s1: T_M2_mpy <0b00, 1, 1, 1, 0>;
2031 def M2_mpy_sat_rnd_ll_s0: T_M2_mpy <0b00, 1, 1, 0, 0>;
2032 def M2_mpy_sat_rnd_lh_s1: T_M2_mpy <0b01, 1, 1, 1, 0>;
2033 def M2_mpy_sat_rnd_lh_s0: T_M2_mpy <0b01, 1, 1, 0, 0>;
2034 def M2_mpy_sat_rnd_hl_s1: T_M2_mpy <0b10, 1, 1, 1, 0>;
2035 def M2_mpy_sat_rnd_hl_s0: T_M2_mpy <0b10, 1, 1, 0, 0>;
2036 def M2_mpy_sat_rnd_hh_s1: T_M2_mpy <0b11, 1, 1, 1, 0>;
2037 def M2_mpy_sat_rnd_hh_s0: T_M2_mpy <0b11, 1, 1, 0, 0>;
2040 //===----------------------------------------------------------------------===//
2042 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
2043 // result from the accumulator.
2044 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2045 //===----------------------------------------------------------------------===//
2047 let hasNewValue = 1, opNewValue = 0 in
2048 class T_M2_mpy_acc < bits<2> LHbits, bit isSat, bit isNac,
2049 bit hasShift, bit isUnsigned >
2050 : MInst_acc<(outs IntRegs:$Rx), (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2051 "$Rx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy")
2052 #"($Rs."#!if(LHbits{1},"h","l")
2053 #", $Rt."#!if(LHbits{0},"h)","l)")
2054 #!if(hasShift,":<<1","")
2055 #!if(isSat,":sat",""),
2056 [], "$dst2 = $Rx", M_tc_3x_SLOT23 > {
2061 let IClass = 0b1110;
2062 let Inst{27-24} = 0b1110;
2063 let Inst{23} = hasShift;
2064 let Inst{22} = isUnsigned;
2065 let Inst{21} = isNac;
2066 let Inst{7} = isSat;
2067 let Inst{6-5} = LHbits;
2069 let Inst{20-16} = Rs;
2070 let Inst{12-8} = Rt;
2073 //Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2074 let isCodeGenOnly = 0 in {
2075 def M2_mpy_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 0>;
2076 def M2_mpy_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 0>;
2077 def M2_mpy_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 0>;
2078 def M2_mpy_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 0>;
2079 def M2_mpy_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 0>;
2080 def M2_mpy_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 0>;
2081 def M2_mpy_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 0>;
2082 def M2_mpy_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 0>;
2085 //Rx += mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2086 let isCodeGenOnly = 0 in {
2087 def M2_mpyu_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 1>;
2088 def M2_mpyu_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 1>;
2089 def M2_mpyu_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 1>;
2090 def M2_mpyu_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 1>;
2091 def M2_mpyu_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 1>;
2092 def M2_mpyu_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 1>;
2093 def M2_mpyu_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 1>;
2094 def M2_mpyu_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 1>;
2097 //Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2098 let isCodeGenOnly = 0 in {
2099 def M2_mpy_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 0>;
2100 def M2_mpy_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 0>;
2101 def M2_mpy_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 0>;
2102 def M2_mpy_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 0>;
2103 def M2_mpy_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 0>;
2104 def M2_mpy_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 0>;
2105 def M2_mpy_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 0>;
2106 def M2_mpy_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 0>;
2109 //Rx -= mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2110 let isCodeGenOnly = 0 in {
2111 def M2_mpyu_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 1>;
2112 def M2_mpyu_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 1>;
2113 def M2_mpyu_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 1>;
2114 def M2_mpyu_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 1>;
2115 def M2_mpyu_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 1>;
2116 def M2_mpyu_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 1>;
2117 def M2_mpyu_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 1>;
2118 def M2_mpyu_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 1>;
2121 //Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat
2122 let isCodeGenOnly = 0 in {
2123 def M2_mpy_acc_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 0, 1, 0>;
2124 def M2_mpy_acc_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 0, 0, 0>;
2125 def M2_mpy_acc_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 0, 1, 0>;
2126 def M2_mpy_acc_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 0, 0, 0>;
2127 def M2_mpy_acc_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 0, 1, 0>;
2128 def M2_mpy_acc_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 0, 0, 0>;
2129 def M2_mpy_acc_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 0, 1, 0>;
2130 def M2_mpy_acc_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 0, 0, 0>;
2133 //Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat
2134 let isCodeGenOnly = 0 in {
2135 def M2_mpy_nac_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 1, 1, 0>;
2136 def M2_mpy_nac_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 1, 0, 0>;
2137 def M2_mpy_nac_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 1, 1, 0>;
2138 def M2_mpy_nac_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 1, 0, 0>;
2139 def M2_mpy_nac_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 1, 1, 0>;
2140 def M2_mpy_nac_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 1, 0, 0>;
2141 def M2_mpy_nac_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 1, 1, 0>;
2142 def M2_mpy_nac_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 1, 0, 0>;
2145 //===----------------------------------------------------------------------===//
2147 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
2148 // result from the 64-bit destination register.
2149 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2150 //===----------------------------------------------------------------------===//
2152 class T_M2_mpyd_acc < bits<2> LHbits, bit isNac, bit hasShift, bit isUnsigned>
2153 : MInst_acc<(outs DoubleRegs:$Rxx),
2154 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2155 "$Rxx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy")
2156 #"($Rs."#!if(LHbits{1},"h","l")
2157 #", $Rt."#!if(LHbits{0},"h)","l)")
2158 #!if(hasShift,":<<1",""),
2159 [], "$dst2 = $Rxx", M_tc_3x_SLOT23 > {
2164 let IClass = 0b1110;
2166 let Inst{27-24} = 0b0110;
2167 let Inst{23} = hasShift;
2168 let Inst{22} = isUnsigned;
2169 let Inst{21} = isNac;
2171 let Inst{6-5} = LHbits;
2172 let Inst{4-0} = Rxx;
2173 let Inst{20-16} = Rs;
2174 let Inst{12-8} = Rt;
2177 let isCodeGenOnly = 0 in {
2178 def M2_mpyd_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 0>;
2179 def M2_mpyd_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 0>;
2180 def M2_mpyd_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 0>;
2181 def M2_mpyd_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 0>;
2183 def M2_mpyd_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 0>;
2184 def M2_mpyd_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 0>;
2185 def M2_mpyd_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 0>;
2186 def M2_mpyd_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 0>;
2188 def M2_mpyd_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 0>;
2189 def M2_mpyd_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 0>;
2190 def M2_mpyd_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 0>;
2191 def M2_mpyd_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 0>;
2193 def M2_mpyd_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 0>;
2194 def M2_mpyd_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 0>;
2195 def M2_mpyd_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 0>;
2196 def M2_mpyd_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 0>;
2198 def M2_mpyud_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 1>;
2199 def M2_mpyud_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 1>;
2200 def M2_mpyud_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 1>;
2201 def M2_mpyud_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 1>;
2203 def M2_mpyud_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 1>;
2204 def M2_mpyud_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 1>;
2205 def M2_mpyud_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 1>;
2206 def M2_mpyud_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 1>;
2208 def M2_mpyud_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 1>;
2209 def M2_mpyud_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 1>;
2210 def M2_mpyud_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 1>;
2211 def M2_mpyud_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 1>;
2213 def M2_mpyud_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 1>;
2214 def M2_mpyud_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 1>;
2215 def M2_mpyud_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 1>;
2216 def M2_mpyud_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 1>;
2219 let hasNewValue = 1, opNewValue = 0 in
2220 class T_MType_mpy <string mnemonic, bits<4> RegTyBits, RegisterClass RC,
2221 bits<3> MajOp, bits<3> MinOp, bit isSat = 0, bit isRnd = 0,
2222 string op2Suffix = "", bit isRaw = 0, bit isHi = 0 >
2223 : MInst <(outs IntRegs:$dst), (ins RC:$src1, RC:$src2),
2225 #"($src1, $src2"#op2Suffix#")"
2226 #!if(MajOp{2}, ":<<1", "")
2227 #!if(isRnd, ":rnd", "")
2228 #!if(isSat, ":sat", "")
2229 #!if(isRaw, !if(isHi, ":raw:hi", ":raw:lo"), ""), [] > {
2234 let IClass = 0b1110;
2236 let Inst{27-24} = RegTyBits;
2237 let Inst{23-21} = MajOp;
2238 let Inst{20-16} = src1;
2240 let Inst{12-8} = src2;
2241 let Inst{7-5} = MinOp;
2242 let Inst{4-0} = dst;
2245 class T_MType_dd <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2246 bit isSat = 0, bit isRnd = 0 >
2247 : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, isSat, isRnd>;
2249 class T_MType_rr1 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2250 bit isSat = 0, bit isRnd = 0 >
2251 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd>;
2253 class T_MType_rr2 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2254 bit isSat = 0, bit isRnd = 0, string op2str = "" >
2255 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd, op2str>;
2257 let CextOpcode = "mpyi", InputType = "reg", isCodeGenOnly = 0 in
2258 def M2_mpyi : T_MType_rr1 <"mpyi", 0b000, 0b000>, ImmRegRel;
2260 let isCodeGenOnly = 0 in {
2261 def M2_mpy_up : T_MType_rr1 <"mpy", 0b000, 0b001>;
2262 def M2_mpyu_up : T_MType_rr1 <"mpyu", 0b010, 0b001>;
2265 let isCodeGenOnly = 0 in
2266 def M2_dpmpyss_rnd_s0 : T_MType_rr1 <"mpy", 0b001, 0b001, 0, 1>;
2268 let isCodeGenOnly = 0 in {
2269 def M2_hmmpyh_rs1 : T_MType_rr2 <"mpy", 0b101, 0b100, 1, 1, ".h">;
2270 def M2_hmmpyl_rs1 : T_MType_rr2 <"mpy", 0b111, 0b100, 1, 1, ".l">;
2274 let isCodeGenOnly = 0 in {
2275 def M2_mpysu_up : T_MType_rr1 <"mpysu", 0b011, 0b001, 0>;
2276 def M2_mpy_up_s1_sat : T_MType_rr1 <"mpy", 0b111, 0b000, 1>;
2278 def M2_hmmpyh_s1 : T_MType_rr2 <"mpy", 0b101, 0b000, 1, 0, ".h">;
2279 def M2_hmmpyl_s1 : T_MType_rr2 <"mpy", 0b101, 0b001, 1, 0, ".l">;
2282 def: Pat<(i32 (mul I32:$src1, I32:$src2)), (M2_mpyi I32:$src1, I32:$src2)>;
2283 def: Pat<(i32 (mulhs I32:$src1, I32:$src2)), (M2_mpy_up I32:$src1, I32:$src2)>;
2284 def: Pat<(i32 (mulhu I32:$src1, I32:$src2)), (M2_mpyu_up I32:$src1, I32:$src2)>;
2286 let hasNewValue = 1, opNewValue = 0 in
2287 class T_MType_mpy_ri <bit isNeg, Operand ImmOp, list<dag> pattern>
2288 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, ImmOp:$u8),
2289 "$Rd ="#!if(isNeg, "- ", "+ ")#"mpyi($Rs, #$u8)" ,
2290 pattern, "", M_tc_3x_SLOT23> {
2295 let IClass = 0b1110;
2297 let Inst{27-24} = 0b0000;
2298 let Inst{23} = isNeg;
2301 let Inst{20-16} = Rs;
2302 let Inst{12-5} = u8;
2305 let isExtendable = 1, opExtentBits = 8, opExtendable = 2, isCodeGenOnly = 0 in
2306 def M2_mpysip : T_MType_mpy_ri <0, u8Ext,
2307 [(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u8ExtPred:$u8))]>;
2309 let isCodeGenOnly = 0 in
2310 def M2_mpysin : T_MType_mpy_ri <1, u8Imm,
2311 [(set (i32 IntRegs:$Rd), (ineg (mul IntRegs:$Rs,
2314 // Assember mapped to M2_mpyi
2315 let isAsmParserOnly = 1 in
2316 def M2_mpyui : MInst<(outs IntRegs:$dst),
2317 (ins IntRegs:$src1, IntRegs:$src2),
2318 "$dst = mpyui($src1, $src2)">;
2321 // s9 is NOT the same as m9 - but it works.. so far.
2322 // Assembler maps to either Rd=+mpyi(Rs,#u8) or Rd=-mpyi(Rs,#u8)
2323 // depending on the value of m9. See Arch Spec.
2324 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
2325 CextOpcode = "mpyi", InputType = "imm", hasNewValue = 1 in
2326 def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
2327 "$dst = mpyi($src1, #$src2)",
2328 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
2329 s9ExtPred:$src2))]>, ImmRegRel;
2331 let hasNewValue = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 3,
2332 InputType = "imm" in
2333 class T_MType_acc_ri <string mnemonic, bits<3> MajOp, Operand ImmOp,
2334 list<dag> pattern = []>
2335 : MInst < (outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, ImmOp:$src3),
2336 "$dst "#mnemonic#"($src2, #$src3)",
2337 pattern, "$src1 = $dst", M_tc_2_SLOT23> {
2342 let IClass = 0b1110;
2344 let Inst{27-26} = 0b00;
2345 let Inst{25-23} = MajOp;
2346 let Inst{20-16} = src2;
2348 let Inst{12-5} = src3;
2349 let Inst{4-0} = dst;
2352 let InputType = "reg", hasNewValue = 1 in
2353 class T_MType_acc_rr <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2354 bit isSwap = 0, list<dag> pattern = [], bit hasNot = 0,
2355 bit isSat = 0, bit isShift = 0>
2356 : MInst < (outs IntRegs:$dst),
2357 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2358 "$dst "#mnemonic#"($src2, "#!if(hasNot, "~$src3)","$src3)")
2359 #!if(isShift, ":<<1", "")
2360 #!if(isSat, ":sat", ""),
2361 pattern, "$src1 = $dst", M_tc_2_SLOT23 > {
2366 let IClass = 0b1110;
2368 let Inst{27-24} = 0b1111;
2369 let Inst{23-21} = MajOp;
2370 let Inst{20-16} = !if(isSwap, src3, src2);
2372 let Inst{12-8} = !if(isSwap, src2, src3);
2373 let Inst{7-5} = MinOp;
2374 let Inst{4-0} = dst;
2377 let CextOpcode = "MPYI_acc", Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in {
2378 def M2_macsip : T_MType_acc_ri <"+= mpyi", 0b010, u8Ext,
2379 [(set (i32 IntRegs:$dst),
2380 (add (mul IntRegs:$src2, u8ExtPred:$src3),
2381 IntRegs:$src1))]>, ImmRegRel;
2383 def M2_maci : T_MType_acc_rr <"+= mpyi", 0b000, 0b000, 0,
2384 [(set (i32 IntRegs:$dst),
2385 (add (mul IntRegs:$src2, IntRegs:$src3),
2386 IntRegs:$src1))]>, ImmRegRel;
2389 let CextOpcode = "ADD_acc", isCodeGenOnly = 0 in {
2390 let isExtentSigned = 1 in
2391 def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8Ext,
2392 [(set (i32 IntRegs:$dst),
2393 (add (add (i32 IntRegs:$src2), s8_16ExtPred:$src3),
2394 (i32 IntRegs:$src1)))]>, ImmRegRel;
2396 def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0,
2397 [(set (i32 IntRegs:$dst),
2398 (add (add (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
2399 (i32 IntRegs:$src1)))]>, ImmRegRel;
2402 let CextOpcode = "SUB_acc", isCodeGenOnly = 0 in {
2403 let isExtentSigned = 1 in
2404 def M2_naccii : T_MType_acc_ri <"-= add", 0b101, s8Ext>, ImmRegRel;
2406 def M2_nacci : T_MType_acc_rr <"-= add", 0b100, 0b001, 0>, ImmRegRel;
2409 let Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in
2410 def M2_macsin : T_MType_acc_ri <"-= mpyi", 0b011, u8Ext>;
2412 let isCodeGenOnly = 0 in {
2413 def M2_xor_xacc : T_MType_acc_rr < "^= xor", 0b100, 0b011, 0>;
2414 def M2_subacc : T_MType_acc_rr <"+= sub", 0b000, 0b011, 1>;
2417 class T_MType_acc_pat1 <InstHexagon MI, SDNode firstOp, SDNode secOp,
2419 : Pat <(secOp IntRegs:$src1, (firstOp IntRegs:$src2, ImmPred:$src3)),
2420 (MI IntRegs:$src1, IntRegs:$src2, ImmPred:$src3)>;
2422 class T_MType_acc_pat2 <InstHexagon MI, SDNode firstOp, SDNode secOp>
2423 : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2, IntRegs:$src3))),
2424 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2426 def : T_MType_acc_pat2 <M2_xor_xacc, xor, xor>;
2427 def : T_MType_acc_pat1 <M2_macsin, mul, sub, u8ExtPred>;
2429 def : T_MType_acc_pat1 <M2_naccii, add, sub, s8_16ExtPred>;
2430 def : T_MType_acc_pat2 <M2_nacci, add, sub>;
2431 //===----------------------------------------------------------------------===//
2432 // Template Class -- Multiply signed/unsigned halfwords with and without
2433 // saturation and rounding
2434 //===----------------------------------------------------------------------===//
2435 class T_M2_mpyd < bits<2> LHbits, bit isRnd, bit hasShift, bit isUnsigned >
2436 : MInst < (outs DoubleRegs:$Rdd), (ins IntRegs:$Rs, IntRegs:$Rt),
2437 "$Rdd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
2438 #", $Rt."#!if(LHbits{0},"h)","l)")
2439 #!if(hasShift,":<<1","")
2440 #!if(isRnd,":rnd",""),
2446 let IClass = 0b1110;
2448 let Inst{27-24} = 0b0100;
2449 let Inst{23} = hasShift;
2450 let Inst{22} = isUnsigned;
2451 let Inst{21} = isRnd;
2452 let Inst{6-5} = LHbits;
2453 let Inst{4-0} = Rdd;
2454 let Inst{20-16} = Rs;
2455 let Inst{12-8} = Rt;
2458 let isCodeGenOnly = 0 in {
2459 def M2_mpyd_hh_s0: T_M2_mpyd<0b11, 0, 0, 0>;
2460 def M2_mpyd_hl_s0: T_M2_mpyd<0b10, 0, 0, 0>;
2461 def M2_mpyd_lh_s0: T_M2_mpyd<0b01, 0, 0, 0>;
2462 def M2_mpyd_ll_s0: T_M2_mpyd<0b00, 0, 0, 0>;
2464 def M2_mpyd_hh_s1: T_M2_mpyd<0b11, 0, 1, 0>;
2465 def M2_mpyd_hl_s1: T_M2_mpyd<0b10, 0, 1, 0>;
2466 def M2_mpyd_lh_s1: T_M2_mpyd<0b01, 0, 1, 0>;
2467 def M2_mpyd_ll_s1: T_M2_mpyd<0b00, 0, 1, 0>;
2469 def M2_mpyd_rnd_hh_s0: T_M2_mpyd<0b11, 1, 0, 0>;
2470 def M2_mpyd_rnd_hl_s0: T_M2_mpyd<0b10, 1, 0, 0>;
2471 def M2_mpyd_rnd_lh_s0: T_M2_mpyd<0b01, 1, 0, 0>;
2472 def M2_mpyd_rnd_ll_s0: T_M2_mpyd<0b00, 1, 0, 0>;
2474 def M2_mpyd_rnd_hh_s1: T_M2_mpyd<0b11, 1, 1, 0>;
2475 def M2_mpyd_rnd_hl_s1: T_M2_mpyd<0b10, 1, 1, 0>;
2476 def M2_mpyd_rnd_lh_s1: T_M2_mpyd<0b01, 1, 1, 0>;
2477 def M2_mpyd_rnd_ll_s1: T_M2_mpyd<0b00, 1, 1, 0>;
2479 //Rdd=mpyu(Rs.[HL],Rt.[HL])[:<<1]
2480 def M2_mpyud_hh_s0: T_M2_mpyd<0b11, 0, 0, 1>;
2481 def M2_mpyud_hl_s0: T_M2_mpyd<0b10, 0, 0, 1>;
2482 def M2_mpyud_lh_s0: T_M2_mpyd<0b01, 0, 0, 1>;
2483 def M2_mpyud_ll_s0: T_M2_mpyd<0b00, 0, 0, 1>;
2485 def M2_mpyud_hh_s1: T_M2_mpyd<0b11, 0, 1, 1>;
2486 def M2_mpyud_hl_s1: T_M2_mpyd<0b10, 0, 1, 1>;
2487 def M2_mpyud_lh_s1: T_M2_mpyd<0b01, 0, 1, 1>;
2488 def M2_mpyud_ll_s1: T_M2_mpyd<0b00, 0, 1, 1>;
2490 //===----------------------------------------------------------------------===//
2491 // Template Class for xtype mpy:
2494 // multiply 32X32 and use full result
2495 //===----------------------------------------------------------------------===//
2496 let hasSideEffects = 0 in
2497 class T_XTYPE_mpy64 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2498 bit isSat, bit hasShift, bit isConj>
2499 : MInst <(outs DoubleRegs:$Rdd),
2500 (ins IntRegs:$Rs, IntRegs:$Rt),
2501 "$Rdd = "#mnemonic#"($Rs, $Rt"#!if(isConj,"*)",")")
2502 #!if(hasShift,":<<1","")
2503 #!if(isSat,":sat",""),
2509 let IClass = 0b1110;
2511 let Inst{27-24} = 0b0101;
2512 let Inst{23-21} = MajOp;
2513 let Inst{20-16} = Rs;
2514 let Inst{12-8} = Rt;
2515 let Inst{7-5} = MinOp;
2516 let Inst{4-0} = Rdd;
2519 //===----------------------------------------------------------------------===//
2520 // Template Class for xtype mpy with accumulation into 64-bit:
2523 // multiply 32X32 and use full result
2524 //===----------------------------------------------------------------------===//
2525 class T_XTYPE_mpy64_acc <string op1, string op2, bits<3> MajOp, bits<3> MinOp,
2526 bit isSat, bit hasShift, bit isConj>
2527 : MInst <(outs DoubleRegs:$Rxx),
2528 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2529 "$Rxx "#op2#"= "#op1#"($Rs, $Rt"#!if(isConj,"*)",")")
2530 #!if(hasShift,":<<1","")
2531 #!if(isSat,":sat",""),
2533 [] , "$dst2 = $Rxx" > {
2538 let IClass = 0b1110;
2540 let Inst{27-24} = 0b0111;
2541 let Inst{23-21} = MajOp;
2542 let Inst{20-16} = Rs;
2543 let Inst{12-8} = Rt;
2544 let Inst{7-5} = MinOp;
2545 let Inst{4-0} = Rxx;
2548 // MPY - Multiply and use full result
2549 // Rdd = mpy[u](Rs,Rt)
2550 let isCodeGenOnly = 0 in {
2551 def M2_dpmpyss_s0 : T_XTYPE_mpy64 < "mpy", 0b000, 0b000, 0, 0, 0>;
2552 def M2_dpmpyuu_s0 : T_XTYPE_mpy64 < "mpyu", 0b010, 0b000, 0, 0, 0>;
2554 // Rxx[+-]= mpy[u](Rs,Rt)
2555 def M2_dpmpyss_acc_s0 : T_XTYPE_mpy64_acc < "mpy", "+", 0b000, 0b000, 0, 0, 0>;
2556 def M2_dpmpyss_nac_s0 : T_XTYPE_mpy64_acc < "mpy", "-", 0b001, 0b000, 0, 0, 0>;
2557 def M2_dpmpyuu_acc_s0 : T_XTYPE_mpy64_acc < "mpyu", "+", 0b010, 0b000, 0, 0, 0>;
2558 def M2_dpmpyuu_nac_s0 : T_XTYPE_mpy64_acc < "mpyu", "-", 0b011, 0b000, 0, 0, 0>;
2561 def: Pat<(i64 (mul (i64 (anyext (i32 IntRegs:$src1))),
2562 (i64 (anyext (i32 IntRegs:$src2))))),
2563 (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>;
2565 def: Pat<(i64 (mul (i64 (sext (i32 IntRegs:$src1))),
2566 (i64 (sext (i32 IntRegs:$src2))))),
2567 (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>;
2569 def: Pat<(i64 (mul (is_sext_i32:$src1),
2570 (is_sext_i32:$src2))),
2571 (M2_dpmpyss_s0 (LoReg DoubleRegs:$src1), (LoReg DoubleRegs:$src2))>;
2573 // Multiply and accumulate, use full result.
2574 // Rxx[+-]=mpy(Rs,Rt)
2576 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
2577 (mul (i64 (sext (i32 IntRegs:$src2))),
2578 (i64 (sext (i32 IntRegs:$src3)))))),
2579 (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2581 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
2582 (mul (i64 (sext (i32 IntRegs:$src2))),
2583 (i64 (sext (i32 IntRegs:$src3)))))),
2584 (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2586 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
2587 (mul (i64 (anyext (i32 IntRegs:$src2))),
2588 (i64 (anyext (i32 IntRegs:$src3)))))),
2589 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2591 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
2592 (mul (i64 (zext (i32 IntRegs:$src2))),
2593 (i64 (zext (i32 IntRegs:$src3)))))),
2594 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2596 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
2597 (mul (i64 (anyext (i32 IntRegs:$src2))),
2598 (i64 (anyext (i32 IntRegs:$src3)))))),
2599 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2601 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
2602 (mul (i64 (zext (i32 IntRegs:$src2))),
2603 (i64 (zext (i32 IntRegs:$src3)))))),
2604 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2606 //===----------------------------------------------------------------------===//
2608 //===----------------------------------------------------------------------===//
2610 //===----------------------------------------------------------------------===//
2612 //===----------------------------------------------------------------------===//
2613 //===----------------------------------------------------------------------===//
2615 //===----------------------------------------------------------------------===//
2617 //===----------------------------------------------------------------------===//
2619 //===----------------------------------------------------------------------===//
2620 //===----------------------------------------------------------------------===//
2622 //===----------------------------------------------------------------------===//
2624 //===----------------------------------------------------------------------===//
2626 //===----------------------------------------------------------------------===//
2627 //===----------------------------------------------------------------------===//
2629 //===----------------------------------------------------------------------===//
2631 //===----------------------------------------------------------------------===//
2633 //===----------------------------------------------------------------------===//
2635 // Store doubleword.
2636 //===----------------------------------------------------------------------===//
2637 // Template class for non-predicated post increment stores with immediate offset
2638 //===----------------------------------------------------------------------===//
2639 let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc in
2640 class T_store_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
2641 bits<4> MajOp, bit isHalf >
2642 : STInst <(outs IntRegs:$_dst_),
2643 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
2644 mnemonic#"($src1++#$offset) = $src2"#!if(isHalf, ".h", ""),
2645 [], "$src1 = $_dst_" >,
2652 string ImmOpStr = !cast<string>(ImmOp);
2653 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
2654 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
2655 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
2656 /* s4_0Imm */ offset{3-0})));
2657 let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
2659 let IClass = 0b1010;
2661 let Inst{27-25} = 0b101;
2662 let Inst{24-21} = MajOp;
2663 let Inst{20-16} = src1;
2665 let Inst{12-8} = src2;
2667 let Inst{6-3} = offsetBits;
2671 //===----------------------------------------------------------------------===//
2672 // Template class for predicated post increment stores with immediate offset
2673 //===----------------------------------------------------------------------===//
2674 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
2675 class T_pstore_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
2676 bits<4> MajOp, bit isHalf, bit isPredNot, bit isPredNew >
2677 : STInst <(outs IntRegs:$_dst_),
2678 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
2679 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2680 ") ")#mnemonic#"($src2++#$offset) = $src3"#!if(isHalf, ".h", ""),
2681 [], "$src2 = $_dst_" >,
2689 string ImmOpStr = !cast<string>(ImmOp);
2690 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
2691 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
2692 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
2693 /* s4_0Imm */ offset{3-0})));
2695 let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
2696 let isPredicatedNew = isPredNew;
2697 let isPredicatedFalse = isPredNot;
2699 let IClass = 0b1010;
2701 let Inst{27-25} = 0b101;
2702 let Inst{24-21} = MajOp;
2703 let Inst{20-16} = src2;
2705 let Inst{12-8} = src3;
2706 let Inst{7} = isPredNew;
2707 let Inst{6-3} = offsetBits;
2708 let Inst{2} = isPredNot;
2709 let Inst{1-0} = src1;
2712 multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
2713 Operand ImmOp, bits<4> MajOp, bit isHalf = 0 > {
2715 let BaseOpcode = "POST_"#BaseOp in {
2716 def S2_#NAME#_pi : T_store_pi <mnemonic, RC, ImmOp, MajOp, isHalf>;
2719 def S2_p#NAME#t_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 0, 0>;
2720 def S2_p#NAME#f_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 1, 0>;
2723 def S2_p#NAME#tnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp,
2725 def S2_p#NAME#fnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp,
2730 let accessSize = ByteAccess, isCodeGenOnly = 0 in
2731 defm storerb: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm, 0b1000>;
2733 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in
2734 defm storerh: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm, 0b1010>;
2736 let accessSize = WordAccess, isCodeGenOnly = 0 in
2737 defm storeri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm, 0b1100>;
2739 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
2740 defm storerd: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm, 0b1110>;
2742 let accessSize = HalfWordAccess, isNVStorable = 0, isCodeGenOnly = 0 in
2743 defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>;
2745 // Patterns for generating stores, where the address takes different forms:
2748 // - simple (base address without offset).
2749 // These would usually be used together (via Storex_pat defined below), but
2750 // in some cases one may want to apply different properties (such as
2751 // AddedComplexity) to the individual patterns.
2752 class Storex_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
2753 : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>;
2754 class Storex_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
2756 : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
2757 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
2759 multiclass Storex_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
2761 def: Storex_fi_pat <Store, Value, MI>;
2762 def: Storex_add_pat <Store, Value, ImmPred, MI>;
2765 def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2,
2766 s4_3ImmPred:$offset),
2767 (S2_storerb_pi IntRegs:$src2, s4_0ImmPred:$offset, IntRegs:$src1)>;
2769 def : Pat<(post_truncsti16 (i32 IntRegs:$src1), IntRegs:$src2,
2770 s4_3ImmPred:$offset),
2771 (S2_storerh_pi IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
2773 def : Pat<(post_store (i32 IntRegs:$src1), IntRegs:$src2, s4_2ImmPred:$offset),
2774 (S2_storeri_pi IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
2776 def : Pat<(post_store (i64 DoubleRegs:$src1), IntRegs:$src2,
2777 s4_3ImmPred:$offset),
2778 (S2_storerd_pi IntRegs:$src2, s4_3ImmPred:$offset, DoubleRegs:$src1)>;
2780 //===----------------------------------------------------------------------===//
2781 // Template class for post increment stores with register offset.
2782 //===----------------------------------------------------------------------===//
2783 let isNVStorable = 1 in
2784 class T_store_pr <string mnemonic, RegisterClass RC, bits<3> MajOp,
2785 MemAccessSize AccessSz, bit isHalf = 0>
2786 : STInst <(outs IntRegs:$_dst_),
2787 (ins IntRegs:$src1, ModRegs:$src2, RC:$src3),
2788 mnemonic#"($src1++$src2) = $src3"#!if(isHalf, ".h", ""),
2789 [], "$src1 = $_dst_" > {
2793 let accessSize = AccessSz;
2795 let IClass = 0b1010;
2797 let Inst{27-24} = 0b1101;
2798 let Inst{23-21} = MajOp;
2799 let Inst{20-16} = src1;
2800 let Inst{13} = src2;
2801 let Inst{12-8} = src3;
2805 let isCodeGenOnly = 0 in {
2806 def S2_storerb_pr : T_store_pr<"memb", IntRegs, 0b000, ByteAccess>;
2807 def S2_storerh_pr : T_store_pr<"memh", IntRegs, 0b010, HalfWordAccess>;
2808 def S2_storeri_pr : T_store_pr<"memw", IntRegs, 0b100, WordAccess>;
2809 def S2_storerd_pr : T_store_pr<"memd", DoubleRegs, 0b110, DoubleWordAccess>;
2811 def S2_storerf_pr : T_store_pr<"memh", IntRegs, 0b011, HalfWordAccess, 1>;
2813 let opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
2814 class T_store_io <string mnemonic, RegisterClass RC, Operand ImmOp,
2815 bits<3>MajOp, bit isH = 0>
2817 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
2818 mnemonic#"($src1+#$src2) = $src3"#!if(isH,".h","")>,
2819 AddrModeRel, ImmRegRel {
2821 bits<14> src2; // Actual address offset
2823 bits<11> offsetBits; // Represents offset encoding
2825 string ImmOpStr = !cast<string>(ImmOp);
2827 let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14,
2828 !if (!eq(ImmOpStr, "s11_2Ext"), 13,
2829 !if (!eq(ImmOpStr, "s11_1Ext"), 12,
2830 /* s11_0Ext */ 11)));
2831 let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), src2{13-3},
2832 !if (!eq(ImmOpStr, "s11_2Ext"), src2{12-2},
2833 !if (!eq(ImmOpStr, "s11_1Ext"), src2{11-1},
2834 /* s11_0Ext */ src2{10-0})));
2835 let IClass = 0b1010;
2838 let Inst{26-25} = offsetBits{10-9};
2840 let Inst{23-21} = MajOp;
2841 let Inst{20-16} = src1;
2842 let Inst{13} = offsetBits{8};
2843 let Inst{12-8} = src3;
2844 let Inst{7-0} = offsetBits{7-0};
2847 let opExtendable = 2, isPredicated = 1 in
2848 class T_pstore_io <string mnemonic, RegisterClass RC, Operand ImmOp,
2849 bits<3>MajOp, bit PredNot, bit isPredNew, bit isH = 0>
2851 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
2852 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2853 ") ")#mnemonic#"($src2+#$src3) = $src4"#!if(isH,".h",""),
2854 [],"",V2LDST_tc_st_SLOT01 >,
2855 AddrModeRel, ImmRegRel {
2858 bits<9> src3; // Actual address offset
2860 bits<6> offsetBits; // Represents offset encoding
2862 let isPredicatedNew = isPredNew;
2863 let isPredicatedFalse = PredNot;
2865 string ImmOpStr = !cast<string>(ImmOp);
2866 let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9,
2867 !if (!eq(ImmOpStr, "u6_2Ext"), 8,
2868 !if (!eq(ImmOpStr, "u6_1Ext"), 7,
2870 let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), src3{8-3},
2871 !if (!eq(ImmOpStr, "u6_2Ext"), src3{7-2},
2872 !if (!eq(ImmOpStr, "u6_1Ext"), src3{6-1},
2873 /* u6_0Ext */ src3{5-0})));
2874 let IClass = 0b0100;
2877 let Inst{26} = PredNot;
2878 let Inst{25} = isPredNew;
2880 let Inst{23-21} = MajOp;
2881 let Inst{20-16} = src2;
2882 let Inst{13} = offsetBits{5};
2883 let Inst{12-8} = src4;
2884 let Inst{7-3} = offsetBits{4-0};
2885 let Inst{1-0} = src1;
2888 let isExtendable = 1, isNVStorable = 1, hasSideEffects = 0 in
2889 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
2890 Operand ImmOp, Operand predImmOp, bits<3> MajOp, bit isH = 0> {
2891 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
2892 def S2_#NAME#_io : T_store_io <mnemonic, RC, ImmOp, MajOp, isH>;
2895 def S2_p#NAME#t_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 0, 0, isH>;
2896 def S2_p#NAME#f_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 1, 0, isH>;
2899 def S4_p#NAME#tnew_io : T_pstore_io <mnemonic, RC, predImmOp,
2901 def S4_p#NAME#fnew_io : T_pstore_io <mnemonic, RC, predImmOp,
2906 let addrMode = BaseImmOffset, InputType = "imm", isCodeGenOnly = 0 in {
2907 let accessSize = ByteAccess in
2908 defm storerb: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext, u6_0Ext, 0b000>;
2910 let accessSize = HalfWordAccess, opExtentAlign = 1 in
2911 defm storerh: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext, u6_1Ext, 0b010>;
2913 let accessSize = WordAccess, opExtentAlign = 2 in
2914 defm storeri: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext, u6_2Ext, 0b100>;
2916 let accessSize = DoubleWordAccess, isNVStorable = 0, opExtentAlign = 3 in
2917 defm storerd: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
2920 let accessSize = HalfWordAccess, opExtentAlign = 1 in
2921 defm storerf: ST_Idxd < "memh", "STrif", IntRegs, s11_1Ext,
2925 class Storex_simple_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
2926 : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)),
2927 (MI IntRegs:$Rs, 0, Value:$Rt)>;
2929 // Regular stores in the DAG have two operands: value and address.
2930 // Atomic stores also have two, but they are reversed: address, value.
2931 // To use atomic stores with the patterns, they need to have their operands
2932 // swapped. This relies on the knowledge that the F.Fragment uses names
2934 class SwapSt<PatFrag F>
2935 : PatFrag<(ops node:$val, node:$ptr), F.Fragment>;
2937 def: Storex_simple_pat<SwapSt<atomic_store_8>, I32, S2_storerb_io>;
2938 def: Storex_simple_pat<SwapSt<atomic_store_16>, I32, S2_storerh_io>;
2939 def: Storex_simple_pat<SwapSt<atomic_store_32>, I32, S2_storeri_io>;
2940 def: Storex_simple_pat<SwapSt<atomic_store_64>, I64, S2_storerd_io>;
2942 def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
2943 (S2_storerb_io AddrFI:$addr, 0, (i32 IntRegs:$src1))>;
2945 def : Pat<(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr),
2946 (S2_storerh_io AddrFI:$addr, 0, (i32 IntRegs:$src1))>;
2948 def : Pat<(store (i32 IntRegs:$src1), ADDRriS11_2:$addr),
2949 (S2_storeri_io AddrFI:$addr, 0, (i32 IntRegs:$src1))>;
2951 def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
2952 (S2_storerd_io AddrFI:$addr, 0, (i64 DoubleRegs:$src1))>;
2955 let AddedComplexity = 10 in {
2956 def : Pat<(truncstorei8 (i32 IntRegs:$src1), (add IntRegs:$src2,
2957 s11_0ExtPred:$offset)),
2958 (S2_storerb_io IntRegs:$src2, s11_0ImmPred:$offset,
2959 (i32 IntRegs:$src1))>;
2961 def : Pat<(truncstorei16 (i32 IntRegs:$src1), (add IntRegs:$src2,
2962 s11_1ExtPred:$offset)),
2963 (S2_storerh_io IntRegs:$src2, s11_1ImmPred:$offset,
2964 (i32 IntRegs:$src1))>;
2966 def : Pat<(store (i32 IntRegs:$src1), (add IntRegs:$src2,
2967 s11_2ExtPred:$offset)),
2968 (S2_storeri_io IntRegs:$src2, s11_2ImmPred:$offset,
2969 (i32 IntRegs:$src1))>;
2971 def : Pat<(store (i64 DoubleRegs:$src1), (add IntRegs:$src2,
2972 s11_3ExtPred:$offset)),
2973 (S2_storerd_io IntRegs:$src2, s11_3ImmPred:$offset,
2974 (i64 DoubleRegs:$src1))>;
2977 // memh(Rx++#s4:1)=Rt.H
2980 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
2981 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
2982 def STriw_pred : STInst<(outs),
2983 (ins IntRegs:$addr, s11_2Ext:$off, PredRegs:$src1),
2984 ".error \"should not emit\"", []>;
2986 // S2_allocframe: Allocate stack frame.
2987 let Defs = [R29, R30], Uses = [R29, R31, R30],
2988 hasSideEffects = 0, accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
2989 def S2_allocframe: ST0Inst <
2990 (outs), (ins u11_3Imm:$u11_3),
2991 "allocframe(#$u11_3)" > {
2994 let IClass = 0b1010;
2995 let Inst{27-16} = 0b000010011101;
2996 let Inst{13-11} = 0b000;
2997 let Inst{10-0} = u11_3{13-3};
3000 // S2_storer[bhwdf]_pci: Store byte/half/word/double.
3001 // S2_storer[bhwdf]_pci -> S2_storerbnew_pci
3002 let Uses = [CS], isNVStorable = 1 in
3003 class T_store_pci <string mnemonic, RegisterClass RC,
3004 Operand Imm, bits<4>MajOp,
3005 MemAccessSize AlignSize, string RegSrc = "Rt">
3006 : STInst <(outs IntRegs:$_dst_),
3007 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, RC:$Rt),
3008 #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $"#RegSrc#"",
3015 let accessSize = AlignSize;
3017 let IClass = 0b1010;
3018 let Inst{27-25} = 0b100;
3019 let Inst{24-21} = MajOp;
3020 let Inst{20-16} = Rz;
3022 let Inst{12-8} = Rt;
3025 !if (!eq(!cast<string>(AlignSize), "DoubleWordAccess"), offset{6-3},
3026 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
3027 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
3028 /* ByteAccess */ offset{3-0})));
3032 let isCodeGenOnly = 0 in {
3033 def S2_storerb_pci : T_store_pci<"memb", IntRegs, s4_0Imm, 0b1000,
3035 def S2_storerh_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1010,
3037 def S2_storerf_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1011,
3038 HalfWordAccess, "Rt.h">;
3039 def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100,
3041 def S2_storerd_pci : T_store_pci<"memd", DoubleRegs, s4_3Imm, 0b1110,
3045 let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 4 in
3046 class T_storenew_pci <string mnemonic, Operand Imm,
3047 bits<2>MajOp, MemAccessSize AlignSize>
3048 : NVInst < (outs IntRegs:$_dst_),
3049 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, IntRegs:$Nt),
3050 #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $Nt.new",
3058 let accessSize = AlignSize;
3060 let IClass = 0b1010;
3061 let Inst{27-21} = 0b1001101;
3062 let Inst{20-16} = Rz;
3064 let Inst{12-11} = MajOp;
3065 let Inst{10-8} = Nt;
3068 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
3069 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
3070 /* ByteAccess */ offset{3-0}));
3073 let isCodeGenOnly = 0 in {
3074 def S2_storerbnew_pci : T_storenew_pci <"memb", s4_0Imm, 0b00, ByteAccess>;
3075 def S2_storerhnew_pci : T_storenew_pci <"memh", s4_1Imm, 0b01, HalfWordAccess>;
3076 def S2_storerinew_pci : T_storenew_pci <"memw", s4_2Imm, 0b10, WordAccess>;
3079 //===----------------------------------------------------------------------===//
3080 // Circular stores with auto-increment register
3081 //===----------------------------------------------------------------------===//
3082 let Uses = [CS], isNVStorable = 1, isCodeGenOnly = 0 in
3083 class T_store_pcr <string mnemonic, RegisterClass RC, bits<4>MajOp,
3084 MemAccessSize AlignSize, string RegSrc = "Rt">
3085 : STInst <(outs IntRegs:$_dst_),
3086 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$Rt),
3087 #mnemonic#"($Rz ++ I:circ($Mu)) = $"#RegSrc#"",
3094 let accessSize = AlignSize;
3096 let IClass = 0b1010;
3097 let Inst{27-25} = 0b100;
3098 let Inst{24-21} = MajOp;
3099 let Inst{20-16} = Rz;
3101 let Inst{12-8} = Rt;
3106 let isCodeGenOnly = 0 in {
3107 def S2_storerb_pcr : T_store_pcr<"memb", IntRegs, 0b1000, ByteAccess>;
3108 def S2_storerh_pcr : T_store_pcr<"memh", IntRegs, 0b1010, HalfWordAccess>;
3109 def S2_storeri_pcr : T_store_pcr<"memw", IntRegs, 0b1100, WordAccess>;
3110 def S2_storerd_pcr : T_store_pcr<"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
3111 def S2_storerf_pcr : T_store_pcr<"memh", IntRegs, 0b1011,
3112 HalfWordAccess, "Rt.h">;
3115 //===----------------------------------------------------------------------===//
3116 // Circular .new stores with auto-increment register
3117 //===----------------------------------------------------------------------===//
3118 let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
3119 class T_storenew_pcr <string mnemonic, bits<2>MajOp,
3120 MemAccessSize AlignSize>
3121 : NVInst <(outs IntRegs:$_dst_),
3122 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3123 #mnemonic#"($Rz ++ I:circ($Mu)) = $Nt.new" ,
3130 let accessSize = AlignSize;
3132 let IClass = 0b1010;
3133 let Inst{27-21} = 0b1001101;
3134 let Inst{20-16} = Rz;
3136 let Inst{12-11} = MajOp;
3137 let Inst{10-8} = Nt;
3142 let isCodeGenOnly = 0 in {
3143 def S2_storerbnew_pcr : T_storenew_pcr <"memb", 0b00, ByteAccess>;
3144 def S2_storerhnew_pcr : T_storenew_pcr <"memh", 0b01, HalfWordAccess>;
3145 def S2_storerinew_pcr : T_storenew_pcr <"memw", 0b10, WordAccess>;
3148 //===----------------------------------------------------------------------===//
3149 // Bit-reversed stores with auto-increment register
3150 //===----------------------------------------------------------------------===//
3151 let hasSideEffects = 0 in
3152 class T_store_pbr<string mnemonic, RegisterClass RC,
3153 MemAccessSize addrSize, bits<3> majOp,
3156 <(outs IntRegs:$_dst_),
3157 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$src),
3158 #mnemonic#"($Rz ++ $Mu:brev) = $src"#!if (!eq(isHalf, 1), ".h", ""),
3159 [], "$Rz = $_dst_" > {
3161 let accessSize = addrSize;
3167 let IClass = 0b1010;
3169 let Inst{27-24} = 0b1111;
3170 let Inst{23-21} = majOp;
3172 let Inst{20-16} = Rz;
3174 let Inst{12-8} = src;
3177 let isNVStorable = 1, isCodeGenOnly = 0 in {
3178 let BaseOpcode = "S2_storerb_pbr" in
3179 def S2_storerb_pbr : T_store_pbr<"memb", IntRegs, ByteAccess,
3180 0b000>, NewValueRel;
3181 let BaseOpcode = "S2_storerh_pbr" in
3182 def S2_storerh_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess,
3183 0b010>, NewValueRel;
3184 let BaseOpcode = "S2_storeri_pbr" in
3185 def S2_storeri_pbr : T_store_pbr<"memw", IntRegs, WordAccess,
3186 0b100>, NewValueRel;
3188 let isCodeGenOnly = 0 in {
3189 def S2_storerf_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess, 0b011, 1>;
3190 def S2_storerd_pbr : T_store_pbr<"memd", DoubleRegs, DoubleWordAccess, 0b110>;
3193 //===----------------------------------------------------------------------===//
3194 // Bit-reversed .new stores with auto-increment register
3195 //===----------------------------------------------------------------------===//
3196 let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3,
3197 hasSideEffects = 0 in
3198 class T_storenew_pbr<string mnemonic, MemAccessSize addrSize, bits<2> majOp>
3199 : NVInst <(outs IntRegs:$_dst_),
3200 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3201 #mnemonic#"($Rz ++ $Mu:brev) = $Nt.new", [],
3202 "$Rz = $_dst_">, NewValueRel {
3203 let accessSize = addrSize;
3208 let IClass = 0b1010;
3210 let Inst{27-21} = 0b1111101;
3211 let Inst{12-11} = majOp;
3213 let Inst{20-16} = Rz;
3215 let Inst{10-8} = Nt;
3218 let BaseOpcode = "S2_storerb_pbr", isCodeGenOnly = 0 in
3219 def S2_storerbnew_pbr : T_storenew_pbr<"memb", ByteAccess, 0b00>;
3221 let BaseOpcode = "S2_storerh_pbr", isCodeGenOnly = 0 in
3222 def S2_storerhnew_pbr : T_storenew_pbr<"memh", HalfWordAccess, 0b01>;
3224 let BaseOpcode = "S2_storeri_pbr", isCodeGenOnly = 0 in
3225 def S2_storerinew_pbr : T_storenew_pbr<"memw", WordAccess, 0b10>;
3227 //===----------------------------------------------------------------------===//
3229 //===----------------------------------------------------------------------===//
3231 //===----------------------------------------------------------------------===//
3233 //===----------------------------------------------------------------------===//
3235 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
3236 "$dst = not($src1)",
3237 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
3240 //===----------------------------------------------------------------------===//
3242 //===----------------------------------------------------------------------===//
3244 let hasSideEffects = 0 in
3245 class T_S2op_1 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
3246 RegisterClass RCIn, bits<2> MajOp, bits<3> MinOp, bit isSat>
3247 : SInst <(outs RCOut:$dst), (ins RCIn:$src),
3248 "$dst = "#mnemonic#"($src)"#!if(isSat, ":sat", ""),
3249 [], "", S_2op_tc_1_SLOT23 > {
3253 let IClass = 0b1000;
3255 let Inst{27-24} = RegTyBits;
3256 let Inst{23-22} = MajOp;
3258 let Inst{20-16} = src;
3259 let Inst{7-5} = MinOp;
3260 let Inst{4-0} = dst;
3263 class T_S2op_1_di <string mnemonic, bits<2> MajOp, bits<3> MinOp>
3264 : T_S2op_1 <mnemonic, 0b0100, DoubleRegs, IntRegs, MajOp, MinOp, 0>;
3266 let hasNewValue = 1 in
3267 class T_S2op_1_id <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
3268 : T_S2op_1 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, isSat>;
3270 let hasNewValue = 1 in
3271 class T_S2op_1_ii <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
3272 : T_S2op_1 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, isSat>;
3274 // Sign extend word to doubleword
3275 let isCodeGenOnly = 0 in
3276 def A2_sxtw : T_S2op_1_di <"sxtw", 0b01, 0b000>;
3278 def: Pat <(i64 (sext I32:$src)), (A2_sxtw I32:$src)>;
3280 // Swizzle the bytes of a word
3281 let isCodeGenOnly = 0 in
3282 def A2_swiz : T_S2op_1_ii <"swiz", 0b10, 0b111>;
3285 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
3286 def A2_sat : T_S2op_1_id <"sat", 0b11, 0b000>;
3287 def A2_satb : T_S2op_1_ii <"satb", 0b11, 0b111>;
3288 def A2_satub : T_S2op_1_ii <"satub", 0b11, 0b110>;
3289 def A2_sath : T_S2op_1_ii <"sath", 0b11, 0b100>;
3290 def A2_satuh : T_S2op_1_ii <"satuh", 0b11, 0b101>;
3293 let Itinerary = S_2op_tc_2_SLOT23, isCodeGenOnly = 0 in {
3295 def S2_brev : T_S2op_1_ii <"brev", 0b01, 0b110>;
3297 // Absolute value word
3298 def A2_abs : T_S2op_1_ii <"abs", 0b10, 0b100>;
3300 let Defs = [USR_OVF] in
3301 def A2_abssat : T_S2op_1_ii <"abs", 0b10, 0b101, 1>;
3303 // Negate with saturation
3304 let Defs = [USR_OVF] in
3305 def A2_negsat : T_S2op_1_ii <"neg", 0b10, 0b110, 1>;
3308 def: Pat<(i32 (select (i1 (setlt (i32 IntRegs:$src), 0)),
3309 (i32 (sub 0, (i32 IntRegs:$src))),
3310 (i32 IntRegs:$src))),
3311 (A2_abs IntRegs:$src)>;
3313 let AddedComplexity = 50 in
3314 def: Pat<(i32 (xor (add (sra (i32 IntRegs:$src), (i32 31)),
3315 (i32 IntRegs:$src)),
3316 (sra (i32 IntRegs:$src), (i32 31)))),
3317 (A2_abs IntRegs:$src)>;
3319 class T_S2op_2 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
3320 RegisterClass RCIn, bits<3> MajOp, bits<3> MinOp,
3321 bit isSat, bit isRnd, list<dag> pattern = []>
3322 : SInst <(outs RCOut:$dst),
3323 (ins RCIn:$src, u5Imm:$u5),
3324 "$dst = "#mnemonic#"($src, #$u5)"#!if(isSat, ":sat", "")
3325 #!if(isRnd, ":rnd", ""),
3326 pattern, "", S_2op_tc_2_SLOT23> {
3331 let IClass = 0b1000;
3333 let Inst{27-24} = RegTyBits;
3334 let Inst{23-21} = MajOp;
3335 let Inst{20-16} = src;
3337 let Inst{12-8} = u5;
3338 let Inst{7-5} = MinOp;
3339 let Inst{4-0} = dst;
3342 class T_S2op_2_di <string mnemonic, bits<3> MajOp, bits<3> MinOp>
3343 : T_S2op_2 <mnemonic, 0b1000, DoubleRegs, IntRegs, MajOp, MinOp, 0, 0>;
3345 let hasNewValue = 1 in
3346 class T_S2op_2_id <string mnemonic, bits<3> MajOp, bits<3> MinOp>
3347 : T_S2op_2 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, 0, 0>;
3349 let hasNewValue = 1 in
3350 class T_S2op_2_ii <string mnemonic, bits<3> MajOp, bits<3> MinOp,
3351 bit isSat = 0, bit isRnd = 0, list<dag> pattern = []>
3352 : T_S2op_2 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp,
3353 isSat, isRnd, pattern>;
3355 class T_S2op_shift <string mnemonic, bits<3> MajOp, bits<3> MinOp, SDNode OpNd>
3356 : T_S2op_2_ii <mnemonic, MajOp, MinOp, 0, 0,
3357 [(set (i32 IntRegs:$dst), (OpNd (i32 IntRegs:$src),
3358 (u5ImmPred:$u5)))]>;
3360 // Arithmetic/logical shift right/left by immediate
3361 let Itinerary = S_2op_tc_1_SLOT23, isCodeGenOnly = 0 in {
3362 def S2_asr_i_r : T_S2op_shift <"asr", 0b000, 0b000, sra>;
3363 def S2_lsr_i_r : T_S2op_shift <"lsr", 0b000, 0b001, srl>;
3364 def S2_asl_i_r : T_S2op_shift <"asl", 0b000, 0b010, shl>;
3367 // Shift left by immediate with saturation
3368 let Defs = [USR_OVF], isCodeGenOnly = 0 in
3369 def S2_asl_i_r_sat : T_S2op_2_ii <"asl", 0b010, 0b010, 1>;
3371 // Shift right with round
3372 let isCodeGenOnly = 0 in
3373 def S2_asr_i_r_rnd : T_S2op_2_ii <"asr", 0b010, 0b000, 0, 1>;
3375 def S2_asr_i_r_rnd_goodsyntax
3376 : SInst <(outs IntRegs:$dst), (ins IntRegs:$src, u5Imm:$u5),
3377 "$dst = asrrnd($src, #$u5)",
3378 [], "", S_2op_tc_1_SLOT23>;
3380 def: Pat<(i32 (sra (i32 (add (i32 (sra I32:$src1, u5ImmPred:$src2)),
3383 (S2_asr_i_r_rnd IntRegs:$src1, u5ImmPred:$src2)>;
3385 class T_S2op_3<string opc, bits<2>MajOp, bits<3>minOp, bits<1> sat = 0>
3386 : SInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
3387 "$Rdd = "#opc#"($Rss)"#!if(!eq(sat, 1),":sat","")> {
3390 let IClass = 0b1000;
3391 let Inst{27-24} = 0;
3392 let Inst{23-22} = MajOp;
3393 let Inst{20-16} = Rss;
3394 let Inst{7-5} = minOp;
3395 let Inst{4-0} = Rdd;
3398 let isCodeGenOnly = 0 in {
3399 def A2_absp : T_S2op_3 <"abs", 0b10, 0b110>;
3400 def A2_negp : T_S2op_3 <"neg", 0b10, 0b101>;
3401 def A2_notp : T_S2op_3 <"not", 0b10, 0b100>;
3404 // Innterleave/deinterleave
3405 let isCodeGenOnly = 0 in {
3406 def S2_interleave : T_S2op_3 <"interleave", 0b11, 0b101>;
3407 def S2_deinterleave : T_S2op_3 <"deinterleave", 0b11, 0b100>;
3410 //===----------------------------------------------------------------------===//
3412 //===----------------------------------------------------------------------===//
3415 let hasSideEffects = 0, hasNewValue = 1 in
3416 class T_COUNT_LEADING<string MnOp, bits<3> MajOp, bits<3> MinOp, bit Is32,
3418 : SInst<Out, Inp, "$Rd = "#MnOp#"($Rs)", [], "", S_2op_tc_1_SLOT23> {
3421 let IClass = 0b1000;
3423 let Inst{26} = Is32;
3424 let Inst{25-24} = 0b00;
3425 let Inst{23-21} = MajOp;
3426 let Inst{20-16} = Rs;
3427 let Inst{7-5} = MinOp;
3431 class T_COUNT_LEADING_32<string MnOp, bits<3> MajOp, bits<3> MinOp>
3432 : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b1,
3433 (outs IntRegs:$Rd), (ins IntRegs:$Rs)>;
3435 class T_COUNT_LEADING_64<string MnOp, bits<3> MajOp, bits<3> MinOp>
3436 : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b0,
3437 (outs IntRegs:$Rd), (ins DoubleRegs:$Rs)>;
3439 let isCodeGenOnly = 0 in {
3440 def S2_cl0 : T_COUNT_LEADING_32<"cl0", 0b000, 0b101>;
3441 def S2_cl1 : T_COUNT_LEADING_32<"cl1", 0b000, 0b110>;
3442 def S2_ct0 : T_COUNT_LEADING_32<"ct0", 0b010, 0b100>;
3443 def S2_ct1 : T_COUNT_LEADING_32<"ct1", 0b010, 0b101>;
3444 def S2_cl0p : T_COUNT_LEADING_64<"cl0", 0b010, 0b010>;
3445 def S2_cl1p : T_COUNT_LEADING_64<"cl1", 0b010, 0b100>;
3446 def S2_clb : T_COUNT_LEADING_32<"clb", 0b000, 0b100>;
3447 def S2_clbp : T_COUNT_LEADING_64<"clb", 0b010, 0b000>;
3448 def S2_clbnorm : T_COUNT_LEADING_32<"normamt", 0b000, 0b111>;
3451 def: Pat<(i32 (ctlz I32:$Rs)), (S2_cl0 I32:$Rs)>;
3452 def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>;
3453 def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>;
3454 def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>;
3455 def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>;
3456 def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>;
3458 // Bit set/clear/toggle
3460 let hasSideEffects = 0, hasNewValue = 1 in
3461 class T_SCT_BIT_IMM<string MnOp, bits<3> MinOp>
3462 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u5Imm:$u5),
3463 "$Rd = "#MnOp#"($Rs, #$u5)", [], "", S_2op_tc_1_SLOT23> {
3467 let IClass = 0b1000;
3468 let Inst{27-21} = 0b1100110;
3469 let Inst{20-16} = Rs;
3471 let Inst{12-8} = u5;
3472 let Inst{7-5} = MinOp;
3476 let hasSideEffects = 0, hasNewValue = 1 in
3477 class T_SCT_BIT_REG<string MnOp, bits<2> MinOp>
3478 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
3479 "$Rd = "#MnOp#"($Rs, $Rt)", [], "", S_3op_tc_1_SLOT23> {
3483 let IClass = 0b1100;
3484 let Inst{27-22} = 0b011010;
3485 let Inst{20-16} = Rs;
3486 let Inst{12-8} = Rt;
3487 let Inst{7-6} = MinOp;
3491 let isCodeGenOnly = 0 in {
3492 def S2_clrbit_i : T_SCT_BIT_IMM<"clrbit", 0b001>;
3493 def S2_setbit_i : T_SCT_BIT_IMM<"setbit", 0b000>;
3494 def S2_togglebit_i : T_SCT_BIT_IMM<"togglebit", 0b010>;
3495 def S2_clrbit_r : T_SCT_BIT_REG<"clrbit", 0b01>;
3496 def S2_setbit_r : T_SCT_BIT_REG<"setbit", 0b00>;
3497 def S2_togglebit_r : T_SCT_BIT_REG<"togglebit", 0b10>;
3500 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, u5ImmPred:$u5)))),
3501 (S2_clrbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
3502 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
3503 (S2_setbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
3504 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
3505 (S2_togglebit_i IntRegs:$Rs, u5ImmPred:$u5)>;
3506 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, (i32 IntRegs:$Rt))))),
3507 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>;
3508 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
3509 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>;
3510 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
3511 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>;
3515 let hasSideEffects = 0 in
3516 class T_TEST_BIT_IMM<string MnOp, bits<3> MajOp>
3517 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5Imm:$u5),
3518 "$Pd = "#MnOp#"($Rs, #$u5)",
3519 [], "", S_2op_tc_2early_SLOT23> {
3523 let IClass = 0b1000;
3524 let Inst{27-24} = 0b0101;
3525 let Inst{23-21} = MajOp;
3526 let Inst{20-16} = Rs;
3528 let Inst{12-8} = u5;
3532 let hasSideEffects = 0 in
3533 class T_TEST_BIT_REG<string MnOp, bit IsNeg>
3534 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
3535 "$Pd = "#MnOp#"($Rs, $Rt)",
3536 [], "", S_3op_tc_2early_SLOT23> {
3540 let IClass = 0b1100;
3541 let Inst{27-22} = 0b011100;
3542 let Inst{21} = IsNeg;
3543 let Inst{20-16} = Rs;
3544 let Inst{12-8} = Rt;
3548 let isCodeGenOnly = 0 in {
3549 def S2_tstbit_i : T_TEST_BIT_IMM<"tstbit", 0b000>;
3550 def S2_tstbit_r : T_TEST_BIT_REG<"tstbit", 0>;
3553 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
3554 def: Pat<(i1 (setne (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
3555 (S2_tstbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
3556 def: Pat<(i1 (setne (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
3557 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>;
3558 def: Pat<(i1 (trunc (i32 IntRegs:$Rs))),
3559 (S2_tstbit_i IntRegs:$Rs, 0)>;
3560 def: Pat<(i1 (trunc (i64 DoubleRegs:$Rs))),
3561 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>;
3563 let hasSideEffects = 0 in
3564 class T_TEST_BITS_IMM<string MnOp, bits<2> MajOp, bit IsNeg>
3565 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u6Imm:$u6),
3566 "$Pd = "#MnOp#"($Rs, #$u6)",
3567 [], "", S_2op_tc_2early_SLOT23> {
3571 let IClass = 0b1000;
3572 let Inst{27-24} = 0b0101;
3573 let Inst{23-22} = MajOp;
3574 let Inst{21} = IsNeg;
3575 let Inst{20-16} = Rs;
3576 let Inst{13-8} = u6;
3580 let hasSideEffects = 0 in
3581 class T_TEST_BITS_REG<string MnOp, bits<2> MajOp, bit IsNeg>
3582 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
3583 "$Pd = "#MnOp#"($Rs, $Rt)",
3584 [], "", S_3op_tc_2early_SLOT23> {
3588 let IClass = 0b1100;
3589 let Inst{27-24} = 0b0111;
3590 let Inst{23-22} = MajOp;
3591 let Inst{21} = IsNeg;
3592 let Inst{20-16} = Rs;
3593 let Inst{12-8} = Rt;
3597 let isCodeGenOnly = 0 in {
3598 def C2_bitsclri : T_TEST_BITS_IMM<"bitsclr", 0b10, 0>;
3599 def C2_bitsclr : T_TEST_BITS_REG<"bitsclr", 0b10, 0>;
3600 def C2_bitsset : T_TEST_BITS_REG<"bitsset", 0b01, 0>;
3603 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm.
3604 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), u6ImmPred:$u6), 0)),
3605 (C2_bitsclri IntRegs:$Rs, u6ImmPred:$u6)>;
3606 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), 0)),
3607 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>;
3610 let AddedComplexity = 10 in // Complexity greater than compare reg-reg.
3611 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), IntRegs:$Rt)),
3612 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>;
3614 //===----------------------------------------------------------------------===//
3616 //===----------------------------------------------------------------------===//
3618 //===----------------------------------------------------------------------===//
3620 //===----------------------------------------------------------------------===//
3621 //===----------------------------------------------------------------------===//
3623 //===----------------------------------------------------------------------===//
3625 //===----------------------------------------------------------------------===//
3627 //===----------------------------------------------------------------------===//
3629 //===----------------------------------------------------------------------===//
3631 //===----------------------------------------------------------------------===//
3633 //===----------------------------------------------------------------------===//
3635 //===----------------------------------------------------------------------===//
3637 // Predicate transfer.
3638 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
3639 def C2_tfrpr : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps),
3640 "$Rd = $Ps", [], "", S_2op_tc_1_SLOT23> {
3644 let IClass = 0b1000;
3645 let Inst{27-24} = 0b1001;
3647 let Inst{17-16} = Ps;
3651 // Transfer general register to predicate.
3652 let hasSideEffects = 0, isCodeGenOnly = 0 in
3653 def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs),
3654 "$Pd = $Rs", [], "", S_2op_tc_2early_SLOT23> {
3658 let IClass = 0b1000;
3659 let Inst{27-21} = 0b0101010;
3660 let Inst{20-16} = Rs;
3665 //===----------------------------------------------------------------------===//
3667 //===----------------------------------------------------------------------===//
3669 //===----------------------------------------------------------------------===//
3671 //===----------------------------------------------------------------------===//
3672 class S_2OpInstImm<string Mnemonic, bits<3>MajOp, bits<3>MinOp,
3673 Operand Imm, list<dag> pattern = [], bit isRnd = 0>
3674 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, Imm:$src2),
3675 "$dst = "#Mnemonic#"($src1, #$src2)"#!if(isRnd, ":rnd", ""),
3679 let IClass = 0b1000;
3680 let Inst{27-24} = 0;
3681 let Inst{23-21} = MajOp;
3682 let Inst{20-16} = src1;
3683 let Inst{7-5} = MinOp;
3684 let Inst{4-0} = dst;
3687 class S_2OpInstImmI6<string Mnemonic, SDNode OpNode, bits<3>MinOp>
3688 : S_2OpInstImm<Mnemonic, 0b000, MinOp, u6Imm,
3689 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1),
3690 u6ImmPred:$src2))]> {
3692 let Inst{13-8} = src2;
3695 // Shift by immediate.
3696 let isCodeGenOnly = 0 in {
3697 def S2_asr_i_p : S_2OpInstImmI6<"asr", sra, 0b000>;
3698 def S2_asl_i_p : S_2OpInstImmI6<"asl", shl, 0b010>;
3699 def S2_lsr_i_p : S_2OpInstImmI6<"lsr", srl, 0b001>;
3702 // Shift left by small amount and add.
3703 let AddedComplexity = 100, hasNewValue = 1, hasSideEffects = 0,
3704 isCodeGenOnly = 0 in
3705 def S2_addasl_rrri: SInst <(outs IntRegs:$Rd),
3706 (ins IntRegs:$Rt, IntRegs:$Rs, u3Imm:$u3),
3707 "$Rd = addasl($Rt, $Rs, #$u3)" ,
3708 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rt),
3709 (shl (i32 IntRegs:$Rs), u3ImmPred:$u3)))],
3710 "", S_3op_tc_2_SLOT23> {
3716 let IClass = 0b1100;
3718 let Inst{27-21} = 0b0100000;
3719 let Inst{20-16} = Rs;
3721 let Inst{12-8} = Rt;
3726 //===----------------------------------------------------------------------===//
3728 //===----------------------------------------------------------------------===//
3730 //===----------------------------------------------------------------------===//
3732 //===----------------------------------------------------------------------===//
3733 //===----------------------------------------------------------------------===//
3735 //===----------------------------------------------------------------------===//
3737 //===----------------------------------------------------------------------===//
3739 //===----------------------------------------------------------------------===//
3740 //===----------------------------------------------------------------------===//
3742 //===----------------------------------------------------------------------===//
3744 //===----------------------------------------------------------------------===//
3746 //===----------------------------------------------------------------------===//
3748 //===----------------------------------------------------------------------===//
3750 //===----------------------------------------------------------------------===//
3751 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>;
3753 let hasSideEffects = 1, isSoloAX = 1, isCodeGenOnly = 0 in
3754 def BARRIER : SYSInst<(outs), (ins),
3756 [(HexagonBARRIER)],"",ST_tc_st_SLOT0> {
3757 let Inst{31-28} = 0b1010;
3758 let Inst{27-21} = 0b1000000;
3761 //===----------------------------------------------------------------------===//
3763 //===----------------------------------------------------------------------===//
3764 //===----------------------------------------------------------------------===//
3766 //===----------------------------------------------------------------------===//
3768 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
3769 opExtendable = 0, hasSideEffects = 0 in
3770 class LOOP_iBase<string mnemonic, Operand brOp, bit mustExtend = 0>
3771 : CRInst<(outs), (ins brOp:$offset, u10Imm:$src2),
3772 #mnemonic#"($offset, #$src2)",
3773 [], "" , CR_tc_3x_SLOT3> {
3777 let IClass = 0b0110;
3779 let Inst{27-22} = 0b100100;
3780 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
3781 let Inst{20-16} = src2{9-5};
3782 let Inst{12-8} = offset{8-4};
3783 let Inst{7-5} = src2{4-2};
3784 let Inst{4-3} = offset{3-2};
3785 let Inst{1-0} = src2{1-0};
3788 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
3789 opExtendable = 0, hasSideEffects = 0 in
3790 class LOOP_rBase<string mnemonic, Operand brOp, bit mustExtend = 0>
3791 : CRInst<(outs), (ins brOp:$offset, IntRegs:$src2),
3792 #mnemonic#"($offset, $src2)",
3793 [], "" ,CR_tc_3x_SLOT3> {
3797 let IClass = 0b0110;
3799 let Inst{27-22} = 0b000000;
3800 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
3801 let Inst{20-16} = src2;
3802 let Inst{12-8} = offset{8-4};
3803 let Inst{4-3} = offset{3-2};
3806 multiclass LOOP_ri<string mnemonic> {
3807 def i : LOOP_iBase<mnemonic, brtarget>;
3808 def r : LOOP_rBase<mnemonic, brtarget>;
3812 let Defs = [SA0, LC0, USR], isCodeGenOnly = 0 in
3813 defm J2_loop0 : LOOP_ri<"loop0">;
3815 // Interestingly only loop0's appear to set usr.lpcfg
3816 let Defs = [SA1, LC1], isCodeGenOnly = 0 in
3817 defm J2_loop1 : LOOP_ri<"loop1">;
3819 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
3820 Defs = [PC, LC0], Uses = [SA0, LC0] in {
3821 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
3826 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
3827 Defs = [PC, LC1], Uses = [SA1, LC1] in {
3828 def ENDLOOP1 : Endloop<(outs), (ins brtarget:$offset),
3833 // Pipelined loop instructions, sp[123]loop0
3834 let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0,
3835 isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2,
3836 opExtendable = 0, isPredicateLate = 1 in
3837 class SPLOOP_iBase<string SP, bits<2> op>
3838 : CRInst <(outs), (ins brtarget:$r7_2, u10Imm:$U10),
3839 "p3 = sp"#SP#"loop0($r7_2, #$U10)" > {
3843 let IClass = 0b0110;
3845 let Inst{22-21} = op;
3846 let Inst{27-23} = 0b10011;
3847 let Inst{20-16} = U10{9-5};
3848 let Inst{12-8} = r7_2{8-4};
3849 let Inst{7-5} = U10{4-2};
3850 let Inst{4-3} = r7_2{3-2};
3851 let Inst{1-0} = U10{1-0};
3854 let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0,
3855 isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2,
3856 opExtendable = 0, isPredicateLate = 1 in
3857 class SPLOOP_rBase<string SP, bits<2> op>
3858 : CRInst <(outs), (ins brtarget:$r7_2, IntRegs:$Rs),
3859 "p3 = sp"#SP#"loop0($r7_2, $Rs)" > {
3863 let IClass = 0b0110;
3865 let Inst{22-21} = op;
3866 let Inst{27-23} = 0b00001;
3867 let Inst{20-16} = Rs;
3868 let Inst{12-8} = r7_2{8-4};
3869 let Inst{4-3} = r7_2{3-2};
3872 multiclass SPLOOP_ri<string mnemonic, bits<2> op> {
3873 def i : SPLOOP_iBase<mnemonic, op>;
3874 def r : SPLOOP_rBase<mnemonic, op>;
3877 let isCodeGenOnly = 0 in {
3878 defm J2_ploop1s : SPLOOP_ri<"1", 0b01>;
3879 defm J2_ploop2s : SPLOOP_ri<"2", 0b10>;
3880 defm J2_ploop3s : SPLOOP_ri<"3", 0b11>;
3883 // Transfer to/from Control/GPR Guest/GPR
3884 let hasSideEffects = 0 in
3885 class TFR_CR_RS_base<RegisterClass CTRC, RegisterClass RC, bit isDouble>
3886 : CRInst <(outs CTRC:$dst), (ins RC:$src),
3887 "$dst = $src", [], "", CR_tc_3x_SLOT3> {
3891 let IClass = 0b0110;
3893 let Inst{27-25} = 0b001;
3894 let Inst{24} = isDouble;
3895 let Inst{23-21} = 0b001;
3896 let Inst{20-16} = src;
3897 let Inst{4-0} = dst;
3899 let isCodeGenOnly = 0 in
3900 def A2_tfrrcr : TFR_CR_RS_base<CtrRegs, IntRegs, 0b0>;
3901 def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>;
3902 def : InstAlias<"m1 = $Rs", (A2_tfrrcr C7, IntRegs:$Rs)>;
3904 let hasSideEffects = 0 in
3905 class TFR_RD_CR_base<RegisterClass RC, RegisterClass CTRC, bit isSingle>
3906 : CRInst <(outs RC:$dst), (ins CTRC:$src),
3907 "$dst = $src", [], "", CR_tc_3x_SLOT3> {
3911 let IClass = 0b0110;
3913 let Inst{27-26} = 0b10;
3914 let Inst{25} = isSingle;
3915 let Inst{24-21} = 0b0000;
3916 let Inst{20-16} = src;
3917 let Inst{4-0} = dst;
3920 let hasNewValue = 1, opNewValue = 0, isCodeGenOnly = 0 in
3921 def A2_tfrcrr : TFR_RD_CR_base<IntRegs, CtrRegs, 1>;
3922 def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>;
3923 def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>;
3925 // Y4_trace: Send value to etm trace.
3926 let isSoloAX = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
3927 def Y4_trace: CRInst <(outs), (ins IntRegs:$Rs),
3931 let IClass = 0b0110;
3932 let Inst{27-21} = 0b0010010;
3933 let Inst{20-16} = Rs;
3936 let AddedComplexity = 100, isPredicated = 1 in
3937 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
3938 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
3939 "Error; should not emit",
3940 [(set (i32 IntRegs:$dst),
3941 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
3942 s12ImmPred:$src3)))]>;
3944 let AddedComplexity = 100, isPredicated = 1 in
3945 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
3946 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
3947 "Error; should not emit",
3948 [(set (i32 IntRegs:$dst),
3949 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
3950 (i32 IntRegs:$src3))))]>;
3952 let AddedComplexity = 100, isPredicated = 1 in
3953 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
3954 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
3955 "Error; should not emit",
3956 [(set (i32 IntRegs:$dst),
3957 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
3958 s12ImmPred:$src3)))]>;
3960 // Generate frameindex addresses.
3961 let isReMaterializable = 1 in
3962 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
3963 "$dst = add($src1)",
3964 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
3966 // Support for generating global address.
3967 // Taken from X86InstrInfo.td.
3968 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
3971 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
3972 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
3974 // HI/LO Instructions
3975 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
3976 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
3977 "$dst.l = #LO($global)",
3980 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
3981 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
3982 "$dst.h = #HI($global)",
3985 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
3986 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
3987 "$dst.l = #LO($imm_value)",
3991 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
3992 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
3993 "$dst.h = #HI($imm_value)",
3996 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
3997 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
3998 "$dst.l = #LO($jt)",
4001 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
4002 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
4003 "$dst.h = #HI($jt)",
4007 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
4008 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4009 "$dst.l = #LO($label)",
4012 let isReMaterializable = 1, isMoveImm = 1 , hasSideEffects = 0 in
4013 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4014 "$dst.h = #HI($label)",
4017 // This pattern is incorrect. When we add small data, we should change
4018 // this pattern to use memw(#foo).
4019 // This is for sdata.
4020 let isMoveImm = 1 in
4021 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
4022 "$dst = CONST32(#$global)",
4023 [(set (i32 IntRegs:$dst),
4024 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
4026 // This is for non-sdata.
4027 let isReMaterializable = 1, isMoveImm = 1 in
4028 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
4029 "$dst = CONST32(#$global)",
4030 [(set (i32 IntRegs:$dst),
4031 (HexagonCONST32 tglobaladdr:$global))]>;
4033 let isReMaterializable = 1, isMoveImm = 1 in
4034 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
4035 "$dst = CONST32(#$jt)",
4036 [(set (i32 IntRegs:$dst),
4037 (HexagonCONST32 tjumptable:$jt))]>;
4039 let isReMaterializable = 1, isMoveImm = 1 in
4040 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
4041 "$dst = CONST32(#$global)",
4042 [(set (i32 IntRegs:$dst),
4043 (HexagonCONST32_GP tglobaladdr:$global))]>;
4045 let isReMaterializable = 1, isMoveImm = 1 in
4046 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
4047 "$dst = CONST32(#$global)",
4048 [(set (i32 IntRegs:$dst), imm:$global) ]>;
4050 // Map BlockAddress lowering to CONST32_Int_Real
4051 def : Pat<(HexagonCONST32_GP tblockaddress:$addr),
4052 (CONST32_Int_Real tblockaddress:$addr)>;
4054 let isReMaterializable = 1, isMoveImm = 1 in
4055 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
4056 "$dst = CONST32($label)",
4057 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
4059 let isReMaterializable = 1, isMoveImm = 1 in
4060 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
4061 "$dst = CONST64(#$global)",
4062 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
4064 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
4065 "$dst = xor($dst, $dst)",
4066 [(set (i1 PredRegs:$dst), 0)]>;
4068 // Pseudo instructions.
4069 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
4070 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
4071 SDTCisVT<1, i32> ]>;
4073 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
4074 [SDNPHasChain, SDNPOutGlue]>;
4075 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
4076 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
4078 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
4080 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
4081 // Optional Flag and Variable Arguments.
4082 // Its 1 Operand has pointer type.
4083 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
4084 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
4086 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
4087 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
4088 "Should never be emitted",
4089 [(callseq_start timm:$amt)]>;
4092 let Defs = [R29, R30, R31], Uses = [R29] in {
4093 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
4094 "Should never be emitted",
4095 [(callseq_end timm:$amt1, timm:$amt2)]>;
4098 let isCall = 1, hasSideEffects = 0,
4099 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
4100 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
4101 def CALL : JInst<(outs), (ins calltarget:$dst),
4105 // Call subroutine indirectly.
4106 let Defs = VolatileV3.Regs, isCodeGenOnly = 0 in
4107 def J2_callr : JUMPR_MISC_CALLR<0, 1>;
4109 // Indirect tail-call.
4110 let isCodeGenOnly = 1, isCall = 1, isReturn = 1 in
4111 def TCRETURNR : T_JMPr;
4113 // Direct tail-calls.
4114 let isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
4115 isTerminator = 1, isCodeGenOnly = 1 in {
4116 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst), "jump $dst",
4117 [], "", J_tc_2early_SLOT23>;
4118 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst), "jump $dst",
4119 [], "", J_tc_2early_SLOT23>;
4123 def : Pat<(HexagonTCRet tglobaladdr:$dst),
4124 (TCRETURNtg tglobaladdr:$dst)>;
4125 def : Pat<(HexagonTCRet texternalsym:$dst),
4126 (TCRETURNtext texternalsym:$dst)>;
4127 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
4128 (TCRETURNR (i32 IntRegs:$dst))>;
4130 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
4131 def : Pat <(and (i32 IntRegs:$src1), 65535),
4132 (A2_zxth (i32 IntRegs:$src1))>;
4134 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
4135 def : Pat <(and (i32 IntRegs:$src1), 255),
4136 (A2_zxtb (i32 IntRegs:$src1))>;
4138 // Map Add(p1, true) to p1 = not(p1).
4139 // Add(p1, false) should never be produced,
4140 // if it does, it got to be mapped to NOOP.
4141 def : Pat <(add (i1 PredRegs:$src1), -1),
4142 (C2_not (i1 PredRegs:$src1))>;
4144 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
4145 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
4146 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
4149 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
4150 // => r0 = TFR_condset_ri(p0, r1, #i)
4151 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
4152 (i32 IntRegs:$src3)),
4153 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
4154 s12ImmPred:$src2))>;
4156 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
4157 // => r0 = TFR_condset_ir(p0, #i, r1)
4158 def : Pat <(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s12ImmPred:$src3),
4159 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
4160 (i32 IntRegs:$src2)))>;
4162 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
4163 def : Pat <(brcond (not (i1 PredRegs:$src1)), bb:$offset),
4164 (J2_jumpf (i1 PredRegs:$src1), bb:$offset)>;
4166 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
4167 def : Pat <(and (i1 PredRegs:$src1), (not (i1 PredRegs:$src2))),
4168 (i1 (C2_andn (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
4171 let AddedComplexity = 100 in
4172 def : Pat <(i64 (zextloadi1 (HexagonCONST32 tglobaladdr:$global))),
4173 (i64 (A2_combinew (A2_tfrsi 0),
4174 (L2_loadrub_io (CONST32_set tglobaladdr:$global), 0)))>,
4177 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
4178 let AddedComplexity = 10 in
4179 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
4180 (i32 (A2_and (i32 (L2_loadrb_io AddrFI:$addr, 0)), (A2_tfrsi 0x1)))>;
4182 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = A2_sxtw(Rss.lo).
4183 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
4184 (i64 (A2_sxtw (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
4186 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = A2_sxtw(SXTH(Rss.lo)).
4187 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
4188 (i64 (A2_sxtw (i32 (A2_sxth (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
4189 subreg_loreg))))))>;
4191 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = A2_sxtw(SXTB(Rss.lo)).
4192 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
4193 (i64 (A2_sxtw (i32 (A2_sxtb (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
4194 subreg_loreg))))))>;
4196 // We want to prevent emitting pnot's as much as possible.
4197 // Map brcond with an unsupported setcc to a J2_jumpf.
4198 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4200 (J2_jumpf (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
4203 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
4205 (J2_jumpf (C2_cmpeqi (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
4207 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
4208 (J2_jumpf (i1 PredRegs:$src1), bb:$offset)>;
4210 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
4211 (J2_jumpt (i1 PredRegs:$src1), bb:$offset)>;
4213 // cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1)
4214 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
4216 (J2_jumpf (C2_cmpgti (i32 IntRegs:$src1),
4217 (DEC_CONST_SIGNED s8ImmPred:$src2)), bb:$offset)>;
4219 // cmp.lt(r0, r1) -> cmp.gt(r1, r0)
4220 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4222 (J2_jumpt (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)), bb:$offset)>;
4224 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4226 (J2_jumpf (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
4229 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4231 (J2_jumpf (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
4234 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4236 (J2_jumpf (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
4239 // Map from a 64-bit select to an emulated 64-bit mux.
4240 // Hexagon does not support 64-bit MUXes; so emulate with combines.
4241 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
4242 (i64 DoubleRegs:$src3)),
4243 (i64 (A2_combinew (i32 (C2_mux (i1 PredRegs:$src1),
4244 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
4246 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
4248 (i32 (C2_mux (i1 PredRegs:$src1),
4249 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
4251 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
4252 subreg_loreg))))))>;
4254 // Map from a 1-bit select to logical ops.
4255 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
4256 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
4257 (i1 PredRegs:$src3)),
4258 (C2_or (C2_and (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
4259 (C2_and (C2_not (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
4261 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
4262 def : Pat<(i1 (load ADDRriS11_2:$addr)),
4263 (i1 (C2_tfrrp (i32 (L2_loadrb_io AddrFI:$addr, 0))))>;
4265 // Map for truncating from 64 immediates to 32 bit immediates.
4266 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
4267 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
4269 // Map for truncating from i64 immediates to i1 bit immediates.
4270 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
4271 (i1 (C2_tfrrp (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4274 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
4275 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4276 (S2_storerb_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4279 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
4280 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4281 (S2_storerh_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4283 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
4284 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4285 (S2_storeri_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4288 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
4289 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4290 (S2_storeri_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4293 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
4294 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
4295 (S2_storerb_io AddrFI:$addr, 0, (A2_tfrsi 1))>;
4298 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
4299 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
4300 (S2_storerb_io AddrFI:$addr, 0, (A2_tfrsi 1))>;
4302 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
4303 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
4304 (S2_storerb_io AddrFI:$addr, 0, (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0)) )>;
4306 // Map Rdd = anyext(Rs) -> Rdd = A2_sxtw(Rs).
4307 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
4308 // Better way to do this?
4309 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
4310 (i64 (A2_sxtw (i32 IntRegs:$src1)))>;
4312 // Map cmple -> cmpgt.
4313 // rs <= rt -> !(rs > rt).
4314 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
4315 (i1 (C2_not (C2_cmpgti (i32 IntRegs:$src1), s10ExtPred:$src2)))>;
4317 // rs <= rt -> !(rs > rt).
4318 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4319 (i1 (C2_not (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
4321 // Rss <= Rtt -> !(Rss > Rtt).
4322 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4323 (i1 (C2_not (C2_cmpgtp (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
4325 // Map cmpne -> cmpeq.
4326 // Hexagon_TODO: We should improve on this.
4327 // rs != rt -> !(rs == rt).
4328 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
4329 (i1 (C2_not(i1 (C2_cmpeqi (i32 IntRegs:$src1), s10ExtPred:$src2))))>;
4331 // Map cmpne(Rs) -> !cmpeqe(Rs).
4332 // rs != rt -> !(rs == rt).
4333 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4334 (i1 (C2_not (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
4336 // Convert setne back to xor for hexagon since we compute w/ pred registers.
4337 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
4338 (i1 (C2_xor (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
4340 // Map cmpne(Rss) -> !cmpew(Rss).
4341 // rs != rt -> !(rs == rt).
4342 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4343 (i1 (C2_not (i1 (C2_cmpeqp (i64 DoubleRegs:$src1),
4344 (i64 DoubleRegs:$src2)))))>;
4346 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
4347 // rs >= rt -> !(rt > rs).
4348 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4349 (i1 (C2_not (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
4351 // cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
4352 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)),
4353 (i1 (C2_cmpgti (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
4355 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
4356 // rss >= rtt -> !(rtt > rss).
4357 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4358 (i1 (C2_not (i1 (C2_cmpgtp (i64 DoubleRegs:$src2),
4359 (i64 DoubleRegs:$src1)))))>;
4361 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
4362 // !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
4363 // rs < rt -> !(rs >= rt).
4364 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
4365 (i1 (C2_not (C2_cmpgti (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2))))>;
4367 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
4368 // rs < rt -> rt > rs.
4369 // We can let assembler map it, or we can do in the compiler itself.
4370 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4371 (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
4373 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
4374 // rss < rtt -> (rtt > rss).
4375 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4376 (i1 (C2_cmpgtp (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
4378 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
4379 // rs < rt -> rt > rs.
4380 // We can let assembler map it, or we can do in the compiler itself.
4381 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4382 (i1 (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
4384 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
4385 // rs < rt -> rt > rs.
4386 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4387 (i1 (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
4389 // Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs)
4390 def : Pat <(i1 (setuge (i32 IntRegs:$src1), 0)),
4391 (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src1)))>;
4393 // Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1)
4394 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ExtPred:$src2)),
4395 (i1 (C2_cmpgtui (i32 IntRegs:$src1), (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
4397 // Generate cmpgtu(Rs, #u9)
4398 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)),
4399 (i1 (C2_cmpgtui (i32 IntRegs:$src1), u9ExtPred:$src2))>;
4401 // Map from Rs >= Rt -> !(Rt > Rs).
4402 // rs >= rt -> !(rt > rs).
4403 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4404 (i1 (C2_not (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
4406 // Map from Rs >= Rt -> !(Rt > Rs).
4407 // rs >= rt -> !(rt > rs).
4408 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4409 (i1 (C2_not (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
4411 // Map from cmpleu(Rs, Rt) -> !cmpgtu(Rs, Rt).
4412 // Map from (Rs <= Rt) -> !(Rs > Rt).
4413 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4414 (i1 (C2_not (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
4416 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
4417 // Map from (Rs <= Rt) -> !(Rs > Rt).
4418 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4419 (i1 (C2_not (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
4423 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
4424 (i32 (C2_muxii (i1 PredRegs:$src1), -1, 0))>;
4427 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
4428 (i64 (A2_combinew (A2_tfrsi -1), (C2_muxii (i1 PredRegs:$src1), -1, 0)))>;
4430 // Convert sign-extended load back to load and sign extend.
4432 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
4433 (i64 (A2_sxtw (L2_loadrb_io AddrFI:$src1, 0)))>;
4435 // Convert any-extended load back to load and sign extend.
4437 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
4438 (i64 (A2_sxtw (L2_loadrb_io AddrFI:$src1, 0)))>;
4440 // Convert sign-extended load back to load and sign extend.
4442 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
4443 (i64 (A2_sxtw (L2_loadrh_io AddrFI:$src1, 0)))>;
4445 // Convert sign-extended load back to load and sign extend.
4447 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
4448 (i64 (A2_sxtw (L2_loadri_io AddrFI:$src1, 0)))>;
4453 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
4454 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
4457 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
4458 (i64 (A2_combinew (A2_tfrsi 0), (C2_muxii (i1 PredRegs:$src1), 1, 0)))>,
4462 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
4463 (i64 (A2_combinew (A2_tfrsi 0), (i32 IntRegs:$src1)))>,
4467 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
4468 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io AddrFI:$src1, 0)))>,
4471 let AddedComplexity = 20 in
4472 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
4473 s11_0ExtPred:$offset))),
4474 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io IntRegs:$src1,
4475 s11_0ExtPred:$offset)))>,
4479 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
4480 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io AddrFI:$src1, 0)))>,
4483 let AddedComplexity = 20 in
4484 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
4485 s11_0ExtPred:$offset))),
4486 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io IntRegs:$src1,
4487 s11_0ExtPred:$offset)))>,
4491 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
4492 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadruh_io AddrFI:$src1, 0)))>,
4495 let AddedComplexity = 20 in
4496 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
4497 s11_1ExtPred:$offset))),
4498 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadruh_io IntRegs:$src1,
4499 s11_1ExtPred:$offset)))>,
4503 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
4504 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io AddrFI:$src1, 0)))>,
4507 let AddedComplexity = 100 in
4508 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
4509 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io IntRegs:$src1,
4510 s11_2ExtPred:$offset)))>,
4513 let AddedComplexity = 10 in
4514 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
4515 (i32 (L2_loadri_io AddrFI:$src1, 0))>;
4517 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
4518 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
4519 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
4521 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
4522 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
4523 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
4525 // Map from Rss = Pd to Rdd = A2_sxtw (mux(Pd, #1, #0))
4526 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
4527 (i64 (A2_sxtw (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))))>;
4530 let AddedComplexity = 100 in
4531 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
4533 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
4534 s11_2ExtPred:$offset2)))))),
4535 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
4536 (L2_loadri_io IntRegs:$src2,
4537 s11_2ExtPred:$offset2)))>;
4539 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
4541 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
4542 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
4543 (L2_loadri_io AddrFI:$srcLow, 0)))>;
4545 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
4547 (i64 (zext (i32 IntRegs:$srcLow))))),
4548 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
4551 let AddedComplexity = 100 in
4552 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
4554 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
4555 s11_2ExtPred:$offset2)))))),
4556 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
4557 (L2_loadri_io IntRegs:$src2,
4558 s11_2ExtPred:$offset2)))>;
4560 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
4562 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
4563 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
4564 (L2_loadri_io AddrFI:$srcLow, 0)))>;
4566 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
4568 (i64 (zext (i32 IntRegs:$srcLow))))),
4569 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
4572 // Any extended 64-bit load.
4573 // anyext i32 -> i64
4574 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
4575 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io AddrFI:$src1, 0)))>,
4578 // When there is an offset we should prefer the pattern below over the pattern above.
4579 // The complexity of the above is 13 (gleaned from HexagonGenDAGIsel.inc)
4580 // So this complexity below is comfortably higher to allow for choosing the below.
4581 // If this is not done then we generate addresses such as
4582 // ********************************************
4583 // r1 = add (r0, #4)
4584 // r1 = memw(r1 + #0)
4586 // r1 = memw(r0 + #4)
4587 // ********************************************
4588 let AddedComplexity = 100 in
4589 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
4590 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io IntRegs:$src1,
4591 s11_2ExtPred:$offset)))>,
4594 // anyext i16 -> i64.
4595 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
4596 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrh_io AddrFI:$src1, 0)))>,
4599 let AddedComplexity = 20 in
4600 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
4601 s11_1ExtPred:$offset))),
4602 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrh_io IntRegs:$src1,
4603 s11_1ExtPred:$offset)))>,
4606 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
4607 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
4608 (i64 (A2_combinew (A2_tfrsi 0), (i32 IntRegs:$src1)))>,
4611 // Multiply 64-bit unsigned and use upper result.
4612 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
4627 (A2_combinew (A2_tfrsi 0),
4634 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
4636 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
4637 subreg_loreg)))), 32)),
4639 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
4640 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
4641 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
4642 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
4643 32)), subreg_loreg)))),
4644 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
4645 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
4647 // Multiply 64-bit signed and use upper result.
4648 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
4652 (A2_combinew (A2_tfrsi 0),
4662 (A2_combinew (A2_tfrsi 0),
4669 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
4671 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
4672 subreg_loreg)))), 32)),
4674 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
4675 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
4676 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
4677 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
4678 32)), subreg_loreg)))),
4679 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
4680 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
4682 // Hexagon specific ISD nodes.
4683 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
4684 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
4685 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
4686 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
4687 SDTHexagonADJDYNALLOC>;
4688 // Needed to tag these instructions for stack layout.
4689 let usesCustomInserter = 1 in
4690 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
4692 "$dst = add($src1, #$src2)",
4693 [(set (i32 IntRegs:$dst),
4694 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
4695 s16ImmPred:$src2))]>;
4697 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
4698 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
4699 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
4701 [(set (i32 IntRegs:$dst),
4702 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
4704 let AddedComplexity = 100 in
4705 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
4706 (COPY (i32 IntRegs:$src1))>;
4708 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
4710 def : Pat<(HexagonWrapperJT tjumptable:$dst),
4711 (i32 (CONST32_set_jt tjumptable:$dst))>;
4715 //===----------------------------------------------------------------------===//
4717 // Shift by immediate/register and accumulate/logical
4718 //===----------------------------------------------------------------------===//
4720 // Rx[+-&|]=asr(Rs,#u5)
4721 // Rx[+-&|^]=lsr(Rs,#u5)
4722 // Rx[+-&|^]=asl(Rs,#u5)
4724 let hasNewValue = 1, opNewValue = 0 in
4725 class T_shift_imm_acc_r <string opc1, string opc2, SDNode OpNode1,
4726 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
4727 : SInst_acc<(outs IntRegs:$Rx),
4728 (ins IntRegs:$src1, IntRegs:$Rs, u5Imm:$u5),
4729 "$Rx "#opc2#opc1#"($Rs, #$u5)",
4730 [(set (i32 IntRegs:$Rx),
4731 (OpNode2 (i32 IntRegs:$src1),
4732 (OpNode1 (i32 IntRegs:$Rs), u5ImmPred:$u5)))],
4733 "$src1 = $Rx", S_2op_tc_2_SLOT23> {
4738 let IClass = 0b1000;
4740 let Inst{27-24} = 0b1110;
4741 let Inst{23-22} = majOp{2-1};
4743 let Inst{7} = majOp{0};
4744 let Inst{6-5} = minOp;
4746 let Inst{20-16} = Rs;
4747 let Inst{12-8} = u5;
4750 // Rx[+-&|]=asr(Rs,Rt)
4751 // Rx[+-&|^]=lsr(Rs,Rt)
4752 // Rx[+-&|^]=asl(Rs,Rt)
4754 let hasNewValue = 1, opNewValue = 0 in
4755 class T_shift_reg_acc_r <string opc1, string opc2, SDNode OpNode1,
4756 SDNode OpNode2, bits<2> majOp, bits<2> minOp>
4757 : SInst_acc<(outs IntRegs:$Rx),
4758 (ins IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt),
4759 "$Rx "#opc2#opc1#"($Rs, $Rt)",
4760 [(set (i32 IntRegs:$Rx),
4761 (OpNode2 (i32 IntRegs:$src1),
4762 (OpNode1 (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))],
4763 "$src1 = $Rx", S_3op_tc_2_SLOT23 > {
4768 let IClass = 0b1100;
4770 let Inst{27-24} = 0b1100;
4771 let Inst{23-22} = majOp;
4772 let Inst{7-6} = minOp;
4774 let Inst{20-16} = Rs;
4775 let Inst{12-8} = Rt;
4778 // Rxx[+-&|]=asr(Rss,#u6)
4779 // Rxx[+-&|^]=lsr(Rss,#u6)
4780 // Rxx[+-&|^]=asl(Rss,#u6)
4782 class T_shift_imm_acc_p <string opc1, string opc2, SDNode OpNode1,
4783 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
4784 : SInst_acc<(outs DoubleRegs:$Rxx),
4785 (ins DoubleRegs:$src1, DoubleRegs:$Rss, u6Imm:$u6),
4786 "$Rxx "#opc2#opc1#"($Rss, #$u6)",
4787 [(set (i64 DoubleRegs:$Rxx),
4788 (OpNode2 (i64 DoubleRegs:$src1),
4789 (OpNode1 (i64 DoubleRegs:$Rss), u6ImmPred:$u6)))],
4790 "$src1 = $Rxx", S_2op_tc_2_SLOT23> {
4795 let IClass = 0b1000;
4797 let Inst{27-24} = 0b0010;
4798 let Inst{23-22} = majOp{2-1};
4799 let Inst{7} = majOp{0};
4800 let Inst{6-5} = minOp;
4801 let Inst{4-0} = Rxx;
4802 let Inst{20-16} = Rss;
4803 let Inst{13-8} = u6;
4807 // Rxx[+-&|]=asr(Rss,Rt)
4808 // Rxx[+-&|^]=lsr(Rss,Rt)
4809 // Rxx[+-&|^]=asl(Rss,Rt)
4810 // Rxx[+-&|^]=lsl(Rss,Rt)
4812 class T_shift_reg_acc_p <string opc1, string opc2, SDNode OpNode1,
4813 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
4814 : SInst_acc<(outs DoubleRegs:$Rxx),
4815 (ins DoubleRegs:$src1, DoubleRegs:$Rss, IntRegs:$Rt),
4816 "$Rxx "#opc2#opc1#"($Rss, $Rt)",
4817 [(set (i64 DoubleRegs:$Rxx),
4818 (OpNode2 (i64 DoubleRegs:$src1),
4819 (OpNode1 (i64 DoubleRegs:$Rss), (i32 IntRegs:$Rt))))],
4820 "$src1 = $Rxx", S_3op_tc_2_SLOT23> {
4825 let IClass = 0b1100;
4827 let Inst{27-24} = 0b1011;
4828 let Inst{23-21} = majOp;
4829 let Inst{20-16} = Rss;
4830 let Inst{12-8} = Rt;
4831 let Inst{7-6} = minOp;
4832 let Inst{4-0} = Rxx;
4835 //===----------------------------------------------------------------------===//
4836 // Multi-class for the shift instructions with logical/arithmetic operators.
4837 //===----------------------------------------------------------------------===//
4839 multiclass xtype_imm_base<string OpcStr1, string OpcStr2, SDNode OpNode1,
4840 SDNode OpNode2, bits<3> majOp, bits<2> minOp > {
4841 def _i_r#NAME : T_shift_imm_acc_r< OpcStr1, OpcStr2, OpNode1,
4842 OpNode2, majOp, minOp >;
4843 def _i_p#NAME : T_shift_imm_acc_p< OpcStr1, OpcStr2, OpNode1,
4844 OpNode2, majOp, minOp >;
4847 multiclass xtype_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
4848 let AddedComplexity = 100 in
4849 defm _acc : xtype_imm_base< opc1, "+= ", OpNode, add, 0b001, minOp>;
4851 defm _nac : xtype_imm_base< opc1, "-= ", OpNode, sub, 0b000, minOp>;
4852 defm _and : xtype_imm_base< opc1, "&= ", OpNode, and, 0b010, minOp>;
4853 defm _or : xtype_imm_base< opc1, "|= ", OpNode, or, 0b011, minOp>;
4856 multiclass xtype_xor_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
4857 let AddedComplexity = 100 in
4858 defm _xacc : xtype_imm_base< opc1, "^= ", OpNode, xor, 0b100, minOp>;
4861 let isCodeGenOnly = 0 in {
4862 defm S2_asr : xtype_imm_acc<"asr", sra, 0b00>;
4864 defm S2_lsr : xtype_imm_acc<"lsr", srl, 0b01>,
4865 xtype_xor_imm_acc<"lsr", srl, 0b01>;
4867 defm S2_asl : xtype_imm_acc<"asl", shl, 0b10>,
4868 xtype_xor_imm_acc<"asl", shl, 0b10>;
4871 multiclass xtype_reg_acc_r<string opc1, SDNode OpNode, bits<2>minOp> {
4872 let AddedComplexity = 100 in
4873 def _acc : T_shift_reg_acc_r <opc1, "+= ", OpNode, add, 0b11, minOp>;
4875 def _nac : T_shift_reg_acc_r <opc1, "-= ", OpNode, sub, 0b10, minOp>;
4876 def _and : T_shift_reg_acc_r <opc1, "&= ", OpNode, and, 0b01, minOp>;
4877 def _or : T_shift_reg_acc_r <opc1, "|= ", OpNode, or, 0b00, minOp>;
4880 multiclass xtype_reg_acc_p<string opc1, SDNode OpNode, bits<2>minOp> {
4881 let AddedComplexity = 100 in
4882 def _acc : T_shift_reg_acc_p <opc1, "+= ", OpNode, add, 0b110, minOp>;
4884 def _nac : T_shift_reg_acc_p <opc1, "-= ", OpNode, sub, 0b100, minOp>;
4885 def _and : T_shift_reg_acc_p <opc1, "&= ", OpNode, and, 0b010, minOp>;
4886 def _or : T_shift_reg_acc_p <opc1, "|= ", OpNode, or, 0b000, minOp>;
4887 def _xor : T_shift_reg_acc_p <opc1, "^= ", OpNode, xor, 0b011, minOp>;
4890 multiclass xtype_reg_acc<string OpcStr, SDNode OpNode, bits<2> minOp > {
4891 defm _r_r : xtype_reg_acc_r <OpcStr, OpNode, minOp>;
4892 defm _r_p : xtype_reg_acc_p <OpcStr, OpNode, minOp>;
4895 let isCodeGenOnly = 0 in {
4896 defm S2_asl : xtype_reg_acc<"asl", shl, 0b10>;
4897 defm S2_asr : xtype_reg_acc<"asr", sra, 0b00>;
4898 defm S2_lsr : xtype_reg_acc<"lsr", srl, 0b01>;
4899 defm S2_lsl : xtype_reg_acc<"lsl", shl, 0b11>;
4902 //===----------------------------------------------------------------------===//
4903 let hasSideEffects = 0 in
4904 class T_S3op_1 <string mnemonic, RegisterClass RC, bits<2> MajOp, bits<3> MinOp,
4905 bit SwapOps, bit isSat = 0, bit isRnd = 0, bit hasShift = 0>
4906 : SInst <(outs RC:$dst),
4907 (ins DoubleRegs:$src1, DoubleRegs:$src2),
4908 "$dst = "#mnemonic#"($src1, $src2)"#!if(isRnd, ":rnd", "")
4909 #!if(hasShift,":>>1","")
4910 #!if(isSat, ":sat", ""),
4911 [], "", S_3op_tc_2_SLOT23 > {
4916 let IClass = 0b1100;
4918 let Inst{27-24} = 0b0001;
4919 let Inst{23-22} = MajOp;
4920 let Inst{20-16} = !if (SwapOps, src2, src1);
4921 let Inst{12-8} = !if (SwapOps, src1, src2);
4922 let Inst{7-5} = MinOp;
4923 let Inst{4-0} = dst;
4926 class T_S3op_64 <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit SwapOps,
4927 bit isSat = 0, bit isRnd = 0, bit hasShift = 0 >
4928 : T_S3op_1 <mnemonic, DoubleRegs, MajOp, MinOp, SwapOps,
4929 isSat, isRnd, hasShift>;
4931 let isCodeGenOnly = 0 in
4932 def S2_lfsp : T_S3op_64 < "lfs", 0b10, 0b110, 0>;
4934 let hasSideEffects = 0 in
4935 class T_S3op_2 <string mnemonic, bits<3> MajOp, bit SwapOps>
4936 : SInst < (outs DoubleRegs:$Rdd),
4937 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
4938 "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu)",
4939 [], "", S_3op_tc_1_SLOT23 > {
4945 let IClass = 0b1100;
4947 let Inst{27-24} = 0b0010;
4948 let Inst{23-21} = MajOp;
4949 let Inst{20-16} = !if (SwapOps, Rtt, Rss);
4950 let Inst{12-8} = !if (SwapOps, Rss, Rtt);
4952 let Inst{4-0} = Rdd;
4955 let isCodeGenOnly = 0 in {
4956 def S2_valignrb : T_S3op_2 < "valignb", 0b000, 1>;
4957 def S2_vsplicerb : T_S3op_2 < "vspliceb", 0b100, 0>;
4960 //===----------------------------------------------------------------------===//
4961 // Template class used by vector shift, vector rotate, vector neg,
4962 // 32-bit shift, 64-bit shifts, etc.
4963 //===----------------------------------------------------------------------===//
4965 let hasSideEffects = 0 in
4966 class T_S3op_3 <string mnemonic, RegisterClass RC, bits<2> MajOp,
4967 bits<2> MinOp, bit isSat = 0, list<dag> pattern = [] >
4968 : SInst <(outs RC:$dst),
4969 (ins RC:$src1, IntRegs:$src2),
4970 "$dst = "#mnemonic#"($src1, $src2)"#!if(isSat, ":sat", ""),
4971 pattern, "", S_3op_tc_1_SLOT23> {
4976 let IClass = 0b1100;
4978 let Inst{27-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b0110, 0b0011);
4979 let Inst{23-22} = MajOp;
4980 let Inst{20-16} = src1;
4981 let Inst{12-8} = src2;
4982 let Inst{7-6} = MinOp;
4983 let Inst{4-0} = dst;
4986 let hasNewValue = 1 in
4987 class T_S3op_shift32 <string mnemonic, SDNode OpNode, bits<2> MinOp>
4988 : T_S3op_3 <mnemonic, IntRegs, 0b01, MinOp, 0,
4989 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
4990 (i32 IntRegs:$src2)))]>;
4992 let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in
4993 class T_S3op_shift32_Sat <string mnemonic, bits<2> MinOp>
4994 : T_S3op_3 <mnemonic, IntRegs, 0b00, MinOp, 1, []>;
4997 class T_S3op_shift64 <string mnemonic, SDNode OpNode, bits<2> MinOp>
4998 : T_S3op_3 <mnemonic, DoubleRegs, 0b10, MinOp, 0,
4999 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1),
5000 (i32 IntRegs:$src2)))]>;
5003 class T_S3op_shiftVect <string mnemonic, bits<2> MajOp, bits<2> MinOp>
5004 : T_S3op_3 <mnemonic, DoubleRegs, MajOp, MinOp, 0, []>;
5007 // Shift by register
5008 // Rdd=[asr|lsr|asl|lsl](Rss,Rt)
5010 let isCodeGenOnly = 0 in {
5011 def S2_asr_r_p : T_S3op_shift64 < "asr", sra, 0b00>;
5012 def S2_lsr_r_p : T_S3op_shift64 < "lsr", srl, 0b01>;
5013 def S2_asl_r_p : T_S3op_shift64 < "asl", shl, 0b10>;
5014 def S2_lsl_r_p : T_S3op_shift64 < "lsl", shl, 0b11>;
5017 // Rd=[asr|lsr|asl|lsl](Rs,Rt)
5019 let isCodeGenOnly = 0 in {
5020 def S2_asr_r_r : T_S3op_shift32<"asr", sra, 0b00>;
5021 def S2_lsr_r_r : T_S3op_shift32<"lsr", srl, 0b01>;
5022 def S2_asl_r_r : T_S3op_shift32<"asl", shl, 0b10>;
5023 def S2_lsl_r_r : T_S3op_shift32<"lsl", shl, 0b11>;
5026 // Shift by register with saturation
5027 // Rd=asr(Rs,Rt):sat
5028 // Rd=asl(Rs,Rt):sat
5030 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
5031 def S2_asr_r_r_sat : T_S3op_shift32_Sat<"asr", 0b00>;
5032 def S2_asl_r_r_sat : T_S3op_shift32_Sat<"asl", 0b10>;
5035 //===----------------------------------------------------------------------===//
5036 // Template class for 'insert bitfield' instructions
5037 //===----------------------------------------------------------------------===//
5038 let hasSideEffects = 0 in
5039 class T_S3op_insert <string mnemonic, RegisterClass RC>
5040 : SInst <(outs RC:$dst),
5041 (ins RC:$src1, RC:$src2, DoubleRegs:$src3),
5042 "$dst = "#mnemonic#"($src2, $src3)" ,
5043 [], "$src1 = $dst", S_3op_tc_1_SLOT23 > {
5048 let IClass = 0b1100;
5050 let Inst{27-26} = 0b10;
5051 let Inst{25-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b00, 0b10);
5053 let Inst{20-16} = src2;
5054 let Inst{12-8} = src3;
5055 let Inst{4-0} = dst;
5058 let hasSideEffects = 0 in
5059 class T_S2op_insert <bits<4> RegTyBits, RegisterClass RC, Operand ImmOp>
5060 : SInst <(outs RC:$dst), (ins RC:$dst2, RC:$src1, ImmOp:$src2, ImmOp:$src3),
5061 "$dst = insert($src1, #$src2, #$src3)",
5062 [], "$dst2 = $dst", S_2op_tc_2_SLOT23> {
5069 string ImmOpStr = !cast<string>(ImmOp);
5071 let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5}, 0);
5072 let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0);
5074 let IClass = 0b1000;
5076 let Inst{27-24} = RegTyBits;
5077 let Inst{23} = bit23;
5078 let Inst{22-21} = src3{4-3};
5079 let Inst{20-16} = src1;
5080 let Inst{13} = bit13;
5081 let Inst{12-8} = src2{4-0};
5082 let Inst{7-5} = src3{2-0};
5083 let Inst{4-0} = dst;
5086 // Rx=insert(Rs,Rtt)
5087 // Rx=insert(Rs,#u5,#U5)
5088 let hasNewValue = 1, isCodeGenOnly = 0 in {
5089 def S2_insert_rp : T_S3op_insert <"insert", IntRegs>;
5090 def S2_insert : T_S2op_insert <0b1111, IntRegs, u5Imm>;
5093 // Rxx=insert(Rss,Rtt)
5094 // Rxx=insert(Rss,#u6,#U6)
5095 let isCodeGenOnly = 0 in {
5096 def S2_insertp_rp : T_S3op_insert<"insert", DoubleRegs>;
5097 def S2_insertp : T_S2op_insert <0b0011, DoubleRegs, u6Imm>;
5100 //===----------------------------------------------------------------------===//
5101 // Template class for 'extract bitfield' instructions
5102 //===----------------------------------------------------------------------===//
5103 let hasNewValue = 1, hasSideEffects = 0 in
5104 class T_S3op_extract <string mnemonic, bits<2> MinOp>
5105 : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
5106 "$Rd = "#mnemonic#"($Rs, $Rtt)",
5107 [], "", S_3op_tc_2_SLOT23 > {
5112 let IClass = 0b1100;
5114 let Inst{27-22} = 0b100100;
5115 let Inst{20-16} = Rs;
5116 let Inst{12-8} = Rtt;
5117 let Inst{7-6} = MinOp;
5121 let hasSideEffects = 0 in
5122 class T_S2op_extract <string mnemonic, bits<4> RegTyBits,
5123 RegisterClass RC, Operand ImmOp>
5124 : SInst <(outs RC:$dst), (ins RC:$src1, ImmOp:$src2, ImmOp:$src3),
5125 "$dst = "#mnemonic#"($src1, #$src2, #$src3)",
5126 [], "", S_2op_tc_2_SLOT23> {
5133 string ImmOpStr = !cast<string>(ImmOp);
5135 let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5},
5136 !if (!eq(mnemonic, "extractu"), 0, 1));
5138 let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0);
5140 let IClass = 0b1000;
5142 let Inst{27-24} = RegTyBits;
5143 let Inst{23} = bit23;
5144 let Inst{22-21} = src3{4-3};
5145 let Inst{20-16} = src1;
5146 let Inst{13} = bit13;
5147 let Inst{12-8} = src2{4-0};
5148 let Inst{7-5} = src3{2-0};
5149 let Inst{4-0} = dst;
5154 // Rdd=extractu(Rss,Rtt)
5155 // Rdd=extractu(Rss,#u6,#U6)
5156 let isCodeGenOnly = 0 in {
5157 def S2_extractup_rp : T_S3op_64 < "extractu", 0b00, 0b000, 0>;
5158 def S2_extractup : T_S2op_extract <"extractu", 0b0001, DoubleRegs, u6Imm>;
5161 // Rd=extractu(Rs,Rtt)
5162 // Rd=extractu(Rs,#u5,#U5)
5163 let hasNewValue = 1, isCodeGenOnly = 0 in {
5164 def S2_extractu_rp : T_S3op_extract<"extractu", 0b00>;
5165 def S2_extractu : T_S2op_extract <"extractu", 0b1101, IntRegs, u5Imm>;
5168 //===----------------------------------------------------------------------===//
5169 // :raw for of tableindx[bdhw] insns
5170 //===----------------------------------------------------------------------===//
5172 let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
5173 class tableidxRaw<string OpStr, bits<2>MinOp>
5174 : SInst <(outs IntRegs:$Rx),
5175 (ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, s6Imm:$S6),
5176 "$Rx = "#OpStr#"($Rs, #$u4, #$S6):raw",
5177 [], "$Rx = $_dst_" > {
5183 let IClass = 0b1000;
5185 let Inst{27-24} = 0b0111;
5186 let Inst{23-22} = MinOp;
5187 let Inst{21} = u4{3};
5188 let Inst{20-16} = Rs;
5189 let Inst{13-8} = S6;
5190 let Inst{7-5} = u4{2-0};
5194 let isCodeGenOnly = 0 in {
5195 def S2_tableidxb : tableidxRaw<"tableidxb", 0b00>;
5196 def S2_tableidxh : tableidxRaw<"tableidxh", 0b01>;
5197 def S2_tableidxw : tableidxRaw<"tableidxw", 0b10>;
5198 def S2_tableidxd : tableidxRaw<"tableidxd", 0b11>;
5201 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
5202 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
5203 (i32 (M2_mpysin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
5205 //===----------------------------------------------------------------------===//
5206 // V3 Instructions +
5207 //===----------------------------------------------------------------------===//
5209 include "HexagonInstrInfoV3.td"
5211 //===----------------------------------------------------------------------===//
5212 // V3 Instructions -
5213 //===----------------------------------------------------------------------===//
5215 //===----------------------------------------------------------------------===//
5216 // V4 Instructions +
5217 //===----------------------------------------------------------------------===//
5219 include "HexagonInstrInfoV4.td"
5221 //===----------------------------------------------------------------------===//
5222 // V4 Instructions -
5223 //===----------------------------------------------------------------------===//
5225 //===----------------------------------------------------------------------===//
5226 // V5 Instructions +
5227 //===----------------------------------------------------------------------===//
5229 include "HexagonInstrInfoV5.td"
5231 //===----------------------------------------------------------------------===//
5232 // V5 Instructions -
5233 //===----------------------------------------------------------------------===//