1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
17 // Pattern fragment that combines the value type and the register class
18 // into a single parameter.
19 // The pat frags in the definitions below need to have a named register,
20 // otherwise i32 will be assumed regardless of the register class. The
21 // name of the register does not matter.
22 def I1 : PatLeaf<(i1 PredRegs:$R)>;
23 def I32 : PatLeaf<(i32 IntRegs:$R)>;
24 def I64 : PatLeaf<(i64 DoubleRegs:$R)>;
25 def F32 : PatLeaf<(f32 IntRegs:$R)>;
26 def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
28 // Pattern fragments to extract the low and high subregisters from a
30 def LoReg: OutPatFrag<(ops node:$Rs),
31 (EXTRACT_SUBREG (i64 $Rs), subreg_loreg)>;
32 def HiReg: OutPatFrag<(ops node:$Rs),
33 (EXTRACT_SUBREG (i64 $Rs), subreg_hireg)>;
35 // SDNode for converting immediate C to C-1.
36 def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
37 // Return the byte immediate const-1 as an SDNode.
38 int32_t imm = N->getSExtValue();
39 return XformSToSM1Imm(imm);
42 // SDNode for converting immediate C to C-2.
43 def DEC2_CONST_SIGNED : SDNodeXForm<imm, [{
44 // Return the byte immediate const-2 as an SDNode.
45 int32_t imm = N->getSExtValue();
46 return XformSToSM2Imm(imm);
49 // SDNode for converting immediate C to C-3.
50 def DEC3_CONST_SIGNED : SDNodeXForm<imm, [{
51 // Return the byte immediate const-3 as an SDNode.
52 int32_t imm = N->getSExtValue();
53 return XformSToSM3Imm(imm);
56 // SDNode for converting immediate C to C-1.
57 def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
58 // Return the byte immediate const-1 as an SDNode.
59 uint32_t imm = N->getZExtValue();
60 return XformUToUM1Imm(imm);
63 //===----------------------------------------------------------------------===//
65 //===----------------------------------------------------------------------===//
66 let hasSideEffects = 0, isCompare = 1, InputType = "imm", isExtendable = 1,
68 class T_CMP <string mnemonic, bits<2> MajOp, bit isNot, Operand ImmOp>
69 : ALU32Inst <(outs PredRegs:$dst),
70 (ins IntRegs:$src1, ImmOp:$src2),
71 "$dst = "#!if(isNot, "!","")#mnemonic#"($src1, #$src2)",
72 [], "",ALU32_2op_tc_2early_SLOT0123 >, ImmRegRel {
76 let CextOpcode = mnemonic;
77 let opExtentBits = !if(!eq(mnemonic, "cmp.gtu"), 9, 10);
78 let isExtentSigned = !if(!eq(mnemonic, "cmp.gtu"), 0, 1);
82 let Inst{27-24} = 0b0101;
83 let Inst{23-22} = MajOp;
84 let Inst{21} = !if(!eq(mnemonic, "cmp.gtu"), 0, src2{9});
85 let Inst{20-16} = src1;
86 let Inst{13-5} = src2{8-0};
92 def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10Ext>;
93 def C2_cmpgti : T_CMP <"cmp.gt", 0b01, 0, s10Ext>;
94 def C2_cmpgtui : T_CMP <"cmp.gtu", 0b10, 0, u9Ext>;
96 class T_CMP_pat <InstHexagon MI, PatFrag OpNode, PatLeaf ImmPred>
97 : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)),
98 (MI IntRegs:$src1, ImmPred:$src2)>;
100 def : T_CMP_pat <C2_cmpeqi, seteq, s10ImmPred>;
101 def : T_CMP_pat <C2_cmpgti, setgt, s10ImmPred>;
102 def : T_CMP_pat <C2_cmpgtui, setugt, u9ImmPred>;
104 //===----------------------------------------------------------------------===//
106 //===----------------------------------------------------------------------===//
109 def SDT_Int32Leaf : SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>;
110 def SDT_Int32Unary : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
112 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
113 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
115 def HexagonCOMBINE : SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>;
116 def HexagonPACKHL : SDNode<"HexagonISD::PACKHL", SDTHexagonI64I32I32>;
118 let hasSideEffects = 0, hasNewValue = 1, InputType = "reg" in
119 class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev,
121 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
122 "$Rd = "#mnemonic#"($Rs, $Rt)",
123 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredRel {
124 let isCommutable = IsComm;
125 let BaseOpcode = mnemonic#_rr;
126 let CextOpcode = mnemonic;
134 let Inst{26-24} = MajOp;
135 let Inst{23-21} = MinOp;
136 let Inst{20-16} = !if(OpsRev,Rt,Rs);
137 let Inst{12-8} = !if(OpsRev,Rs,Rt);
141 let hasSideEffects = 0, hasNewValue = 1 in
142 class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp,
143 bit OpsRev, bit PredNot, bit PredNew>
144 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
145 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") "#
146 "$Rd = "#mnemonic#"($Rs, $Rt)",
147 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
148 let isPredicated = 1;
149 let isPredicatedFalse = PredNot;
150 let isPredicatedNew = PredNew;
151 let BaseOpcode = mnemonic#_rr;
152 let CextOpcode = mnemonic;
161 let Inst{26-24} = MajOp;
162 let Inst{23-21} = MinOp;
163 let Inst{20-16} = !if(OpsRev,Rt,Rs);
164 let Inst{13} = PredNew;
165 let Inst{12-8} = !if(OpsRev,Rs,Rt);
166 let Inst{7} = PredNot;
171 class T_ALU32_combineh<string Op1, string Op2, bits<3> MajOp, bits<3> MinOp,
173 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, 0> {
174 let AsmString = "$Rd = combine($Rs"#Op1#", $Rt"#Op2#")";
177 def A2_combine_hh : T_ALU32_combineh<".h", ".h", 0b011, 0b100, 1>;
178 def A2_combine_hl : T_ALU32_combineh<".h", ".l", 0b011, 0b101, 1>;
179 def A2_combine_lh : T_ALU32_combineh<".l", ".h", 0b011, 0b110, 1>;
180 def A2_combine_ll : T_ALU32_combineh<".l", ".l", 0b011, 0b111, 1>;
182 class T_ALU32_3op_sfx<string mnemonic, string suffix, bits<3> MajOp,
183 bits<3> MinOp, bit OpsRev, bit IsComm>
184 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, IsComm> {
185 let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix;
188 def A2_svaddh : T_ALU32_3op<"vaddh", 0b110, 0b000, 0, 1>;
189 def A2_svsubh : T_ALU32_3op<"vsubh", 0b110, 0b100, 1, 0>;
191 let Defs = [USR_OVF], Itinerary = ALU32_3op_tc_2_SLOT0123 in {
192 def A2_svaddhs : T_ALU32_3op_sfx<"vaddh", ":sat", 0b110, 0b001, 0, 1>;
193 def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>;
194 def A2_svadduhs : T_ALU32_3op_sfx<"vadduh", ":sat", 0b110, 0b011, 0, 1>;
195 def A2_svsubhs : T_ALU32_3op_sfx<"vsubh", ":sat", 0b110, 0b101, 1, 0>;
196 def A2_subsat : T_ALU32_3op_sfx<"sub", ":sat", 0b110, 0b110, 1, 0>;
197 def A2_svsubuhs : T_ALU32_3op_sfx<"vsubuh", ":sat", 0b110, 0b111, 1, 0>;
200 let Itinerary = ALU32_3op_tc_2_SLOT0123 in
201 def A2_svavghs : T_ALU32_3op_sfx<"vavgh", ":rnd", 0b111, 0b001, 0, 1>;
203 def A2_svavgh : T_ALU32_3op<"vavgh", 0b111, 0b000, 0, 1>;
204 def A2_svnavgh : T_ALU32_3op<"vnavgh", 0b111, 0b011, 1, 0>;
206 multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,
208 def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>;
209 def f : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 0>;
210 def tnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 1>;
211 def fnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 1>;
214 multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp,
215 bit OpsRev, bit IsComm> {
216 let isPredicable = 1 in
217 def A2_#NAME : T_ALU32_3op <mnemonic, MajOp, MinOp, OpsRev, IsComm>;
218 defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>;
221 defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
222 defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>;
223 defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>;
224 defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>;
225 defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>;
227 // Pats for instruction selection.
228 class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
229 : Pat<(ResT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
230 (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
232 def: BinOp32_pat<add, A2_add, i32>;
233 def: BinOp32_pat<and, A2_and, i32>;
234 def: BinOp32_pat<or, A2_or, i32>;
235 def: BinOp32_pat<sub, A2_sub, i32>;
236 def: BinOp32_pat<xor, A2_xor, i32>;
238 // A few special cases producing register pairs:
239 let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0 in {
240 def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>;
242 let isPredicable = 1 in
243 def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>;
245 // Conditional combinew uses "newt/f" instead of "t/fnew".
246 def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>;
247 def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>;
248 def C2_ccombinewnewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 1>;
249 def C2_ccombinewnewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 1>;
252 def: BinOp32_pat<HexagonCOMBINE, A2_combinew, i64>;
253 def: BinOp32_pat<HexagonPACKHL, S2_packhl, i64>;
255 let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in
256 class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm>
257 : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
258 "$Pd = "#mnemonic#"($Rs, $Rt)",
259 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
260 let CextOpcode = mnemonic;
261 let isCommutable = IsComm;
267 let Inst{27-24} = 0b0010;
268 let Inst{22-21} = MinOp;
269 let Inst{20-16} = Rs;
272 let Inst{3-2} = 0b00;
276 let Itinerary = ALU32_3op_tc_2early_SLOT0123 in {
277 def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>;
278 def C2_cmpgt : T_ALU32_3op_cmp< "cmp.gt", 0b10, 0, 0>;
279 def C2_cmpgtu : T_ALU32_3op_cmp< "cmp.gtu", 0b11, 0, 0>;
282 // Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones
283 // that reverse the order of the operands.
284 class RevCmp<PatFrag F> : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment>;
286 // Pats for compares. They use PatFrags as operands, not SDNodes,
287 // since seteq/setgt/etc. are defined as ParFrags.
288 class T_cmp32_rr_pat<InstHexagon MI, PatFrag Op, ValueType VT>
289 : Pat<(VT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
290 (VT (MI IntRegs:$Rs, IntRegs:$Rt))>;
292 def: T_cmp32_rr_pat<C2_cmpeq, seteq, i1>;
293 def: T_cmp32_rr_pat<C2_cmpgt, setgt, i1>;
294 def: T_cmp32_rr_pat<C2_cmpgtu, setugt, i1>;
296 def: T_cmp32_rr_pat<C2_cmpgt, RevCmp<setlt>, i1>;
297 def: T_cmp32_rr_pat<C2_cmpgtu, RevCmp<setult>, i1>;
299 let CextOpcode = "MUX", InputType = "reg", hasNewValue = 1 in
300 def C2_mux: ALU32_rr<(outs IntRegs:$Rd),
301 (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
302 "$Rd = mux($Pu, $Rs, $Rt)", [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
308 let CextOpcode = "mux";
309 let InputType = "reg";
310 let hasSideEffects = 0;
313 let Inst{27-24} = 0b0100;
314 let Inst{20-16} = Rs;
320 def: Pat<(i32 (select (i1 PredRegs:$Pu), (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
321 (C2_mux PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt)>;
323 // Combines the two immediates into a double register.
324 // Increase complexity to make it greater than any complexity of a combine
325 // that involves a register.
327 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
328 isExtentSigned = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 1,
329 AddedComplexity = 75 in
330 def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8),
331 "$Rdd = combine(#$s8, #$S8)",
332 [(set (i64 DoubleRegs:$Rdd),
333 (i64 (HexagonCOMBINE(i32 s32ImmPred:$s8), (i32 s8ImmPred:$S8))))]> {
339 let Inst{27-23} = 0b11000;
340 let Inst{22-16} = S8{7-1};
341 let Inst{13} = S8{0};
346 //===----------------------------------------------------------------------===//
347 // Template class for predicated ADD of a reg and an Immediate value.
348 //===----------------------------------------------------------------------===//
349 let hasNewValue = 1, hasSideEffects = 0 in
350 class T_Addri_Pred <bit PredNot, bit PredNew>
351 : ALU32_ri <(outs IntRegs:$Rd),
352 (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
353 !if(PredNot, "if (!$Pu", "if ($Pu")#!if(PredNew,".new) $Rd = ",
354 ") $Rd = ")#"add($Rs, #$s8)"> {
360 let isPredicatedNew = PredNew;
363 let Inst{27-24} = 0b0100;
364 let Inst{23} = PredNot;
365 let Inst{22-21} = Pu;
366 let Inst{20-16} = Rs;
367 let Inst{13} = PredNew;
372 //===----------------------------------------------------------------------===//
373 // A2_addi: Add a signed immediate to a register.
374 //===----------------------------------------------------------------------===//
375 let hasNewValue = 1, hasSideEffects = 0 in
376 class T_Addri <Operand immOp>
377 : ALU32_ri <(outs IntRegs:$Rd),
378 (ins IntRegs:$Rs, immOp:$s16),
379 "$Rd = add($Rs, #$s16)", [], "", ALU32_ADDI_tc_1_SLOT0123> {
386 let Inst{27-21} = s16{15-9};
387 let Inst{20-16} = Rs;
388 let Inst{13-5} = s16{8-0};
392 //===----------------------------------------------------------------------===//
393 // Multiclass for ADD of a register and an immediate value.
394 //===----------------------------------------------------------------------===//
395 multiclass Addri_Pred<string mnemonic, bit PredNot> {
396 let isPredicatedFalse = PredNot in {
397 def NAME : T_Addri_Pred<PredNot, 0>;
399 def NAME#new : T_Addri_Pred<PredNot, 1>;
403 let isExtendable = 1, isExtentSigned = 1, InputType = "imm" in
404 multiclass Addri_base<string mnemonic, SDNode OpNode> {
405 let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in {
406 let opExtendable = 2, opExtentBits = 16, isPredicable = 1 in
407 def A2_#NAME : T_Addri<s16Ext>;
409 let opExtendable = 3, opExtentBits = 8, isPredicated = 1 in {
410 defm A2_p#NAME#t : Addri_Pred<mnemonic, 0>;
411 defm A2_p#NAME#f : Addri_Pred<mnemonic, 1>;
416 defm addi : Addri_base<"add", add>, ImmRegRel, PredNewRel;
418 def: Pat<(i32 (add I32:$Rs, s32ImmPred:$s16)),
419 (i32 (A2_addi I32:$Rs, imm:$s16))>;
421 //===----------------------------------------------------------------------===//
422 // Template class used for the following ALU32 instructions.
425 //===----------------------------------------------------------------------===//
426 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
427 InputType = "imm", hasNewValue = 1 in
428 class T_ALU32ri_logical <string mnemonic, SDNode OpNode, bits<2> MinOp>
429 : ALU32_ri <(outs IntRegs:$Rd),
430 (ins IntRegs:$Rs, s10Ext:$s10),
431 "$Rd = "#mnemonic#"($Rs, #$s10)" ,
432 [(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s32ImmPred:$s10))]> {
436 let CextOpcode = mnemonic;
440 let Inst{27-24} = 0b0110;
441 let Inst{23-22} = MinOp;
442 let Inst{21} = s10{9};
443 let Inst{20-16} = Rs;
444 let Inst{13-5} = s10{8-0};
448 def A2_orir : T_ALU32ri_logical<"or", or, 0b10>, ImmRegRel;
449 def A2_andir : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel;
451 // Subtract register from immediate
452 // Rd32=sub(#s10,Rs32)
453 let isExtendable = 1, CextOpcode = "sub", opExtendable = 1, isExtentSigned = 1,
454 opExtentBits = 10, InputType = "imm", hasNewValue = 1, hasSideEffects = 0 in
455 def A2_subri: ALU32_ri <(outs IntRegs:$Rd), (ins s10Ext:$s10, IntRegs:$Rs),
456 "$Rd = sub(#$s10, $Rs)", []>, ImmRegRel {
463 let Inst{27-22} = 0b011001;
464 let Inst{21} = s10{9};
465 let Inst{20-16} = Rs;
466 let Inst{13-5} = s10{8-0};
471 let hasSideEffects = 0 in
472 def A2_nop: ALU32Inst <(outs), (ins), "nop" > {
474 let Inst{27-24} = 0b1111;
477 def: Pat<(sub s32ImmPred:$s10, IntRegs:$Rs),
478 (A2_subri imm:$s10, IntRegs:$Rs)>;
480 // Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
481 def: Pat<(not (i32 IntRegs:$src1)),
482 (A2_subri -1, IntRegs:$src1)>;
484 let hasSideEffects = 0, hasNewValue = 1 in
485 class T_tfr16<bit isHi>
486 : ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16Imm:$u16),
487 "$Rx"#!if(isHi, ".h", ".l")#" = #$u16",
488 [], "$src1 = $Rx" > {
493 let Inst{27-26} = 0b00;
494 let Inst{25-24} = !if(isHi, 0b10, 0b01);
495 let Inst{23-22} = u16{15-14};
497 let Inst{20-16} = Rx;
498 let Inst{13-0} = u16{13-0};
501 def A2_tfril: T_tfr16<0>;
502 def A2_tfrih: T_tfr16<1>;
504 // Conditional transfer is an alias to conditional "Rd = add(Rs, #0)".
505 let isPredicated = 1, hasNewValue = 1, opNewValue = 0 in
506 class T_tfr_pred<bit isPredNot, bit isPredNew>
507 : ALU32Inst<(outs IntRegs:$dst),
508 (ins PredRegs:$src1, IntRegs:$src2),
509 "if ("#!if(isPredNot, "!", "")#
510 "$src1"#!if(isPredNew, ".new", "")#
516 let isPredicatedFalse = isPredNot;
517 let isPredicatedNew = isPredNew;
520 let Inst{27-24} = 0b0100;
521 let Inst{23} = isPredNot;
522 let Inst{13} = isPredNew;
525 let Inst{22-21} = src1;
526 let Inst{20-16} = src2;
529 let isPredicable = 1 in
530 class T_tfr : ALU32Inst<(outs IntRegs:$dst), (ins IntRegs:$src),
537 let Inst{27-21} = 0b0000011;
538 let Inst{20-16} = src;
543 let InputType = "reg", hasNewValue = 1, hasSideEffects = 0 in
544 multiclass tfr_base<string CextOp> {
545 let CextOpcode = CextOp, BaseOpcode = CextOp in {
549 def t : T_tfr_pred<0, 0>;
550 def f : T_tfr_pred<1, 0>;
552 def tnew : T_tfr_pred<0, 1>;
553 def fnew : T_tfr_pred<1, 1>;
557 // Assembler mapped to C2_ccombinew[t|f|newt|newf].
558 // Please don't add bits to this instruction as it'll be converted into
559 // 'combine' before object code emission.
560 let isPredicated = 1 in
561 class T_tfrp_pred<bit PredNot, bit PredNew>
562 : ALU32_rr <(outs DoubleRegs:$dst),
563 (ins PredRegs:$src1, DoubleRegs:$src2),
564 "if ("#!if(PredNot, "!", "")#"$src1"
565 #!if(PredNew, ".new", "")#") $dst = $src2" > {
566 let isPredicatedFalse = PredNot;
567 let isPredicatedNew = PredNew;
570 // Assembler mapped to A2_combinew.
571 // Please don't add bits to this instruction as it'll be converted into
572 // 'combine' before object code emission.
573 class T_tfrp : ALU32Inst <(outs DoubleRegs:$dst),
574 (ins DoubleRegs:$src),
577 let hasSideEffects = 0 in
578 multiclass TFR64_base<string BaseName> {
579 let BaseOpcode = BaseName in {
580 let isPredicable = 1 in
583 def t : T_tfrp_pred <0, 0>;
584 def f : T_tfrp_pred <1, 0>;
586 def tnew : T_tfrp_pred <0, 1>;
587 def fnew : T_tfrp_pred <1, 1>;
591 let InputType = "imm", isExtendable = 1, isExtentSigned = 1, opExtentBits = 12,
592 isMoveImm = 1, opExtendable = 2, BaseOpcode = "TFRI", CextOpcode = "TFR",
593 hasSideEffects = 0, isPredicated = 1, hasNewValue = 1 in
594 class T_TFRI_Pred<bit PredNot, bit PredNew>
595 : ALU32_ri<(outs IntRegs:$Rd), (ins PredRegs:$Pu, s12Ext:$s12),
596 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") $Rd = #$s12",
597 [], "", ALU32_2op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
598 let isPredicatedFalse = PredNot;
599 let isPredicatedNew = PredNew;
606 let Inst{27-24} = 0b1110;
607 let Inst{23} = PredNot;
608 let Inst{22-21} = Pu;
610 let Inst{19-16,12-5} = s12;
611 let Inst{13} = PredNew;
615 def C2_cmoveit : T_TFRI_Pred<0, 0>;
616 def C2_cmoveif : T_TFRI_Pred<1, 0>;
617 def C2_cmovenewit : T_TFRI_Pred<0, 1>;
618 def C2_cmovenewif : T_TFRI_Pred<1, 1>;
620 let InputType = "imm", isExtendable = 1, isExtentSigned = 1,
621 CextOpcode = "TFR", BaseOpcode = "TFRI", hasNewValue = 1, opNewValue = 0,
622 isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16, isMoveImm = 1,
623 isPredicated = 0, isPredicable = 1, isReMaterializable = 1 in
624 def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16Ext:$s16), "$Rd = #$s16",
625 [(set (i32 IntRegs:$Rd), s32ImmPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>,
631 let Inst{27-24} = 0b1000;
632 let Inst{23-22,20-16,13-5} = s16;
636 defm A2_tfr : tfr_base<"TFR">, ImmRegRel, PredNewRel;
637 let isAsmParserOnly = 1 in
638 defm A2_tfrp : TFR64_base<"TFR64">, PredNewRel;
641 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
642 isAsmParserOnly = 1 in
643 def A2_tfrpi : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
645 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
647 // TODO: see if this instruction can be deleted..
648 let isExtendable = 1, opExtendable = 1, opExtentBits = 6,
649 isAsmParserOnly = 1 in {
650 def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u64Imm:$src1),
652 def TFRI64_V2_ext : ALU64_rr<(outs DoubleRegs:$dst),
653 (ins s8Ext:$src1, s8Imm:$src2),
654 "$dst = combine(##$src1, #$src2)">;
657 //===----------------------------------------------------------------------===//
659 //===----------------------------------------------------------------------===//
662 //===----------------------------------------------------------------------===//
664 //===----------------------------------------------------------------------===//
665 // Scalar mux register immediate.
666 let hasSideEffects = 0, isExtentSigned = 1, CextOpcode = "MUX",
667 InputType = "imm", hasNewValue = 1, isExtendable = 1, opExtentBits = 8 in
668 class T_MUX1 <bit MajOp, dag ins, string AsmStr>
669 : ALU32Inst <(outs IntRegs:$Rd), ins, AsmStr>, ImmRegRel {
676 let Inst{27-24} = 0b0011;
677 let Inst{23} = MajOp;
678 let Inst{22-21} = Pu;
679 let Inst{20-16} = Rs;
685 let opExtendable = 2 in
686 def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8Ext:$s8, IntRegs:$Rs),
687 "$Rd = mux($Pu, #$s8, $Rs)">;
689 let opExtendable = 3 in
690 def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
691 "$Rd = mux($Pu, $Rs, #$s8)">;
693 def : Pat<(i32 (select I1:$Pu, s32ImmPred:$s8, I32:$Rs)),
694 (C2_muxri I1:$Pu, s32ImmPred:$s8, I32:$Rs)>;
696 def : Pat<(i32 (select I1:$Pu, I32:$Rs, s32ImmPred:$s8)),
697 (C2_muxir I1:$Pu, I32:$Rs, s32ImmPred:$s8)>;
699 // C2_muxii: Scalar mux immediates.
700 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1,
701 opExtentBits = 8, opExtendable = 2 in
702 def C2_muxii: ALU32Inst <(outs IntRegs:$Rd),
703 (ins PredRegs:$Pu, s8Ext:$s8, s8Imm:$S8),
704 "$Rd = mux($Pu, #$s8, #$S8)" ,
705 [(set (i32 IntRegs:$Rd),
706 (i32 (select I1:$Pu, s32ImmPred:$s8, s8ImmPred:$S8)))] > {
714 let Inst{27-25} = 0b101;
715 let Inst{24-23} = Pu;
716 let Inst{22-16} = S8{7-1};
717 let Inst{13} = S8{0};
722 let isCodeGenOnly = 1, isPseudo = 1 in
723 def MUX64_rr : ALU64_rr<(outs DoubleRegs:$Rd),
724 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
725 ".error \"should not emit\" ", []>;
728 //===----------------------------------------------------------------------===//
729 // template class for non-predicated alu32_2op instructions
730 // - aslh, asrh, sxtb, sxth, zxth
731 //===----------------------------------------------------------------------===//
732 let hasNewValue = 1, opNewValue = 0 in
733 class T_ALU32_2op <string mnemonic, bits<3> minOp> :
734 ALU32Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rs),
735 "$Rd = "#mnemonic#"($Rs)", [] > {
741 let Inst{27-24} = 0b0000;
742 let Inst{23-21} = minOp;
745 let Inst{20-16} = Rs;
748 //===----------------------------------------------------------------------===//
749 // template class for predicated alu32_2op instructions
750 // - aslh, asrh, sxtb, sxth, zxtb, zxth
751 //===----------------------------------------------------------------------===//
752 let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
753 class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot,
755 ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
756 !if(isPredNot, "if (!$Pu", "if ($Pu")
757 #!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> {
764 let Inst{27-24} = 0b0000;
765 let Inst{23-21} = minOp;
767 let Inst{11} = isPredNot;
768 let Inst{10} = isPredNew;
771 let Inst{20-16} = Rs;
774 multiclass ALU32_2op_Pred<string mnemonic, bits<3> minOp, bit PredNot> {
775 let isPredicatedFalse = PredNot in {
776 def NAME : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 0>;
779 let isPredicatedNew = 1 in
780 def NAME#new : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 1>;
784 multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
785 let BaseOpcode = mnemonic in {
786 let isPredicable = 1, hasSideEffects = 0 in
787 def A2_#NAME : T_ALU32_2op<mnemonic, minOp>;
789 let isPredicated = 1, hasSideEffects = 0 in {
790 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
791 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
796 defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
797 defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel;
798 defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
799 defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
800 defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
802 // Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
803 // Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has
804 // predicated forms while 'and' doesn't. Since integrated assembler can't
805 // handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where
806 // immediate operand is set to '255'.
808 let hasNewValue = 1, opNewValue = 0 in
809 class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
810 "$Rd = zxtb($Rs)", [] > { // Rd = and(Rs,255)
817 let Inst{27-22} = 0b011000;
819 let Inst{20-16} = Rs;
820 let Inst{21} = s10{9};
821 let Inst{13-5} = s10{8-0};
824 //Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255)
825 multiclass ZXTB_base <string mnemonic, bits<3> minOp> {
826 let BaseOpcode = mnemonic in {
827 let isPredicable = 1, hasSideEffects = 0 in
828 def A2_#NAME : T_ZXTB;
830 let isPredicated = 1, hasSideEffects = 0 in {
831 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
832 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
837 defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
839 def: Pat<(shl I32:$src1, (i32 16)), (A2_aslh I32:$src1)>;
840 def: Pat<(sra I32:$src1, (i32 16)), (A2_asrh I32:$src1)>;
841 def: Pat<(sext_inreg I32:$src1, i8), (A2_sxtb I32:$src1)>;
842 def: Pat<(sext_inreg I32:$src1, i16), (A2_sxth I32:$src1)>;
844 //===----------------------------------------------------------------------===//
845 // Template class for vector add and avg
846 //===----------------------------------------------------------------------===//
848 class T_VectALU_64 <string opc, bits<3> majOp, bits<3> minOp,
849 bit isSat, bit isRnd, bit isCrnd, bit SwapOps >
850 : ALU64_rr < (outs DoubleRegs:$Rdd),
851 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
852 "$Rdd = "#opc#"($Rss, $Rtt)"#!if(isRnd, ":rnd", "")
853 #!if(isCrnd,":crnd","")
854 #!if(isSat, ":sat", ""),
855 [], "", ALU64_tc_2_SLOT23 > {
862 let Inst{27-24} = 0b0011;
863 let Inst{23-21} = majOp;
864 let Inst{20-16} = !if (SwapOps, Rtt, Rss);
865 let Inst{12-8} = !if (SwapOps, Rss, Rtt);
866 let Inst{7-5} = minOp;
870 // ALU64 - Vector add
871 // Rdd=vadd[u][bhw](Rss,Rtt)
872 let Itinerary = ALU64_tc_1_SLOT23 in {
873 def A2_vaddub : T_VectALU_64 < "vaddub", 0b000, 0b000, 0, 0, 0, 0>;
874 def A2_vaddh : T_VectALU_64 < "vaddh", 0b000, 0b010, 0, 0, 0, 0>;
875 def A2_vaddw : T_VectALU_64 < "vaddw", 0b000, 0b101, 0, 0, 0, 0>;
878 // Rdd=vadd[u][bhw](Rss,Rtt):sat
879 let Defs = [USR_OVF] in {
880 def A2_vaddubs : T_VectALU_64 < "vaddub", 0b000, 0b001, 1, 0, 0, 0>;
881 def A2_vaddhs : T_VectALU_64 < "vaddh", 0b000, 0b011, 1, 0, 0, 0>;
882 def A2_vadduhs : T_VectALU_64 < "vadduh", 0b000, 0b100, 1, 0, 0, 0>;
883 def A2_vaddws : T_VectALU_64 < "vaddw", 0b000, 0b110, 1, 0, 0, 0>;
886 // ALU64 - Vector average
887 // Rdd=vavg[u][bhw](Rss,Rtt)
888 let Itinerary = ALU64_tc_1_SLOT23 in {
889 def A2_vavgub : T_VectALU_64 < "vavgub", 0b010, 0b000, 0, 0, 0, 0>;
890 def A2_vavgh : T_VectALU_64 < "vavgh", 0b010, 0b010, 0, 0, 0, 0>;
891 def A2_vavguh : T_VectALU_64 < "vavguh", 0b010, 0b101, 0, 0, 0, 0>;
892 def A2_vavgw : T_VectALU_64 < "vavgw", 0b011, 0b000, 0, 0, 0, 0>;
893 def A2_vavguw : T_VectALU_64 < "vavguw", 0b011, 0b011, 0, 0, 0, 0>;
896 // Rdd=vavg[u][bhw](Rss,Rtt)[:rnd|:crnd]
897 def A2_vavgubr : T_VectALU_64 < "vavgub", 0b010, 0b001, 0, 1, 0, 0>;
898 def A2_vavghr : T_VectALU_64 < "vavgh", 0b010, 0b011, 0, 1, 0, 0>;
899 def A2_vavghcr : T_VectALU_64 < "vavgh", 0b010, 0b100, 0, 0, 1, 0>;
900 def A2_vavguhr : T_VectALU_64 < "vavguh", 0b010, 0b110, 0, 1, 0, 0>;
902 def A2_vavgwr : T_VectALU_64 < "vavgw", 0b011, 0b001, 0, 1, 0, 0>;
903 def A2_vavgwcr : T_VectALU_64 < "vavgw", 0b011, 0b010, 0, 0, 1, 0>;
904 def A2_vavguwr : T_VectALU_64 < "vavguw", 0b011, 0b100, 0, 1, 0, 0>;
906 // Rdd=vnavg[bh](Rss,Rtt)
907 let Itinerary = ALU64_tc_1_SLOT23 in {
908 def A2_vnavgh : T_VectALU_64 < "vnavgh", 0b100, 0b000, 0, 0, 0, 1>;
909 def A2_vnavgw : T_VectALU_64 < "vnavgw", 0b100, 0b011, 0, 0, 0, 1>;
912 // Rdd=vnavg[bh](Rss,Rtt)[:rnd|:crnd]:sat
913 let Defs = [USR_OVF] in {
914 def A2_vnavghr : T_VectALU_64 < "vnavgh", 0b100, 0b001, 1, 1, 0, 1>;
915 def A2_vnavghcr : T_VectALU_64 < "vnavgh", 0b100, 0b010, 1, 0, 1, 1>;
916 def A2_vnavgwr : T_VectALU_64 < "vnavgw", 0b100, 0b100, 1, 1, 0, 1>;
917 def A2_vnavgwcr : T_VectALU_64 < "vnavgw", 0b100, 0b110, 1, 0, 1, 1>;
920 // Rdd=vsub[u][bh](Rss,Rtt)
921 let Itinerary = ALU64_tc_1_SLOT23 in {
922 def A2_vsubub : T_VectALU_64 < "vsubub", 0b001, 0b000, 0, 0, 0, 1>;
923 def A2_vsubh : T_VectALU_64 < "vsubh", 0b001, 0b010, 0, 0, 0, 1>;
924 def A2_vsubw : T_VectALU_64 < "vsubw", 0b001, 0b101, 0, 0, 0, 1>;
927 // Rdd=vsub[u][bh](Rss,Rtt):sat
928 let Defs = [USR_OVF] in {
929 def A2_vsububs : T_VectALU_64 < "vsubub", 0b001, 0b001, 1, 0, 0, 1>;
930 def A2_vsubhs : T_VectALU_64 < "vsubh", 0b001, 0b011, 1, 0, 0, 1>;
931 def A2_vsubuhs : T_VectALU_64 < "vsubuh", 0b001, 0b100, 1, 0, 0, 1>;
932 def A2_vsubws : T_VectALU_64 < "vsubw", 0b001, 0b110, 1, 0, 0, 1>;
935 // Rdd=vmax[u][bhw](Rss,Rtt)
936 def A2_vmaxb : T_VectALU_64 < "vmaxb", 0b110, 0b110, 0, 0, 0, 1>;
937 def A2_vmaxub : T_VectALU_64 < "vmaxub", 0b110, 0b000, 0, 0, 0, 1>;
938 def A2_vmaxh : T_VectALU_64 < "vmaxh", 0b110, 0b001, 0, 0, 0, 1>;
939 def A2_vmaxuh : T_VectALU_64 < "vmaxuh", 0b110, 0b010, 0, 0, 0, 1>;
940 def A2_vmaxw : T_VectALU_64 < "vmaxw", 0b110, 0b011, 0, 0, 0, 1>;
941 def A2_vmaxuw : T_VectALU_64 < "vmaxuw", 0b101, 0b101, 0, 0, 0, 1>;
943 // Rdd=vmin[u][bhw](Rss,Rtt)
944 def A2_vminb : T_VectALU_64 < "vminb", 0b110, 0b111, 0, 0, 0, 1>;
945 def A2_vminub : T_VectALU_64 < "vminub", 0b101, 0b000, 0, 0, 0, 1>;
946 def A2_vminh : T_VectALU_64 < "vminh", 0b101, 0b001, 0, 0, 0, 1>;
947 def A2_vminuh : T_VectALU_64 < "vminuh", 0b101, 0b010, 0, 0, 0, 1>;
948 def A2_vminw : T_VectALU_64 < "vminw", 0b101, 0b011, 0, 0, 0, 1>;
949 def A2_vminuw : T_VectALU_64 < "vminuw", 0b101, 0b100, 0, 0, 0, 1>;
951 //===----------------------------------------------------------------------===//
952 // Template class for vector compare
953 //===----------------------------------------------------------------------===//
954 let hasSideEffects = 0 in
955 class T_vcmp <string Str, bits<4> minOp>
956 : ALU64_rr <(outs PredRegs:$Pd),
957 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
958 "$Pd = "#Str#"($Rss, $Rtt)", [],
959 "", ALU64_tc_2early_SLOT23> {
966 let Inst{27-23} = 0b00100;
967 let Inst{13} = minOp{3};
968 let Inst{7-5} = minOp{2-0};
970 let Inst{20-16} = Rss;
971 let Inst{12-8} = Rtt;
974 class T_vcmp_pat<InstHexagon MI, PatFrag Op, ValueType T>
975 : Pat<(i1 (Op (T DoubleRegs:$Rss), (T DoubleRegs:$Rtt))),
976 (i1 (MI DoubleRegs:$Rss, DoubleRegs:$Rtt))>;
978 // Vector compare bytes
979 def A2_vcmpbeq : T_vcmp <"vcmpb.eq", 0b0110>;
980 def A2_vcmpbgtu : T_vcmp <"vcmpb.gtu", 0b0111>;
982 // Vector compare halfwords
983 def A2_vcmpheq : T_vcmp <"vcmph.eq", 0b0011>;
984 def A2_vcmphgt : T_vcmp <"vcmph.gt", 0b0100>;
985 def A2_vcmphgtu : T_vcmp <"vcmph.gtu", 0b0101>;
987 // Vector compare words
988 def A2_vcmpweq : T_vcmp <"vcmpw.eq", 0b0000>;
989 def A2_vcmpwgt : T_vcmp <"vcmpw.gt", 0b0001>;
990 def A2_vcmpwgtu : T_vcmp <"vcmpw.gtu", 0b0010>;
992 def: T_vcmp_pat<A2_vcmpbeq, seteq, v8i8>;
993 def: T_vcmp_pat<A2_vcmpbgtu, setugt, v8i8>;
994 def: T_vcmp_pat<A2_vcmpheq, seteq, v4i16>;
995 def: T_vcmp_pat<A2_vcmphgt, setgt, v4i16>;
996 def: T_vcmp_pat<A2_vcmphgtu, setugt, v4i16>;
997 def: T_vcmp_pat<A2_vcmpweq, seteq, v2i32>;
998 def: T_vcmp_pat<A2_vcmpwgt, setgt, v2i32>;
999 def: T_vcmp_pat<A2_vcmpwgtu, setugt, v2i32>;
1001 //===----------------------------------------------------------------------===//
1003 //===----------------------------------------------------------------------===//
1006 //===----------------------------------------------------------------------===//
1008 //===----------------------------------------------------------------------===//
1009 // No bits needed. If cmp.ge is found the assembler parser will
1010 // transform it to cmp.gt subtracting 1 from the immediate.
1011 let isPseudo = 1 in {
1012 def C2_cmpgei: ALU32Inst <
1013 (outs PredRegs:$Pd), (ins IntRegs:$Rs, s8Ext:$s8),
1014 "$Pd = cmp.ge($Rs, #$s8)">;
1015 def C2_cmpgeui: ALU32Inst <
1016 (outs PredRegs:$Pd), (ins IntRegs:$Rs, u8Ext:$s8),
1017 "$Pd = cmp.geu($Rs, #$s8)">;
1021 //===----------------------------------------------------------------------===//
1023 //===----------------------------------------------------------------------===//
1026 //===----------------------------------------------------------------------===//
1028 //===----------------------------------------------------------------------===//
1030 //===----------------------------------------------------------------------===//
1032 // Add/Subtract halfword
1033 // Rd=add(Rt.L,Rs.[HL])[:sat]
1034 // Rd=sub(Rt.L,Rs.[HL])[:sat]
1035 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
1036 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
1037 //===----------------------------------------------------------------------===//
1039 let hasNewValue = 1, opNewValue = 0 in
1040 class T_XTYPE_ADD_SUB <bits<2> LHbits, bit isSat, bit hasShift, bit isSub>
1041 : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1042 "$Rd = "#!if(isSub,"sub","add")#"($Rt."
1043 #!if(hasShift, !if(LHbits{1},"h","l"),"l") #", $Rs."
1044 #!if(hasShift, !if(LHbits{0},"h)","l)"), !if(LHbits{1},"h)","l)"))
1045 #!if(isSat,":sat","")
1046 #!if(hasShift,":<<16",""), [], "", ALU64_tc_1_SLOT23> {
1050 let IClass = 0b1101;
1052 let Inst{27-23} = 0b01010;
1053 let Inst{22} = hasShift;
1054 let Inst{21} = isSub;
1055 let Inst{7} = isSat;
1056 let Inst{6-5} = LHbits;
1058 let Inst{12-8} = Rt;
1059 let Inst{20-16} = Rs;
1062 //Rd=sub(Rt.L,Rs.[LH])
1063 def A2_subh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 1>;
1064 def A2_subh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 1>;
1066 //Rd=add(Rt.L,Rs.[LH])
1067 def A2_addh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 0>;
1068 def A2_addh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 0>;
1070 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF] in {
1071 //Rd=sub(Rt.L,Rs.[LH]):sat
1072 def A2_subh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 1>;
1073 def A2_subh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 1>;
1075 //Rd=add(Rt.L,Rs.[LH]):sat
1076 def A2_addh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 0>;
1077 def A2_addh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 0>;
1080 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
1081 def A2_subh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 1>;
1082 def A2_subh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 1>;
1083 def A2_subh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 1>;
1084 def A2_subh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 1>;
1086 //Rd=add(Rt.[LH],Rs.[LH]):<<16
1087 def A2_addh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 0>;
1088 def A2_addh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 0>;
1089 def A2_addh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 0>;
1090 def A2_addh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 0>;
1092 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF] in {
1093 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
1094 def A2_subh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 1>;
1095 def A2_subh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 1>;
1096 def A2_subh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 1>;
1097 def A2_subh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 1>;
1099 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
1100 def A2_addh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 0>;
1101 def A2_addh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 0>;
1102 def A2_addh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 0>;
1103 def A2_addh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 0>;
1107 def: Pat<(sext_inreg (add I32:$src1, I32:$src2), i16),
1108 (A2_addh_l16_ll I32:$src1, I32:$src2)>;
1110 def: Pat<(sra (add (shl I32:$src1, (i32 16)), I32:$src2), (i32 16)),
1111 (A2_addh_l16_hl I32:$src1, I32:$src2)>;
1113 def: Pat<(shl (add I32:$src1, I32:$src2), (i32 16)),
1114 (A2_addh_h16_ll I32:$src1, I32:$src2)>;
1116 // Subtract halfword.
1117 def: Pat<(sext_inreg (sub I32:$src1, I32:$src2), i16),
1118 (A2_subh_l16_ll I32:$src1, I32:$src2)>;
1120 def: Pat<(shl (sub I32:$src1, I32:$src2), (i32 16)),
1121 (A2_subh_h16_ll I32:$src1, I32:$src2)>;
1123 let hasSideEffects = 0, hasNewValue = 1 in
1124 def S2_parityp: ALU64Inst<(outs IntRegs:$Rd),
1125 (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1126 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1131 let IClass = 0b1101;
1132 let Inst{27-24} = 0b0000;
1133 let Inst{20-16} = Rs;
1134 let Inst{12-8} = Rt;
1138 let hasNewValue = 1, opNewValue = 0, hasSideEffects = 0 in
1139 class T_XTYPE_MIN_MAX < bit isMax, bit isUnsigned >
1140 : ALU64Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1141 "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
1142 #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
1147 let IClass = 0b1101;
1149 let Inst{27-23} = 0b01011;
1150 let Inst{22-21} = !if(isMax, 0b10, 0b01);
1151 let Inst{7} = isUnsigned;
1153 let Inst{12-8} = !if(isMax, Rs, Rt);
1154 let Inst{20-16} = !if(isMax, Rt, Rs);
1157 def A2_min : T_XTYPE_MIN_MAX < 0, 0 >;
1158 def A2_minu : T_XTYPE_MIN_MAX < 0, 1 >;
1159 def A2_max : T_XTYPE_MIN_MAX < 1, 0 >;
1160 def A2_maxu : T_XTYPE_MIN_MAX < 1, 1 >;
1162 // Here, depending on the operand being selected, we'll either generate a
1163 // min or max instruction.
1165 // (a>b)?a:b --> max(a,b) => Here check performed is '>' and the value selected
1166 // is the larger of two. So, the corresponding HexagonInst is passed in 'Inst'.
1167 // (a>b)?b:a --> min(a,b) => Here check performed is '>' but the smaller value
1168 // is selected and the corresponding HexagonInst is passed in 'SwapInst'.
1170 multiclass T_MinMax_pats <PatFrag Op, RegisterClass RC, ValueType VT,
1171 InstHexagon Inst, InstHexagon SwapInst> {
1172 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1173 (VT RC:$src1), (VT RC:$src2)),
1174 (Inst RC:$src1, RC:$src2)>;
1175 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1176 (VT RC:$src2), (VT RC:$src1)),
1177 (SwapInst RC:$src1, RC:$src2)>;
1181 multiclass MinMax_pats <PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
1182 defm: T_MinMax_pats<Op, IntRegs, i32, Inst, SwapInst>;
1184 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1185 (i32 PositiveHalfWord:$src2))),
1186 (i32 PositiveHalfWord:$src1),
1187 (i32 PositiveHalfWord:$src2))), i16),
1188 (Inst IntRegs:$src1, IntRegs:$src2)>;
1190 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1191 (i32 PositiveHalfWord:$src2))),
1192 (i32 PositiveHalfWord:$src2),
1193 (i32 PositiveHalfWord:$src1))), i16),
1194 (SwapInst IntRegs:$src1, IntRegs:$src2)>;
1197 let AddedComplexity = 200 in {
1198 defm: MinMax_pats<setge, A2_max, A2_min>;
1199 defm: MinMax_pats<setgt, A2_max, A2_min>;
1200 defm: MinMax_pats<setle, A2_min, A2_max>;
1201 defm: MinMax_pats<setlt, A2_min, A2_max>;
1202 defm: MinMax_pats<setuge, A2_maxu, A2_minu>;
1203 defm: MinMax_pats<setugt, A2_maxu, A2_minu>;
1204 defm: MinMax_pats<setule, A2_minu, A2_maxu>;
1205 defm: MinMax_pats<setult, A2_minu, A2_maxu>;
1208 class T_cmp64_rr<string mnemonic, bits<3> MinOp, bit IsComm>
1209 : ALU64_rr<(outs PredRegs:$Pd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1210 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", ALU64_tc_2early_SLOT23> {
1212 let isCommutable = IsComm;
1213 let hasSideEffects = 0;
1219 let IClass = 0b1101;
1220 let Inst{27-21} = 0b0010100;
1221 let Inst{20-16} = Rs;
1222 let Inst{12-8} = Rt;
1223 let Inst{7-5} = MinOp;
1227 def C2_cmpeqp : T_cmp64_rr<"cmp.eq", 0b000, 1>;
1228 def C2_cmpgtp : T_cmp64_rr<"cmp.gt", 0b010, 0>;
1229 def C2_cmpgtup : T_cmp64_rr<"cmp.gtu", 0b100, 0>;
1231 class T_cmp64_rr_pat<InstHexagon MI, PatFrag CmpOp>
1232 : Pat<(i1 (CmpOp (i64 DoubleRegs:$Rs), (i64 DoubleRegs:$Rt))),
1233 (i1 (MI DoubleRegs:$Rs, DoubleRegs:$Rt))>;
1235 def: T_cmp64_rr_pat<C2_cmpeqp, seteq>;
1236 def: T_cmp64_rr_pat<C2_cmpgtp, setgt>;
1237 def: T_cmp64_rr_pat<C2_cmpgtup, setugt>;
1238 def: T_cmp64_rr_pat<C2_cmpgtp, RevCmp<setlt>>;
1239 def: T_cmp64_rr_pat<C2_cmpgtup, RevCmp<setult>>;
1241 def C2_vmux : ALU64_rr<(outs DoubleRegs:$Rd),
1242 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
1243 "$Rd = vmux($Pu, $Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
1244 let hasSideEffects = 0;
1251 let IClass = 0b1101;
1252 let Inst{27-24} = 0b0001;
1253 let Inst{20-16} = Rs;
1254 let Inst{12-8} = Rt;
1259 class T_ALU64_rr<string mnemonic, string suffix, bits<4> RegType,
1260 bits<3> MajOp, bits<3> MinOp, bit OpsRev, bit IsComm,
1262 : ALU64_rr<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1263 "$Rd = " #mnemonic# "($Rs, " #Op2Pfx# "$Rt)" #suffix, [],
1264 "", ALU64_tc_1_SLOT23> {
1265 let hasSideEffects = 0;
1266 let isCommutable = IsComm;
1272 let IClass = 0b1101;
1273 let Inst{27-24} = RegType;
1274 let Inst{23-21} = MajOp;
1275 let Inst{20-16} = !if (OpsRev,Rt,Rs);
1276 let Inst{12-8} = !if (OpsRev,Rs,Rt);
1277 let Inst{7-5} = MinOp;
1281 class T_ALU64_arith<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit IsSat,
1282 bit OpsRev, bit IsComm>
1283 : T_ALU64_rr<mnemonic, !if(IsSat,":sat",""), 0b0011, MajOp, MinOp, OpsRev,
1286 def A2_addp : T_ALU64_arith<"add", 0b000, 0b111, 0, 0, 1>;
1287 def A2_subp : T_ALU64_arith<"sub", 0b001, 0b111, 0, 1, 0>;
1289 def: Pat<(i64 (add I64:$Rs, I64:$Rt)), (A2_addp I64:$Rs, I64:$Rt)>;
1290 def: Pat<(i64 (sub I64:$Rs, I64:$Rt)), (A2_subp I64:$Rs, I64:$Rt)>;
1292 class T_ALU64_logical<string mnemonic, bits<3> MinOp, bit OpsRev, bit IsComm,
1294 : T_ALU64_rr<mnemonic, "", 0b0011, 0b111, MinOp, OpsRev, IsComm,
1297 def A2_andp : T_ALU64_logical<"and", 0b000, 0, 1, 0>;
1298 def A2_orp : T_ALU64_logical<"or", 0b010, 0, 1, 0>;
1299 def A2_xorp : T_ALU64_logical<"xor", 0b100, 0, 1, 0>;
1301 def: Pat<(i64 (and I64:$Rs, I64:$Rt)), (A2_andp I64:$Rs, I64:$Rt)>;
1302 def: Pat<(i64 (or I64:$Rs, I64:$Rt)), (A2_orp I64:$Rs, I64:$Rt)>;
1303 def: Pat<(i64 (xor I64:$Rs, I64:$Rt)), (A2_xorp I64:$Rs, I64:$Rt)>;
1305 //===----------------------------------------------------------------------===//
1307 //===----------------------------------------------------------------------===//
1309 //===----------------------------------------------------------------------===//
1311 //===----------------------------------------------------------------------===//
1313 //===----------------------------------------------------------------------===//
1315 //===----------------------------------------------------------------------===//
1317 //===----------------------------------------------------------------------===//
1319 //===----------------------------------------------------------------------===//
1321 //===----------------------------------------------------------------------===//
1323 //===----------------------------------------------------------------------===//
1325 //===----------------------------------------------------------------------===//
1327 //===----------------------------------------------------------------------===//
1328 // Logical reductions on predicates.
1330 // Looping instructions.
1332 // Pipelined looping instructions.
1334 // Logical operations on predicates.
1335 let hasSideEffects = 0 in
1336 class T_LOGICAL_1OP<string MnOp, bits<2> OpBits>
1337 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps),
1338 "$Pd = " # MnOp # "($Ps)", [], "", CR_tc_2early_SLOT23> {
1342 let IClass = 0b0110;
1343 let Inst{27-23} = 0b10111;
1344 let Inst{22-21} = OpBits;
1346 let Inst{17-16} = Ps;
1351 def C2_any8 : T_LOGICAL_1OP<"any8", 0b00>;
1352 def C2_all8 : T_LOGICAL_1OP<"all8", 0b01>;
1353 def C2_not : T_LOGICAL_1OP<"not", 0b10>;
1355 def: Pat<(i1 (not (i1 PredRegs:$Ps))),
1356 (C2_not PredRegs:$Ps)>;
1358 let hasSideEffects = 0 in
1359 class T_LOGICAL_2OP<string MnOp, bits<3> OpBits, bit IsNeg, bit Rev>
1360 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps, PredRegs:$Pt),
1361 "$Pd = " # MnOp # "($Ps, " # !if (IsNeg,"!","") # "$Pt)",
1362 [], "", CR_tc_2early_SLOT23> {
1367 let IClass = 0b0110;
1368 let Inst{27-24} = 0b1011;
1369 let Inst{23-21} = OpBits;
1371 let Inst{17-16} = !if(Rev,Pt,Ps); // Rs and Rt are reversed for some
1372 let Inst{13} = 0b0; // instructions.
1373 let Inst{9-8} = !if(Rev,Ps,Pt);
1377 def C2_and : T_LOGICAL_2OP<"and", 0b000, 0, 1>;
1378 def C2_or : T_LOGICAL_2OP<"or", 0b001, 0, 1>;
1379 def C2_xor : T_LOGICAL_2OP<"xor", 0b010, 0, 0>;
1380 def C2_andn : T_LOGICAL_2OP<"and", 0b011, 1, 1>;
1381 def C2_orn : T_LOGICAL_2OP<"or", 0b111, 1, 1>;
1383 def: Pat<(i1 (and I1:$Ps, I1:$Pt)), (C2_and I1:$Ps, I1:$Pt)>;
1384 def: Pat<(i1 (or I1:$Ps, I1:$Pt)), (C2_or I1:$Ps, I1:$Pt)>;
1385 def: Pat<(i1 (xor I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>;
1386 def: Pat<(i1 (and I1:$Ps, (not I1:$Pt))), (C2_andn I1:$Ps, I1:$Pt)>;
1387 def: Pat<(i1 (or I1:$Ps, (not I1:$Pt))), (C2_orn I1:$Ps, I1:$Pt)>;
1389 let hasSideEffects = 0, hasNewValue = 1 in
1390 def C2_vitpack : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps, PredRegs:$Pt),
1391 "$Rd = vitpack($Ps, $Pt)", [], "", S_2op_tc_1_SLOT23> {
1396 let IClass = 0b1000;
1397 let Inst{27-24} = 0b1001;
1398 let Inst{22-21} = 0b00;
1399 let Inst{17-16} = Ps;
1404 let hasSideEffects = 0 in
1405 def C2_mask : SInst<(outs DoubleRegs:$Rd), (ins PredRegs:$Pt),
1406 "$Rd = mask($Pt)", [], "", S_2op_tc_1_SLOT23> {
1410 let IClass = 0b1000;
1411 let Inst{27-24} = 0b0110;
1416 // User control register transfer.
1417 //===----------------------------------------------------------------------===//
1419 //===----------------------------------------------------------------------===//
1421 //===----------------------------------------------------------------------===//
1423 //===----------------------------------------------------------------------===//
1425 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
1426 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1427 def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>;
1429 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
1430 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
1432 class CondStr<string CReg, bit True, bit New> {
1433 string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") ";
1435 class JumpOpcStr<string Mnemonic, bit New, bit Taken> {
1436 string S = Mnemonic # !if(Taken, ":t", !if(New, ":nt", ""));
1439 let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0,
1441 isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
1442 opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in
1443 class T_JMP<string ExtStr>
1444 : JInst<(outs), (ins brtarget:$dst),
1445 "jump " # ExtStr # "$dst",
1446 [], "", J_tc_2early_SLOT23> {
1448 let IClass = 0b0101;
1450 let Inst{27-25} = 0b100;
1451 let Inst{24-16} = dst{23-15};
1452 let Inst{13-1} = dst{14-2};
1455 let isBranch = 1, Defs = [PC], hasSideEffects = 0, isPredicated = 1,
1456 isExtendable = 1, opExtendable = 1, isExtentSigned = 1,
1457 opExtentBits = 17, opExtentAlign = 2, InputType = "imm" in
1458 class T_JMP_c<bit PredNot, bit isPredNew, bit isTak, string ExtStr>
1459 : JInst<(outs), (ins PredRegs:$src, brtarget:$dst),
1460 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
1461 JumpOpcStr<"jump", isPredNew, isTak>.S # " " #
1463 [], "", J_tc_2early_SLOT23>, ImmRegRel {
1464 let isTaken = isTak;
1465 let isPredicatedFalse = PredNot;
1466 let isPredicatedNew = isPredNew;
1470 let IClass = 0b0101;
1472 let Inst{27-24} = 0b1100;
1473 let Inst{21} = PredNot;
1474 let Inst{12} = isTak;
1475 let Inst{11} = isPredNew;
1476 let Inst{9-8} = src;
1477 let Inst{23-22} = dst{16-15};
1478 let Inst{20-16} = dst{14-10};
1479 let Inst{13} = dst{9};
1480 let Inst{7-1} = dst{8-2};
1483 multiclass JMP_Pred<bit PredNot, string ExtStr> {
1484 def NAME : T_JMP_c<PredNot, 0, 0, ExtStr>; // not taken
1486 def NAME#newpt : T_JMP_c<PredNot, 1, 1, ExtStr>; // taken
1487 def NAME#new : T_JMP_c<PredNot, 1, 0, ExtStr>; // not taken
1490 multiclass JMP_base<string BaseOp, string ExtStr> {
1491 let BaseOpcode = BaseOp in {
1492 def NAME : T_JMP<ExtStr>;
1493 defm t : JMP_Pred<0, ExtStr>;
1494 defm f : JMP_Pred<1, ExtStr>;
1498 // Jumps to address stored in a register, JUMPR_MISC
1499 // if ([[!]P[.new]]) jumpr[:t/nt] Rs
1500 let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC],
1501 isPredicable = 1, hasSideEffects = 0, InputType = "reg" in
1503 : JRInst<(outs), (ins IntRegs:$dst),
1504 "jumpr $dst", [], "", J_tc_2early_SLOT2> {
1507 let IClass = 0b0101;
1508 let Inst{27-21} = 0b0010100;
1509 let Inst{20-16} = dst;
1512 let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1,
1513 hasSideEffects = 0, InputType = "reg" in
1514 class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>
1515 : JRInst <(outs), (ins PredRegs:$src, IntRegs:$dst),
1516 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
1517 JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst", [],
1518 "", J_tc_2early_SLOT2> {
1520 let isTaken = isTak;
1521 let isPredicatedFalse = PredNot;
1522 let isPredicatedNew = isPredNew;
1526 let IClass = 0b0101;
1528 let Inst{27-22} = 0b001101;
1529 let Inst{21} = PredNot;
1530 let Inst{20-16} = dst;
1531 let Inst{12} = isTak;
1532 let Inst{11} = isPredNew;
1533 let Inst{9-8} = src;
1536 multiclass JMPR_Pred<bit PredNot> {
1537 def NAME : T_JMPr_c<PredNot, 0, 0>; // not taken
1539 def NAME#newpt : T_JMPr_c<PredNot, 1, 1>; // taken
1540 def NAME#new : T_JMPr_c<PredNot, 1, 0>; // not taken
1543 multiclass JMPR_base<string BaseOp> {
1544 let BaseOpcode = BaseOp in {
1546 defm t : JMPR_Pred<0>;
1547 defm f : JMPR_Pred<1>;
1551 let isCall = 1, hasSideEffects = 1 in
1552 class JUMPR_MISC_CALLR<bit isPred, bit isPredNot,
1553 dag InputDag = (ins IntRegs:$Rs)>
1554 : JRInst<(outs), InputDag,
1555 !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs",
1556 "if ($Pu) callr $Rs"),
1558 [], "", J_tc_2early_SLOT2> {
1561 let isPredicated = isPred;
1562 let isPredicatedFalse = isPredNot;
1564 let IClass = 0b0101;
1565 let Inst{27-25} = 0b000;
1566 let Inst{24-23} = !if (isPred, 0b10, 0b01);
1568 let Inst{21} = isPredNot;
1569 let Inst{9-8} = !if (isPred, Pu, 0b00);
1570 let Inst{20-16} = Rs;
1574 let Defs = VolatileV3.Regs in {
1575 def J2_callrt : JUMPR_MISC_CALLR<1, 0, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1576 def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1579 let isTerminator = 1, hasSideEffects = 0 in {
1580 defm J2_jump : JMP_base<"JMP", "">, PredNewRel;
1582 // Deal with explicit assembly
1583 // - never extened a jump #, always extend a jump ##
1584 let isAsmParserOnly = 1 in {
1585 defm J2_jump_ext : JMP_base<"JMP", "##">;
1586 defm J2_jump_noext : JMP_base<"JMP", "#">;
1589 defm J2_jumpr : JMPR_base<"JMPr">, PredNewRel;
1591 let isReturn = 1, isCodeGenOnly = 1 in
1592 defm JMPret : JMPR_base<"JMPret">, PredNewRel;
1595 def: Pat<(br bb:$dst),
1596 (J2_jump brtarget:$dst)>;
1598 (JMPret (i32 R31))>;
1599 def: Pat<(brcond (i1 PredRegs:$src1), bb:$offset),
1600 (J2_jumpt PredRegs:$src1, bb:$offset)>;
1602 // A return through builtin_eh_return.
1603 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
1604 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
1605 def EH_RETURN_JMPR : T_JMPr;
1607 def: Pat<(eh_return),
1608 (EH_RETURN_JMPR (i32 R31))>;
1609 def: Pat<(HexagonBR_JT (i32 IntRegs:$dst)),
1610 (J2_jumpr IntRegs:$dst)>;
1611 def: Pat<(brind (i32 IntRegs:$dst)),
1612 (J2_jumpr IntRegs:$dst)>;
1614 //===----------------------------------------------------------------------===//
1616 //===----------------------------------------------------------------------===//
1618 //===----------------------------------------------------------------------===//
1620 //===----------------------------------------------------------------------===//
1622 // Load - Base with Immediate offset addressing mode
1623 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, AddedComplexity = 20 in
1624 class T_load_io <string mnemonic, RegisterClass RC, bits<4> MajOp,
1626 : LDInst<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1627 "$dst = "#mnemonic#"($src1 + #$offset)", []>, AddrModeRel {
1632 bits<11> offsetBits;
1634 string ImmOpStr = !cast<string>(ImmOp);
1635 let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), offset{13-3},
1636 !if (!eq(ImmOpStr, "s11_2Ext"), offset{12-2},
1637 !if (!eq(ImmOpStr, "s11_1Ext"), offset{11-1},
1638 /* s11_0Ext */ offset{10-0})));
1639 let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14,
1640 !if (!eq(ImmOpStr, "s11_2Ext"), 13,
1641 !if (!eq(ImmOpStr, "s11_1Ext"), 12,
1642 /* s11_0Ext */ 11)));
1643 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
1645 let IClass = 0b1001;
1648 let Inst{26-25} = offsetBits{10-9};
1649 let Inst{24-21} = MajOp;
1650 let Inst{20-16} = src1;
1651 let Inst{13-5} = offsetBits{8-0};
1652 let Inst{4-0} = dst;
1655 let opExtendable = 3, isExtentSigned = 0, isPredicated = 1 in
1656 class T_pload_io <string mnemonic, RegisterClass RC, bits<4>MajOp,
1657 Operand ImmOp, bit isNot, bit isPredNew>
1658 : LDInst<(outs RC:$dst),
1659 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1660 "if ("#!if(isNot, "!$src1", "$src1")
1661 #!if(isPredNew, ".new", "")
1662 #") $dst = "#mnemonic#"($src2 + #$offset)",
1663 [],"", V2LDST_tc_ld_SLOT01> , AddrModeRel {
1669 string ImmOpStr = !cast<string>(ImmOp);
1671 let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), offset{8-3},
1672 !if (!eq(ImmOpStr, "u6_2Ext"), offset{7-2},
1673 !if (!eq(ImmOpStr, "u6_1Ext"), offset{6-1},
1674 /* u6_0Ext */ offset{5-0})));
1675 let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9,
1676 !if (!eq(ImmOpStr, "u6_2Ext"), 8,
1677 !if (!eq(ImmOpStr, "u6_1Ext"), 7,
1679 let hasNewValue = !if (!eq(ImmOpStr, "u6_3Ext"), 0, 1);
1680 let isPredicatedNew = isPredNew;
1681 let isPredicatedFalse = isNot;
1683 let IClass = 0b0100;
1687 let Inst{26} = isNot;
1688 let Inst{25} = isPredNew;
1689 let Inst{24-21} = MajOp;
1690 let Inst{20-16} = src2;
1692 let Inst{12-11} = src1;
1693 let Inst{10-5} = offsetBits;
1694 let Inst{4-0} = dst;
1697 let isExtendable = 1, hasSideEffects = 0, addrMode = BaseImmOffset in
1698 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1699 Operand ImmOp, Operand predImmOp, bits<4>MajOp> {
1700 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1701 let isPredicable = 1 in
1702 def L2_#NAME#_io : T_load_io <mnemonic, RC, MajOp, ImmOp>;
1705 def L2_p#NAME#t_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 0>;
1706 def L2_p#NAME#f_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 0>;
1709 def L2_p#NAME#tnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 1>;
1710 def L2_p#NAME#fnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 1>;
1714 let accessSize = ByteAccess in {
1715 defm loadrb: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext, 0b1000>;
1716 defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>;
1719 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1720 defm loadrh: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, 0b1010>;
1721 defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>;
1724 let accessSize = WordAccess, opExtentAlign = 2 in
1725 defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>;
1727 let accessSize = DoubleWordAccess, opExtentAlign = 3 in
1728 defm loadrd: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, 0b1110>;
1730 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1731 def L2_loadbsw2_io: T_load_io<"membh", IntRegs, 0b0001, s11_1Ext>;
1732 def L2_loadbzw2_io: T_load_io<"memubh", IntRegs, 0b0011, s11_1Ext>;
1735 let accessSize = WordAccess, opExtentAlign = 2 in {
1736 def L2_loadbzw4_io: T_load_io<"memubh", DoubleRegs, 0b0101, s11_2Ext>;
1737 def L2_loadbsw4_io: T_load_io<"membh", DoubleRegs, 0b0111, s11_2Ext>;
1740 let addrMode = BaseImmOffset, isExtendable = 1, hasSideEffects = 0,
1741 opExtendable = 3, isExtentSigned = 1 in
1742 class T_loadalign_io <string str, bits<4> MajOp, Operand ImmOp>
1743 : LDInst<(outs DoubleRegs:$dst),
1744 (ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1745 "$dst = "#str#"($src2 + #$offset)", [],
1746 "$src1 = $dst">, AddrModeRel {
1751 bits<11> offsetBits;
1753 let offsetBits = !if (!eq(!cast<string>(ImmOp), "s11_1Ext"), offset{11-1},
1754 /* s11_0Ext */ offset{10-0});
1755 let IClass = 0b1001;
1758 let Inst{26-25} = offsetBits{10-9};
1759 let Inst{24-21} = MajOp;
1760 let Inst{20-16} = src2;
1761 let Inst{13-5} = offsetBits{8-0};
1762 let Inst{4-0} = dst;
1765 let accessSize = HalfWordAccess, opExtentBits = 12, opExtentAlign = 1 in
1766 def L2_loadalignh_io: T_loadalign_io <"memh_fifo", 0b0010, s11_1Ext>;
1768 let accessSize = ByteAccess, opExtentBits = 11 in
1769 def L2_loadalignb_io: T_loadalign_io <"memb_fifo", 0b0100, s11_0Ext>;
1771 // Patterns to select load-indexed (i.e. load from base+offset).
1772 multiclass Loadx_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
1774 def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>;
1775 def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))),
1776 (VT (MI AddrFI:$fi, imm:$Off))>;
1777 def: Pat<(VT (Load (add (i32 IntRegs:$Rs), ImmPred:$Off))),
1778 (VT (MI IntRegs:$Rs, imm:$Off))>;
1779 def: Pat<(VT (Load (i32 IntRegs:$Rs))), (VT (MI IntRegs:$Rs, 0))>;
1782 let AddedComplexity = 20 in {
1783 defm: Loadx_pat<load, i32, s30_2ImmPred, L2_loadri_io>;
1784 defm: Loadx_pat<load, i64, s29_3ImmPred, L2_loadrd_io>;
1785 defm: Loadx_pat<atomic_load_8 , i32, s32_0ImmPred, L2_loadrub_io>;
1786 defm: Loadx_pat<atomic_load_16, i32, s31_1ImmPred, L2_loadruh_io>;
1787 defm: Loadx_pat<atomic_load_32, i32, s30_2ImmPred, L2_loadri_io>;
1788 defm: Loadx_pat<atomic_load_64, i64, s29_3ImmPred, L2_loadrd_io>;
1790 defm: Loadx_pat<extloadi1, i32, s32_0ImmPred, L2_loadrub_io>;
1791 defm: Loadx_pat<extloadi8, i32, s32_0ImmPred, L2_loadrub_io>;
1792 defm: Loadx_pat<extloadi16, i32, s31_1ImmPred, L2_loadruh_io>;
1793 defm: Loadx_pat<sextloadi8, i32, s32_0ImmPred, L2_loadrb_io>;
1794 defm: Loadx_pat<sextloadi16, i32, s31_1ImmPred, L2_loadrh_io>;
1795 defm: Loadx_pat<zextloadi1, i32, s32_0ImmPred, L2_loadrub_io>;
1796 defm: Loadx_pat<zextloadi8, i32, s32_0ImmPred, L2_loadrub_io>;
1797 defm: Loadx_pat<zextloadi16, i32, s31_1ImmPred, L2_loadruh_io>;
1801 // Sign-extending loads of i1 need to replicate the lowest bit throughout
1802 // the 32-bit value. Since the loaded value can only be 0 or 1, 0-v should
1804 let AddedComplexity = 20 in
1805 def: Pat<(i32 (sextloadi1 (i32 IntRegs:$Rs))),
1806 (A2_subri 0, (L2_loadrub_io IntRegs:$Rs, 0))>;
1808 //===----------------------------------------------------------------------===//
1809 // Post increment load
1810 //===----------------------------------------------------------------------===//
1811 //===----------------------------------------------------------------------===//
1812 // Template class for non-predicated post increment loads with immediate offset.
1813 //===----------------------------------------------------------------------===//
1814 let hasSideEffects = 0, addrMode = PostInc in
1815 class T_load_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
1817 : LDInstPI <(outs RC:$dst, IntRegs:$dst2),
1818 (ins IntRegs:$src1, ImmOp:$offset),
1819 "$dst = "#mnemonic#"($src1++#$offset)" ,
1828 string ImmOpStr = !cast<string>(ImmOp);
1829 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
1830 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1831 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1832 /* s4_0Imm */ offset{3-0})));
1833 let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
1835 let IClass = 0b1001;
1837 let Inst{27-25} = 0b101;
1838 let Inst{24-21} = MajOp;
1839 let Inst{20-16} = src1;
1840 let Inst{13-12} = 0b00;
1841 let Inst{8-5} = offsetBits;
1842 let Inst{4-0} = dst;
1845 //===----------------------------------------------------------------------===//
1846 // Template class for predicated post increment loads with immediate offset.
1847 //===----------------------------------------------------------------------===//
1848 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
1849 class T_pload_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
1850 bits<4> MajOp, bit isPredNot, bit isPredNew >
1851 : LDInst <(outs RC:$dst, IntRegs:$dst2),
1852 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1853 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1854 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1864 let isPredicatedNew = isPredNew;
1865 let isPredicatedFalse = isPredNot;
1867 string ImmOpStr = !cast<string>(ImmOp);
1868 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
1869 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1870 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1871 /* s4_0Imm */ offset{3-0})));
1872 let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
1874 let IClass = 0b1001;
1876 let Inst{27-25} = 0b101;
1877 let Inst{24-21} = MajOp;
1878 let Inst{20-16} = src2;
1880 let Inst{12} = isPredNew;
1881 let Inst{11} = isPredNot;
1882 let Inst{10-9} = src1;
1883 let Inst{8-5} = offsetBits;
1884 let Inst{4-0} = dst;
1887 //===----------------------------------------------------------------------===//
1888 // Multiclass for post increment loads with immediate offset.
1889 //===----------------------------------------------------------------------===//
1891 multiclass LD_PostInc <string mnemonic, string BaseOp, RegisterClass RC,
1892 Operand ImmOp, bits<4> MajOp> {
1893 let BaseOpcode = "POST_"#BaseOp in {
1894 let isPredicable = 1 in
1895 def L2_#NAME#_pi : T_load_pi < mnemonic, RC, ImmOp, MajOp>;
1898 def L2_p#NAME#t_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 0>;
1899 def L2_p#NAME#f_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 0>;
1902 def L2_p#NAME#tnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 1>;
1903 def L2_p#NAME#fnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 1>;
1907 // post increment byte loads with immediate offset
1908 let accessSize = ByteAccess in {
1909 defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>;
1910 defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>;
1913 // post increment halfword loads with immediate offset
1914 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1915 defm loadrh : LD_PostInc <"memh", "LDrih", IntRegs, s4_1Imm, 0b1010>;
1916 defm loadruh : LD_PostInc <"memuh", "LDriuh", IntRegs, s4_1Imm, 0b1011>;
1919 // post increment word loads with immediate offset
1920 let accessSize = WordAccess, opExtentAlign = 2 in
1921 defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>;
1923 // post increment doubleword loads with immediate offset
1924 let accessSize = DoubleWordAccess, opExtentAlign = 3 in
1925 defm loadrd : LD_PostInc <"memd", "LDrid", DoubleRegs, s4_3Imm, 0b1110>;
1927 // Rd=memb[u]h(Rx++#s4:1)
1928 // Rdd=memb[u]h(Rx++#s4:2)
1929 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1930 def L2_loadbsw2_pi : T_load_pi <"membh", IntRegs, s4_1Imm, 0b0001>;
1931 def L2_loadbzw2_pi : T_load_pi <"memubh", IntRegs, s4_1Imm, 0b0011>;
1933 let accessSize = WordAccess, opExtentAlign = 2, hasNewValue = 0 in {
1934 def L2_loadbsw4_pi : T_load_pi <"membh", DoubleRegs, s4_2Imm, 0b0111>;
1935 def L2_loadbzw4_pi : T_load_pi <"memubh", DoubleRegs, s4_2Imm, 0b0101>;
1938 //===----------------------------------------------------------------------===//
1939 // Template class for post increment fifo loads with immediate offset.
1940 //===----------------------------------------------------------------------===//
1941 let hasSideEffects = 0, addrMode = PostInc in
1942 class T_loadalign_pi <string mnemonic, Operand ImmOp, bits<4> MajOp >
1943 : LDInstPI <(outs DoubleRegs:$dst, IntRegs:$dst2),
1944 (ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1945 "$dst = "#mnemonic#"($src2++#$offset)" ,
1946 [], "$src2 = $dst2, $src1 = $dst" > ,
1953 let offsetBits = !if (!eq(!cast<string>(ImmOp), "s4_1Imm"), offset{4-1},
1954 /* s4_0Imm */ offset{3-0});
1955 let IClass = 0b1001;
1957 let Inst{27-25} = 0b101;
1958 let Inst{24-21} = MajOp;
1959 let Inst{20-16} = src2;
1960 let Inst{13-12} = 0b00;
1961 let Inst{8-5} = offsetBits;
1962 let Inst{4-0} = dst;
1965 // Ryy=memh_fifo(Rx++#s4:1)
1966 // Ryy=memb_fifo(Rx++#s4:0)
1967 let accessSize = ByteAccess in
1968 def L2_loadalignb_pi : T_loadalign_pi <"memb_fifo", s4_0Imm, 0b0100>;
1970 let accessSize = HalfWordAccess, opExtentAlign = 1 in
1971 def L2_loadalignh_pi : T_loadalign_pi <"memh_fifo", s4_1Imm, 0b0010>;
1973 //===----------------------------------------------------------------------===//
1974 // Template class for post increment loads with register offset.
1975 //===----------------------------------------------------------------------===//
1976 let hasSideEffects = 0, addrMode = PostInc in
1977 class T_load_pr <string mnemonic, RegisterClass RC, bits<4> MajOp,
1978 MemAccessSize AccessSz>
1979 : LDInstPI <(outs RC:$dst, IntRegs:$_dst_),
1980 (ins IntRegs:$src1, ModRegs:$src2),
1981 "$dst = "#mnemonic#"($src1++$src2)" ,
1982 [], "$src1 = $_dst_" > {
1987 let accessSize = AccessSz;
1988 let IClass = 0b1001;
1990 let Inst{27-25} = 0b110;
1991 let Inst{24-21} = MajOp;
1992 let Inst{20-16} = src1;
1993 let Inst{13} = src2;
1996 let Inst{4-0} = dst;
1999 let hasNewValue = 1 in {
2000 def L2_loadrb_pr : T_load_pr <"memb", IntRegs, 0b1000, ByteAccess>;
2001 def L2_loadrub_pr : T_load_pr <"memub", IntRegs, 0b1001, ByteAccess>;
2002 def L2_loadrh_pr : T_load_pr <"memh", IntRegs, 0b1010, HalfWordAccess>;
2003 def L2_loadruh_pr : T_load_pr <"memuh", IntRegs, 0b1011, HalfWordAccess>;
2004 def L2_loadri_pr : T_load_pr <"memw", IntRegs, 0b1100, WordAccess>;
2006 def L2_loadbzw2_pr : T_load_pr <"memubh", IntRegs, 0b0011, HalfWordAccess>;
2009 def L2_loadrd_pr : T_load_pr <"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
2010 def L2_loadbzw4_pr : T_load_pr <"memubh", DoubleRegs, 0b0101, WordAccess>;
2013 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
2014 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
2015 def LDriw_pred : LDInst<(outs PredRegs:$dst),
2016 (ins IntRegs:$addr, s11_2Ext:$off),
2017 ".error \"should not emit\"", []>;
2019 let Defs = [R29, R30, R31], Uses = [R30], hasSideEffects = 0 in
2020 def L2_deallocframe : LDInst<(outs), (ins),
2023 let IClass = 0b1001;
2025 let Inst{27-16} = 0b000000011110;
2027 let Inst{4-0} = 0b11110;
2030 // Load / Post increment circular addressing mode.
2031 let Uses = [CS], hasSideEffects = 0 in
2032 class T_load_pcr<string mnemonic, RegisterClass RC, bits<4> MajOp>
2033 : LDInst <(outs RC:$dst, IntRegs:$_dst_),
2034 (ins IntRegs:$Rz, ModRegs:$Mu),
2035 "$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [],
2041 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
2042 let IClass = 0b1001;
2044 let Inst{27-25} = 0b100;
2045 let Inst{24-21} = MajOp;
2046 let Inst{20-16} = Rz;
2051 let Inst{4-0} = dst;
2054 let accessSize = ByteAccess in {
2055 def L2_loadrb_pcr : T_load_pcr <"memb", IntRegs, 0b1000>;
2056 def L2_loadrub_pcr : T_load_pcr <"memub", IntRegs, 0b1001>;
2059 let accessSize = HalfWordAccess in {
2060 def L2_loadrh_pcr : T_load_pcr <"memh", IntRegs, 0b1010>;
2061 def L2_loadruh_pcr : T_load_pcr <"memuh", IntRegs, 0b1011>;
2062 def L2_loadbsw2_pcr : T_load_pcr <"membh", IntRegs, 0b0001>;
2063 def L2_loadbzw2_pcr : T_load_pcr <"memubh", IntRegs, 0b0011>;
2066 let accessSize = WordAccess in {
2067 def L2_loadri_pcr : T_load_pcr <"memw", IntRegs, 0b1100>;
2068 let hasNewValue = 0 in {
2069 def L2_loadbzw4_pcr : T_load_pcr <"memubh", DoubleRegs, 0b0101>;
2070 def L2_loadbsw4_pcr : T_load_pcr <"membh", DoubleRegs, 0b0111>;
2074 let accessSize = DoubleWordAccess in
2075 def L2_loadrd_pcr : T_load_pcr <"memd", DoubleRegs, 0b1110>;
2077 // Load / Post increment circular addressing mode.
2078 let Uses = [CS], hasSideEffects = 0 in
2079 class T_loadalign_pcr<string mnemonic, bits<4> MajOp, MemAccessSize AccessSz >
2080 : LDInst <(outs DoubleRegs:$dst, IntRegs:$_dst_),
2081 (ins DoubleRegs:$_src_, IntRegs:$Rz, ModRegs:$Mu),
2082 "$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [],
2083 "$Rz = $_dst_, $dst = $_src_" > {
2088 let accessSize = AccessSz;
2089 let IClass = 0b1001;
2091 let Inst{27-25} = 0b100;
2092 let Inst{24-21} = MajOp;
2093 let Inst{20-16} = Rz;
2098 let Inst{4-0} = dst;
2101 def L2_loadalignb_pcr : T_loadalign_pcr <"memb_fifo", 0b0100, ByteAccess>;
2102 def L2_loadalignh_pcr : T_loadalign_pcr <"memh_fifo", 0b0010, HalfWordAccess>;
2104 //===----------------------------------------------------------------------===//
2105 // Circular loads with immediate offset.
2106 //===----------------------------------------------------------------------===//
2107 let Uses = [CS], mayLoad = 1, hasSideEffects = 0 in
2108 class T_load_pci <string mnemonic, RegisterClass RC,
2109 Operand ImmOp, bits<4> MajOp>
2110 : LDInstPI<(outs RC:$dst, IntRegs:$_dst_),
2111 (ins IntRegs:$Rz, ImmOp:$offset, ModRegs:$Mu),
2112 "$dst = "#mnemonic#"($Rz ++ #$offset:circ($Mu))", [],
2120 string ImmOpStr = !cast<string>(ImmOp);
2121 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
2122 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
2123 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
2124 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
2125 /* s4_0Imm */ offset{3-0})));
2126 let IClass = 0b1001;
2127 let Inst{27-25} = 0b100;
2128 let Inst{24-21} = MajOp;
2129 let Inst{20-16} = Rz;
2133 let Inst{8-5} = offsetBits;
2134 let Inst{4-0} = dst;
2137 // Byte variants of circ load
2138 let accessSize = ByteAccess in {
2139 def L2_loadrb_pci : T_load_pci <"memb", IntRegs, s4_0Imm, 0b1000>;
2140 def L2_loadrub_pci : T_load_pci <"memub", IntRegs, s4_0Imm, 0b1001>;
2143 // Half word variants of circ load
2144 let accessSize = HalfWordAccess in {
2145 def L2_loadrh_pci : T_load_pci <"memh", IntRegs, s4_1Imm, 0b1010>;
2146 def L2_loadruh_pci : T_load_pci <"memuh", IntRegs, s4_1Imm, 0b1011>;
2147 def L2_loadbzw2_pci : T_load_pci <"memubh", IntRegs, s4_1Imm, 0b0011>;
2148 def L2_loadbsw2_pci : T_load_pci <"membh", IntRegs, s4_1Imm, 0b0001>;
2151 // Word variants of circ load
2152 let accessSize = WordAccess in
2153 def L2_loadri_pci : T_load_pci <"memw", IntRegs, s4_2Imm, 0b1100>;
2155 let accessSize = WordAccess, hasNewValue = 0 in {
2156 def L2_loadbzw4_pci : T_load_pci <"memubh", DoubleRegs, s4_2Imm, 0b0101>;
2157 def L2_loadbsw4_pci : T_load_pci <"membh", DoubleRegs, s4_2Imm, 0b0111>;
2160 let accessSize = DoubleWordAccess, hasNewValue = 0 in
2161 def L2_loadrd_pci : T_load_pci <"memd", DoubleRegs, s4_3Imm, 0b1110>;
2163 //===----------------------------------------------------------------------===//
2164 // Circular loads - Pseudo
2166 // Please note that the input operand order in the pseudo instructions
2167 // doesn't match with the real instructions. Pseudo instructions operand
2168 // order should mimics the ordering in the intrinsics. Also, 'src2' doesn't
2169 // appear in the AsmString because it's same as 'dst'.
2170 //===----------------------------------------------------------------------===//
2171 let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0, isPseudo = 1 in
2172 class T_load_pci_pseudo <string opc, RegisterClass RC>
2173 : LDInstPI<(outs IntRegs:$_dst_, RC:$dst),
2174 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4Imm:$src4),
2175 ".error \"$dst = "#opc#"($src1++#$src4:circ($src3))\"",
2176 [], "$src1 = $_dst_">;
2178 def L2_loadrb_pci_pseudo : T_load_pci_pseudo <"memb", IntRegs>;
2179 def L2_loadrub_pci_pseudo : T_load_pci_pseudo <"memub", IntRegs>;
2180 def L2_loadrh_pci_pseudo : T_load_pci_pseudo <"memh", IntRegs>;
2181 def L2_loadruh_pci_pseudo : T_load_pci_pseudo <"memuh", IntRegs>;
2182 def L2_loadri_pci_pseudo : T_load_pci_pseudo <"memw", IntRegs>;
2183 def L2_loadrd_pci_pseudo : T_load_pci_pseudo <"memd", DoubleRegs>;
2186 // TODO: memb_fifo and memh_fifo must take destination register as input.
2187 // One-off circ loads - not enough in common to break into a class.
2188 let accessSize = ByteAccess in
2189 def L2_loadalignb_pci : T_load_pci <"memb_fifo", DoubleRegs, s4_0Imm, 0b0100>;
2191 let accessSize = HalfWordAccess, opExtentAlign = 1 in
2192 def L2_loadalignh_pci : T_load_pci <"memh_fifo", DoubleRegs, s4_1Imm, 0b0010>;
2194 // L[24]_load[wd]_locked: Load word/double with lock.
2196 class T_load_locked <string mnemonic, RegisterClass RC>
2197 : LD0Inst <(outs RC:$dst),
2199 "$dst = "#mnemonic#"($src)"> {
2202 let IClass = 0b1001;
2203 let Inst{27-21} = 0b0010000;
2204 let Inst{20-16} = src;
2205 let Inst{13-12} = !if (!eq(mnemonic, "memd_locked"), 0b01, 0b00);
2207 let Inst{4-0} = dst;
2209 let hasNewValue = 1, accessSize = WordAccess, opNewValue = 0 in
2210 def L2_loadw_locked : T_load_locked <"memw_locked", IntRegs>;
2211 let accessSize = DoubleWordAccess in
2212 def L4_loadd_locked : T_load_locked <"memd_locked", DoubleRegs>;
2214 // S[24]_store[wd]_locked: Store word/double conditionally.
2215 let isSoloAX = 1, isPredicateLate = 1 in
2216 class T_store_locked <string mnemonic, RegisterClass RC>
2217 : ST0Inst <(outs PredRegs:$Pd), (ins IntRegs:$Rs, RC:$Rt),
2218 mnemonic#"($Rs, $Pd) = $Rt"> {
2223 let IClass = 0b1010;
2224 let Inst{27-23} = 0b00001;
2225 let Inst{22} = !if (!eq(mnemonic, "memw_locked"), 0b0, 0b1);
2227 let Inst{20-16} = Rs;
2228 let Inst{12-8} = Rt;
2232 let accessSize = WordAccess in
2233 def S2_storew_locked : T_store_locked <"memw_locked", IntRegs>;
2235 let accessSize = DoubleWordAccess in
2236 def S4_stored_locked : T_store_locked <"memd_locked", DoubleRegs>;
2238 //===----------------------------------------------------------------------===//
2239 // Bit-reversed loads with auto-increment register
2240 //===----------------------------------------------------------------------===//
2241 let hasSideEffects = 0 in
2242 class T_load_pbr<string mnemonic, RegisterClass RC,
2243 MemAccessSize addrSize, bits<4> majOp>
2245 <(outs RC:$dst, IntRegs:$_dst_),
2246 (ins IntRegs:$Rz, ModRegs:$Mu),
2247 "$dst = "#mnemonic#"($Rz ++ $Mu:brev)" ,
2248 [] , "$Rz = $_dst_" > {
2250 let accessSize = addrSize;
2256 let IClass = 0b1001;
2258 let Inst{27-25} = 0b111;
2259 let Inst{24-21} = majOp;
2260 let Inst{20-16} = Rz;
2264 let Inst{4-0} = dst;
2267 let hasNewValue =1, opNewValue = 0 in {
2268 def L2_loadrb_pbr : T_load_pbr <"memb", IntRegs, ByteAccess, 0b1000>;
2269 def L2_loadrub_pbr : T_load_pbr <"memub", IntRegs, ByteAccess, 0b1001>;
2270 def L2_loadrh_pbr : T_load_pbr <"memh", IntRegs, HalfWordAccess, 0b1010>;
2271 def L2_loadruh_pbr : T_load_pbr <"memuh", IntRegs, HalfWordAccess, 0b1011>;
2272 def L2_loadbsw2_pbr : T_load_pbr <"membh", IntRegs, HalfWordAccess, 0b0001>;
2273 def L2_loadbzw2_pbr : T_load_pbr <"memubh", IntRegs, HalfWordAccess, 0b0011>;
2274 def L2_loadri_pbr : T_load_pbr <"memw", IntRegs, WordAccess, 0b1100>;
2277 def L2_loadbzw4_pbr : T_load_pbr <"memubh", DoubleRegs, WordAccess, 0b0101>;
2278 def L2_loadbsw4_pbr : T_load_pbr <"membh", DoubleRegs, WordAccess, 0b0111>;
2279 def L2_loadrd_pbr : T_load_pbr <"memd", DoubleRegs, DoubleWordAccess, 0b1110>;
2281 def L2_loadalignb_pbr :T_load_pbr <"memb_fifo", DoubleRegs, ByteAccess, 0b0100>;
2282 def L2_loadalignh_pbr :T_load_pbr <"memh_fifo", DoubleRegs,
2283 HalfWordAccess, 0b0010>;
2285 //===----------------------------------------------------------------------===//
2286 // Bit-reversed loads - Pseudo
2288 // Please note that 'src2' doesn't appear in the AsmString because
2289 // it's same as 'dst'.
2290 //===----------------------------------------------------------------------===//
2291 let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0, isPseudo = 1 in
2292 class T_load_pbr_pseudo <string opc, RegisterClass RC>
2293 : LDInstPI<(outs IntRegs:$_dst_, RC:$dst),
2294 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2295 ".error \"$dst = "#opc#"($src1++$src3:brev)\"",
2296 [], "$src1 = $_dst_">;
2298 def L2_loadrb_pbr_pseudo : T_load_pbr_pseudo <"memb", IntRegs>;
2299 def L2_loadrub_pbr_pseudo : T_load_pbr_pseudo <"memub", IntRegs>;
2300 def L2_loadrh_pbr_pseudo : T_load_pbr_pseudo <"memh", IntRegs>;
2301 def L2_loadruh_pbr_pseudo : T_load_pbr_pseudo <"memuh", IntRegs>;
2302 def L2_loadri_pbr_pseudo : T_load_pbr_pseudo <"memw", IntRegs>;
2303 def L2_loadrd_pbr_pseudo : T_load_pbr_pseudo <"memd", DoubleRegs>;
2305 //===----------------------------------------------------------------------===//
2307 //===----------------------------------------------------------------------===//
2309 //===----------------------------------------------------------------------===//
2311 //===----------------------------------------------------------------------===//
2312 //===----------------------------------------------------------------------===//
2314 //===----------------------------------------------------------------------===//
2316 //===----------------------------------------------------------------------===//
2318 //===----------------------------------------------------------------------===//
2319 //===----------------------------------------------------------------------===//
2321 //===----------------------------------------------------------------------===//
2323 //===----------------------------------------------------------------------===//
2325 //===----------------------------------------------------------------------===//
2327 //===----------------------------------------------------------------------===//
2329 // MPYS / Multipy signed/unsigned halfwords
2330 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
2331 //===----------------------------------------------------------------------===//
2333 let hasNewValue = 1, opNewValue = 0 in
2334 class T_M2_mpy < bits<2> LHbits, bit isSat, bit isRnd,
2335 bit hasShift, bit isUnsigned>
2336 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
2337 "$Rd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
2338 #", $Rt."#!if(LHbits{0},"h)","l)")
2339 #!if(hasShift,":<<1","")
2340 #!if(isRnd,":rnd","")
2341 #!if(isSat,":sat",""),
2342 [], "", M_tc_3x_SLOT23 > {
2347 let IClass = 0b1110;
2349 let Inst{27-24} = 0b1100;
2350 let Inst{23} = hasShift;
2351 let Inst{22} = isUnsigned;
2352 let Inst{21} = isRnd;
2353 let Inst{7} = isSat;
2354 let Inst{6-5} = LHbits;
2356 let Inst{20-16} = Rs;
2357 let Inst{12-8} = Rt;
2360 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2361 def M2_mpy_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 0>;
2362 def M2_mpy_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 0>;
2363 def M2_mpy_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 0>;
2364 def M2_mpy_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 0>;
2365 def M2_mpy_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 0>;
2366 def M2_mpy_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 0>;
2367 def M2_mpy_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 0>;
2368 def M2_mpy_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 0>;
2370 //Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2371 def M2_mpyu_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 1>;
2372 def M2_mpyu_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 1>;
2373 def M2_mpyu_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 1>;
2374 def M2_mpyu_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 1>;
2375 def M2_mpyu_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 1>;
2376 def M2_mpyu_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 1>;
2377 def M2_mpyu_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 1>;
2378 def M2_mpyu_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 1>;
2380 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]:rnd
2381 def M2_mpy_rnd_ll_s1: T_M2_mpy <0b00, 0, 1, 1, 0>;
2382 def M2_mpy_rnd_ll_s0: T_M2_mpy <0b00, 0, 1, 0, 0>;
2383 def M2_mpy_rnd_lh_s1: T_M2_mpy <0b01, 0, 1, 1, 0>;
2384 def M2_mpy_rnd_lh_s0: T_M2_mpy <0b01, 0, 1, 0, 0>;
2385 def M2_mpy_rnd_hl_s1: T_M2_mpy <0b10, 0, 1, 1, 0>;
2386 def M2_mpy_rnd_hl_s0: T_M2_mpy <0b10, 0, 1, 0, 0>;
2387 def M2_mpy_rnd_hh_s1: T_M2_mpy <0b11, 0, 1, 1, 0>;
2388 def M2_mpy_rnd_hh_s0: T_M2_mpy <0b11, 0, 1, 0, 0>;
2390 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2391 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
2392 let Defs = [USR_OVF] in {
2393 def M2_mpy_sat_ll_s1: T_M2_mpy <0b00, 1, 0, 1, 0>;
2394 def M2_mpy_sat_ll_s0: T_M2_mpy <0b00, 1, 0, 0, 0>;
2395 def M2_mpy_sat_lh_s1: T_M2_mpy <0b01, 1, 0, 1, 0>;
2396 def M2_mpy_sat_lh_s0: T_M2_mpy <0b01, 1, 0, 0, 0>;
2397 def M2_mpy_sat_hl_s1: T_M2_mpy <0b10, 1, 0, 1, 0>;
2398 def M2_mpy_sat_hl_s0: T_M2_mpy <0b10, 1, 0, 0, 0>;
2399 def M2_mpy_sat_hh_s1: T_M2_mpy <0b11, 1, 0, 1, 0>;
2400 def M2_mpy_sat_hh_s0: T_M2_mpy <0b11, 1, 0, 0, 0>;
2402 def M2_mpy_sat_rnd_ll_s1: T_M2_mpy <0b00, 1, 1, 1, 0>;
2403 def M2_mpy_sat_rnd_ll_s0: T_M2_mpy <0b00, 1, 1, 0, 0>;
2404 def M2_mpy_sat_rnd_lh_s1: T_M2_mpy <0b01, 1, 1, 1, 0>;
2405 def M2_mpy_sat_rnd_lh_s0: T_M2_mpy <0b01, 1, 1, 0, 0>;
2406 def M2_mpy_sat_rnd_hl_s1: T_M2_mpy <0b10, 1, 1, 1, 0>;
2407 def M2_mpy_sat_rnd_hl_s0: T_M2_mpy <0b10, 1, 1, 0, 0>;
2408 def M2_mpy_sat_rnd_hh_s1: T_M2_mpy <0b11, 1, 1, 1, 0>;
2409 def M2_mpy_sat_rnd_hh_s0: T_M2_mpy <0b11, 1, 1, 0, 0>;
2412 //===----------------------------------------------------------------------===//
2414 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
2415 // result from the accumulator.
2416 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2417 //===----------------------------------------------------------------------===//
2419 let hasNewValue = 1, opNewValue = 0 in
2420 class T_M2_mpy_acc < bits<2> LHbits, bit isSat, bit isNac,
2421 bit hasShift, bit isUnsigned >
2422 : MInst_acc<(outs IntRegs:$Rx), (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2423 "$Rx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy")
2424 #"($Rs."#!if(LHbits{1},"h","l")
2425 #", $Rt."#!if(LHbits{0},"h)","l)")
2426 #!if(hasShift,":<<1","")
2427 #!if(isSat,":sat",""),
2428 [], "$dst2 = $Rx", M_tc_3x_SLOT23 > {
2433 let IClass = 0b1110;
2434 let Inst{27-24} = 0b1110;
2435 let Inst{23} = hasShift;
2436 let Inst{22} = isUnsigned;
2437 let Inst{21} = isNac;
2438 let Inst{7} = isSat;
2439 let Inst{6-5} = LHbits;
2441 let Inst{20-16} = Rs;
2442 let Inst{12-8} = Rt;
2445 //Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2446 def M2_mpy_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 0>;
2447 def M2_mpy_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 0>;
2448 def M2_mpy_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 0>;
2449 def M2_mpy_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 0>;
2450 def M2_mpy_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 0>;
2451 def M2_mpy_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 0>;
2452 def M2_mpy_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 0>;
2453 def M2_mpy_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 0>;
2455 //Rx += mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2456 def M2_mpyu_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 1>;
2457 def M2_mpyu_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 1>;
2458 def M2_mpyu_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 1>;
2459 def M2_mpyu_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 1>;
2460 def M2_mpyu_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 1>;
2461 def M2_mpyu_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 1>;
2462 def M2_mpyu_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 1>;
2463 def M2_mpyu_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 1>;
2465 //Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2466 def M2_mpy_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 0>;
2467 def M2_mpy_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 0>;
2468 def M2_mpy_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 0>;
2469 def M2_mpy_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 0>;
2470 def M2_mpy_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 0>;
2471 def M2_mpy_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 0>;
2472 def M2_mpy_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 0>;
2473 def M2_mpy_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 0>;
2475 //Rx -= mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2476 def M2_mpyu_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 1>;
2477 def M2_mpyu_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 1>;
2478 def M2_mpyu_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 1>;
2479 def M2_mpyu_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 1>;
2480 def M2_mpyu_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 1>;
2481 def M2_mpyu_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 1>;
2482 def M2_mpyu_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 1>;
2483 def M2_mpyu_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 1>;
2485 //Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat
2486 def M2_mpy_acc_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 0, 1, 0>;
2487 def M2_mpy_acc_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 0, 0, 0>;
2488 def M2_mpy_acc_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 0, 1, 0>;
2489 def M2_mpy_acc_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 0, 0, 0>;
2490 def M2_mpy_acc_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 0, 1, 0>;
2491 def M2_mpy_acc_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 0, 0, 0>;
2492 def M2_mpy_acc_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 0, 1, 0>;
2493 def M2_mpy_acc_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 0, 0, 0>;
2495 //Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat
2496 def M2_mpy_nac_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 1, 1, 0>;
2497 def M2_mpy_nac_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 1, 0, 0>;
2498 def M2_mpy_nac_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 1, 1, 0>;
2499 def M2_mpy_nac_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 1, 0, 0>;
2500 def M2_mpy_nac_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 1, 1, 0>;
2501 def M2_mpy_nac_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 1, 0, 0>;
2502 def M2_mpy_nac_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 1, 1, 0>;
2503 def M2_mpy_nac_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 1, 0, 0>;
2505 //===----------------------------------------------------------------------===//
2507 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
2508 // result from the 64-bit destination register.
2509 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2510 //===----------------------------------------------------------------------===//
2512 class T_M2_mpyd_acc < bits<2> LHbits, bit isNac, bit hasShift, bit isUnsigned>
2513 : MInst_acc<(outs DoubleRegs:$Rxx),
2514 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2515 "$Rxx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy")
2516 #"($Rs."#!if(LHbits{1},"h","l")
2517 #", $Rt."#!if(LHbits{0},"h)","l)")
2518 #!if(hasShift,":<<1",""),
2519 [], "$dst2 = $Rxx", M_tc_3x_SLOT23 > {
2524 let IClass = 0b1110;
2526 let Inst{27-24} = 0b0110;
2527 let Inst{23} = hasShift;
2528 let Inst{22} = isUnsigned;
2529 let Inst{21} = isNac;
2531 let Inst{6-5} = LHbits;
2532 let Inst{4-0} = Rxx;
2533 let Inst{20-16} = Rs;
2534 let Inst{12-8} = Rt;
2537 def M2_mpyd_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 0>;
2538 def M2_mpyd_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 0>;
2539 def M2_mpyd_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 0>;
2540 def M2_mpyd_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 0>;
2542 def M2_mpyd_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 0>;
2543 def M2_mpyd_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 0>;
2544 def M2_mpyd_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 0>;
2545 def M2_mpyd_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 0>;
2547 def M2_mpyd_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 0>;
2548 def M2_mpyd_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 0>;
2549 def M2_mpyd_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 0>;
2550 def M2_mpyd_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 0>;
2552 def M2_mpyd_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 0>;
2553 def M2_mpyd_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 0>;
2554 def M2_mpyd_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 0>;
2555 def M2_mpyd_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 0>;
2557 def M2_mpyud_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 1>;
2558 def M2_mpyud_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 1>;
2559 def M2_mpyud_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 1>;
2560 def M2_mpyud_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 1>;
2562 def M2_mpyud_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 1>;
2563 def M2_mpyud_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 1>;
2564 def M2_mpyud_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 1>;
2565 def M2_mpyud_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 1>;
2567 def M2_mpyud_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 1>;
2568 def M2_mpyud_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 1>;
2569 def M2_mpyud_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 1>;
2570 def M2_mpyud_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 1>;
2572 def M2_mpyud_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 1>;
2573 def M2_mpyud_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 1>;
2574 def M2_mpyud_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 1>;
2575 def M2_mpyud_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 1>;
2577 //===----------------------------------------------------------------------===//
2578 // Template Class -- Vector Multipy
2579 // Used for complex multiply real or imaginary, dual multiply and even halfwords
2580 //===----------------------------------------------------------------------===//
2581 class T_M2_vmpy < string opc, bits<3> MajOp, bits<3> MinOp, bit hasShift,
2582 bit isRnd, bit isSat >
2583 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
2584 "$Rdd = "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
2585 #!if(isRnd,":rnd","")
2586 #!if(isSat,":sat",""),
2592 let IClass = 0b1110;
2594 let Inst{27-24} = 0b1000;
2595 let Inst{23-21} = MajOp;
2596 let Inst{7-5} = MinOp;
2597 let Inst{4-0} = Rdd;
2598 let Inst{20-16} = Rss;
2599 let Inst{12-8} = Rtt;
2602 // Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat
2603 let Defs = [USR_OVF] in {
2604 def M2_vcmpy_s1_sat_i: T_M2_vmpy <"vcmpyi", 0b110, 0b110, 1, 0, 1>;
2605 def M2_vcmpy_s0_sat_i: T_M2_vmpy <"vcmpyi", 0b010, 0b110, 0, 0, 1>;
2607 // Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat
2608 def M2_vcmpy_s1_sat_r: T_M2_vmpy <"vcmpyr", 0b101, 0b110, 1, 0, 1>;
2609 def M2_vcmpy_s0_sat_r: T_M2_vmpy <"vcmpyr", 0b001, 0b110, 0, 0, 1>;
2611 // Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat
2612 def M2_vdmpys_s1: T_M2_vmpy <"vdmpy", 0b100, 0b100, 1, 0, 1>;
2613 def M2_vdmpys_s0: T_M2_vmpy <"vdmpy", 0b000, 0b100, 0, 0, 1>;
2615 // Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat
2616 def M2_vmpy2es_s1: T_M2_vmpy <"vmpyeh", 0b100, 0b110, 1, 0, 1>;
2617 def M2_vmpy2es_s0: T_M2_vmpy <"vmpyeh", 0b000, 0b110, 0, 0, 1>;
2619 //Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat
2620 def M2_mmpyh_s0: T_M2_vmpy <"vmpywoh", 0b000, 0b111, 0, 0, 1>;
2621 def M2_mmpyh_s1: T_M2_vmpy <"vmpywoh", 0b100, 0b111, 1, 0, 1>;
2622 def M2_mmpyh_rs0: T_M2_vmpy <"vmpywoh", 0b001, 0b111, 0, 1, 1>;
2623 def M2_mmpyh_rs1: T_M2_vmpy <"vmpywoh", 0b101, 0b111, 1, 1, 1>;
2625 //Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat
2626 def M2_mmpyl_s0: T_M2_vmpy <"vmpyweh", 0b000, 0b101, 0, 0, 1>;
2627 def M2_mmpyl_s1: T_M2_vmpy <"vmpyweh", 0b100, 0b101, 1, 0, 1>;
2628 def M2_mmpyl_rs0: T_M2_vmpy <"vmpyweh", 0b001, 0b101, 0, 1, 1>;
2629 def M2_mmpyl_rs1: T_M2_vmpy <"vmpyweh", 0b101, 0b101, 1, 1, 1>;
2631 //Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat
2632 def M2_mmpyuh_s0: T_M2_vmpy <"vmpywouh", 0b010, 0b111, 0, 0, 1>;
2633 def M2_mmpyuh_s1: T_M2_vmpy <"vmpywouh", 0b110, 0b111, 1, 0, 1>;
2634 def M2_mmpyuh_rs0: T_M2_vmpy <"vmpywouh", 0b011, 0b111, 0, 1, 1>;
2635 def M2_mmpyuh_rs1: T_M2_vmpy <"vmpywouh", 0b111, 0b111, 1, 1, 1>;
2637 //Rdd=vmpyweuh(Rss,Rtt)[:<<1][:rnd]:sat
2638 def M2_mmpyul_s0: T_M2_vmpy <"vmpyweuh", 0b010, 0b101, 0, 0, 1>;
2639 def M2_mmpyul_s1: T_M2_vmpy <"vmpyweuh", 0b110, 0b101, 1, 0, 1>;
2640 def M2_mmpyul_rs0: T_M2_vmpy <"vmpyweuh", 0b011, 0b101, 0, 1, 1>;
2641 def M2_mmpyul_rs1: T_M2_vmpy <"vmpyweuh", 0b111, 0b101, 1, 1, 1>;
2644 let hasNewValue = 1, opNewValue = 0 in
2645 class T_MType_mpy <string mnemonic, bits<4> RegTyBits, RegisterClass RC,
2646 bits<3> MajOp, bits<3> MinOp, bit isSat = 0, bit isRnd = 0,
2647 string op2Suffix = "", bit isRaw = 0, bit isHi = 0 >
2648 : MInst <(outs IntRegs:$dst), (ins RC:$src1, RC:$src2),
2650 #"($src1, $src2"#op2Suffix#")"
2651 #!if(MajOp{2}, ":<<1", "")
2652 #!if(isRnd, ":rnd", "")
2653 #!if(isSat, ":sat", "")
2654 #!if(isRaw, !if(isHi, ":raw:hi", ":raw:lo"), ""), [] > {
2659 let IClass = 0b1110;
2661 let Inst{27-24} = RegTyBits;
2662 let Inst{23-21} = MajOp;
2663 let Inst{20-16} = src1;
2665 let Inst{12-8} = src2;
2666 let Inst{7-5} = MinOp;
2667 let Inst{4-0} = dst;
2670 class T_MType_vrcmpy <string mnemonic, bits<3> MajOp, bits<3> MinOp, bit isHi>
2671 : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, 1, 1, "", 1, isHi>;
2673 class T_MType_dd <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2674 bit isSat = 0, bit isRnd = 0 >
2675 : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, isSat, isRnd>;
2677 class T_MType_rr1 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2678 bit isSat = 0, bit isRnd = 0 >
2679 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd>;
2681 class T_MType_rr2 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2682 bit isSat = 0, bit isRnd = 0, string op2str = "" >
2683 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd, op2str>;
2685 def M2_vradduh : T_MType_dd <"vradduh", 0b000, 0b001, 0, 0>;
2686 def M2_vdmpyrs_s0 : T_MType_dd <"vdmpy", 0b000, 0b000, 1, 1>;
2687 def M2_vdmpyrs_s1 : T_MType_dd <"vdmpy", 0b100, 0b000, 1, 1>;
2689 let CextOpcode = "mpyi", InputType = "reg" in
2690 def M2_mpyi : T_MType_rr1 <"mpyi", 0b000, 0b000>, ImmRegRel;
2692 def M2_mpy_up : T_MType_rr1 <"mpy", 0b000, 0b001>;
2693 def M2_mpyu_up : T_MType_rr1 <"mpyu", 0b010, 0b001>;
2695 def M2_dpmpyss_rnd_s0 : T_MType_rr1 <"mpy", 0b001, 0b001, 0, 1>;
2697 def M2_vmpy2s_s0pack : T_MType_rr1 <"vmpyh", 0b001, 0b111, 1, 1>;
2698 def M2_vmpy2s_s1pack : T_MType_rr1 <"vmpyh", 0b101, 0b111, 1, 1>;
2700 def M2_hmmpyh_rs1 : T_MType_rr2 <"mpy", 0b101, 0b100, 1, 1, ".h">;
2701 def M2_hmmpyl_rs1 : T_MType_rr2 <"mpy", 0b111, 0b100, 1, 1, ".l">;
2703 def M2_cmpyrs_s0 : T_MType_rr2 <"cmpy", 0b001, 0b110, 1, 1>;
2704 def M2_cmpyrs_s1 : T_MType_rr2 <"cmpy", 0b101, 0b110, 1, 1>;
2705 def M2_cmpyrsc_s0 : T_MType_rr2 <"cmpy", 0b011, 0b110, 1, 1, "*">;
2706 def M2_cmpyrsc_s1 : T_MType_rr2 <"cmpy", 0b111, 0b110, 1, 1, "*">;
2709 def M2_vraddh : T_MType_dd <"vraddh", 0b001, 0b111, 0>;
2710 def M2_mpysu_up : T_MType_rr1 <"mpysu", 0b011, 0b001, 0>;
2711 def M2_mpy_up_s1 : T_MType_rr1 <"mpy", 0b101, 0b010, 0>;
2712 def M2_mpy_up_s1_sat : T_MType_rr1 <"mpy", 0b111, 0b000, 1>;
2714 def M2_hmmpyh_s1 : T_MType_rr2 <"mpy", 0b101, 0b000, 1, 0, ".h">;
2715 def M2_hmmpyl_s1 : T_MType_rr2 <"mpy", 0b101, 0b001, 1, 0, ".l">;
2717 def: Pat<(i32 (mul I32:$src1, I32:$src2)), (M2_mpyi I32:$src1, I32:$src2)>;
2718 def: Pat<(i32 (mulhs I32:$src1, I32:$src2)), (M2_mpy_up I32:$src1, I32:$src2)>;
2719 def: Pat<(i32 (mulhu I32:$src1, I32:$src2)), (M2_mpyu_up I32:$src1, I32:$src2)>;
2721 let hasNewValue = 1, opNewValue = 0 in
2722 class T_MType_mpy_ri <bit isNeg, Operand ImmOp, list<dag> pattern>
2723 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, ImmOp:$u8),
2724 "$Rd ="#!if(isNeg, "- ", "+ ")#"mpyi($Rs, #$u8)" ,
2725 pattern, "", M_tc_3x_SLOT23> {
2730 let IClass = 0b1110;
2732 let Inst{27-24} = 0b0000;
2733 let Inst{23} = isNeg;
2736 let Inst{20-16} = Rs;
2737 let Inst{12-5} = u8;
2740 let isExtendable = 1, opExtentBits = 8, opExtendable = 2 in
2741 def M2_mpysip : T_MType_mpy_ri <0, u8Ext,
2742 [(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u32ImmPred:$u8))]>;
2744 def M2_mpysin : T_MType_mpy_ri <1, u8Imm,
2745 [(set (i32 IntRegs:$Rd), (ineg (mul IntRegs:$Rs,
2748 // Assember mapped to M2_mpyi
2749 let isAsmParserOnly = 1 in
2750 def M2_mpyui : MInst<(outs IntRegs:$dst),
2751 (ins IntRegs:$src1, IntRegs:$src2),
2752 "$dst = mpyui($src1, $src2)">;
2755 // s9 is NOT the same as m9 - but it works.. so far.
2756 // Assembler maps to either Rd=+mpyi(Rs,#u8) or Rd=-mpyi(Rs,#u8)
2757 // depending on the value of m9. See Arch Spec.
2758 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
2759 CextOpcode = "mpyi", InputType = "imm", hasNewValue = 1,
2760 isAsmParserOnly = 1 in
2761 def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
2762 "$dst = mpyi($src1, #$src2)",
2763 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
2764 s32ImmPred:$src2))]>, ImmRegRel;
2766 let hasNewValue = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 3,
2767 InputType = "imm" in
2768 class T_MType_acc_ri <string mnemonic, bits<3> MajOp, Operand ImmOp,
2769 list<dag> pattern = []>
2770 : MInst < (outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, ImmOp:$src3),
2771 "$dst "#mnemonic#"($src2, #$src3)",
2772 pattern, "$src1 = $dst", M_tc_2_SLOT23> {
2777 let IClass = 0b1110;
2779 let Inst{27-26} = 0b00;
2780 let Inst{25-23} = MajOp;
2781 let Inst{20-16} = src2;
2783 let Inst{12-5} = src3;
2784 let Inst{4-0} = dst;
2787 let InputType = "reg", hasNewValue = 1 in
2788 class T_MType_acc_rr <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2789 bit isSwap = 0, list<dag> pattern = [], bit hasNot = 0,
2790 bit isSat = 0, bit isShift = 0>
2791 : MInst < (outs IntRegs:$dst),
2792 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2793 "$dst "#mnemonic#"($src2, "#!if(hasNot, "~$src3)","$src3)")
2794 #!if(isShift, ":<<1", "")
2795 #!if(isSat, ":sat", ""),
2796 pattern, "$src1 = $dst", M_tc_2_SLOT23 > {
2801 let IClass = 0b1110;
2803 let Inst{27-24} = 0b1111;
2804 let Inst{23-21} = MajOp;
2805 let Inst{20-16} = !if(isSwap, src3, src2);
2807 let Inst{12-8} = !if(isSwap, src2, src3);
2808 let Inst{7-5} = MinOp;
2809 let Inst{4-0} = dst;
2812 let CextOpcode = "MPYI_acc", Itinerary = M_tc_3x_SLOT23 in {
2813 def M2_macsip : T_MType_acc_ri <"+= mpyi", 0b010, u8Ext,
2814 [(set (i32 IntRegs:$dst),
2815 (add (mul IntRegs:$src2, u32ImmPred:$src3),
2816 IntRegs:$src1))]>, ImmRegRel;
2818 def M2_maci : T_MType_acc_rr <"+= mpyi", 0b000, 0b000, 0,
2819 [(set (i32 IntRegs:$dst),
2820 (add (mul IntRegs:$src2, IntRegs:$src3),
2821 IntRegs:$src1))]>, ImmRegRel;
2824 let CextOpcode = "ADD_acc" in {
2825 let isExtentSigned = 1 in
2826 def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8Ext,
2827 [(set (i32 IntRegs:$dst),
2828 (add (add (i32 IntRegs:$src2), s16_16ImmPred:$src3),
2829 (i32 IntRegs:$src1)))]>, ImmRegRel;
2831 def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0,
2832 [(set (i32 IntRegs:$dst),
2833 (add (add (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
2834 (i32 IntRegs:$src1)))]>, ImmRegRel;
2837 let CextOpcode = "SUB_acc" in {
2838 let isExtentSigned = 1 in
2839 def M2_naccii : T_MType_acc_ri <"-= add", 0b101, s8Ext>, ImmRegRel;
2841 def M2_nacci : T_MType_acc_rr <"-= add", 0b100, 0b001, 0>, ImmRegRel;
2844 let Itinerary = M_tc_3x_SLOT23 in
2845 def M2_macsin : T_MType_acc_ri <"-= mpyi", 0b011, u8Ext>;
2847 def M2_xor_xacc : T_MType_acc_rr < "^= xor", 0b100, 0b011, 0>;
2848 def M2_subacc : T_MType_acc_rr <"+= sub", 0b000, 0b011, 1>;
2850 class T_MType_acc_pat1 <InstHexagon MI, SDNode firstOp, SDNode secOp,
2852 : Pat <(secOp IntRegs:$src1, (firstOp IntRegs:$src2, ImmPred:$src3)),
2853 (MI IntRegs:$src1, IntRegs:$src2, ImmPred:$src3)>;
2855 class T_MType_acc_pat2 <InstHexagon MI, SDNode firstOp, SDNode secOp>
2856 : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2, IntRegs:$src3))),
2857 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2859 def : T_MType_acc_pat2 <M2_xor_xacc, xor, xor>;
2860 def : T_MType_acc_pat1 <M2_macsin, mul, sub, u32ImmPred>;
2862 def : T_MType_acc_pat1 <M2_naccii, add, sub, s16_16ImmPred>;
2863 def : T_MType_acc_pat2 <M2_nacci, add, sub>;
2865 //===----------------------------------------------------------------------===//
2866 // Template Class -- XType Vector Instructions
2867 //===----------------------------------------------------------------------===//
2868 class T_XTYPE_Vect < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj >
2869 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
2870 "$Rdd = "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"),
2876 let IClass = 0b1110;
2878 let Inst{27-24} = 0b1000;
2879 let Inst{23-21} = MajOp;
2880 let Inst{7-5} = MinOp;
2881 let Inst{4-0} = Rdd;
2882 let Inst{20-16} = Rss;
2883 let Inst{12-8} = Rtt;
2886 class T_XTYPE_Vect_acc < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj >
2887 : MInst <(outs DoubleRegs:$Rdd),
2888 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2889 "$Rdd += "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"),
2890 [], "$dst2 = $Rdd",M_tc_3x_SLOT23 > {
2895 let IClass = 0b1110;
2897 let Inst{27-24} = 0b1010;
2898 let Inst{23-21} = MajOp;
2899 let Inst{7-5} = MinOp;
2900 let Inst{4-0} = Rdd;
2901 let Inst{20-16} = Rss;
2902 let Inst{12-8} = Rtt;
2905 class T_XTYPE_Vect_diff < bits<3> MajOp, string opc >
2906 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rtt, DoubleRegs:$Rss),
2907 "$Rdd = "#opc#"($Rtt, $Rss)",
2908 [], "",M_tc_2_SLOT23 > {
2913 let IClass = 0b1110;
2915 let Inst{27-24} = 0b1000;
2916 let Inst{23-21} = MajOp;
2917 let Inst{7-5} = 0b000;
2918 let Inst{4-0} = Rdd;
2919 let Inst{20-16} = Rss;
2920 let Inst{12-8} = Rtt;
2923 // Vector reduce add unsigned bytes: Rdd32=vrmpybu(Rss32,Rtt32)
2924 def A2_vraddub: T_XTYPE_Vect <"vraddub", 0b010, 0b001, 0>;
2925 def A2_vraddub_acc: T_XTYPE_Vect_acc <"vraddub", 0b010, 0b001, 0>;
2927 // Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt)
2928 def A2_vrsadub: T_XTYPE_Vect <"vrsadub", 0b010, 0b010, 0>;
2929 def A2_vrsadub_acc: T_XTYPE_Vect_acc <"vrsadub", 0b010, 0b010, 0>;
2931 // Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss)
2932 def M2_vabsdiffh: T_XTYPE_Vect_diff<0b011, "vabsdiffh">;
2934 // Vector absolute difference words: Rdd=vabsdiffw(Rtt,Rss)
2935 def M2_vabsdiffw: T_XTYPE_Vect_diff<0b001, "vabsdiffw">;
2937 // Vector reduce complex multiply real or imaginary:
2938 // Rdd[+]=vrcmpy[ir](Rss,Rtt[*])
2939 def M2_vrcmpyi_s0: T_XTYPE_Vect <"vrcmpyi", 0b000, 0b000, 0>;
2940 def M2_vrcmpyi_s0c: T_XTYPE_Vect <"vrcmpyi", 0b010, 0b000, 1>;
2941 def M2_vrcmaci_s0: T_XTYPE_Vect_acc <"vrcmpyi", 0b000, 0b000, 0>;
2942 def M2_vrcmaci_s0c: T_XTYPE_Vect_acc <"vrcmpyi", 0b010, 0b000, 1>;
2944 def M2_vrcmpyr_s0: T_XTYPE_Vect <"vrcmpyr", 0b000, 0b001, 0>;
2945 def M2_vrcmpyr_s0c: T_XTYPE_Vect <"vrcmpyr", 0b011, 0b001, 1>;
2946 def M2_vrcmacr_s0: T_XTYPE_Vect_acc <"vrcmpyr", 0b000, 0b001, 0>;
2947 def M2_vrcmacr_s0c: T_XTYPE_Vect_acc <"vrcmpyr", 0b011, 0b001, 1>;
2949 // Vector reduce halfwords:
2950 // Rdd[+]=vrmpyh(Rss,Rtt)
2951 def M2_vrmpy_s0: T_XTYPE_Vect <"vrmpyh", 0b000, 0b010, 0>;
2952 def M2_vrmac_s0: T_XTYPE_Vect_acc <"vrmpyh", 0b000, 0b010, 0>;
2954 //===----------------------------------------------------------------------===//
2955 // Template Class -- Vector Multipy with accumulation.
2956 // Used for complex multiply real or imaginary, dual multiply and even halfwords
2957 //===----------------------------------------------------------------------===//
2958 let Defs = [USR_OVF] in
2959 class T_M2_vmpy_acc_sat < string opc, bits<3> MajOp, bits<3> MinOp,
2960 bit hasShift, bit isRnd >
2961 : MInst <(outs DoubleRegs:$Rxx),
2962 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2963 "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
2964 #!if(isRnd,":rnd","")#":sat",
2965 [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > {
2970 let IClass = 0b1110;
2972 let Inst{27-24} = 0b1010;
2973 let Inst{23-21} = MajOp;
2974 let Inst{7-5} = MinOp;
2975 let Inst{4-0} = Rxx;
2976 let Inst{20-16} = Rss;
2977 let Inst{12-8} = Rtt;
2980 class T_M2_vmpy_acc < string opc, bits<3> MajOp, bits<3> MinOp,
2981 bit hasShift, bit isRnd >
2982 : MInst <(outs DoubleRegs:$Rxx),
2983 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2984 "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
2985 #!if(isRnd,":rnd",""),
2986 [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > {
2991 let IClass = 0b1110;
2993 let Inst{27-24} = 0b1010;
2994 let Inst{23-21} = MajOp;
2995 let Inst{7-5} = MinOp;
2996 let Inst{4-0} = Rxx;
2997 let Inst{20-16} = Rss;
2998 let Inst{12-8} = Rtt;
3001 // Vector multiply word by signed half with accumulation
3002 // Rxx+=vmpyw[eo]h(Rss,Rtt)[:<<1][:rnd]:sat
3003 def M2_mmacls_s1: T_M2_vmpy_acc_sat <"vmpyweh", 0b100, 0b101, 1, 0>;
3004 def M2_mmacls_s0: T_M2_vmpy_acc_sat <"vmpyweh", 0b000, 0b101, 0, 0>;
3005 def M2_mmacls_rs1: T_M2_vmpy_acc_sat <"vmpyweh", 0b101, 0b101, 1, 1>;
3006 def M2_mmacls_rs0: T_M2_vmpy_acc_sat <"vmpyweh", 0b001, 0b101, 0, 1>;
3008 def M2_mmachs_s1: T_M2_vmpy_acc_sat <"vmpywoh", 0b100, 0b111, 1, 0>;
3009 def M2_mmachs_s0: T_M2_vmpy_acc_sat <"vmpywoh", 0b000, 0b111, 0, 0>;
3010 def M2_mmachs_rs1: T_M2_vmpy_acc_sat <"vmpywoh", 0b101, 0b111, 1, 1>;
3011 def M2_mmachs_rs0: T_M2_vmpy_acc_sat <"vmpywoh", 0b001, 0b111, 0, 1>;
3013 // Vector multiply word by unsigned half with accumulation
3014 // Rxx+=vmpyw[eo]uh(Rss,Rtt)[:<<1][:rnd]:sat
3015 def M2_mmaculs_s1: T_M2_vmpy_acc_sat <"vmpyweuh", 0b110, 0b101, 1, 0>;
3016 def M2_mmaculs_s0: T_M2_vmpy_acc_sat <"vmpyweuh", 0b010, 0b101, 0, 0>;
3017 def M2_mmaculs_rs1: T_M2_vmpy_acc_sat <"vmpyweuh", 0b111, 0b101, 1, 1>;
3018 def M2_mmaculs_rs0: T_M2_vmpy_acc_sat <"vmpyweuh", 0b011, 0b101, 0, 1>;
3020 def M2_mmacuhs_s1: T_M2_vmpy_acc_sat <"vmpywouh", 0b110, 0b111, 1, 0>;
3021 def M2_mmacuhs_s0: T_M2_vmpy_acc_sat <"vmpywouh", 0b010, 0b111, 0, 0>;
3022 def M2_mmacuhs_rs1: T_M2_vmpy_acc_sat <"vmpywouh", 0b111, 0b111, 1, 1>;
3023 def M2_mmacuhs_rs0: T_M2_vmpy_acc_sat <"vmpywouh", 0b011, 0b111, 0, 1>;
3025 // Vector multiply even halfwords with accumulation
3026 // Rxx+=vmpyeh(Rss,Rtt)[:<<1][:sat]
3027 def M2_vmac2es: T_M2_vmpy_acc <"vmpyeh", 0b001, 0b010, 0, 0>;
3028 def M2_vmac2es_s1: T_M2_vmpy_acc_sat <"vmpyeh", 0b100, 0b110, 1, 0>;
3029 def M2_vmac2es_s0: T_M2_vmpy_acc_sat <"vmpyeh", 0b000, 0b110, 0, 0>;
3031 // Vector dual multiply with accumulation
3032 // Rxx+=vdmpy(Rss,Rtt)[:sat]
3033 def M2_vdmacs_s1: T_M2_vmpy_acc_sat <"vdmpy", 0b100, 0b100, 1, 0>;
3034 def M2_vdmacs_s0: T_M2_vmpy_acc_sat <"vdmpy", 0b000, 0b100, 0, 0>;
3036 // Vector complex multiply real or imaginary with accumulation
3037 // Rxx+=vcmpy[ir](Rss,Rtt):sat
3038 def M2_vcmac_s0_sat_r: T_M2_vmpy_acc_sat <"vcmpyr", 0b001, 0b100, 0, 0>;
3039 def M2_vcmac_s0_sat_i: T_M2_vmpy_acc_sat <"vcmpyi", 0b010, 0b100, 0, 0>;
3041 //===----------------------------------------------------------------------===//
3042 // Template Class -- Multiply signed/unsigned halfwords with and without
3043 // saturation and rounding
3044 //===----------------------------------------------------------------------===//
3045 class T_M2_mpyd < bits<2> LHbits, bit isRnd, bit hasShift, bit isUnsigned >
3046 : MInst < (outs DoubleRegs:$Rdd), (ins IntRegs:$Rs, IntRegs:$Rt),
3047 "$Rdd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
3048 #", $Rt."#!if(LHbits{0},"h)","l)")
3049 #!if(hasShift,":<<1","")
3050 #!if(isRnd,":rnd",""),
3056 let IClass = 0b1110;
3058 let Inst{27-24} = 0b0100;
3059 let Inst{23} = hasShift;
3060 let Inst{22} = isUnsigned;
3061 let Inst{21} = isRnd;
3062 let Inst{6-5} = LHbits;
3063 let Inst{4-0} = Rdd;
3064 let Inst{20-16} = Rs;
3065 let Inst{12-8} = Rt;
3068 def M2_mpyd_hh_s0: T_M2_mpyd<0b11, 0, 0, 0>;
3069 def M2_mpyd_hl_s0: T_M2_mpyd<0b10, 0, 0, 0>;
3070 def M2_mpyd_lh_s0: T_M2_mpyd<0b01, 0, 0, 0>;
3071 def M2_mpyd_ll_s0: T_M2_mpyd<0b00, 0, 0, 0>;
3073 def M2_mpyd_hh_s1: T_M2_mpyd<0b11, 0, 1, 0>;
3074 def M2_mpyd_hl_s1: T_M2_mpyd<0b10, 0, 1, 0>;
3075 def M2_mpyd_lh_s1: T_M2_mpyd<0b01, 0, 1, 0>;
3076 def M2_mpyd_ll_s1: T_M2_mpyd<0b00, 0, 1, 0>;
3078 def M2_mpyd_rnd_hh_s0: T_M2_mpyd<0b11, 1, 0, 0>;
3079 def M2_mpyd_rnd_hl_s0: T_M2_mpyd<0b10, 1, 0, 0>;
3080 def M2_mpyd_rnd_lh_s0: T_M2_mpyd<0b01, 1, 0, 0>;
3081 def M2_mpyd_rnd_ll_s0: T_M2_mpyd<0b00, 1, 0, 0>;
3083 def M2_mpyd_rnd_hh_s1: T_M2_mpyd<0b11, 1, 1, 0>;
3084 def M2_mpyd_rnd_hl_s1: T_M2_mpyd<0b10, 1, 1, 0>;
3085 def M2_mpyd_rnd_lh_s1: T_M2_mpyd<0b01, 1, 1, 0>;
3086 def M2_mpyd_rnd_ll_s1: T_M2_mpyd<0b00, 1, 1, 0>;
3088 //Rdd=mpyu(Rs.[HL],Rt.[HL])[:<<1]
3089 def M2_mpyud_hh_s0: T_M2_mpyd<0b11, 0, 0, 1>;
3090 def M2_mpyud_hl_s0: T_M2_mpyd<0b10, 0, 0, 1>;
3091 def M2_mpyud_lh_s0: T_M2_mpyd<0b01, 0, 0, 1>;
3092 def M2_mpyud_ll_s0: T_M2_mpyd<0b00, 0, 0, 1>;
3094 def M2_mpyud_hh_s1: T_M2_mpyd<0b11, 0, 1, 1>;
3095 def M2_mpyud_hl_s1: T_M2_mpyd<0b10, 0, 1, 1>;
3096 def M2_mpyud_lh_s1: T_M2_mpyd<0b01, 0, 1, 1>;
3097 def M2_mpyud_ll_s1: T_M2_mpyd<0b00, 0, 1, 1>;
3099 //===----------------------------------------------------------------------===//
3100 // Template Class for xtype mpy:
3103 // multiply 32X32 and use full result
3104 //===----------------------------------------------------------------------===//
3105 let hasSideEffects = 0 in
3106 class T_XTYPE_mpy64 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
3107 bit isSat, bit hasShift, bit isConj>
3108 : MInst <(outs DoubleRegs:$Rdd),
3109 (ins IntRegs:$Rs, IntRegs:$Rt),
3110 "$Rdd = "#mnemonic#"($Rs, $Rt"#!if(isConj,"*)",")")
3111 #!if(hasShift,":<<1","")
3112 #!if(isSat,":sat",""),
3118 let IClass = 0b1110;
3120 let Inst{27-24} = 0b0101;
3121 let Inst{23-21} = MajOp;
3122 let Inst{20-16} = Rs;
3123 let Inst{12-8} = Rt;
3124 let Inst{7-5} = MinOp;
3125 let Inst{4-0} = Rdd;
3128 //===----------------------------------------------------------------------===//
3129 // Template Class for xtype mpy with accumulation into 64-bit:
3132 // multiply 32X32 and use full result
3133 //===----------------------------------------------------------------------===//
3134 class T_XTYPE_mpy64_acc <string op1, string op2, bits<3> MajOp, bits<3> MinOp,
3135 bit isSat, bit hasShift, bit isConj>
3136 : MInst <(outs DoubleRegs:$Rxx),
3137 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
3138 "$Rxx "#op2#"= "#op1#"($Rs, $Rt"#!if(isConj,"*)",")")
3139 #!if(hasShift,":<<1","")
3140 #!if(isSat,":sat",""),
3142 [] , "$dst2 = $Rxx" > {
3147 let IClass = 0b1110;
3149 let Inst{27-24} = 0b0111;
3150 let Inst{23-21} = MajOp;
3151 let Inst{20-16} = Rs;
3152 let Inst{12-8} = Rt;
3153 let Inst{7-5} = MinOp;
3154 let Inst{4-0} = Rxx;
3157 // MPY - Multiply and use full result
3158 // Rdd = mpy[u](Rs,Rt)
3159 def M2_dpmpyss_s0 : T_XTYPE_mpy64 < "mpy", 0b000, 0b000, 0, 0, 0>;
3160 def M2_dpmpyuu_s0 : T_XTYPE_mpy64 < "mpyu", 0b010, 0b000, 0, 0, 0>;
3162 // Rxx[+-]= mpy[u](Rs,Rt)
3163 def M2_dpmpyss_acc_s0 : T_XTYPE_mpy64_acc < "mpy", "+", 0b000, 0b000, 0, 0, 0>;
3164 def M2_dpmpyss_nac_s0 : T_XTYPE_mpy64_acc < "mpy", "-", 0b001, 0b000, 0, 0, 0>;
3165 def M2_dpmpyuu_acc_s0 : T_XTYPE_mpy64_acc < "mpyu", "+", 0b010, 0b000, 0, 0, 0>;
3166 def M2_dpmpyuu_nac_s0 : T_XTYPE_mpy64_acc < "mpyu", "-", 0b011, 0b000, 0, 0, 0>;
3168 // Complex multiply real or imaginary
3169 // Rxx=cmpy[ir](Rs,Rt)
3170 def M2_cmpyi_s0 : T_XTYPE_mpy64 < "cmpyi", 0b000, 0b001, 0, 0, 0>;
3171 def M2_cmpyr_s0 : T_XTYPE_mpy64 < "cmpyr", 0b000, 0b010, 0, 0, 0>;
3173 // Rxx+=cmpy[ir](Rs,Rt)
3174 def M2_cmaci_s0 : T_XTYPE_mpy64_acc < "cmpyi", "+", 0b000, 0b001, 0, 0, 0>;
3175 def M2_cmacr_s0 : T_XTYPE_mpy64_acc < "cmpyr", "+", 0b000, 0b010, 0, 0, 0>;
3178 // Rdd=cmpy(Rs,Rt)[:<<]:sat
3179 def M2_cmpys_s0 : T_XTYPE_mpy64 < "cmpy", 0b000, 0b110, 1, 0, 0>;
3180 def M2_cmpys_s1 : T_XTYPE_mpy64 < "cmpy", 0b100, 0b110, 1, 1, 0>;
3182 // Rdd=cmpy(Rs,Rt*)[:<<]:sat
3183 def M2_cmpysc_s0 : T_XTYPE_mpy64 < "cmpy", 0b010, 0b110, 1, 0, 1>;
3184 def M2_cmpysc_s1 : T_XTYPE_mpy64 < "cmpy", 0b110, 0b110, 1, 1, 1>;
3186 // Rxx[-+]=cmpy(Rs,Rt)[:<<1]:sat
3187 def M2_cmacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b000, 0b110, 1, 0, 0>;
3188 def M2_cnacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b000, 0b111, 1, 0, 0>;
3189 def M2_cmacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b100, 0b110, 1, 1, 0>;
3190 def M2_cnacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b100, 0b111, 1, 1, 0>;
3192 // Rxx[-+]=cmpy(Rs,Rt*)[:<<1]:sat
3193 def M2_cmacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b010, 0b110, 1, 0, 1>;
3194 def M2_cnacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b010, 0b111, 1, 0, 1>;
3195 def M2_cmacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b110, 0b110, 1, 1, 1>;
3196 def M2_cnacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b110, 0b111, 1, 1, 1>;
3198 // Vector multiply halfwords
3199 // Rdd=vmpyh(Rs,Rt)[:<<]:sat
3200 //let Defs = [USR_OVF] in {
3201 def M2_vmpy2s_s1 : T_XTYPE_mpy64 < "vmpyh", 0b100, 0b101, 1, 1, 0>;
3202 def M2_vmpy2s_s0 : T_XTYPE_mpy64 < "vmpyh", 0b000, 0b101, 1, 0, 0>;
3205 // Rxx+=vmpyh(Rs,Rt)[:<<1][:sat]
3206 def M2_vmac2 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b001, 0b001, 0, 0, 0>;
3207 def M2_vmac2s_s1 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b100, 0b101, 1, 1, 0>;
3208 def M2_vmac2s_s0 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b000, 0b101, 1, 0, 0>;
3210 def: Pat<(i64 (mul (i64 (anyext (i32 IntRegs:$src1))),
3211 (i64 (anyext (i32 IntRegs:$src2))))),
3212 (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>;
3214 def: Pat<(i64 (mul (i64 (sext (i32 IntRegs:$src1))),
3215 (i64 (sext (i32 IntRegs:$src2))))),
3216 (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>;
3218 def: Pat<(i64 (mul (is_sext_i32:$src1),
3219 (is_sext_i32:$src2))),
3220 (M2_dpmpyss_s0 (LoReg DoubleRegs:$src1), (LoReg DoubleRegs:$src2))>;
3222 // Multiply and accumulate, use full result.
3223 // Rxx[+-]=mpy(Rs,Rt)
3225 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
3226 (mul (i64 (sext (i32 IntRegs:$src2))),
3227 (i64 (sext (i32 IntRegs:$src3)))))),
3228 (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3230 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
3231 (mul (i64 (sext (i32 IntRegs:$src2))),
3232 (i64 (sext (i32 IntRegs:$src3)))))),
3233 (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3235 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
3236 (mul (i64 (anyext (i32 IntRegs:$src2))),
3237 (i64 (anyext (i32 IntRegs:$src3)))))),
3238 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3240 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
3241 (mul (i64 (zext (i32 IntRegs:$src2))),
3242 (i64 (zext (i32 IntRegs:$src3)))))),
3243 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3245 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
3246 (mul (i64 (anyext (i32 IntRegs:$src2))),
3247 (i64 (anyext (i32 IntRegs:$src3)))))),
3248 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3250 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
3251 (mul (i64 (zext (i32 IntRegs:$src2))),
3252 (i64 (zext (i32 IntRegs:$src3)))))),
3253 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3255 //===----------------------------------------------------------------------===//
3257 //===----------------------------------------------------------------------===//
3259 //===----------------------------------------------------------------------===//
3261 //===----------------------------------------------------------------------===//
3262 //===----------------------------------------------------------------------===//
3264 //===----------------------------------------------------------------------===//
3266 //===----------------------------------------------------------------------===//
3268 //===----------------------------------------------------------------------===//
3269 //===----------------------------------------------------------------------===//
3271 //===----------------------------------------------------------------------===//
3273 //===----------------------------------------------------------------------===//
3275 //===----------------------------------------------------------------------===//
3276 //===----------------------------------------------------------------------===//
3278 //===----------------------------------------------------------------------===//
3280 //===----------------------------------------------------------------------===//
3282 //===----------------------------------------------------------------------===//
3284 // Store doubleword.
3285 //===----------------------------------------------------------------------===//
3286 // Template class for non-predicated post increment stores with immediate offset
3287 //===----------------------------------------------------------------------===//
3288 let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc in
3289 class T_store_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
3290 bits<4> MajOp, bit isHalf >
3291 : STInst <(outs IntRegs:$_dst_),
3292 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
3293 mnemonic#"($src1++#$offset) = $src2"#!if(isHalf, ".h", ""),
3294 [], "$src1 = $_dst_" >,
3301 string ImmOpStr = !cast<string>(ImmOp);
3302 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
3303 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
3304 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
3305 /* s4_0Imm */ offset{3-0})));
3306 let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
3308 let IClass = 0b1010;
3310 let Inst{27-25} = 0b101;
3311 let Inst{24-21} = MajOp;
3312 let Inst{20-16} = src1;
3314 let Inst{12-8} = src2;
3316 let Inst{6-3} = offsetBits;
3320 //===----------------------------------------------------------------------===//
3321 // Template class for predicated post increment stores with immediate offset
3322 //===----------------------------------------------------------------------===//
3323 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
3324 class T_pstore_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
3325 bits<4> MajOp, bit isHalf, bit isPredNot, bit isPredNew >
3326 : STInst <(outs IntRegs:$_dst_),
3327 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
3328 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3329 ") ")#mnemonic#"($src2++#$offset) = $src3"#!if(isHalf, ".h", ""),
3330 [], "$src2 = $_dst_" >,
3338 string ImmOpStr = !cast<string>(ImmOp);
3339 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
3340 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
3341 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
3342 /* s4_0Imm */ offset{3-0})));
3344 let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
3345 let isPredicatedNew = isPredNew;
3346 let isPredicatedFalse = isPredNot;
3348 let IClass = 0b1010;
3350 let Inst{27-25} = 0b101;
3351 let Inst{24-21} = MajOp;
3352 let Inst{20-16} = src2;
3354 let Inst{12-8} = src3;
3355 let Inst{7} = isPredNew;
3356 let Inst{6-3} = offsetBits;
3357 let Inst{2} = isPredNot;
3358 let Inst{1-0} = src1;
3361 multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
3362 Operand ImmOp, bits<4> MajOp, bit isHalf = 0 > {
3364 let BaseOpcode = "POST_"#BaseOp in {
3365 def S2_#NAME#_pi : T_store_pi <mnemonic, RC, ImmOp, MajOp, isHalf>;
3368 def S2_p#NAME#t_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 0, 0>;
3369 def S2_p#NAME#f_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 1, 0>;
3372 def S2_p#NAME#tnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp,
3374 def S2_p#NAME#fnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp,
3379 let accessSize = ByteAccess in
3380 defm storerb: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm, 0b1000>;
3382 let accessSize = HalfWordAccess in
3383 defm storerh: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm, 0b1010>;
3385 let accessSize = WordAccess in
3386 defm storeri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm, 0b1100>;
3388 let accessSize = DoubleWordAccess in
3389 defm storerd: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm, 0b1110>;
3391 let accessSize = HalfWordAccess, isNVStorable = 0 in
3392 defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>;
3394 class Storepi_pat<PatFrag Store, PatFrag Value, PatFrag Offset,
3396 : Pat<(Store Value:$src1, I32:$src2, Offset:$offset),
3397 (MI I32:$src2, imm:$offset, Value:$src1)>;
3399 def: Storepi_pat<post_truncsti8, I32, s4_0ImmPred, S2_storerb_pi>;
3400 def: Storepi_pat<post_truncsti16, I32, s4_1ImmPred, S2_storerh_pi>;
3401 def: Storepi_pat<post_store, I32, s4_2ImmPred, S2_storeri_pi>;
3402 def: Storepi_pat<post_store, I64, s4_3ImmPred, S2_storerd_pi>;
3404 //===----------------------------------------------------------------------===//
3405 // Template class for post increment stores with register offset.
3406 //===----------------------------------------------------------------------===//
3407 let isNVStorable = 1 in
3408 class T_store_pr <string mnemonic, RegisterClass RC, bits<3> MajOp,
3409 MemAccessSize AccessSz, bit isHalf = 0>
3410 : STInst <(outs IntRegs:$_dst_),
3411 (ins IntRegs:$src1, ModRegs:$src2, RC:$src3),
3412 mnemonic#"($src1++$src2) = $src3"#!if(isHalf, ".h", ""),
3413 [], "$src1 = $_dst_" > {
3417 let accessSize = AccessSz;
3419 let IClass = 0b1010;
3421 let Inst{27-24} = 0b1101;
3422 let Inst{23-21} = MajOp;
3423 let Inst{20-16} = src1;
3424 let Inst{13} = src2;
3425 let Inst{12-8} = src3;
3429 def S2_storerb_pr : T_store_pr<"memb", IntRegs, 0b000, ByteAccess>;
3430 def S2_storerh_pr : T_store_pr<"memh", IntRegs, 0b010, HalfWordAccess>;
3431 def S2_storeri_pr : T_store_pr<"memw", IntRegs, 0b100, WordAccess>;
3432 def S2_storerd_pr : T_store_pr<"memd", DoubleRegs, 0b110, DoubleWordAccess>;
3434 def S2_storerf_pr : T_store_pr<"memh", IntRegs, 0b011, HalfWordAccess, 1>;
3436 let opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
3437 class T_store_io <string mnemonic, RegisterClass RC, Operand ImmOp,
3438 bits<3>MajOp, bit isH = 0>
3440 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
3441 mnemonic#"($src1+#$src2) = $src3"#!if(isH,".h","")>,
3442 AddrModeRel, ImmRegRel {
3444 bits<14> src2; // Actual address offset
3446 bits<11> offsetBits; // Represents offset encoding
3448 string ImmOpStr = !cast<string>(ImmOp);
3450 let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14,
3451 !if (!eq(ImmOpStr, "s11_2Ext"), 13,
3452 !if (!eq(ImmOpStr, "s11_1Ext"), 12,
3453 /* s11_0Ext */ 11)));
3454 let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), src2{13-3},
3455 !if (!eq(ImmOpStr, "s11_2Ext"), src2{12-2},
3456 !if (!eq(ImmOpStr, "s11_1Ext"), src2{11-1},
3457 /* s11_0Ext */ src2{10-0})));
3458 let IClass = 0b1010;
3461 let Inst{26-25} = offsetBits{10-9};
3463 let Inst{23-21} = MajOp;
3464 let Inst{20-16} = src1;
3465 let Inst{13} = offsetBits{8};
3466 let Inst{12-8} = src3;
3467 let Inst{7-0} = offsetBits{7-0};
3470 let opExtendable = 2, isPredicated = 1 in
3471 class T_pstore_io <string mnemonic, RegisterClass RC, Operand ImmOp,
3472 bits<3>MajOp, bit PredNot, bit isPredNew, bit isH = 0>
3474 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
3475 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3476 ") ")#mnemonic#"($src2+#$src3) = $src4"#!if(isH,".h",""),
3477 [],"",V2LDST_tc_st_SLOT01 >,
3478 AddrModeRel, ImmRegRel {
3481 bits<9> src3; // Actual address offset
3483 bits<6> offsetBits; // Represents offset encoding
3485 let isPredicatedNew = isPredNew;
3486 let isPredicatedFalse = PredNot;
3488 string ImmOpStr = !cast<string>(ImmOp);
3489 let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9,
3490 !if (!eq(ImmOpStr, "u6_2Ext"), 8,
3491 !if (!eq(ImmOpStr, "u6_1Ext"), 7,
3493 let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), src3{8-3},
3494 !if (!eq(ImmOpStr, "u6_2Ext"), src3{7-2},
3495 !if (!eq(ImmOpStr, "u6_1Ext"), src3{6-1},
3496 /* u6_0Ext */ src3{5-0})));
3497 let IClass = 0b0100;
3500 let Inst{26} = PredNot;
3501 let Inst{25} = isPredNew;
3503 let Inst{23-21} = MajOp;
3504 let Inst{20-16} = src2;
3505 let Inst{13} = offsetBits{5};
3506 let Inst{12-8} = src4;
3507 let Inst{7-3} = offsetBits{4-0};
3508 let Inst{1-0} = src1;
3511 let isExtendable = 1, isNVStorable = 1, hasSideEffects = 0 in
3512 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
3513 Operand ImmOp, Operand predImmOp, bits<3> MajOp, bit isH = 0> {
3514 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
3515 def S2_#NAME#_io : T_store_io <mnemonic, RC, ImmOp, MajOp, isH>;
3518 def S2_p#NAME#t_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 0, 0, isH>;
3519 def S2_p#NAME#f_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 1, 0, isH>;
3522 def S4_p#NAME#tnew_io : T_pstore_io <mnemonic, RC, predImmOp,
3524 def S4_p#NAME#fnew_io : T_pstore_io <mnemonic, RC, predImmOp,
3529 let addrMode = BaseImmOffset, InputType = "imm" in {
3530 let accessSize = ByteAccess in
3531 defm storerb: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext, u6_0Ext, 0b000>;
3533 let accessSize = HalfWordAccess, opExtentAlign = 1 in
3534 defm storerh: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext, u6_1Ext, 0b010>;
3536 let accessSize = WordAccess, opExtentAlign = 2 in
3537 defm storeri: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext, u6_2Ext, 0b100>;
3539 let accessSize = DoubleWordAccess, isNVStorable = 0, opExtentAlign = 3 in
3540 defm storerd: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
3543 let accessSize = HalfWordAccess, opExtentAlign = 1 in
3544 defm storerf: ST_Idxd < "memh", "STrif", IntRegs, s11_1Ext,
3548 // Patterns for generating stores, where the address takes different forms:
3550 // - frameindex + offset,
3552 // - simple (base address without offset).
3553 // These would usually be used together (via Storex_pat defined below), but
3554 // in some cases one may want to apply different properties (such as
3555 // AddedComplexity) to the individual patterns.
3556 class Storex_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
3557 : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>;
3558 class Storex_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
3560 : Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)),
3561 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>;
3562 class Storex_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
3564 : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
3565 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
3566 class Storex_simple_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
3567 : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)),
3568 (MI IntRegs:$Rs, 0, Value:$Rt)>;
3570 // Patterns for generating stores, where the address takes different forms,
3571 // and where the value being stored is transformed through the value modifier
3572 // ValueMod. The address forms are same as above.
3573 class Storexm_fi_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod,
3575 : Pat<(Store Value:$Rs, AddrFI:$fi),
3576 (MI AddrFI:$fi, 0, (ValueMod Value:$Rs))>;
3577 class Storexm_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
3578 PatFrag ValueMod, InstHexagon MI>
3579 : Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)),
3580 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>;
3581 class Storexm_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
3582 PatFrag ValueMod, InstHexagon MI>
3583 : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
3584 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>;
3585 class Storexm_simple_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod,
3587 : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)),
3588 (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>;
3590 multiclass Storex_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
3592 def: Storex_fi_pat <Store, Value, MI>;
3593 def: Storex_fi_add_pat <Store, Value, ImmPred, MI>;
3594 def: Storex_add_pat <Store, Value, ImmPred, MI>;
3597 multiclass Storexm_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
3598 PatFrag ValueMod, InstHexagon MI> {
3599 def: Storexm_fi_pat <Store, Value, ValueMod, MI>;
3600 def: Storexm_fi_add_pat <Store, Value, ImmPred, ValueMod, MI>;
3601 def: Storexm_add_pat <Store, Value, ImmPred, ValueMod, MI>;
3604 // Regular stores in the DAG have two operands: value and address.
3605 // Atomic stores also have two, but they are reversed: address, value.
3606 // To use atomic stores with the patterns, they need to have their operands
3607 // swapped. This relies on the knowledge that the F.Fragment uses names
3609 class SwapSt<PatFrag F>
3610 : PatFrag<(ops node:$val, node:$ptr), F.Fragment>;
3612 let AddedComplexity = 20 in {
3613 defm: Storex_pat<truncstorei8, I32, s32_0ImmPred, S2_storerb_io>;
3614 defm: Storex_pat<truncstorei16, I32, s31_1ImmPred, S2_storerh_io>;
3615 defm: Storex_pat<store, I32, s30_2ImmPred, S2_storeri_io>;
3616 defm: Storex_pat<store, I64, s29_3ImmPred, S2_storerd_io>;
3618 defm: Storex_pat<SwapSt<atomic_store_8>, I32, s32_0ImmPred, S2_storerb_io>;
3619 defm: Storex_pat<SwapSt<atomic_store_16>, I32, s31_1ImmPred, S2_storerh_io>;
3620 defm: Storex_pat<SwapSt<atomic_store_32>, I32, s30_2ImmPred, S2_storeri_io>;
3621 defm: Storex_pat<SwapSt<atomic_store_64>, I64, s29_3ImmPred, S2_storerd_io>;
3624 // Simple patterns should be tried with the least priority.
3625 def: Storex_simple_pat<truncstorei8, I32, S2_storerb_io>;
3626 def: Storex_simple_pat<truncstorei16, I32, S2_storerh_io>;
3627 def: Storex_simple_pat<store, I32, S2_storeri_io>;
3628 def: Storex_simple_pat<store, I64, S2_storerd_io>;
3630 def: Storex_simple_pat<SwapSt<atomic_store_8>, I32, S2_storerb_io>;
3631 def: Storex_simple_pat<SwapSt<atomic_store_16>, I32, S2_storerh_io>;
3632 def: Storex_simple_pat<SwapSt<atomic_store_32>, I32, S2_storeri_io>;
3633 def: Storex_simple_pat<SwapSt<atomic_store_64>, I64, S2_storerd_io>;
3635 let AddedComplexity = 20 in {
3636 defm: Storexm_pat<truncstorei8, I64, s32_0ImmPred, LoReg, S2_storerb_io>;
3637 defm: Storexm_pat<truncstorei16, I64, s31_1ImmPred, LoReg, S2_storerh_io>;
3638 defm: Storexm_pat<truncstorei32, I64, s30_2ImmPred, LoReg, S2_storeri_io>;
3641 def: Storexm_simple_pat<truncstorei8, I64, LoReg, S2_storerb_io>;
3642 def: Storexm_simple_pat<truncstorei16, I64, LoReg, S2_storerh_io>;
3643 def: Storexm_simple_pat<truncstorei32, I64, LoReg, S2_storeri_io>;
3646 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
3647 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
3648 def STriw_pred : STInst<(outs),
3649 (ins IntRegs:$addr, s11_2Ext:$off, PredRegs:$src1),
3650 ".error \"should not emit\"", []>;
3652 // S2_allocframe: Allocate stack frame.
3653 let Defs = [R29, R30], Uses = [R29, R31, R30],
3654 hasSideEffects = 0, accessSize = DoubleWordAccess in
3655 def S2_allocframe: ST0Inst <
3656 (outs), (ins u11_3Imm:$u11_3),
3657 "allocframe(#$u11_3)" > {
3660 let IClass = 0b1010;
3661 let Inst{27-16} = 0b000010011101;
3662 let Inst{13-11} = 0b000;
3663 let Inst{10-0} = u11_3{13-3};
3666 // S2_storer[bhwdf]_pci: Store byte/half/word/double.
3667 // S2_storer[bhwdf]_pci -> S2_storerbnew_pci
3668 let Uses = [CS], isNVStorable = 1 in
3669 class T_store_pci <string mnemonic, RegisterClass RC,
3670 Operand Imm, bits<4>MajOp,
3671 MemAccessSize AlignSize, string RegSrc = "Rt">
3672 : STInst <(outs IntRegs:$_dst_),
3673 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, RC:$Rt),
3674 #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $"#RegSrc#"",
3681 let accessSize = AlignSize;
3683 let IClass = 0b1010;
3684 let Inst{27-25} = 0b100;
3685 let Inst{24-21} = MajOp;
3686 let Inst{20-16} = Rz;
3688 let Inst{12-8} = Rt;
3691 !if (!eq(!cast<string>(AlignSize), "DoubleWordAccess"), offset{6-3},
3692 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
3693 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
3694 /* ByteAccess */ offset{3-0})));
3698 def S2_storerb_pci : T_store_pci<"memb", IntRegs, s4_0Imm, 0b1000,
3700 def S2_storerh_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1010,
3702 def S2_storerf_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1011,
3703 HalfWordAccess, "Rt.h">;
3704 def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100,
3706 def S2_storerd_pci : T_store_pci<"memd", DoubleRegs, s4_3Imm, 0b1110,
3709 let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 4 in
3710 class T_storenew_pci <string mnemonic, Operand Imm,
3711 bits<2>MajOp, MemAccessSize AlignSize>
3712 : NVInst < (outs IntRegs:$_dst_),
3713 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, IntRegs:$Nt),
3714 #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $Nt.new",
3722 let accessSize = AlignSize;
3724 let IClass = 0b1010;
3725 let Inst{27-21} = 0b1001101;
3726 let Inst{20-16} = Rz;
3728 let Inst{12-11} = MajOp;
3729 let Inst{10-8} = Nt;
3732 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
3733 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
3734 /* ByteAccess */ offset{3-0}));
3738 def S2_storerbnew_pci : T_storenew_pci <"memb", s4_0Imm, 0b00, ByteAccess>;
3739 def S2_storerhnew_pci : T_storenew_pci <"memh", s4_1Imm, 0b01, HalfWordAccess>;
3740 def S2_storerinew_pci : T_storenew_pci <"memw", s4_2Imm, 0b10, WordAccess>;
3742 //===----------------------------------------------------------------------===//
3743 // Circular stores - Pseudo
3745 // Please note that the input operand order in the pseudo instructions
3746 // doesn't match with the real instructions. Pseudo instructions operand
3747 // order should mimics the ordering in the intrinsics.
3748 //===----------------------------------------------------------------------===//
3749 let isCodeGenOnly = 1, mayStore = 1, hasSideEffects = 0, isPseudo = 1 in
3750 class T_store_pci_pseudo <string opc, RegisterClass RC>
3751 : STInstPI<(outs IntRegs:$_dst_),
3752 (ins IntRegs:$src1, RC:$src2, IntRegs:$src3, s4Imm:$src4),
3753 ".error \""#opc#"($src1++#$src4:circ($src3)) = $src2\"",
3754 [], "$_dst_ = $src1">;
3756 def S2_storerb_pci_pseudo : T_store_pci_pseudo <"memb", IntRegs>;
3757 def S2_storerh_pci_pseudo : T_store_pci_pseudo <"memh", IntRegs>;
3758 def S2_storerf_pci_pseudo : T_store_pci_pseudo <"memh", IntRegs>;
3759 def S2_storeri_pci_pseudo : T_store_pci_pseudo <"memw", IntRegs>;
3760 def S2_storerd_pci_pseudo : T_store_pci_pseudo <"memd", DoubleRegs>;
3762 //===----------------------------------------------------------------------===//
3763 // Circular stores with auto-increment register
3764 //===----------------------------------------------------------------------===//
3765 let Uses = [CS], isNVStorable = 1 in
3766 class T_store_pcr <string mnemonic, RegisterClass RC, bits<4>MajOp,
3767 MemAccessSize AlignSize, string RegSrc = "Rt">
3768 : STInst <(outs IntRegs:$_dst_),
3769 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$Rt),
3770 #mnemonic#"($Rz ++ I:circ($Mu)) = $"#RegSrc#"",
3777 let accessSize = AlignSize;
3779 let IClass = 0b1010;
3780 let Inst{27-25} = 0b100;
3781 let Inst{24-21} = MajOp;
3782 let Inst{20-16} = Rz;
3784 let Inst{12-8} = Rt;
3789 def S2_storerb_pcr : T_store_pcr<"memb", IntRegs, 0b1000, ByteAccess>;
3790 def S2_storerh_pcr : T_store_pcr<"memh", IntRegs, 0b1010, HalfWordAccess>;
3791 def S2_storeri_pcr : T_store_pcr<"memw", IntRegs, 0b1100, WordAccess>;
3792 def S2_storerd_pcr : T_store_pcr<"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
3793 def S2_storerf_pcr : T_store_pcr<"memh", IntRegs, 0b1011,
3794 HalfWordAccess, "Rt.h">;
3796 //===----------------------------------------------------------------------===//
3797 // Circular .new stores with auto-increment register
3798 //===----------------------------------------------------------------------===//
3799 let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
3800 class T_storenew_pcr <string mnemonic, bits<2>MajOp,
3801 MemAccessSize AlignSize>
3802 : NVInst <(outs IntRegs:$_dst_),
3803 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3804 #mnemonic#"($Rz ++ I:circ($Mu)) = $Nt.new" ,
3811 let accessSize = AlignSize;
3813 let IClass = 0b1010;
3814 let Inst{27-21} = 0b1001101;
3815 let Inst{20-16} = Rz;
3817 let Inst{12-11} = MajOp;
3818 let Inst{10-8} = Nt;
3823 def S2_storerbnew_pcr : T_storenew_pcr <"memb", 0b00, ByteAccess>;
3824 def S2_storerhnew_pcr : T_storenew_pcr <"memh", 0b01, HalfWordAccess>;
3825 def S2_storerinew_pcr : T_storenew_pcr <"memw", 0b10, WordAccess>;
3827 //===----------------------------------------------------------------------===//
3828 // Bit-reversed stores with auto-increment register
3829 //===----------------------------------------------------------------------===//
3830 let hasSideEffects = 0 in
3831 class T_store_pbr<string mnemonic, RegisterClass RC,
3832 MemAccessSize addrSize, bits<3> majOp,
3835 <(outs IntRegs:$_dst_),
3836 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$src),
3837 #mnemonic#"($Rz ++ $Mu:brev) = $src"#!if (!eq(isHalf, 1), ".h", ""),
3838 [], "$Rz = $_dst_" > {
3840 let accessSize = addrSize;
3846 let IClass = 0b1010;
3848 let Inst{27-24} = 0b1111;
3849 let Inst{23-21} = majOp;
3851 let Inst{20-16} = Rz;
3853 let Inst{12-8} = src;
3856 let isNVStorable = 1 in {
3857 let BaseOpcode = "S2_storerb_pbr" in
3858 def S2_storerb_pbr : T_store_pbr<"memb", IntRegs, ByteAccess,
3859 0b000>, NewValueRel;
3860 let BaseOpcode = "S2_storerh_pbr" in
3861 def S2_storerh_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess,
3862 0b010>, NewValueRel;
3863 let BaseOpcode = "S2_storeri_pbr" in
3864 def S2_storeri_pbr : T_store_pbr<"memw", IntRegs, WordAccess,
3865 0b100>, NewValueRel;
3868 def S2_storerf_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess, 0b011, 1>;
3869 def S2_storerd_pbr : T_store_pbr<"memd", DoubleRegs, DoubleWordAccess, 0b110>;
3871 //===----------------------------------------------------------------------===//
3872 // Bit-reversed .new stores with auto-increment register
3873 //===----------------------------------------------------------------------===//
3874 let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3,
3875 hasSideEffects = 0 in
3876 class T_storenew_pbr<string mnemonic, MemAccessSize addrSize, bits<2> majOp>
3877 : NVInst <(outs IntRegs:$_dst_),
3878 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3879 #mnemonic#"($Rz ++ $Mu:brev) = $Nt.new", [],
3880 "$Rz = $_dst_">, NewValueRel {
3881 let accessSize = addrSize;
3886 let IClass = 0b1010;
3888 let Inst{27-21} = 0b1111101;
3889 let Inst{12-11} = majOp;
3891 let Inst{20-16} = Rz;
3893 let Inst{10-8} = Nt;
3896 let BaseOpcode = "S2_storerb_pbr" in
3897 def S2_storerbnew_pbr : T_storenew_pbr<"memb", ByteAccess, 0b00>;
3899 let BaseOpcode = "S2_storerh_pbr" in
3900 def S2_storerhnew_pbr : T_storenew_pbr<"memh", HalfWordAccess, 0b01>;
3902 let BaseOpcode = "S2_storeri_pbr" in
3903 def S2_storerinew_pbr : T_storenew_pbr<"memw", WordAccess, 0b10>;
3905 //===----------------------------------------------------------------------===//
3906 // Bit-reversed stores - Pseudo
3908 // Please note that the input operand order in the pseudo instructions
3909 // doesn't match with the real instructions. Pseudo instructions operand
3910 // order should mimics the ordering in the intrinsics.
3911 //===----------------------------------------------------------------------===//
3912 let isCodeGenOnly = 1, mayStore = 1, hasSideEffects = 0, isPseudo = 1 in
3913 class T_store_pbr_pseudo <string opc, RegisterClass RC>
3914 : STInstPI<(outs IntRegs:$_dst_),
3915 (ins IntRegs:$src1, RC:$src2, IntRegs:$src3),
3916 ".error \""#opc#"($src1++$src3:brev) = $src2\"",
3917 [], "$_dst_ = $src1">;
3919 def S2_storerb_pbr_pseudo : T_store_pbr_pseudo <"memb", IntRegs>;
3920 def S2_storerh_pbr_pseudo : T_store_pbr_pseudo <"memh", IntRegs>;
3921 def S2_storeri_pbr_pseudo : T_store_pbr_pseudo <"memw", IntRegs>;
3922 def S2_storerf_pbr_pseudo : T_store_pbr_pseudo <"memh", IntRegs>;
3923 def S2_storerd_pbr_pseudo : T_store_pbr_pseudo <"memd", DoubleRegs>;
3925 //===----------------------------------------------------------------------===//
3927 //===----------------------------------------------------------------------===//
3929 //===----------------------------------------------------------------------===//
3930 // Template class for S_2op instructions.
3931 //===----------------------------------------------------------------------===//
3932 let hasSideEffects = 0 in
3933 class T_S2op_1 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
3934 RegisterClass RCIn, bits<2> MajOp, bits<3> MinOp, bit isSat>
3935 : SInst <(outs RCOut:$dst), (ins RCIn:$src),
3936 "$dst = "#mnemonic#"($src)"#!if(isSat, ":sat", ""),
3937 [], "", S_2op_tc_1_SLOT23 > {
3941 let IClass = 0b1000;
3943 let Inst{27-24} = RegTyBits;
3944 let Inst{23-22} = MajOp;
3946 let Inst{20-16} = src;
3947 let Inst{7-5} = MinOp;
3948 let Inst{4-0} = dst;
3951 class T_S2op_1_di <string mnemonic, bits<2> MajOp, bits<3> MinOp>
3952 : T_S2op_1 <mnemonic, 0b0100, DoubleRegs, IntRegs, MajOp, MinOp, 0>;
3954 let hasNewValue = 1 in
3955 class T_S2op_1_id <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
3956 : T_S2op_1 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, isSat>;
3958 let hasNewValue = 1 in
3959 class T_S2op_1_ii <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
3960 : T_S2op_1 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, isSat>;
3962 // Vector sign/zero extend
3963 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
3964 def S2_vsxtbh : T_S2op_1_di <"vsxtbh", 0b00, 0b000>;
3965 def S2_vsxthw : T_S2op_1_di <"vsxthw", 0b00, 0b100>;
3966 def S2_vzxtbh : T_S2op_1_di <"vzxtbh", 0b00, 0b010>;
3967 def S2_vzxthw : T_S2op_1_di <"vzxthw", 0b00, 0b110>;
3970 // Vector splat bytes/halfwords
3971 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
3972 def S2_vsplatrb : T_S2op_1_ii <"vsplatb", 0b01, 0b111>;
3973 def S2_vsplatrh : T_S2op_1_di <"vsplath", 0b01, 0b010>;
3976 // Sign extend word to doubleword
3977 def A2_sxtw : T_S2op_1_di <"sxtw", 0b01, 0b000>;
3979 def: Pat <(i64 (sext I32:$src)), (A2_sxtw I32:$src)>;
3981 // Vector saturate and pack
3982 let Defs = [USR_OVF] in {
3983 def S2_svsathb : T_S2op_1_ii <"vsathb", 0b10, 0b000>;
3984 def S2_svsathub : T_S2op_1_ii <"vsathub", 0b10, 0b010>;
3985 def S2_vsathb : T_S2op_1_id <"vsathb", 0b00, 0b110>;
3986 def S2_vsathub : T_S2op_1_id <"vsathub", 0b00, 0b000>;
3987 def S2_vsatwh : T_S2op_1_id <"vsatwh", 0b00, 0b010>;
3988 def S2_vsatwuh : T_S2op_1_id <"vsatwuh", 0b00, 0b100>;
3992 def S2_vtrunohb : T_S2op_1_id <"vtrunohb", 0b10, 0b000>;
3993 def S2_vtrunehb : T_S2op_1_id <"vtrunehb", 0b10, 0b010>;
3995 // Swizzle the bytes of a word
3996 def A2_swiz : T_S2op_1_ii <"swiz", 0b10, 0b111>;
3999 let Defs = [USR_OVF] in {
4000 def A2_sat : T_S2op_1_id <"sat", 0b11, 0b000>;
4001 def A2_satb : T_S2op_1_ii <"satb", 0b11, 0b111>;
4002 def A2_satub : T_S2op_1_ii <"satub", 0b11, 0b110>;
4003 def A2_sath : T_S2op_1_ii <"sath", 0b11, 0b100>;
4004 def A2_satuh : T_S2op_1_ii <"satuh", 0b11, 0b101>;
4005 def A2_roundsat : T_S2op_1_id <"round", 0b11, 0b001, 0b1>;
4008 let Itinerary = S_2op_tc_2_SLOT23 in {
4009 // Vector round and pack
4010 def S2_vrndpackwh : T_S2op_1_id <"vrndwh", 0b10, 0b100>;
4012 let Defs = [USR_OVF] in
4013 def S2_vrndpackwhs : T_S2op_1_id <"vrndwh", 0b10, 0b110, 1>;
4016 def S2_brev : T_S2op_1_ii <"brev", 0b01, 0b110>;
4018 // Absolute value word
4019 def A2_abs : T_S2op_1_ii <"abs", 0b10, 0b100>;
4021 let Defs = [USR_OVF] in
4022 def A2_abssat : T_S2op_1_ii <"abs", 0b10, 0b101, 1>;
4024 // Negate with saturation
4025 let Defs = [USR_OVF] in
4026 def A2_negsat : T_S2op_1_ii <"neg", 0b10, 0b110, 1>;
4029 def: Pat<(i32 (select (i1 (setlt (i32 IntRegs:$src), 0)),
4030 (i32 (sub 0, (i32 IntRegs:$src))),
4031 (i32 IntRegs:$src))),
4032 (A2_abs IntRegs:$src)>;
4034 let AddedComplexity = 50 in
4035 def: Pat<(i32 (xor (add (sra (i32 IntRegs:$src), (i32 31)),
4036 (i32 IntRegs:$src)),
4037 (sra (i32 IntRegs:$src), (i32 31)))),
4038 (A2_abs IntRegs:$src)>;
4040 class T_S2op_2 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
4041 RegisterClass RCIn, bits<3> MajOp, bits<3> MinOp,
4042 bit isSat, bit isRnd, list<dag> pattern = []>
4043 : SInst <(outs RCOut:$dst),
4044 (ins RCIn:$src, u5Imm:$u5),
4045 "$dst = "#mnemonic#"($src, #$u5)"#!if(isSat, ":sat", "")
4046 #!if(isRnd, ":rnd", ""),
4047 pattern, "", S_2op_tc_2_SLOT23> {
4052 let IClass = 0b1000;
4054 let Inst{27-24} = RegTyBits;
4055 let Inst{23-21} = MajOp;
4056 let Inst{20-16} = src;
4058 let Inst{12-8} = u5;
4059 let Inst{7-5} = MinOp;
4060 let Inst{4-0} = dst;
4063 class T_S2op_2_di <string mnemonic, bits<3> MajOp, bits<3> MinOp>
4064 : T_S2op_2 <mnemonic, 0b1000, DoubleRegs, IntRegs, MajOp, MinOp, 0, 0>;
4066 let hasNewValue = 1 in
4067 class T_S2op_2_id <string mnemonic, bits<3> MajOp, bits<3> MinOp>
4068 : T_S2op_2 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, 0, 0>;
4070 let hasNewValue = 1 in
4071 class T_S2op_2_ii <string mnemonic, bits<3> MajOp, bits<3> MinOp,
4072 bit isSat = 0, bit isRnd = 0, list<dag> pattern = []>
4073 : T_S2op_2 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp,
4074 isSat, isRnd, pattern>;
4076 class T_S2op_shift <string mnemonic, bits<3> MajOp, bits<3> MinOp, SDNode OpNd>
4077 : T_S2op_2_ii <mnemonic, MajOp, MinOp, 0, 0,
4078 [(set (i32 IntRegs:$dst), (OpNd (i32 IntRegs:$src),
4079 (u5ImmPred:$u5)))]>;
4081 // Vector arithmetic shift right by immediate with truncate and pack
4082 def S2_asr_i_svw_trun : T_S2op_2_id <"vasrw", 0b110, 0b010>;
4084 // Arithmetic/logical shift right/left by immediate
4085 let Itinerary = S_2op_tc_1_SLOT23 in {
4086 def S2_asr_i_r : T_S2op_shift <"asr", 0b000, 0b000, sra>;
4087 def S2_lsr_i_r : T_S2op_shift <"lsr", 0b000, 0b001, srl>;
4088 def S2_asl_i_r : T_S2op_shift <"asl", 0b000, 0b010, shl>;
4091 // Shift left by immediate with saturation
4092 let Defs = [USR_OVF] in
4093 def S2_asl_i_r_sat : T_S2op_2_ii <"asl", 0b010, 0b010, 1>;
4095 // Shift right with round
4096 def S2_asr_i_r_rnd : T_S2op_2_ii <"asr", 0b010, 0b000, 0, 1>;
4098 let isAsmParserOnly = 1 in
4099 def S2_asr_i_r_rnd_goodsyntax
4100 : SInst <(outs IntRegs:$dst), (ins IntRegs:$src, u5Imm:$u5),
4101 "$dst = asrrnd($src, #$u5)",
4102 [], "", S_2op_tc_1_SLOT23>;
4104 let isAsmParserOnly = 1 in
4105 def A2_not: ALU32_rr<(outs IntRegs:$dst),(ins IntRegs:$src),
4106 "$dst = not($src)">;
4108 def: Pat<(i32 (sra (i32 (add (i32 (sra I32:$src1, u5ImmPred:$src2)),
4111 (S2_asr_i_r_rnd IntRegs:$src1, u5ImmPred:$src2)>;
4113 class T_S2op_3<string opc, bits<2>MajOp, bits<3>minOp, bits<1> sat = 0>
4114 : SInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
4115 "$Rdd = "#opc#"($Rss)"#!if(!eq(sat, 1),":sat","")> {
4118 let IClass = 0b1000;
4119 let Inst{27-24} = 0;
4120 let Inst{23-22} = MajOp;
4121 let Inst{20-16} = Rss;
4122 let Inst{7-5} = minOp;
4123 let Inst{4-0} = Rdd;
4126 def A2_absp : T_S2op_3 <"abs", 0b10, 0b110>;
4127 def A2_negp : T_S2op_3 <"neg", 0b10, 0b101>;
4128 def A2_notp : T_S2op_3 <"not", 0b10, 0b100>;
4130 // Innterleave/deinterleave
4131 def S2_interleave : T_S2op_3 <"interleave", 0b11, 0b101>;
4132 def S2_deinterleave : T_S2op_3 <"deinterleave", 0b11, 0b100>;
4134 // Vector Complex conjugate
4135 def A2_vconj : T_S2op_3 <"vconj", 0b10, 0b111, 1>;
4137 // Vector saturate without pack
4138 def S2_vsathb_nopack : T_S2op_3 <"vsathb", 0b00, 0b111>;
4139 def S2_vsathub_nopack : T_S2op_3 <"vsathub", 0b00, 0b100>;
4140 def S2_vsatwh_nopack : T_S2op_3 <"vsatwh", 0b00, 0b110>;
4141 def S2_vsatwuh_nopack : T_S2op_3 <"vsatwuh", 0b00, 0b101>;
4143 // Vector absolute value halfwords with and without saturation
4144 // Rdd64=vabsh(Rss64)[:sat]
4145 def A2_vabsh : T_S2op_3 <"vabsh", 0b01, 0b100>;
4146 def A2_vabshsat : T_S2op_3 <"vabsh", 0b01, 0b101, 1>;
4148 // Vector absolute value words with and without saturation
4149 def A2_vabsw : T_S2op_3 <"vabsw", 0b01, 0b110>;
4150 def A2_vabswsat : T_S2op_3 <"vabsw", 0b01, 0b111, 1>;
4152 def : Pat<(not (i64 DoubleRegs:$src1)),
4153 (A2_notp DoubleRegs:$src1)>;
4155 //===----------------------------------------------------------------------===//
4157 //===----------------------------------------------------------------------===//
4160 let hasSideEffects = 0, hasNewValue = 1 in
4161 class T_COUNT_LEADING<string MnOp, bits<3> MajOp, bits<3> MinOp, bit Is32,
4163 : SInst<Out, Inp, "$Rd = "#MnOp#"($Rs)", [], "", S_2op_tc_1_SLOT23> {
4166 let IClass = 0b1000;
4168 let Inst{26} = Is32;
4169 let Inst{25-24} = 0b00;
4170 let Inst{23-21} = MajOp;
4171 let Inst{20-16} = Rs;
4172 let Inst{7-5} = MinOp;
4176 class T_COUNT_LEADING_32<string MnOp, bits<3> MajOp, bits<3> MinOp>
4177 : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b1,
4178 (outs IntRegs:$Rd), (ins IntRegs:$Rs)>;
4180 class T_COUNT_LEADING_64<string MnOp, bits<3> MajOp, bits<3> MinOp>
4181 : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b0,
4182 (outs IntRegs:$Rd), (ins DoubleRegs:$Rs)>;
4184 def S2_cl0 : T_COUNT_LEADING_32<"cl0", 0b000, 0b101>;
4185 def S2_cl1 : T_COUNT_LEADING_32<"cl1", 0b000, 0b110>;
4186 def S2_ct0 : T_COUNT_LEADING_32<"ct0", 0b010, 0b100>;
4187 def S2_ct1 : T_COUNT_LEADING_32<"ct1", 0b010, 0b101>;
4188 def S2_cl0p : T_COUNT_LEADING_64<"cl0", 0b010, 0b010>;
4189 def S2_cl1p : T_COUNT_LEADING_64<"cl1", 0b010, 0b100>;
4190 def S2_clb : T_COUNT_LEADING_32<"clb", 0b000, 0b100>;
4191 def S2_clbp : T_COUNT_LEADING_64<"clb", 0b010, 0b000>;
4192 def S2_clbnorm : T_COUNT_LEADING_32<"normamt", 0b000, 0b111>;
4194 def: Pat<(i32 (ctlz I32:$Rs)), (S2_cl0 I32:$Rs)>;
4195 def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>;
4196 def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>;
4197 def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>;
4198 def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>;
4199 def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>;
4201 // Bit set/clear/toggle
4203 let hasSideEffects = 0, hasNewValue = 1 in
4204 class T_SCT_BIT_IMM<string MnOp, bits<3> MinOp>
4205 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u5Imm:$u5),
4206 "$Rd = "#MnOp#"($Rs, #$u5)", [], "", S_2op_tc_1_SLOT23> {
4210 let IClass = 0b1000;
4211 let Inst{27-21} = 0b1100110;
4212 let Inst{20-16} = Rs;
4214 let Inst{12-8} = u5;
4215 let Inst{7-5} = MinOp;
4219 let hasSideEffects = 0, hasNewValue = 1 in
4220 class T_SCT_BIT_REG<string MnOp, bits<2> MinOp>
4221 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
4222 "$Rd = "#MnOp#"($Rs, $Rt)", [], "", S_3op_tc_1_SLOT23> {
4226 let IClass = 0b1100;
4227 let Inst{27-22} = 0b011010;
4228 let Inst{20-16} = Rs;
4229 let Inst{12-8} = Rt;
4230 let Inst{7-6} = MinOp;
4234 def S2_clrbit_i : T_SCT_BIT_IMM<"clrbit", 0b001>;
4235 def S2_setbit_i : T_SCT_BIT_IMM<"setbit", 0b000>;
4236 def S2_togglebit_i : T_SCT_BIT_IMM<"togglebit", 0b010>;
4237 def S2_clrbit_r : T_SCT_BIT_REG<"clrbit", 0b01>;
4238 def S2_setbit_r : T_SCT_BIT_REG<"setbit", 0b00>;
4239 def S2_togglebit_r : T_SCT_BIT_REG<"togglebit", 0b10>;
4241 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, u5ImmPred:$u5)))),
4242 (S2_clrbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4243 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
4244 (S2_setbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4245 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
4246 (S2_togglebit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4247 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, (i32 IntRegs:$Rt))))),
4248 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4249 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
4250 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4251 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
4252 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>;
4256 let hasSideEffects = 0 in
4257 class T_TEST_BIT_IMM<string MnOp, bits<3> MajOp>
4258 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5Imm:$u5),
4259 "$Pd = "#MnOp#"($Rs, #$u5)",
4260 [], "", S_2op_tc_2early_SLOT23> {
4264 let IClass = 0b1000;
4265 let Inst{27-24} = 0b0101;
4266 let Inst{23-21} = MajOp;
4267 let Inst{20-16} = Rs;
4269 let Inst{12-8} = u5;
4273 let hasSideEffects = 0 in
4274 class T_TEST_BIT_REG<string MnOp, bit IsNeg>
4275 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
4276 "$Pd = "#MnOp#"($Rs, $Rt)",
4277 [], "", S_3op_tc_2early_SLOT23> {
4281 let IClass = 0b1100;
4282 let Inst{27-22} = 0b011100;
4283 let Inst{21} = IsNeg;
4284 let Inst{20-16} = Rs;
4285 let Inst{12-8} = Rt;
4289 def S2_tstbit_i : T_TEST_BIT_IMM<"tstbit", 0b000>;
4290 def S2_tstbit_r : T_TEST_BIT_REG<"tstbit", 0>;
4292 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
4293 def: Pat<(i1 (setne (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
4294 (S2_tstbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4295 def: Pat<(i1 (setne (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
4296 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4297 def: Pat<(i1 (trunc (i32 IntRegs:$Rs))),
4298 (S2_tstbit_i IntRegs:$Rs, 0)>;
4299 def: Pat<(i1 (trunc (i64 DoubleRegs:$Rs))),
4300 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>;
4303 let hasSideEffects = 0 in
4304 class T_TEST_BITS_IMM<string MnOp, bits<2> MajOp, bit IsNeg>
4305 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u6Imm:$u6),
4306 "$Pd = "#MnOp#"($Rs, #$u6)",
4307 [], "", S_2op_tc_2early_SLOT23> {
4311 let IClass = 0b1000;
4312 let Inst{27-24} = 0b0101;
4313 let Inst{23-22} = MajOp;
4314 let Inst{21} = IsNeg;
4315 let Inst{20-16} = Rs;
4316 let Inst{13-8} = u6;
4320 let hasSideEffects = 0 in
4321 class T_TEST_BITS_REG<string MnOp, bits<2> MajOp, bit IsNeg>
4322 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
4323 "$Pd = "#MnOp#"($Rs, $Rt)",
4324 [], "", S_3op_tc_2early_SLOT23> {
4328 let IClass = 0b1100;
4329 let Inst{27-24} = 0b0111;
4330 let Inst{23-22} = MajOp;
4331 let Inst{21} = IsNeg;
4332 let Inst{20-16} = Rs;
4333 let Inst{12-8} = Rt;
4337 def C2_bitsclri : T_TEST_BITS_IMM<"bitsclr", 0b10, 0>;
4338 def C2_bitsclr : T_TEST_BITS_REG<"bitsclr", 0b10, 0>;
4339 def C2_bitsset : T_TEST_BITS_REG<"bitsset", 0b01, 0>;
4341 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm.
4342 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), u6ImmPred:$u6), 0)),
4343 (C2_bitsclri IntRegs:$Rs, u6ImmPred:$u6)>;
4344 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), 0)),
4345 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>;
4348 let AddedComplexity = 10 in // Complexity greater than compare reg-reg.
4349 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), IntRegs:$Rt)),
4350 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>;
4352 //===----------------------------------------------------------------------===//
4354 //===----------------------------------------------------------------------===//
4356 //===----------------------------------------------------------------------===//
4358 //===----------------------------------------------------------------------===//
4359 //===----------------------------------------------------------------------===//
4361 //===----------------------------------------------------------------------===//
4363 //===----------------------------------------------------------------------===//
4365 //===----------------------------------------------------------------------===//
4367 def: Pat<(or (or (shl (or (shl (i32 (extloadi8 (add (i32 IntRegs:$b), 3))),
4369 (i32 (zextloadi8 (add (i32 IntRegs:$b), 2)))),
4371 (shl (i32 (zextloadi8 (add (i32 IntRegs:$b), 1))), (i32 8))),
4372 (zextloadi8 (i32 IntRegs:$b))),
4373 (A2_swiz (L2_loadri_io IntRegs:$b, 0))>;
4375 //===----------------------------------------------------------------------===//
4377 //===----------------------------------------------------------------------===//
4379 //===----------------------------------------------------------------------===//
4381 //===----------------------------------------------------------------------===//
4383 // Predicate transfer.
4384 let hasSideEffects = 0, hasNewValue = 1 in
4385 def C2_tfrpr : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps),
4386 "$Rd = $Ps", [], "", S_2op_tc_1_SLOT23> {
4390 let IClass = 0b1000;
4391 let Inst{27-24} = 0b1001;
4393 let Inst{17-16} = Ps;
4397 // Transfer general register to predicate.
4398 let hasSideEffects = 0 in
4399 def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs),
4400 "$Pd = $Rs", [], "", S_2op_tc_2early_SLOT23> {
4404 let IClass = 0b1000;
4405 let Inst{27-21} = 0b0101010;
4406 let Inst{20-16} = Rs;
4410 let hasSideEffects = 0, isCodeGenOnly = 1 in
4411 def C2_pxfer_map: SInst<(outs PredRegs:$dst), (ins PredRegs:$src),
4415 // Patterns for loads of i1:
4416 def: Pat<(i1 (load AddrFI:$fi)),
4417 (C2_tfrrp (L2_loadrub_io AddrFI:$fi, 0))>;
4418 def: Pat<(i1 (load (add (i32 IntRegs:$Rs), s32ImmPred:$Off))),
4419 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>;
4420 def: Pat<(i1 (load (i32 IntRegs:$Rs))),
4421 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>;
4423 def I1toI32: OutPatFrag<(ops node:$Rs),
4424 (C2_muxii (i1 $Rs), 1, 0)>;
4426 def I32toI1: OutPatFrag<(ops node:$Rs),
4427 (i1 (C2_tfrrp (i32 $Rs)))>;
4429 defm: Storexm_pat<store, I1, s32ImmPred, I1toI32, S2_storerb_io>;
4430 def: Storexm_simple_pat<store, I1, I1toI32, S2_storerb_io>;
4432 //===----------------------------------------------------------------------===//
4434 //===----------------------------------------------------------------------===//
4436 //===----------------------------------------------------------------------===//
4438 //===----------------------------------------------------------------------===//
4439 class S_2OpInstImm<string Mnemonic, bits<3>MajOp, bits<3>MinOp,
4440 Operand Imm, list<dag> pattern = [], bit isRnd = 0>
4441 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, Imm:$src2),
4442 "$dst = "#Mnemonic#"($src1, #$src2)"#!if(isRnd, ":rnd", ""),
4446 let IClass = 0b1000;
4447 let Inst{27-24} = 0;
4448 let Inst{23-21} = MajOp;
4449 let Inst{20-16} = src1;
4450 let Inst{7-5} = MinOp;
4451 let Inst{4-0} = dst;
4454 class S_2OpInstImmI6<string Mnemonic, SDNode OpNode, bits<3>MinOp>
4455 : S_2OpInstImm<Mnemonic, 0b000, MinOp, u6Imm,
4456 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1),
4457 u6ImmPred:$src2))]> {
4459 let Inst{13-8} = src2;
4462 // Shift by immediate.
4463 def S2_asr_i_p : S_2OpInstImmI6<"asr", sra, 0b000>;
4464 def S2_asl_i_p : S_2OpInstImmI6<"asl", shl, 0b010>;
4465 def S2_lsr_i_p : S_2OpInstImmI6<"lsr", srl, 0b001>;
4467 // Shift left by small amount and add.
4468 let AddedComplexity = 100, hasNewValue = 1, hasSideEffects = 0 in
4469 def S2_addasl_rrri: SInst <(outs IntRegs:$Rd),
4470 (ins IntRegs:$Rt, IntRegs:$Rs, u3Imm:$u3),
4471 "$Rd = addasl($Rt, $Rs, #$u3)" ,
4472 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rt),
4473 (shl (i32 IntRegs:$Rs), u3ImmPred:$u3)))],
4474 "", S_3op_tc_2_SLOT23> {
4480 let IClass = 0b1100;
4482 let Inst{27-21} = 0b0100000;
4483 let Inst{20-16} = Rs;
4485 let Inst{12-8} = Rt;
4490 //===----------------------------------------------------------------------===//
4492 //===----------------------------------------------------------------------===//
4494 //===----------------------------------------------------------------------===//
4496 //===----------------------------------------------------------------------===//
4497 //===----------------------------------------------------------------------===//
4499 //===----------------------------------------------------------------------===//
4501 //===----------------------------------------------------------------------===//
4503 //===----------------------------------------------------------------------===//
4504 //===----------------------------------------------------------------------===//
4506 //===----------------------------------------------------------------------===//
4508 //===----------------------------------------------------------------------===//
4510 //===----------------------------------------------------------------------===//
4512 //===----------------------------------------------------------------------===//
4514 //===----------------------------------------------------------------------===//
4515 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>;
4517 let hasSideEffects = 1, isSoloAX = 1 in
4518 def Y2_barrier : SYSInst<(outs), (ins),
4520 [(HexagonBARRIER)],"",ST_tc_st_SLOT0> {
4521 let Inst{31-28} = 0b1010;
4522 let Inst{27-21} = 0b1000000;
4525 //===----------------------------------------------------------------------===//
4527 //===----------------------------------------------------------------------===//
4529 // Generate frameindex addresses. The main reason for the offset operand is
4530 // that every instruction that is allowed to have frame index as an operand
4531 // will then have that operand followed by an immediate operand (the offset).
4532 // This simplifies the frame-index elimination code.
4534 let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
4535 isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in {
4536 def TFR_FI : ALU32_ri<(outs IntRegs:$Rd),
4537 (ins IntRegs:$fi, s32Imm:$off), "">;
4538 def TFR_FIA : ALU32_ri<(outs IntRegs:$Rd),
4539 (ins IntRegs:$Rs, IntRegs:$fi, s32Imm:$off), "">;
4542 //===----------------------------------------------------------------------===//
4544 //===----------------------------------------------------------------------===//
4546 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
4547 opExtendable = 0, hasSideEffects = 0 in
4548 class LOOP_iBase<string mnemonic, Operand brOp, bit mustExtend = 0>
4549 : CRInst<(outs), (ins brOp:$offset, u10Imm:$src2),
4550 #mnemonic#"($offset, #$src2)",
4551 [], "" , CR_tc_3x_SLOT3> {
4555 let IClass = 0b0110;
4557 let Inst{27-22} = 0b100100;
4558 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
4559 let Inst{20-16} = src2{9-5};
4560 let Inst{12-8} = offset{8-4};
4561 let Inst{7-5} = src2{4-2};
4562 let Inst{4-3} = offset{3-2};
4563 let Inst{1-0} = src2{1-0};
4566 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
4567 opExtendable = 0, hasSideEffects = 0 in
4568 class LOOP_rBase<string mnemonic, Operand brOp, bit mustExtend = 0>
4569 : CRInst<(outs), (ins brOp:$offset, IntRegs:$src2),
4570 #mnemonic#"($offset, $src2)",
4571 [], "" ,CR_tc_3x_SLOT3> {
4575 let IClass = 0b0110;
4577 let Inst{27-22} = 0b000000;
4578 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
4579 let Inst{20-16} = src2;
4580 let Inst{12-8} = offset{8-4};
4581 let Inst{4-3} = offset{3-2};
4584 multiclass LOOP_ri<string mnemonic> {
4585 def i : LOOP_iBase<mnemonic, brtarget>;
4586 def r : LOOP_rBase<mnemonic, brtarget>;
4588 let isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in {
4589 def iext: LOOP_iBase<mnemonic, brtargetExt, 1>;
4590 def rext: LOOP_rBase<mnemonic, brtargetExt, 1>;
4595 let Defs = [SA0, LC0, USR] in
4596 defm J2_loop0 : LOOP_ri<"loop0">;
4598 // Interestingly only loop0's appear to set usr.lpcfg
4599 let Defs = [SA1, LC1] in
4600 defm J2_loop1 : LOOP_ri<"loop1">;
4602 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
4603 Defs = [PC, LC0], Uses = [SA0, LC0] in {
4604 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
4609 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
4610 Defs = [PC, LC1], Uses = [SA1, LC1] in {
4611 def ENDLOOP1 : Endloop<(outs), (ins brtarget:$offset),
4616 // Pipelined loop instructions, sp[123]loop0
4617 let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0,
4618 isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2,
4619 opExtendable = 0, isPredicateLate = 1 in
4620 class SPLOOP_iBase<string SP, bits<2> op>
4621 : CRInst <(outs), (ins brtarget:$r7_2, u10Imm:$U10),
4622 "p3 = sp"#SP#"loop0($r7_2, #$U10)" > {
4626 let IClass = 0b0110;
4628 let Inst{22-21} = op;
4629 let Inst{27-23} = 0b10011;
4630 let Inst{20-16} = U10{9-5};
4631 let Inst{12-8} = r7_2{8-4};
4632 let Inst{7-5} = U10{4-2};
4633 let Inst{4-3} = r7_2{3-2};
4634 let Inst{1-0} = U10{1-0};
4637 let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0,
4638 isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2,
4639 opExtendable = 0, isPredicateLate = 1 in
4640 class SPLOOP_rBase<string SP, bits<2> op>
4641 : CRInst <(outs), (ins brtarget:$r7_2, IntRegs:$Rs),
4642 "p3 = sp"#SP#"loop0($r7_2, $Rs)" > {
4646 let IClass = 0b0110;
4648 let Inst{22-21} = op;
4649 let Inst{27-23} = 0b00001;
4650 let Inst{20-16} = Rs;
4651 let Inst{12-8} = r7_2{8-4};
4652 let Inst{4-3} = r7_2{3-2};
4655 multiclass SPLOOP_ri<string mnemonic, bits<2> op> {
4656 def i : SPLOOP_iBase<mnemonic, op>;
4657 def r : SPLOOP_rBase<mnemonic, op>;
4660 defm J2_ploop1s : SPLOOP_ri<"1", 0b01>;
4661 defm J2_ploop2s : SPLOOP_ri<"2", 0b10>;
4662 defm J2_ploop3s : SPLOOP_ri<"3", 0b11>;
4664 // if (Rs[!>=<]=#0) jump:[t/nt]
4665 let Defs = [PC], isPredicated = 1, isBranch = 1, hasSideEffects = 0,
4666 hasSideEffects = 0 in
4667 class J2_jump_0_Base<string compare, bit isTak, bits<2> op>
4668 : CRInst <(outs), (ins IntRegs:$Rs, brtarget:$r13_2),
4669 "if ($Rs"#compare#"#0) jump"#!if(isTak, ":t", ":nt")#" $r13_2" > {
4673 let IClass = 0b0110;
4675 let Inst{27-24} = 0b0001;
4676 let Inst{23-22} = op;
4677 let Inst{12} = isTak;
4678 let Inst{21} = r13_2{14};
4679 let Inst{20-16} = Rs;
4680 let Inst{11-1} = r13_2{12-2};
4681 let Inst{13} = r13_2{13};
4684 multiclass J2_jump_compare_0<string compare, bits<2> op> {
4685 def NAME : J2_jump_0_Base<compare, 0, op>;
4686 def NAME#pt : J2_jump_0_Base<compare, 1, op>;
4689 defm J2_jumprz : J2_jump_compare_0<"!=", 0b00>;
4690 defm J2_jumprgtez : J2_jump_compare_0<">=", 0b01>;
4691 defm J2_jumprnz : J2_jump_compare_0<"==", 0b10>;
4692 defm J2_jumprltez : J2_jump_compare_0<"<=", 0b11>;
4694 // Transfer to/from Control/GPR Guest/GPR
4695 let hasSideEffects = 0 in
4696 class TFR_CR_RS_base<RegisterClass CTRC, RegisterClass RC, bit isDouble>
4697 : CRInst <(outs CTRC:$dst), (ins RC:$src),
4698 "$dst = $src", [], "", CR_tc_3x_SLOT3> {
4702 let IClass = 0b0110;
4704 let Inst{27-25} = 0b001;
4705 let Inst{24} = isDouble;
4706 let Inst{23-21} = 0b001;
4707 let Inst{20-16} = src;
4708 let Inst{4-0} = dst;
4711 def A2_tfrrcr : TFR_CR_RS_base<CtrRegs, IntRegs, 0b0>;
4712 def A4_tfrpcp : TFR_CR_RS_base<CtrRegs64, DoubleRegs, 0b1>;
4713 def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>;
4714 def : InstAlias<"m1 = $Rs", (A2_tfrrcr C7, IntRegs:$Rs)>;
4716 let hasSideEffects = 0 in
4717 class TFR_RD_CR_base<RegisterClass RC, RegisterClass CTRC, bit isSingle>
4718 : CRInst <(outs RC:$dst), (ins CTRC:$src),
4719 "$dst = $src", [], "", CR_tc_3x_SLOT3> {
4723 let IClass = 0b0110;
4725 let Inst{27-26} = 0b10;
4726 let Inst{25} = isSingle;
4727 let Inst{24-21} = 0b0000;
4728 let Inst{20-16} = src;
4729 let Inst{4-0} = dst;
4732 let hasNewValue = 1, opNewValue = 0 in
4733 def A2_tfrcrr : TFR_RD_CR_base<IntRegs, CtrRegs, 1>;
4734 def A4_tfrcpp : TFR_RD_CR_base<DoubleRegs, CtrRegs64, 0>;
4735 def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>;
4736 def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>;
4738 // Y4_trace: Send value to etm trace.
4739 let isSoloAX = 1, hasSideEffects = 0 in
4740 def Y4_trace: CRInst <(outs), (ins IntRegs:$Rs),
4744 let IClass = 0b0110;
4745 let Inst{27-21} = 0b0010010;
4746 let Inst{20-16} = Rs;
4749 // Support for generating global address.
4750 // Taken from X86InstrInfo.td.
4751 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
4754 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
4755 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
4757 // HI/LO Instructions
4758 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
4759 hasNewValue = 1, opNewValue = 0 in
4760 class REG_IMMED<string RegHalf, string Op, bit Rs, bits<3> MajOp, bit MinOp>
4761 : ALU32_ri<(outs IntRegs:$dst),
4762 (ins i32imm:$imm_value),
4763 "$dst"#RegHalf#" = #"#Op#"($imm_value)", []> {
4766 let IClass = 0b0111;
4769 let Inst{26-24} = MajOp;
4770 let Inst{21} = MinOp;
4771 let Inst{20-16} = dst;
4772 let Inst{23-22} = !if (!eq(Op, "LO"), imm_value{15-14}, imm_value{31-30});
4773 let Inst{13-0} = !if (!eq(Op, "LO"), imm_value{13-0}, imm_value{29-16});
4776 let isAsmParserOnly = 1 in {
4777 def LO : REG_IMMED<".l", "LO", 0b0, 0b001, 0b1>;
4778 def LO_H : REG_IMMED<".l", "HI", 0b0, 0b001, 0b1>;
4779 def HI : REG_IMMED<".h", "HI", 0b0, 0b010, 0b1>;
4780 def HI_L : REG_IMMED<".h", "LO", 0b0, 0b010, 0b1>;
4783 let isMoveImm = 1, isCodeGenOnly = 1 in
4784 def LO_PIC : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4785 "$dst.l = #LO($label@GOTREL)",
4788 let isMoveImm = 1, isCodeGenOnly = 1 in
4789 def HI_PIC : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4790 "$dst.h = #HI($label@GOTREL)",
4793 let isReMaterializable = 1, isMoveImm = 1,
4794 isCodeGenOnly = 1, hasSideEffects = 0 in
4795 def HI_GOT : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4796 "$dst.h = #HI($global@GOT)",
4799 let isReMaterializable = 1, isMoveImm = 1,
4800 isCodeGenOnly = 1, hasSideEffects = 0 in
4801 def LO_GOT : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4802 "$dst.l = #LO($global@GOT)",
4805 let isReMaterializable = 1, isMoveImm = 1,
4806 isCodeGenOnly = 1, hasSideEffects = 0 in
4807 def HI_GOTREL : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4808 "$dst.h = #HI($global@GOTREL)",
4811 let isReMaterializable = 1, isMoveImm = 1,
4812 isCodeGenOnly = 1, hasSideEffects = 0 in
4813 def LO_GOTREL : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4814 "$dst.l = #LO($global@GOTREL)",
4817 // This pattern is incorrect. When we add small data, we should change
4818 // this pattern to use memw(#foo).
4819 // This is for sdata.
4820 let isMoveImm = 1, isAsmParserOnly = 1 in
4821 def CONST32 : CONSTLDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
4822 "$dst = CONST32(#$global)",
4823 [(set (i32 IntRegs:$dst),
4824 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
4826 let isReMaterializable = 1, isMoveImm = 1 in
4827 def CONST32_set_jt : CONSTLDInst<(outs IntRegs:$dst), (ins jumptablebase:$jt),
4828 "$dst = CONST32(#$jt)",
4829 [(set (i32 IntRegs:$dst),
4830 (HexagonCONST32 tjumptable:$jt))]>;
4832 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
4833 def CONST32_Int_Real : CONSTLDInst<(outs IntRegs:$dst), (ins i32imm:$global),
4834 "$dst = CONST32(#$global)",
4835 [(set (i32 IntRegs:$dst), imm:$global) ]>;
4837 // Map TLS addressses to a CONST32 instruction
4838 def: Pat<(HexagonCONST32 tglobaltlsaddr:$addr), (A2_tfrsi s16Ext:$addr)>;
4839 def: Pat<(HexagonCONST32 bbl:$label), (A2_tfrsi s16Ext:$label)>;
4841 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
4842 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
4843 "$dst = CONST32($label)",
4844 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
4846 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
4847 def CONST64_Int_Real : CONSTLDInst<(outs DoubleRegs:$dst), (ins i64imm:$global),
4848 "$dst = CONST64(#$global)",
4849 [(set (i64 DoubleRegs:$dst), imm:$global)]>;
4851 let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
4852 isCodeGenOnly = 1 in
4853 def TFR_PdTrue : SInst<(outs PredRegs:$dst), (ins), "",
4854 [(set (i1 PredRegs:$dst), 1)]>;
4856 let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
4857 isCodeGenOnly = 1 in
4858 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins), "$dst = xor($dst, $dst)",
4859 [(set (i1 PredRegs:$dst), 0)]>;
4861 // Pseudo instructions.
4862 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
4863 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
4864 SDTCisVT<1, i32> ]>;
4866 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
4867 [SDNPHasChain, SDNPOutGlue]>;
4868 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
4869 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
4871 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
4873 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
4874 // Optional Flag and Variable Arguments.
4875 // Its 1 Operand has pointer type.
4876 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
4877 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
4879 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
4880 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
4881 ".error \"should not emit\" ",
4882 [(callseq_start timm:$amt)]>;
4884 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
4885 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
4886 ".error \"should not emit\" ",
4887 [(callseq_end timm:$amt1, timm:$amt2)]>;
4889 // Call subroutine indirectly.
4890 let Defs = VolatileV3.Regs in
4891 def J2_callr : JUMPR_MISC_CALLR<0, 1>;
4893 // Indirect tail-call.
4894 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
4895 isTerminator = 1, isCodeGenOnly = 1 in
4896 def TCRETURNr : T_JMPr;
4898 // Direct tail-calls.
4899 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
4900 isTerminator = 1, isCodeGenOnly = 1 in
4901 def TCRETURNi : JInst<(outs), (ins calltarget:$dst), "", []>;
4904 def: Pat<(HexagonTCRet tglobaladdr:$dst),
4905 (TCRETURNi tglobaladdr:$dst)>;
4906 def: Pat<(HexagonTCRet texternalsym:$dst),
4907 (TCRETURNi texternalsym:$dst)>;
4908 def: Pat<(HexagonTCRet (i32 IntRegs:$dst)),
4909 (TCRETURNr IntRegs:$dst)>;
4911 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
4912 def: Pat<(and (i32 IntRegs:$src1), 65535),
4913 (A2_zxth IntRegs:$src1)>;
4915 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
4916 def: Pat<(and (i32 IntRegs:$src1), 255),
4917 (A2_zxtb IntRegs:$src1)>;
4919 // Map Add(p1, true) to p1 = not(p1).
4920 // Add(p1, false) should never be produced,
4921 // if it does, it got to be mapped to NOOP.
4922 def: Pat<(add (i1 PredRegs:$src1), -1),
4923 (C2_not PredRegs:$src1)>;
4925 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
4926 def: Pat<(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s32ImmPred:$src3),
4927 (C2_muxii PredRegs:$src1, s32ImmPred:$src3, s8ImmPred:$src2)>;
4929 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
4930 // => r0 = C2_muxir(p0, r1, #i)
4931 def: Pat<(select (not (i1 PredRegs:$src1)), s32ImmPred:$src2,
4932 (i32 IntRegs:$src3)),
4933 (C2_muxir PredRegs:$src1, IntRegs:$src3, s32ImmPred:$src2)>;
4935 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
4936 // => r0 = C2_muxri (p0, #i, r1)
4937 def: Pat<(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s32ImmPred:$src3),
4938 (C2_muxri PredRegs:$src1, s32ImmPred:$src3, IntRegs:$src2)>;
4940 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
4941 def: Pat<(brcond (not (i1 PredRegs:$src1)), bb:$offset),
4942 (J2_jumpf PredRegs:$src1, bb:$offset)>;
4944 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = A2_sxtw(Rss.lo).
4945 def: Pat<(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
4946 (A2_sxtw (LoReg DoubleRegs:$src1))>;
4948 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = A2_sxtw(A2_sxth(Rss.lo)).
4949 def: Pat<(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
4950 (A2_sxtw (A2_sxth (LoReg DoubleRegs:$src1)))>;
4952 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = A2_sxtw(A2_sxtb(Rss.lo)).
4953 def: Pat<(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
4954 (A2_sxtw (A2_sxtb (LoReg DoubleRegs:$src1)))>;
4956 // We want to prevent emitting pnot's as much as possible.
4957 // Map brcond with an unsupported setcc to a J2_jumpf.
4958 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4960 (J2_jumpf (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
4963 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
4965 (J2_jumpf (C2_cmpeqi (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
4967 def: Pat<(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
4968 (J2_jumpf PredRegs:$src1, bb:$offset)>;
4970 def: Pat<(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
4971 (J2_jumpt PredRegs:$src1, bb:$offset)>;
4973 // cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1)
4974 def: Pat<(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)), bb:$offset),
4975 (J2_jumpf (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s8ImmPred:$src2)),
4978 // Map from a 64-bit select to an emulated 64-bit mux.
4979 // Hexagon does not support 64-bit MUXes; so emulate with combines.
4980 def: Pat<(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
4981 (i64 DoubleRegs:$src3)),
4982 (A2_combinew (C2_mux PredRegs:$src1, (HiReg DoubleRegs:$src2),
4983 (HiReg DoubleRegs:$src3)),
4984 (C2_mux PredRegs:$src1, (LoReg DoubleRegs:$src2),
4985 (LoReg DoubleRegs:$src3)))>;
4987 // Map from a 1-bit select to logical ops.
4988 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
4989 def: Pat<(select (i1 PredRegs:$src1), (i1 PredRegs:$src2), (i1 PredRegs:$src3)),
4990 (C2_or (C2_and PredRegs:$src1, PredRegs:$src2),
4991 (C2_and (C2_not PredRegs:$src1), PredRegs:$src3))>;
4993 // Map for truncating from 64 immediates to 32 bit immediates.
4994 def: Pat<(i32 (trunc (i64 DoubleRegs:$src))),
4995 (LoReg DoubleRegs:$src)>;
4997 // Map for truncating from i64 immediates to i1 bit immediates.
4998 def: Pat<(i1 (trunc (i64 DoubleRegs:$src))),
4999 (C2_tfrrp (LoReg DoubleRegs:$src))>;
5001 // rs <= rt -> !(rs > rt).
5002 let AddedComplexity = 30 in
5003 def: Pat<(i1 (setle (i32 IntRegs:$src1), s32ImmPred:$src2)),
5004 (C2_not (C2_cmpgti IntRegs:$src1, s32ImmPred:$src2))>;
5006 // rs <= rt -> !(rs > rt).
5007 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
5008 (i1 (C2_not (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
5010 // Rss <= Rtt -> !(Rss > Rtt).
5011 def: Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
5012 (C2_not (C2_cmpgtp DoubleRegs:$src1, DoubleRegs:$src2))>;
5014 // Map cmpne -> cmpeq.
5015 // Hexagon_TODO: We should improve on this.
5016 // rs != rt -> !(rs == rt).
5017 let AddedComplexity = 30 in
5018 def: Pat<(i1 (setne (i32 IntRegs:$src1), s32ImmPred:$src2)),
5019 (C2_not (C2_cmpeqi IntRegs:$src1, s32ImmPred:$src2))>;
5021 // Convert setne back to xor for hexagon since we compute w/ pred registers.
5022 def: Pat<(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
5023 (C2_xor PredRegs:$src1, PredRegs:$src2)>;
5025 // Map cmpne(Rss) -> !cmpew(Rss).
5026 // rs != rt -> !(rs == rt).
5027 def: Pat<(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
5028 (C2_not (C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2))>;
5030 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
5031 // rs >= rt -> !(rt > rs).
5032 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
5033 (i1 (C2_not (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
5035 // cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
5036 let AddedComplexity = 30 in
5037 def: Pat<(i1 (setge (i32 IntRegs:$src1), s32ImmPred:$src2)),
5038 (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s32ImmPred:$src2))>;
5040 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
5041 // rss >= rtt -> !(rtt > rss).
5042 def: Pat<(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
5043 (C2_not (C2_cmpgtp DoubleRegs:$src2, DoubleRegs:$src1))>;
5045 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
5046 // !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
5047 // rs < rt -> !(rs >= rt).
5048 let AddedComplexity = 30 in
5049 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32ImmPred:$src2)),
5050 (C2_not (C2_cmpgti IntRegs:$src1,
5051 (DEC_CONST_SIGNED s32ImmPred:$src2)))>;
5053 // Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs)
5054 def: Pat<(i1 (setuge (i32 IntRegs:$src1), 0)),
5055 (C2_cmpeq IntRegs:$src1, IntRegs:$src1)>;
5057 // Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1)
5058 def: Pat<(i1 (setuge (i32 IntRegs:$src1), u32ImmPred:$src2)),
5059 (C2_cmpgtui IntRegs:$src1, (DEC_CONST_UNSIGNED u32ImmPred:$src2))>;
5061 // Generate cmpgtu(Rs, #u9)
5062 def: Pat<(i1 (setugt (i32 IntRegs:$src1), u32ImmPred:$src2)),
5063 (C2_cmpgtui IntRegs:$src1, u32ImmPred:$src2)>;
5065 // Map from Rs >= Rt -> !(Rt > Rs).
5066 // rs >= rt -> !(rt > rs).
5067 def: Pat<(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
5068 (C2_not (C2_cmpgtup DoubleRegs:$src2, DoubleRegs:$src1))>;
5070 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
5071 // Map from (Rs <= Rt) -> !(Rs > Rt).
5072 def: Pat<(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
5073 (C2_not (C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2))>;
5077 def: Pat<(i32 (sext (i1 PredRegs:$src1))),
5078 (C2_muxii PredRegs:$src1, -1, 0)>;
5081 def: Pat<(i64 (sext (i1 PredRegs:$src1))),
5082 (A2_combinew (A2_tfrsi -1), (C2_muxii PredRegs:$src1, -1, 0))>;
5086 def: Pat<(i32 (zext (i1 PredRegs:$src1))),
5087 (C2_muxii PredRegs:$src1, 1, 0)>;
5089 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
5090 def: Pat<(i32 (anyext (i1 PredRegs:$src1))),
5091 (C2_muxii PredRegs:$src1, 1, 0)>;
5093 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
5094 def: Pat<(i64 (anyext (i1 PredRegs:$src1))),
5095 (A2_sxtw (C2_muxii PredRegs:$src1, 1, 0))>;
5097 // Multiply 64-bit unsigned and use upper result.
5098 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
5104 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $src1), (LoReg $src2)), 32),
5107 (A2_combinew (A2_tfrsi 0),
5108 (LoReg (M2_dpmpyuu_s0 (LoReg $src1), (HiReg $src2))))),
5112 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $src1), (HiReg $src2)), 32)
5115 // Hexagon specific ISD nodes.
5116 def SDTHexagonALLOCA : SDTypeProfile<1, 2,
5117 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
5118 def HexagonALLOCA : SDNode<"HexagonISD::ALLOCA", SDTHexagonALLOCA,
5121 // The reason for the custom inserter is to record all ALLOCA instructions
5122 // in MachineFunctionInfo.
5123 let Defs = [R29], isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 1,
5124 usesCustomInserter = 1 in
5125 def ALLOCA: ALU32Inst<(outs IntRegs:$Rd),
5126 (ins IntRegs:$Rs, u32Imm:$A), "",
5127 [(set (i32 IntRegs:$Rd),
5128 (HexagonALLOCA (i32 IntRegs:$Rs), (i32 imm:$A)))]>;
5130 let isCodeGenOnly = 1, isPseudo = 1, Uses = [R30], hasSideEffects = 0 in
5131 def ALIGNA : ALU32Inst<(outs IntRegs:$Rd), (ins u32Imm:$A), "", []>;
5133 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
5134 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
5135 let isCodeGenOnly = 1 in
5136 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
5138 [(set (i32 IntRegs:$dst),
5139 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
5141 let AddedComplexity = 100 in
5142 def: Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
5143 (i32 IntRegs:$src1)>;
5145 def HexagonJT: SDNode<"HexagonISD::JT", SDTIntUnaryOp>;
5146 def HexagonCP: SDNode<"HexagonISD::CP", SDTIntUnaryOp>;
5148 def: Pat<(HexagonJT tjumptable:$dst),
5149 (CONST32_set_jt tjumptable:$dst)>;
5150 def: Pat<(HexagonCP tconstpool :$dst),
5151 (CONST32_set_jt tconstpool:$dst)>;
5155 //===----------------------------------------------------------------------===//
5157 // Shift by immediate/register and accumulate/logical
5158 //===----------------------------------------------------------------------===//
5160 // Rx[+-&|]=asr(Rs,#u5)
5161 // Rx[+-&|^]=lsr(Rs,#u5)
5162 // Rx[+-&|^]=asl(Rs,#u5)
5164 let hasNewValue = 1, opNewValue = 0 in
5165 class T_shift_imm_acc_r <string opc1, string opc2, SDNode OpNode1,
5166 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
5167 : SInst_acc<(outs IntRegs:$Rx),
5168 (ins IntRegs:$src1, IntRegs:$Rs, u5Imm:$u5),
5169 "$Rx "#opc2#opc1#"($Rs, #$u5)",
5170 [(set (i32 IntRegs:$Rx),
5171 (OpNode2 (i32 IntRegs:$src1),
5172 (OpNode1 (i32 IntRegs:$Rs), u5ImmPred:$u5)))],
5173 "$src1 = $Rx", S_2op_tc_2_SLOT23> {
5178 let IClass = 0b1000;
5180 let Inst{27-24} = 0b1110;
5181 let Inst{23-22} = majOp{2-1};
5183 let Inst{7} = majOp{0};
5184 let Inst{6-5} = minOp;
5186 let Inst{20-16} = Rs;
5187 let Inst{12-8} = u5;
5190 // Rx[+-&|]=asr(Rs,Rt)
5191 // Rx[+-&|^]=lsr(Rs,Rt)
5192 // Rx[+-&|^]=asl(Rs,Rt)
5194 let hasNewValue = 1, opNewValue = 0 in
5195 class T_shift_reg_acc_r <string opc1, string opc2, SDNode OpNode1,
5196 SDNode OpNode2, bits<2> majOp, bits<2> minOp>
5197 : SInst_acc<(outs IntRegs:$Rx),
5198 (ins IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt),
5199 "$Rx "#opc2#opc1#"($Rs, $Rt)",
5200 [(set (i32 IntRegs:$Rx),
5201 (OpNode2 (i32 IntRegs:$src1),
5202 (OpNode1 (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))],
5203 "$src1 = $Rx", S_3op_tc_2_SLOT23 > {
5208 let IClass = 0b1100;
5210 let Inst{27-24} = 0b1100;
5211 let Inst{23-22} = majOp;
5212 let Inst{7-6} = minOp;
5214 let Inst{20-16} = Rs;
5215 let Inst{12-8} = Rt;
5218 // Rxx[+-&|]=asr(Rss,#u6)
5219 // Rxx[+-&|^]=lsr(Rss,#u6)
5220 // Rxx[+-&|^]=asl(Rss,#u6)
5222 class T_shift_imm_acc_p <string opc1, string opc2, SDNode OpNode1,
5223 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
5224 : SInst_acc<(outs DoubleRegs:$Rxx),
5225 (ins DoubleRegs:$src1, DoubleRegs:$Rss, u6Imm:$u6),
5226 "$Rxx "#opc2#opc1#"($Rss, #$u6)",
5227 [(set (i64 DoubleRegs:$Rxx),
5228 (OpNode2 (i64 DoubleRegs:$src1),
5229 (OpNode1 (i64 DoubleRegs:$Rss), u6ImmPred:$u6)))],
5230 "$src1 = $Rxx", S_2op_tc_2_SLOT23> {
5235 let IClass = 0b1000;
5237 let Inst{27-24} = 0b0010;
5238 let Inst{23-22} = majOp{2-1};
5239 let Inst{7} = majOp{0};
5240 let Inst{6-5} = minOp;
5241 let Inst{4-0} = Rxx;
5242 let Inst{20-16} = Rss;
5243 let Inst{13-8} = u6;
5247 // Rxx[+-&|]=asr(Rss,Rt)
5248 // Rxx[+-&|^]=lsr(Rss,Rt)
5249 // Rxx[+-&|^]=asl(Rss,Rt)
5250 // Rxx[+-&|^]=lsl(Rss,Rt)
5252 class T_shift_reg_acc_p <string opc1, string opc2, SDNode OpNode1,
5253 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
5254 : SInst_acc<(outs DoubleRegs:$Rxx),
5255 (ins DoubleRegs:$src1, DoubleRegs:$Rss, IntRegs:$Rt),
5256 "$Rxx "#opc2#opc1#"($Rss, $Rt)",
5257 [(set (i64 DoubleRegs:$Rxx),
5258 (OpNode2 (i64 DoubleRegs:$src1),
5259 (OpNode1 (i64 DoubleRegs:$Rss), (i32 IntRegs:$Rt))))],
5260 "$src1 = $Rxx", S_3op_tc_2_SLOT23> {
5265 let IClass = 0b1100;
5267 let Inst{27-24} = 0b1011;
5268 let Inst{23-21} = majOp;
5269 let Inst{20-16} = Rss;
5270 let Inst{12-8} = Rt;
5271 let Inst{7-6} = minOp;
5272 let Inst{4-0} = Rxx;
5275 //===----------------------------------------------------------------------===//
5276 // Multi-class for the shift instructions with logical/arithmetic operators.
5277 //===----------------------------------------------------------------------===//
5279 multiclass xtype_imm_base<string OpcStr1, string OpcStr2, SDNode OpNode1,
5280 SDNode OpNode2, bits<3> majOp, bits<2> minOp > {
5281 def _i_r#NAME : T_shift_imm_acc_r< OpcStr1, OpcStr2, OpNode1,
5282 OpNode2, majOp, minOp >;
5283 def _i_p#NAME : T_shift_imm_acc_p< OpcStr1, OpcStr2, OpNode1,
5284 OpNode2, majOp, minOp >;
5287 multiclass xtype_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
5288 let AddedComplexity = 100 in
5289 defm _acc : xtype_imm_base< opc1, "+= ", OpNode, add, 0b001, minOp>;
5291 defm _nac : xtype_imm_base< opc1, "-= ", OpNode, sub, 0b000, minOp>;
5292 defm _and : xtype_imm_base< opc1, "&= ", OpNode, and, 0b010, minOp>;
5293 defm _or : xtype_imm_base< opc1, "|= ", OpNode, or, 0b011, minOp>;
5296 multiclass xtype_xor_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
5297 let AddedComplexity = 100 in
5298 defm _xacc : xtype_imm_base< opc1, "^= ", OpNode, xor, 0b100, minOp>;
5301 defm S2_asr : xtype_imm_acc<"asr", sra, 0b00>;
5303 defm S2_lsr : xtype_imm_acc<"lsr", srl, 0b01>,
5304 xtype_xor_imm_acc<"lsr", srl, 0b01>;
5306 defm S2_asl : xtype_imm_acc<"asl", shl, 0b10>,
5307 xtype_xor_imm_acc<"asl", shl, 0b10>;
5309 multiclass xtype_reg_acc_r<string opc1, SDNode OpNode, bits<2>minOp> {
5310 let AddedComplexity = 100 in
5311 def _acc : T_shift_reg_acc_r <opc1, "+= ", OpNode, add, 0b11, minOp>;
5313 def _nac : T_shift_reg_acc_r <opc1, "-= ", OpNode, sub, 0b10, minOp>;
5314 def _and : T_shift_reg_acc_r <opc1, "&= ", OpNode, and, 0b01, minOp>;
5315 def _or : T_shift_reg_acc_r <opc1, "|= ", OpNode, or, 0b00, minOp>;
5318 multiclass xtype_reg_acc_p<string opc1, SDNode OpNode, bits<2>minOp> {
5319 let AddedComplexity = 100 in
5320 def _acc : T_shift_reg_acc_p <opc1, "+= ", OpNode, add, 0b110, minOp>;
5322 def _nac : T_shift_reg_acc_p <opc1, "-= ", OpNode, sub, 0b100, minOp>;
5323 def _and : T_shift_reg_acc_p <opc1, "&= ", OpNode, and, 0b010, minOp>;
5324 def _or : T_shift_reg_acc_p <opc1, "|= ", OpNode, or, 0b000, minOp>;
5325 def _xor : T_shift_reg_acc_p <opc1, "^= ", OpNode, xor, 0b011, minOp>;
5328 multiclass xtype_reg_acc<string OpcStr, SDNode OpNode, bits<2> minOp > {
5329 defm _r_r : xtype_reg_acc_r <OpcStr, OpNode, minOp>;
5330 defm _r_p : xtype_reg_acc_p <OpcStr, OpNode, minOp>;
5333 defm S2_asl : xtype_reg_acc<"asl", shl, 0b10>;
5334 defm S2_asr : xtype_reg_acc<"asr", sra, 0b00>;
5335 defm S2_lsr : xtype_reg_acc<"lsr", srl, 0b01>;
5336 defm S2_lsl : xtype_reg_acc<"lsl", shl, 0b11>;
5338 //===----------------------------------------------------------------------===//
5339 let hasSideEffects = 0 in
5340 class T_S3op_1 <string mnemonic, RegisterClass RC, bits<2> MajOp, bits<3> MinOp,
5341 bit SwapOps, bit isSat = 0, bit isRnd = 0, bit hasShift = 0>
5342 : SInst <(outs RC:$dst),
5343 (ins DoubleRegs:$src1, DoubleRegs:$src2),
5344 "$dst = "#mnemonic#"($src1, $src2)"#!if(isRnd, ":rnd", "")
5345 #!if(hasShift,":>>1","")
5346 #!if(isSat, ":sat", ""),
5347 [], "", S_3op_tc_2_SLOT23 > {
5352 let IClass = 0b1100;
5354 let Inst{27-24} = 0b0001;
5355 let Inst{23-22} = MajOp;
5356 let Inst{20-16} = !if (SwapOps, src2, src1);
5357 let Inst{12-8} = !if (SwapOps, src1, src2);
5358 let Inst{7-5} = MinOp;
5359 let Inst{4-0} = dst;
5362 class T_S3op_64 <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit SwapOps,
5363 bit isSat = 0, bit isRnd = 0, bit hasShift = 0 >
5364 : T_S3op_1 <mnemonic, DoubleRegs, MajOp, MinOp, SwapOps,
5365 isSat, isRnd, hasShift>;
5367 let Itinerary = S_3op_tc_1_SLOT23 in {
5368 def S2_shuffeb : T_S3op_64 < "shuffeb", 0b00, 0b010, 0>;
5369 def S2_shuffeh : T_S3op_64 < "shuffeh", 0b00, 0b110, 0>;
5370 def S2_shuffob : T_S3op_64 < "shuffob", 0b00, 0b100, 1>;
5371 def S2_shuffoh : T_S3op_64 < "shuffoh", 0b10, 0b000, 1>;
5373 def S2_vtrunewh : T_S3op_64 < "vtrunewh", 0b10, 0b010, 0>;
5374 def S2_vtrunowh : T_S3op_64 < "vtrunowh", 0b10, 0b100, 0>;
5377 def S2_lfsp : T_S3op_64 < "lfs", 0b10, 0b110, 0>;
5379 let hasSideEffects = 0 in
5380 class T_S3op_2 <string mnemonic, bits<3> MajOp, bit SwapOps>
5381 : SInst < (outs DoubleRegs:$Rdd),
5382 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
5383 "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu)",
5384 [], "", S_3op_tc_1_SLOT23 > {
5390 let IClass = 0b1100;
5392 let Inst{27-24} = 0b0010;
5393 let Inst{23-21} = MajOp;
5394 let Inst{20-16} = !if (SwapOps, Rtt, Rss);
5395 let Inst{12-8} = !if (SwapOps, Rss, Rtt);
5397 let Inst{4-0} = Rdd;
5400 def S2_valignrb : T_S3op_2 < "valignb", 0b000, 1>;
5401 def S2_vsplicerb : T_S3op_2 < "vspliceb", 0b100, 0>;
5403 //===----------------------------------------------------------------------===//
5404 // Template class used by vector shift, vector rotate, vector neg,
5405 // 32-bit shift, 64-bit shifts, etc.
5406 //===----------------------------------------------------------------------===//
5408 let hasSideEffects = 0 in
5409 class T_S3op_3 <string mnemonic, RegisterClass RC, bits<2> MajOp,
5410 bits<2> MinOp, bit isSat = 0, list<dag> pattern = [] >
5411 : SInst <(outs RC:$dst),
5412 (ins RC:$src1, IntRegs:$src2),
5413 "$dst = "#mnemonic#"($src1, $src2)"#!if(isSat, ":sat", ""),
5414 pattern, "", S_3op_tc_1_SLOT23> {
5419 let IClass = 0b1100;
5421 let Inst{27-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b0110, 0b0011);
5422 let Inst{23-22} = MajOp;
5423 let Inst{20-16} = src1;
5424 let Inst{12-8} = src2;
5425 let Inst{7-6} = MinOp;
5426 let Inst{4-0} = dst;
5429 let hasNewValue = 1 in
5430 class T_S3op_shift32 <string mnemonic, SDNode OpNode, bits<2> MinOp>
5431 : T_S3op_3 <mnemonic, IntRegs, 0b01, MinOp, 0,
5432 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
5433 (i32 IntRegs:$src2)))]>;
5435 let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in
5436 class T_S3op_shift32_Sat <string mnemonic, bits<2> MinOp>
5437 : T_S3op_3 <mnemonic, IntRegs, 0b00, MinOp, 1, []>;
5440 class T_S3op_shift64 <string mnemonic, SDNode OpNode, bits<2> MinOp>
5441 : T_S3op_3 <mnemonic, DoubleRegs, 0b10, MinOp, 0,
5442 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1),
5443 (i32 IntRegs:$src2)))]>;
5446 class T_S3op_shiftVect <string mnemonic, bits<2> MajOp, bits<2> MinOp>
5447 : T_S3op_3 <mnemonic, DoubleRegs, MajOp, MinOp, 0, []>;
5450 // Shift by register
5451 // Rdd=[asr|lsr|asl|lsl](Rss,Rt)
5453 def S2_asr_r_p : T_S3op_shift64 < "asr", sra, 0b00>;
5454 def S2_lsr_r_p : T_S3op_shift64 < "lsr", srl, 0b01>;
5455 def S2_asl_r_p : T_S3op_shift64 < "asl", shl, 0b10>;
5456 def S2_lsl_r_p : T_S3op_shift64 < "lsl", shl, 0b11>;
5458 // Rd=[asr|lsr|asl|lsl](Rs,Rt)
5460 def S2_asr_r_r : T_S3op_shift32<"asr", sra, 0b00>;
5461 def S2_lsr_r_r : T_S3op_shift32<"lsr", srl, 0b01>;
5462 def S2_asl_r_r : T_S3op_shift32<"asl", shl, 0b10>;
5463 def S2_lsl_r_r : T_S3op_shift32<"lsl", shl, 0b11>;
5465 // Shift by register with saturation
5466 // Rd=asr(Rs,Rt):sat
5467 // Rd=asl(Rs,Rt):sat
5469 let Defs = [USR_OVF] in {
5470 def S2_asr_r_r_sat : T_S3op_shift32_Sat<"asr", 0b00>;
5471 def S2_asl_r_r_sat : T_S3op_shift32_Sat<"asl", 0b10>;
5474 let hasNewValue = 1, hasSideEffects = 0 in
5475 class T_S3op_8 <string opc, bits<3> MinOp, bit isSat, bit isRnd, bit hasShift, bit hasSplat = 0>
5476 : SInst < (outs IntRegs:$Rd),
5477 (ins DoubleRegs:$Rss, IntRegs:$Rt),
5478 "$Rd = "#opc#"($Rss, $Rt"#!if(hasSplat, "*", "")#")"
5479 #!if(hasShift, ":<<1", "")
5480 #!if(isRnd, ":rnd", "")
5481 #!if(isSat, ":sat", ""),
5482 [], "", S_3op_tc_1_SLOT23 > {
5487 let IClass = 0b1100;
5489 let Inst{27-24} = 0b0101;
5490 let Inst{20-16} = Rss;
5491 let Inst{12-8} = Rt;
5492 let Inst{7-5} = MinOp;
5496 def S2_asr_r_svw_trun : T_S3op_8<"vasrw", 0b010, 0, 0, 0>;
5498 let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in
5499 def S2_vcrotate : T_S3op_shiftVect < "vcrotate", 0b11, 0b00>;
5501 let hasSideEffects = 0 in
5502 class T_S3op_7 <string mnemonic, bit MajOp >
5503 : SInst <(outs DoubleRegs:$Rdd),
5504 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, u3Imm:$u3),
5505 "$Rdd = "#mnemonic#"($Rss, $Rtt, #$u3)" ,
5506 [], "", S_3op_tc_1_SLOT23 > {
5512 let IClass = 0b1100;
5514 let Inst{27-24} = 0b0000;
5515 let Inst{23} = MajOp;
5516 let Inst{20-16} = !if(MajOp, Rss, Rtt);
5517 let Inst{12-8} = !if(MajOp, Rtt, Rss);
5519 let Inst{4-0} = Rdd;
5522 def S2_valignib : T_S3op_7 < "valignb", 0>;
5523 def S2_vspliceib : T_S3op_7 < "vspliceb", 1>;
5525 //===----------------------------------------------------------------------===//
5526 // Template class for 'insert bitfield' instructions
5527 //===----------------------------------------------------------------------===//
5528 let hasSideEffects = 0 in
5529 class T_S3op_insert <string mnemonic, RegisterClass RC>
5530 : SInst <(outs RC:$dst),
5531 (ins RC:$src1, RC:$src2, DoubleRegs:$src3),
5532 "$dst = "#mnemonic#"($src2, $src3)" ,
5533 [], "$src1 = $dst", S_3op_tc_1_SLOT23 > {
5538 let IClass = 0b1100;
5540 let Inst{27-26} = 0b10;
5541 let Inst{25-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b00, 0b10);
5543 let Inst{20-16} = src2;
5544 let Inst{12-8} = src3;
5545 let Inst{4-0} = dst;
5548 let hasSideEffects = 0 in
5549 class T_S2op_insert <bits<4> RegTyBits, RegisterClass RC, Operand ImmOp>
5550 : SInst <(outs RC:$dst), (ins RC:$dst2, RC:$src1, ImmOp:$src2, ImmOp:$src3),
5551 "$dst = insert($src1, #$src2, #$src3)",
5552 [], "$dst2 = $dst", S_2op_tc_2_SLOT23> {
5559 string ImmOpStr = !cast<string>(ImmOp);
5561 let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5}, 0);
5562 let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0);
5564 let IClass = 0b1000;
5566 let Inst{27-24} = RegTyBits;
5567 let Inst{23} = bit23;
5568 let Inst{22-21} = src3{4-3};
5569 let Inst{20-16} = src1;
5570 let Inst{13} = bit13;
5571 let Inst{12-8} = src2{4-0};
5572 let Inst{7-5} = src3{2-0};
5573 let Inst{4-0} = dst;
5576 // Rx=insert(Rs,Rtt)
5577 // Rx=insert(Rs,#u5,#U5)
5578 let hasNewValue = 1 in {
5579 def S2_insert_rp : T_S3op_insert <"insert", IntRegs>;
5580 def S2_insert : T_S2op_insert <0b1111, IntRegs, u5Imm>;
5583 // Rxx=insert(Rss,Rtt)
5584 // Rxx=insert(Rss,#u6,#U6)
5585 def S2_insertp_rp : T_S3op_insert<"insert", DoubleRegs>;
5586 def S2_insertp : T_S2op_insert <0b0011, DoubleRegs, u6Imm>;
5589 def SDTHexagonINSERT_ri : SDTypeProfile<1, 4, [SDTCisVT<0, i32>,
5594 def SDTHexagonINSERT_rd : SDTypeProfile<1, 4, [SDTCisVT<0, i64>,
5599 def SDTHexagonINSERT_riv : SDTypeProfile<1, 3, [SDTCisVT<0, i32>,
5603 def SDTHexagonINSERT_rdv : SDTypeProfile<1, 3, [SDTCisVT<0, i64>,
5607 def HexagonINSERT_ri : SDNode<"HexagonISD::INSERT_ri", SDTHexagonINSERT_ri>;
5608 def HexagonINSERT_rd : SDNode<"HexagonISD::INSERT_rd", SDTHexagonINSERT_rd>;
5609 def HexagonINSERT_riv: SDNode<"HexagonISD::INSERT_riv", SDTHexagonINSERT_riv>;
5610 def HexagonINSERT_rdv: SDNode<"HexagonISD::INSERT_rdv", SDTHexagonINSERT_rdv>;
5612 def: Pat<(HexagonINSERT_ri I32:$Rs, I32:$Rt, u5ImmPred:$u1, u5ImmPred:$u2),
5613 (S2_insert I32:$Rs, I32:$Rt, u5ImmPred:$u1, u5ImmPred:$u2)>;
5615 def: Pat<(HexagonINSERT_rd I64:$Rs, I64:$Rt, u6ImmPred:$u1, u6ImmPred:$u2),
5616 (S2_insertp I64:$Rs, I64:$Rt, u6ImmPred:$u1, u6ImmPred:$u2)>;
5618 def: Pat<(HexagonINSERT_riv I32:$Rs, I32:$Rt, I64:$Ru),
5619 (S2_insert_rp I32:$Rs, I32:$Rt, I64:$Ru)>;
5621 def: Pat<(HexagonINSERT_rdv I64:$Rs, I64:$Rt, I64:$Ru),
5622 (S2_insertp_rp I64:$Rs, I64:$Rt, I64:$Ru)>;
5625 //===----------------------------------------------------------------------===//
5626 // Template class for 'extract bitfield' instructions
5627 //===----------------------------------------------------------------------===//
5628 let hasNewValue = 1, hasSideEffects = 0 in
5629 class T_S3op_extract <string mnemonic, bits<2> MinOp>
5630 : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
5631 "$Rd = "#mnemonic#"($Rs, $Rtt)",
5632 [], "", S_3op_tc_2_SLOT23 > {
5637 let IClass = 0b1100;
5639 let Inst{27-22} = 0b100100;
5640 let Inst{20-16} = Rs;
5641 let Inst{12-8} = Rtt;
5642 let Inst{7-6} = MinOp;
5646 let hasSideEffects = 0 in
5647 class T_S2op_extract <string mnemonic, bits<4> RegTyBits,
5648 RegisterClass RC, Operand ImmOp>
5649 : SInst <(outs RC:$dst), (ins RC:$src1, ImmOp:$src2, ImmOp:$src3),
5650 "$dst = "#mnemonic#"($src1, #$src2, #$src3)",
5651 [], "", S_2op_tc_2_SLOT23> {
5658 string ImmOpStr = !cast<string>(ImmOp);
5660 let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5},
5661 !if (!eq(mnemonic, "extractu"), 0, 1));
5663 let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0);
5665 let IClass = 0b1000;
5667 let Inst{27-24} = RegTyBits;
5668 let Inst{23} = bit23;
5669 let Inst{22-21} = src3{4-3};
5670 let Inst{20-16} = src1;
5671 let Inst{13} = bit13;
5672 let Inst{12-8} = src2{4-0};
5673 let Inst{7-5} = src3{2-0};
5674 let Inst{4-0} = dst;
5679 // Rdd=extractu(Rss,Rtt)
5680 // Rdd=extractu(Rss,#u6,#U6)
5681 def S2_extractup_rp : T_S3op_64 < "extractu", 0b00, 0b000, 0>;
5682 def S2_extractup : T_S2op_extract <"extractu", 0b0001, DoubleRegs, u6Imm>;
5684 // Rd=extractu(Rs,Rtt)
5685 // Rd=extractu(Rs,#u5,#U5)
5686 let hasNewValue = 1 in {
5687 def S2_extractu_rp : T_S3op_extract<"extractu", 0b00>;
5688 def S2_extractu : T_S2op_extract <"extractu", 0b1101, IntRegs, u5Imm>;
5691 def SDTHexagonEXTRACTU_ri : SDTypeProfile<1, 3, [SDTCisVT<0, i32>,
5695 def SDTHexagonEXTRACTU_rd : SDTypeProfile<1, 3, [SDTCisVT<0, i64>,
5699 def SDTHexagonEXTRACTU_riv : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
5702 def SDTHexagonEXTRACTU_rdv : SDTypeProfile<1, 2, [SDTCisVT<0, i64>,
5705 def HexagonEXTRACTU_ri : SDNode<"HexagonISD::EXTRACTU_ri", SDTHexagonEXTRACTU_ri>;
5706 def HexagonEXTRACTU_rd : SDNode<"HexagonISD::EXTRACTU_rd", SDTHexagonEXTRACTU_rd>;
5707 def HexagonEXTRACTU_riv: SDNode<"HexagonISD::EXTRACTU_riv", SDTHexagonEXTRACTU_riv>;
5708 def HexagonEXTRACTU_rdv: SDNode<"HexagonISD::EXTRACTU_rdv", SDTHexagonEXTRACTU_rdv>;
5710 def: Pat<(HexagonEXTRACTU_ri I32:$src1, u5ImmPred:$src2, u5ImmPred:$src3),
5711 (S2_extractu I32:$src1, u5ImmPred:$src2, u5ImmPred:$src3)>;
5713 def: Pat<(HexagonEXTRACTU_rd I64:$src1, u6ImmPred:$src2, u6ImmPred:$src3),
5714 (S2_extractup I64:$src1, u6ImmPred:$src2, u6ImmPred:$src3)>;
5716 def: Pat<(HexagonEXTRACTU_riv I32:$src1, I64:$src2),
5717 (S2_extractu_rp I32:$src1, I64:$src2)>;
5719 def: Pat<(HexagonEXTRACTU_rdv I64:$src1, I64:$src2),
5720 (S2_extractup_rp I64:$src1, I64:$src2)>;
5722 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
5723 def: Pat<(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
5724 (M2_mpysin IntRegs:$src1, u8ImmPred:$src2)>;
5726 //===----------------------------------------------------------------------===//
5727 // :raw for of tableindx[bdhw] insns
5728 //===----------------------------------------------------------------------===//
5730 let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
5731 class tableidxRaw<string OpStr, bits<2>MinOp>
5732 : SInst <(outs IntRegs:$Rx),
5733 (ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, s6Imm:$S6),
5734 "$Rx = "#OpStr#"($Rs, #$u4, #$S6):raw",
5735 [], "$Rx = $_dst_" > {
5741 let IClass = 0b1000;
5743 let Inst{27-24} = 0b0111;
5744 let Inst{23-22} = MinOp;
5745 let Inst{21} = u4{3};
5746 let Inst{20-16} = Rs;
5747 let Inst{13-8} = S6;
5748 let Inst{7-5} = u4{2-0};
5752 def S2_tableidxb : tableidxRaw<"tableidxb", 0b00>;
5753 def S2_tableidxh : tableidxRaw<"tableidxh", 0b01>;
5754 def S2_tableidxw : tableidxRaw<"tableidxw", 0b10>;
5755 def S2_tableidxd : tableidxRaw<"tableidxd", 0b11>;
5757 //===----------------------------------------------------------------------===//
5758 // Template class for 'table index' instructions which are assembler mapped
5759 // to their :raw format.
5760 //===----------------------------------------------------------------------===//
5762 class tableidx_goodsyntax <string mnemonic>
5763 : SInst <(outs IntRegs:$Rx),
5764 (ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, u5Imm:$u5),
5765 "$Rx = "#mnemonic#"($Rs, #$u4, #$u5)",
5766 [], "$Rx = $_dst_" >;
5768 def S2_tableidxb_goodsyntax : tableidx_goodsyntax<"tableidxb">;
5769 def S2_tableidxh_goodsyntax : tableidx_goodsyntax<"tableidxh">;
5770 def S2_tableidxw_goodsyntax : tableidx_goodsyntax<"tableidxw">;
5771 def S2_tableidxd_goodsyntax : tableidx_goodsyntax<"tableidxd">;
5773 //===----------------------------------------------------------------------===//
5774 // V3 Instructions +
5775 //===----------------------------------------------------------------------===//
5777 include "HexagonInstrInfoV3.td"
5779 //===----------------------------------------------------------------------===//
5780 // V3 Instructions -
5781 //===----------------------------------------------------------------------===//
5783 //===----------------------------------------------------------------------===//
5784 // V4 Instructions +
5785 //===----------------------------------------------------------------------===//
5787 include "HexagonInstrInfoV4.td"
5789 //===----------------------------------------------------------------------===//
5790 // V4 Instructions -
5791 //===----------------------------------------------------------------------===//
5793 //===----------------------------------------------------------------------===//
5794 // V5 Instructions +
5795 //===----------------------------------------------------------------------===//
5797 include "HexagonInstrInfoV5.td"
5799 //===----------------------------------------------------------------------===//
5800 // V5 Instructions -
5801 //===----------------------------------------------------------------------===//
5803 //===----------------------------------------------------------------------===//
5804 // ALU32/64/Vector +
5805 //===----------------------------------------------------------------------===///
5807 include "HexagonInstrInfoVector.td"