1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonImmediates.td"
17 //===----------------------------------------------------------------------===//
18 // Hexagon Instruction Predicate Definitions.
19 //===----------------------------------------------------------------------===//
20 def HasV2T : Predicate<"Subtarget.hasV2TOps()">;
21 def HasV2TOnly : Predicate<"Subtarget.hasV2TOpsOnly()">;
22 def NoV2T : Predicate<"!Subtarget.hasV2TOps()">;
23 def HasV3T : Predicate<"Subtarget.hasV3TOps()">;
24 def HasV3TOnly : Predicate<"Subtarget.hasV3TOpsOnly()">;
25 def NoV3T : Predicate<"!Subtarget.hasV3TOps()">;
26 def HasV4T : Predicate<"Subtarget.hasV4TOps()">;
27 def NoV4T : Predicate<"!Subtarget.hasV4TOps()">;
28 def UseMEMOP : Predicate<"Subtarget.useMemOps()">;
31 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
32 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>;
33 def ADDRriS11_0 : ComplexPattern<i32, 2, "SelectADDRriS11_0", [frameindex], []>;
34 def ADDRriS11_1 : ComplexPattern<i32, 2, "SelectADDRriS11_1", [frameindex], []>;
35 def ADDRriS11_2 : ComplexPattern<i32, 2, "SelectADDRriS11_2", [frameindex], []>;
36 def ADDRriS11_3 : ComplexPattern<i32, 2, "SelectADDRriS11_3", [frameindex], []>;
37 def ADDRriU6_0 : ComplexPattern<i32, 2, "SelectADDRriU6_0", [frameindex], []>;
38 def ADDRriU6_1 : ComplexPattern<i32, 2, "SelectADDRriU6_1", [frameindex], []>;
39 def ADDRriU6_2 : ComplexPattern<i32, 2, "SelectADDRriU6_2", [frameindex], []>;
42 def MEMrr : Operand<i32> {
43 let PrintMethod = "printMEMrrOperand";
44 let MIOperandInfo = (ops IntRegs, IntRegs);
48 def MEMri : Operand<i32> {
49 let PrintMethod = "printMEMriOperand";
50 let MIOperandInfo = (ops IntRegs, IntRegs);
53 def MEMri_s11_2 : Operand<i32>,
54 ComplexPattern<i32, 2, "SelectMEMriS11_2", []> {
55 let PrintMethod = "printMEMriOperand";
56 let MIOperandInfo = (ops IntRegs, s11Imm);
59 def FrameIndex : Operand<i32> {
60 let PrintMethod = "printFrameIndexOperand";
61 let MIOperandInfo = (ops IntRegs, s11Imm);
64 let PrintMethod = "printGlobalOperand" in
65 def globaladdress : Operand<i32>;
67 let PrintMethod = "printJumpTable" in
68 def jumptablebase : Operand<i32>;
70 def brtarget : Operand<OtherVT>;
71 def calltarget : Operand<i32>;
73 def bblabel : Operand<i32>;
74 def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf , [], "BasicBlockSDNode">;
76 def symbolHi32 : Operand<i32> {
77 let PrintMethod = "printSymbolHi";
79 def symbolLo32 : Operand<i32> {
80 let PrintMethod = "printSymbolLo";
83 // Multi-class for logical operators.
84 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
85 def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
86 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
87 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),
89 def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
90 !strconcat("$dst = ", !strconcat(OpcStr, "(#$b, $c)")),
91 [(set (i32 IntRegs:$dst), (OpNode s10Imm:$b,
95 // Multi-class for compare ops.
96 let isCompare = 1 in {
97 multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
98 def rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
99 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
100 [(set (i1 PredRegs:$dst),
101 (OpNode (i64 DoubleRegs:$b), (i64 DoubleRegs:$c)))]>;
103 multiclass CMP32_rr<string OpcStr, PatFrag OpNode> {
104 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
105 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
106 [(set (i1 PredRegs:$dst),
107 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
110 multiclass CMP32_rr_ri_s10<string OpcStr, PatFrag OpNode> {
111 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
112 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
113 [(set (i1 PredRegs:$dst),
114 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
115 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Imm:$c),
116 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
117 [(set (i1 PredRegs:$dst),
118 (OpNode (i32 IntRegs:$b), s10ImmPred:$c))]>;
121 multiclass CMP32_rr_ri_u9<string OpcStr, PatFrag OpNode> {
122 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
123 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
124 [(set (i1 PredRegs:$dst),
125 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
126 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Imm:$c),
127 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
128 [(set (i1 PredRegs:$dst),
129 (OpNode (i32 IntRegs:$b), u9ImmPred:$c))]>;
132 multiclass CMP32_ri_u8<string OpcStr, PatFrag OpNode> {
133 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u8Imm:$c),
134 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
135 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
139 multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
140 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Imm:$c),
141 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
142 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
147 //===----------------------------------------------------------------------===//
149 //===----------------------------------------------------------------------===//
151 let isCommutable = 1, isPredicable = 1 in
152 def ADD_rr : ALU32_rr<(outs IntRegs:$dst),
153 (ins IntRegs:$src1, IntRegs:$src2),
154 "$dst = add($src1, $src2)",
155 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
156 (i32 IntRegs:$src2)))]>;
158 let isPredicable = 1 in
159 def ADD_ri : ALU32_ri<(outs IntRegs:$dst),
160 (ins IntRegs:$src1, s16Imm:$src2),
161 "$dst = add($src1, #$src2)",
162 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
163 s16ImmPred:$src2))]>;
165 // Logical operations.
166 let isPredicable = 1 in
167 def XOR_rr : ALU32_rr<(outs IntRegs:$dst),
168 (ins IntRegs:$src1, IntRegs:$src2),
169 "$dst = xor($src1, $src2)",
170 [(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
171 (i32 IntRegs:$src2)))]>;
173 let isCommutable = 1, isPredicable = 1 in
174 def AND_rr : ALU32_rr<(outs IntRegs:$dst),
175 (ins IntRegs:$src1, IntRegs:$src2),
176 "$dst = and($src1, $src2)",
177 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
178 (i32 IntRegs:$src2)))]>;
180 def OR_ri : ALU32_ri<(outs IntRegs:$dst),
181 (ins IntRegs:$src1, s10Imm:$src2),
182 "$dst = or($src1, #$src2)",
183 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
184 s10ImmPred:$src2))]>;
186 def NOT_rr : ALU32_rr<(outs IntRegs:$dst),
189 [(set (i32 IntRegs:$dst), (not (i32 IntRegs:$src1)))]>;
191 def AND_ri : ALU32_ri<(outs IntRegs:$dst),
192 (ins IntRegs:$src1, s10Imm:$src2),
193 "$dst = and($src1, #$src2)",
194 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
195 s10ImmPred:$src2))]>;
197 let isCommutable = 1, isPredicable = 1 in
198 def OR_rr : ALU32_rr<(outs IntRegs:$dst),
199 (ins IntRegs:$src1, IntRegs:$src2),
200 "$dst = or($src1, $src2)",
201 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
202 (i32 IntRegs:$src2)))]>;
205 def NEG : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
207 [(set (i32 IntRegs:$dst), (ineg (i32 IntRegs:$src1)))]>;
209 let neverHasSideEffects = 1 in
210 def NOP : ALU32_rr<(outs), (ins),
215 let isPredicable = 1 in
216 def SUB_rr : ALU32_rr<(outs IntRegs:$dst),
217 (ins IntRegs:$src1, IntRegs:$src2),
218 "$dst = sub($src1, $src2)",
219 [(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
220 (i32 IntRegs:$src2)))]>;
222 // Rd32=sub(#s10,Rs32)
223 def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
224 (ins s10Imm:$src1, IntRegs:$src2),
225 "$dst = sub(#$src1, $src2)",
226 [(set IntRegs:$dst, (sub s10ImmPred:$src1, IntRegs:$src2))]>;
228 // Transfer immediate.
229 let isMoveImm = 1, isReMaterializable = 1, isPredicable = 1 in
230 def TFRI : ALU32_ri<(outs IntRegs:$dst), (ins s16Imm:$src1),
232 [(set (i32 IntRegs:$dst), s16ImmPred:$src1)]>;
234 // Transfer register.
235 let neverHasSideEffects = 1, isPredicable = 1 in
236 def TFR : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1),
240 let neverHasSideEffects = 1, isPredicable = 1 in
241 def TFR64 : ALU32_ri<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
246 // Transfer control register.
247 let neverHasSideEffects = 1 in
248 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
251 //===----------------------------------------------------------------------===//
253 //===----------------------------------------------------------------------===//
256 //===----------------------------------------------------------------------===//
258 //===----------------------------------------------------------------------===//
261 let isPredicable = 1, neverHasSideEffects = 1 in
262 def COMBINE_rr : ALU32_rr<(outs DoubleRegs:$dst),
263 (ins IntRegs:$src1, IntRegs:$src2),
264 "$dst = combine($src1, $src2)",
267 let neverHasSideEffects = 1 in
268 def COMBINE_ii : ALU32_ii<(outs DoubleRegs:$dst),
269 (ins s8Imm:$src1, s8Imm:$src2),
270 "$dst = combine(#$src1, #$src2)",
274 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
277 "$dst = vmux($src1, $src2, $src3)",
280 def MUX_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
281 IntRegs:$src2, IntRegs:$src3),
282 "$dst = mux($src1, $src2, $src3)",
283 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
285 (i32 IntRegs:$src3))))]>;
287 def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Imm:$src2,
289 "$dst = mux($src1, #$src2, $src3)",
290 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
292 (i32 IntRegs:$src3))))]>;
294 def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
296 "$dst = mux($src1, $src2, #$src3)",
297 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
299 s8ImmPred:$src3)))]>;
301 def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Imm:$src2,
303 "$dst = mux($src1, #$src2, #$src3)",
304 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
306 s8ImmPred:$src3)))]>;
309 let isPredicable = 1 in
310 def ASLH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
311 "$dst = aslh($src1)",
312 [(set (i32 IntRegs:$dst), (shl 16, (i32 IntRegs:$src1)))]>;
314 let isPredicable = 1 in
315 def ASRH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
316 "$dst = asrh($src1)",
317 [(set (i32 IntRegs:$dst), (sra 16, (i32 IntRegs:$src1)))]>;
320 let isPredicable = 1 in
321 def SXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
322 "$dst = sxtb($src1)",
323 [(set (i32 IntRegs:$dst), (sext_inreg (i32 IntRegs:$src1), i8))]>;
325 let isPredicable = 1 in
326 def SXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
327 "$dst = sxth($src1)",
328 [(set (i32 IntRegs:$dst), (sext_inreg (i32 IntRegs:$src1), i16))]>;
331 let isPredicable = 1, neverHasSideEffects = 1 in
332 def ZXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
333 "$dst = zxtb($src1)",
336 let isPredicable = 1, neverHasSideEffects = 1 in
337 def ZXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
338 "$dst = zxth($src1)",
340 //===----------------------------------------------------------------------===//
342 //===----------------------------------------------------------------------===//
345 //===----------------------------------------------------------------------===//
347 //===----------------------------------------------------------------------===//
350 let neverHasSideEffects = 1, isPredicated = 1 in
351 def ADD_ri_cPt : ALU32_ri<(outs IntRegs:$dst),
352 (ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
353 "if ($src1) $dst = add($src2, #$src3)",
356 let neverHasSideEffects = 1, isPredicated = 1 in
357 def ADD_ri_cNotPt : ALU32_ri<(outs IntRegs:$dst),
358 (ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
359 "if (!$src1) $dst = add($src2, #$src3)",
362 let neverHasSideEffects = 1, isPredicated = 1 in
363 def ADD_ri_cdnPt : ALU32_ri<(outs IntRegs:$dst),
364 (ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
365 "if ($src1.new) $dst = add($src2, #$src3)",
368 let neverHasSideEffects = 1, isPredicated = 1 in
369 def ADD_ri_cdnNotPt : ALU32_ri<(outs IntRegs:$dst),
370 (ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
371 "if (!$src1.new) $dst = add($src2, #$src3)",
374 let neverHasSideEffects = 1, isPredicated = 1 in
375 def ADD_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
376 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
377 "if ($src1) $dst = add($src2, $src3)",
380 let neverHasSideEffects = 1, isPredicated = 1 in
381 def ADD_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
382 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
383 "if (!$src1) $dst = add($src2, $src3)",
386 let neverHasSideEffects = 1, isPredicated = 1 in
387 def ADD_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
388 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
389 "if ($src1.new) $dst = add($src2, $src3)",
392 let neverHasSideEffects = 1, isPredicated = 1 in
393 def ADD_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
394 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
395 "if (!$src1.new) $dst = add($src2, $src3)",
399 // Conditional combine.
401 let neverHasSideEffects = 1, isPredicated = 1 in
402 def COMBINE_rr_cPt : ALU32_rr<(outs DoubleRegs:$dst),
403 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
404 "if ($src1) $dst = combine($src2, $src3)",
407 let neverHasSideEffects = 1, isPredicated = 1 in
408 def COMBINE_rr_cNotPt : ALU32_rr<(outs DoubleRegs:$dst),
409 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
410 "if (!$src1) $dst = combine($src2, $src3)",
413 let neverHasSideEffects = 1, isPredicated = 1 in
414 def COMBINE_rr_cdnPt : ALU32_rr<(outs DoubleRegs:$dst),
415 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
416 "if ($src1.new) $dst = combine($src2, $src3)",
419 let neverHasSideEffects = 1, isPredicated = 1 in
420 def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst),
421 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
422 "if (!$src1.new) $dst = combine($src2, $src3)",
425 // Conditional logical operations.
427 let isPredicated = 1 in
428 def XOR_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
429 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
430 "if ($src1) $dst = xor($src2, $src3)",
433 let isPredicated = 1 in
434 def XOR_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
435 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
436 "if (!$src1) $dst = xor($src2, $src3)",
439 let isPredicated = 1 in
440 def XOR_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
441 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
442 "if ($src1.new) $dst = xor($src2, $src3)",
445 let isPredicated = 1 in
446 def XOR_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
447 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
448 "if (!$src1.new) $dst = xor($src2, $src3)",
451 let isPredicated = 1 in
452 def AND_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
453 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
454 "if ($src1) $dst = and($src2, $src3)",
457 let isPredicated = 1 in
458 def AND_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
459 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
460 "if (!$src1) $dst = and($src2, $src3)",
463 let isPredicated = 1 in
464 def AND_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
465 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
466 "if ($src1.new) $dst = and($src2, $src3)",
469 let isPredicated = 1 in
470 def AND_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
471 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
472 "if (!$src1.new) $dst = and($src2, $src3)",
475 let isPredicated = 1 in
476 def OR_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
477 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
478 "if ($src1) $dst = or($src2, $src3)",
481 let isPredicated = 1 in
482 def OR_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
483 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
484 "if (!$src1) $dst = or($src2, $src3)",
487 let isPredicated = 1 in
488 def OR_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
489 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
490 "if ($src1.new) $dst = or($src2, $src3)",
493 let isPredicated = 1 in
494 def OR_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
495 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
496 "if (!$src1.new) $dst = or($src2, $src3)",
500 // Conditional subtract.
502 let isPredicated = 1 in
503 def SUB_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
504 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
505 "if ($src1) $dst = sub($src2, $src3)",
508 let isPredicated = 1 in
509 def SUB_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
510 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
511 "if (!$src1) $dst = sub($src2, $src3)",
514 let isPredicated = 1 in
515 def SUB_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
516 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
517 "if ($src1.new) $dst = sub($src2, $src3)",
520 let isPredicated = 1 in
521 def SUB_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
522 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
523 "if (!$src1.new) $dst = sub($src2, $src3)",
527 // Conditional transfer.
528 let neverHasSideEffects = 1, isPredicated = 1 in
529 def TFR_cPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2),
530 "if ($src1) $dst = $src2",
533 let neverHasSideEffects = 1, isPredicated = 1 in
534 def TFR_cNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
536 "if (!$src1) $dst = $src2",
539 let neverHasSideEffects = 1, isPredicated = 1 in
540 def TFR64_cPt : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
542 "if ($src1) $dst = $src2",
545 let neverHasSideEffects = 1, isPredicated = 1 in
546 def TFR64_cNotPt : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
548 "if (!$src1) $dst = $src2",
551 let neverHasSideEffects = 1, isPredicated = 1 in
552 def TFRI_cPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, s12Imm:$src2),
553 "if ($src1) $dst = #$src2",
556 let neverHasSideEffects = 1, isPredicated = 1 in
557 def TFRI_cNotPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
559 "if (!$src1) $dst = #$src2",
562 let neverHasSideEffects = 1, isPredicated = 1 in
563 def TFR_cdnPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
565 "if ($src1.new) $dst = $src2",
568 let neverHasSideEffects = 1, isPredicated = 1 in
569 def TFR_cdnNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
571 "if (!$src1.new) $dst = $src2",
574 let neverHasSideEffects = 1, isPredicated = 1 in
575 def TFRI_cdnPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
577 "if ($src1.new) $dst = #$src2",
580 let neverHasSideEffects = 1, isPredicated = 1 in
581 def TFRI_cdnNotPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
583 "if (!$src1.new) $dst = #$src2",
587 defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", setugt>;
588 defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", setgt>;
589 defm CMPLT : CMP32_rr<"cmp.lt", setlt>;
590 defm CMPLTU : CMP32_rr<"cmp.ltu", setult>;
591 defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", seteq>;
592 defm CMPGE : CMP32_ri_s8<"cmp.ge", setge>;
593 defm CMPGEU : CMP32_ri_u8<"cmp.geu", setuge>;
594 //===----------------------------------------------------------------------===//
596 //===----------------------------------------------------------------------===//
599 //===----------------------------------------------------------------------===//
601 //===----------------------------------------------------------------------===//
603 def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
605 "$dst = add($src1, $src2)",
606 [(set (i64 DoubleRegs:$dst), (add (i64 DoubleRegs:$src1),
607 (i64 DoubleRegs:$src2)))]>;
612 defm CMPEHexagon4 : CMP64_rr<"cmp.eq", seteq>;
613 defm CMPGT64 : CMP64_rr<"cmp.gt", setgt>;
614 defm CMPGTU64 : CMP64_rr<"cmp.gtu", setugt>;
616 // Logical operations.
617 def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
619 "$dst = and($src1, $src2)",
620 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
621 (i64 DoubleRegs:$src2)))]>;
623 def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
625 "$dst = or($src1, $src2)",
626 [(set (i64 DoubleRegs:$dst), (or (i64 DoubleRegs:$src1),
627 (i64 DoubleRegs:$src2)))]>;
629 def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
631 "$dst = xor($src1, $src2)",
632 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
633 (i64 DoubleRegs:$src2)))]>;
636 def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
637 "$dst = max($src2, $src1)",
638 [(set (i32 IntRegs:$dst),
639 (i32 (select (i1 (setlt (i32 IntRegs:$src2),
640 (i32 IntRegs:$src1))),
641 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
643 def MAXUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
644 "$dst = maxu($src2, $src1)",
645 [(set (i32 IntRegs:$dst),
646 (i32 (select (i1 (setult (i32 IntRegs:$src2),
647 (i32 IntRegs:$src1))),
648 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
650 def MAXd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
652 "$dst = max($src2, $src1)",
653 [(set (i64 DoubleRegs:$dst),
654 (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
655 (i64 DoubleRegs:$src1))),
656 (i64 DoubleRegs:$src1),
657 (i64 DoubleRegs:$src2))))]>;
659 def MAXUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
661 "$dst = maxu($src2, $src1)",
662 [(set (i64 DoubleRegs:$dst),
663 (i64 (select (i1 (setult (i64 DoubleRegs:$src2),
664 (i64 DoubleRegs:$src1))),
665 (i64 DoubleRegs:$src1),
666 (i64 DoubleRegs:$src2))))]>;
669 def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
670 "$dst = min($src2, $src1)",
671 [(set (i32 IntRegs:$dst),
672 (i32 (select (i1 (setgt (i32 IntRegs:$src2),
673 (i32 IntRegs:$src1))),
674 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
676 def MINUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
677 "$dst = minu($src2, $src1)",
678 [(set (i32 IntRegs:$dst),
679 (i32 (select (i1 (setugt (i32 IntRegs:$src2),
680 (i32 IntRegs:$src1))),
681 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
683 def MINd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
685 "$dst = min($src2, $src1)",
686 [(set (i64 DoubleRegs:$dst),
687 (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
688 (i64 DoubleRegs:$src1))),
689 (i64 DoubleRegs:$src1),
690 (i64 DoubleRegs:$src2))))]>;
692 def MINUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
694 "$dst = minu($src2, $src1)",
695 [(set (i64 DoubleRegs:$dst),
696 (i64 (select (i1 (setugt (i64 DoubleRegs:$src2),
697 (i64 DoubleRegs:$src1))),
698 (i64 DoubleRegs:$src1),
699 (i64 DoubleRegs:$src2))))]>;
702 def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
704 "$dst = sub($src1, $src2)",
705 [(set (i64 DoubleRegs:$dst), (sub (i64 DoubleRegs:$src1),
706 (i64 DoubleRegs:$src2)))]>;
708 // Subtract halfword.
710 // Transfer register.
711 let neverHasSideEffects = 1 in
712 def TFR_64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
715 //===----------------------------------------------------------------------===//
717 //===----------------------------------------------------------------------===//
719 //===----------------------------------------------------------------------===//
721 //===----------------------------------------------------------------------===//
723 //===----------------------------------------------------------------------===//
725 //===----------------------------------------------------------------------===//
727 //===----------------------------------------------------------------------===//
729 //===----------------------------------------------------------------------===//
731 //===----------------------------------------------------------------------===//
733 //===----------------------------------------------------------------------===//
735 //===----------------------------------------------------------------------===//
737 //===----------------------------------------------------------------------===//
738 // Logical reductions on predicates.
740 // Looping instructions.
742 // Pipelined looping instructions.
744 // Logical operations on predicates.
745 def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
746 "$dst = and($src1, $src2)",
747 [(set (i1 PredRegs:$dst), (and (i1 PredRegs:$src1),
748 (i1 PredRegs:$src2)))]>;
750 let neverHasSideEffects = 1 in
751 def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
753 "$dst = and($src1, !$src2)",
756 def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
757 "$dst = any8($src1)",
760 def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
761 "$dst = all8($src1)",
764 def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
766 "$dst = vitpack($src1, $src2)",
769 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
772 "$dst = valignb($src1, $src2, $src3)",
775 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
778 "$dst = vspliceb($src1, $src2, $src3)",
781 def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
782 "$dst = mask($src1)",
785 def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
787 [(set (i1 PredRegs:$dst), (not (i1 PredRegs:$src1)))]>;
789 def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
790 "$dst = or($src1, $src2)",
791 [(set (i1 PredRegs:$dst), (or (i1 PredRegs:$src1),
792 (i1 PredRegs:$src2)))]>;
794 def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
795 "$dst = xor($src1, $src2)",
796 [(set (i1 PredRegs:$dst), (xor (i1 PredRegs:$src1),
797 (i1 PredRegs:$src2)))]>;
800 // User control register transfer.
801 //===----------------------------------------------------------------------===//
803 //===----------------------------------------------------------------------===//
806 //===----------------------------------------------------------------------===//
808 //===----------------------------------------------------------------------===//
810 let isBranch = 1, isTerminator=1, isBarrier = 1, isPredicable = 1 in {
811 def JMP : JInst< (outs),
812 (ins brtarget:$offset),
818 let isBranch = 1, isTerminator=1, Defs = [PC],
819 isPredicated = 1 in {
820 def JMP_c : JInst< (outs),
821 (ins PredRegs:$src, brtarget:$offset),
822 "if ($src) jump $offset",
823 [(brcond (i1 PredRegs:$src), bb:$offset)]>;
827 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
828 isPredicated = 1 in {
829 def JMP_cNot : JInst< (outs),
830 (ins PredRegs:$src, brtarget:$offset),
831 "if (!$src) jump $offset",
835 let isTerminator = 1, isBranch = 1, neverHasSideEffects = 1, Defs = [PC],
836 isPredicated = 1 in {
837 def BRCOND : JInst < (outs), (ins PredRegs:$pred, brtarget:$dst),
838 "if ($pred) jump $dst",
842 // Jump to address conditioned on new predicate.
844 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
845 isPredicated = 1 in {
846 def JMP_cdnPt : JInst< (outs),
847 (ins PredRegs:$src, brtarget:$offset),
848 "if ($src.new) jump:t $offset",
853 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
854 isPredicated = 1 in {
855 def JMP_cdnNotPt : JInst< (outs),
856 (ins PredRegs:$src, brtarget:$offset),
857 "if (!$src.new) jump:t $offset",
862 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
863 isPredicated = 1 in {
864 def JMP_cdnPnt : JInst< (outs),
865 (ins PredRegs:$src, brtarget:$offset),
866 "if ($src.new) jump:nt $offset",
871 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
872 isPredicated = 1 in {
873 def JMP_cdnNotPnt : JInst< (outs),
874 (ins PredRegs:$src, brtarget:$offset),
875 "if (!$src.new) jump:nt $offset",
878 //===----------------------------------------------------------------------===//
880 //===----------------------------------------------------------------------===//
882 //===----------------------------------------------------------------------===//
884 //===----------------------------------------------------------------------===//
885 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
886 [SDNPHasChain, SDNPOptInGlue]>;
888 // Jump to address from register.
889 let isPredicable =1, isReturn = 1, isTerminator = 1, isBarrier = 1,
890 Defs = [PC], Uses = [R31] in {
891 def JMPR: JRInst<(outs), (ins),
896 // Jump to address from register.
897 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
898 Defs = [PC], Uses = [R31] in {
899 def JMPR_cPt: JRInst<(outs), (ins PredRegs:$src1),
900 "if ($src1) jumpr r31",
904 // Jump to address from register.
905 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
906 Defs = [PC], Uses = [R31] in {
907 def JMPR_cNotPt: JRInst<(outs), (ins PredRegs:$src1),
908 "if (!$src1) jumpr r31",
912 //===----------------------------------------------------------------------===//
914 //===----------------------------------------------------------------------===//
916 //===----------------------------------------------------------------------===//
918 //===----------------------------------------------------------------------===//
920 /// Make sure that in post increment load, the first operand is always the post
921 /// increment operand.
924 let isPredicable = 1 in
925 def LDrid : LDInst<(outs DoubleRegs:$dst),
927 "$dst = memd($addr)",
928 [(set (i64 DoubleRegs:$dst), (i64 (load ADDRriS11_3:$addr)))]>;
930 let isPredicable = 1, AddedComplexity = 20 in
931 def LDrid_indexed : LDInst<(outs DoubleRegs:$dst),
932 (ins IntRegs:$src1, s11_3Imm:$offset),
933 "$dst = memd($src1+#$offset)",
934 [(set (i64 DoubleRegs:$dst),
935 (i64 (load (add (i32 IntRegs:$src1),
936 s11_3ImmPred:$offset))))]>;
938 let neverHasSideEffects = 1 in
939 def LDrid_GP : LDInst2<(outs DoubleRegs:$dst),
940 (ins globaladdress:$global, u16Imm:$offset),
941 "$dst = memd(#$global+$offset)",
945 let neverHasSideEffects = 1 in
946 def LDd_GP : LDInst2<(outs DoubleRegs:$dst),
947 (ins globaladdress:$global),
948 "$dst = memd(#$global)",
952 let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
953 def POST_LDrid : LDInst2PI<(outs DoubleRegs:$dst, IntRegs:$dst2),
954 (ins IntRegs:$src1, s4Imm:$offset),
955 "$dst = memd($src1++#$offset)",
959 // Load doubleword conditionally.
960 let neverHasSideEffects = 1, isPredicated = 1 in
961 def LDrid_cPt : LDInst2<(outs DoubleRegs:$dst),
962 (ins PredRegs:$src1, MEMri:$addr),
963 "if ($src1) $dst = memd($addr)",
967 let neverHasSideEffects = 1, isPredicated = 1 in
968 def LDrid_cNotPt : LDInst2<(outs DoubleRegs:$dst),
969 (ins PredRegs:$src1, MEMri:$addr),
970 "if (!$src1) $dst = memd($addr)",
973 let neverHasSideEffects = 1, isPredicated = 1 in
974 def LDrid_indexed_cPt : LDInst2<(outs DoubleRegs:$dst),
975 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
976 "if ($src1) $dst = memd($src2+#$src3)",
979 let neverHasSideEffects = 1, isPredicated = 1 in
980 def LDrid_indexed_cNotPt : LDInst2<(outs DoubleRegs:$dst),
981 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
982 "if (!$src1) $dst = memd($src2+#$src3)",
985 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
986 def POST_LDrid_cPt : LDInst2PI<(outs DoubleRegs:$dst1, IntRegs:$dst2),
987 (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),
988 "if ($src1) $dst1 = memd($src2++#$src3)",
992 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
993 def POST_LDrid_cNotPt : LDInst2PI<(outs DoubleRegs:$dst1, IntRegs:$dst2),
994 (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),
995 "if (!$src1) $dst1 = memd($src2++#$src3)",
999 let neverHasSideEffects = 1, isPredicated = 1 in
1000 def LDrid_cdnPt : LDInst2<(outs DoubleRegs:$dst),
1001 (ins PredRegs:$src1, MEMri:$addr),
1002 "if ($src1.new) $dst = memd($addr)",
1005 let neverHasSideEffects = 1, isPredicated = 1 in
1006 def LDrid_cdnNotPt : LDInst2<(outs DoubleRegs:$dst),
1007 (ins PredRegs:$src1, MEMri:$addr),
1008 "if (!$src1.new) $dst = memd($addr)",
1011 let neverHasSideEffects = 1, isPredicated = 1 in
1012 def LDrid_indexed_cdnPt : LDInst2<(outs DoubleRegs:$dst),
1013 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
1014 "if ($src1.new) $dst = memd($src2+#$src3)",
1017 let neverHasSideEffects = 1, isPredicated = 1 in
1018 def LDrid_indexed_cdnNotPt : LDInst2<(outs DoubleRegs:$dst),
1019 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
1020 "if (!$src1.new) $dst = memd($src2+#$src3)",
1025 let isPredicable = 1 in
1026 def LDrib : LDInst<(outs IntRegs:$dst),
1028 "$dst = memb($addr)",
1029 [(set (i32 IntRegs:$dst), (i32 (sextloadi8 ADDRriS11_0:$addr)))]>;
1031 // Load byte any-extend.
1032 def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
1033 (i32 (LDrib ADDRriS11_0:$addr)) >;
1035 // Indexed load byte.
1036 let isPredicable = 1, AddedComplexity = 20 in
1037 def LDrib_indexed : LDInst<(outs IntRegs:$dst),
1038 (ins IntRegs:$src1, s11_0Imm:$offset),
1039 "$dst = memb($src1+#$offset)",
1040 [(set (i32 IntRegs:$dst),
1041 (i32 (sextloadi8 (add (i32 IntRegs:$src1),
1042 s11_0ImmPred:$offset))))]>;
1044 // Indexed load byte any-extend.
1045 let AddedComplexity = 20 in
1046 def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1047 (i32 (LDrib_indexed IntRegs:$src1, s11_0ImmPred:$offset)) >;
1049 let neverHasSideEffects = 1 in
1050 def LDrib_GP : LDInst2<(outs IntRegs:$dst),
1051 (ins globaladdress:$global, u16Imm:$offset),
1052 "$dst = memb(#$global+$offset)",
1056 let neverHasSideEffects = 1 in
1057 def LDb_GP : LDInst2<(outs IntRegs:$dst),
1058 (ins globaladdress:$global),
1059 "$dst = memb(#$global)",
1063 let neverHasSideEffects = 1 in
1064 def LDub_GP : LDInst2<(outs IntRegs:$dst),
1065 (ins globaladdress:$global),
1066 "$dst = memub(#$global)",
1070 let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1071 def POST_LDrib : LDInst2PI<(outs IntRegs:$dst, IntRegs:$dst2),
1072 (ins IntRegs:$src1, s4Imm:$offset),
1073 "$dst = memb($src1++#$offset)",
1077 // Load byte conditionally.
1078 let neverHasSideEffects = 1, isPredicated = 1 in
1079 def LDrib_cPt : LDInst2<(outs IntRegs:$dst),
1080 (ins PredRegs:$src1, MEMri:$addr),
1081 "if ($src1) $dst = memb($addr)",
1084 let neverHasSideEffects = 1, isPredicated = 1 in
1085 def LDrib_cNotPt : LDInst2<(outs IntRegs:$dst),
1086 (ins PredRegs:$src1, MEMri:$addr),
1087 "if (!$src1) $dst = memb($addr)",
1090 let neverHasSideEffects = 1, isPredicated = 1 in
1091 def LDrib_indexed_cPt : LDInst2<(outs IntRegs:$dst),
1092 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1093 "if ($src1) $dst = memb($src2+#$src3)",
1096 let neverHasSideEffects = 1, isPredicated = 1 in
1097 def LDrib_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
1098 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1099 "if (!$src1) $dst = memb($src2+#$src3)",
1102 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1103 def POST_LDrib_cPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1104 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1105 "if ($src1) $dst1 = memb($src2++#$src3)",
1109 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1110 def POST_LDrib_cNotPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1111 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1112 "if (!$src1) $dst1 = memb($src2++#$src3)",
1116 let neverHasSideEffects = 1, isPredicated = 1 in
1117 def LDrib_cdnPt : LDInst2<(outs IntRegs:$dst),
1118 (ins PredRegs:$src1, MEMri:$addr),
1119 "if ($src1.new) $dst = memb($addr)",
1122 let neverHasSideEffects = 1, isPredicated = 1 in
1123 def LDrib_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1124 (ins PredRegs:$src1, MEMri:$addr),
1125 "if (!$src1.new) $dst = memb($addr)",
1128 let neverHasSideEffects = 1, isPredicated = 1 in
1129 def LDrib_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
1130 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1131 "if ($src1.new) $dst = memb($src2+#$src3)",
1134 let neverHasSideEffects = 1, isPredicated = 1 in
1135 def LDrib_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1136 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1137 "if (!$src1.new) $dst = memb($src2+#$src3)",
1142 let isPredicable = 1 in
1143 def LDrih : LDInst<(outs IntRegs:$dst),
1145 "$dst = memh($addr)",
1146 [(set (i32 IntRegs:$dst), (i32 (sextloadi16 ADDRriS11_1:$addr)))]>;
1148 let isPredicable = 1, AddedComplexity = 20 in
1149 def LDrih_indexed : LDInst<(outs IntRegs:$dst),
1150 (ins IntRegs:$src1, s11_1Imm:$offset),
1151 "$dst = memh($src1+#$offset)",
1152 [(set (i32 IntRegs:$dst),
1153 (i32 (sextloadi16 (add (i32 IntRegs:$src1),
1154 s11_1ImmPred:$offset))))]>;
1156 def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
1157 (i32 (LDrih ADDRriS11_1:$addr))>;
1159 let AddedComplexity = 20 in
1160 def : Pat < (i32 (extloadi16 (add IntRegs:$src1, s11_1ImmPred:$offset))),
1161 (i32 (LDrih_indexed IntRegs:$src1, s11_1ImmPred:$offset)) >;
1163 let neverHasSideEffects = 1 in
1164 def LDrih_GP : LDInst2<(outs IntRegs:$dst),
1165 (ins globaladdress:$global, u16Imm:$offset),
1166 "$dst = memh(#$global+$offset)",
1170 let neverHasSideEffects = 1 in
1171 def LDh_GP : LDInst2<(outs IntRegs:$dst),
1172 (ins globaladdress:$global),
1173 "$dst = memh(#$global)",
1177 let neverHasSideEffects = 1 in
1178 def LDuh_GP : LDInst2<(outs IntRegs:$dst),
1179 (ins globaladdress:$global),
1180 "$dst = memuh(#$global)",
1184 let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1185 def POST_LDrih : LDInst2PI<(outs IntRegs:$dst, IntRegs:$dst2),
1186 (ins IntRegs:$src1, s4Imm:$offset),
1187 "$dst = memh($src1++#$offset)",
1191 // Load halfword conditionally.
1192 let neverHasSideEffects = 1, isPredicated = 1 in
1193 def LDrih_cPt : LDInst2<(outs IntRegs:$dst),
1194 (ins PredRegs:$src1, MEMri:$addr),
1195 "if ($src1) $dst = memh($addr)",
1198 let neverHasSideEffects = 1, isPredicated = 1 in
1199 def LDrih_cNotPt : LDInst2<(outs IntRegs:$dst),
1200 (ins PredRegs:$src1, MEMri:$addr),
1201 "if (!$src1) $dst = memh($addr)",
1204 let neverHasSideEffects = 1, isPredicated = 1 in
1205 def LDrih_indexed_cPt : LDInst2<(outs IntRegs:$dst),
1206 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1207 "if ($src1) $dst = memh($src2+#$src3)",
1210 let neverHasSideEffects = 1, isPredicated = 1 in
1211 def LDrih_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
1212 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1213 "if (!$src1) $dst = memh($src2+#$src3)",
1216 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1217 def POST_LDrih_cPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1218 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1219 "if ($src1) $dst1 = memh($src2++#$src3)",
1223 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1224 def POST_LDrih_cNotPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1225 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1226 "if (!$src1) $dst1 = memh($src2++#$src3)",
1230 let neverHasSideEffects = 1, isPredicated = 1 in
1231 def LDrih_cdnPt : LDInst2<(outs IntRegs:$dst),
1232 (ins PredRegs:$src1, MEMri:$addr),
1233 "if ($src1.new) $dst = memh($addr)",
1236 let neverHasSideEffects = 1, isPredicated = 1 in
1237 def LDrih_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1238 (ins PredRegs:$src1, MEMri:$addr),
1239 "if (!$src1.new) $dst = memh($addr)",
1242 let neverHasSideEffects = 1, isPredicated = 1 in
1243 def LDrih_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
1244 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1245 "if ($src1.new) $dst = memh($src2+#$src3)",
1248 let neverHasSideEffects = 1, isPredicated = 1 in
1249 def LDrih_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1250 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1251 "if (!$src1.new) $dst = memh($src2+#$src3)",
1254 // Load unsigned byte.
1255 let isPredicable = 1 in
1256 def LDriub : LDInst<(outs IntRegs:$dst),
1258 "$dst = memub($addr)",
1259 [(set (i32 IntRegs:$dst), (i32 (zextloadi8 ADDRriS11_0:$addr)))]>;
1261 def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
1262 (i32 (LDriub ADDRriS11_0:$addr))>;
1264 let isPredicable = 1, AddedComplexity = 20 in
1265 def LDriub_indexed : LDInst<(outs IntRegs:$dst),
1266 (ins IntRegs:$src1, s11_0Imm:$offset),
1267 "$dst = memub($src1+#$offset)",
1268 [(set (i32 IntRegs:$dst),
1269 (i32 (zextloadi8 (add (i32 IntRegs:$src1),
1270 s11_0ImmPred:$offset))))]>;
1272 let AddedComplexity = 20 in
1273 def : Pat < (i32 (zextloadi1 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1274 (i32 (LDriub_indexed IntRegs:$src1, s11_0ImmPred:$offset))>;
1276 let neverHasSideEffects = 1 in
1277 def LDriub_GP : LDInst2<(outs IntRegs:$dst),
1278 (ins globaladdress:$global, u16Imm:$offset),
1279 "$dst = memub(#$global+$offset)",
1283 let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1284 def POST_LDriub : LDInst2PI<(outs IntRegs:$dst, IntRegs:$dst2),
1285 (ins IntRegs:$src1, s4Imm:$offset),
1286 "$dst = memub($src1++#$offset)",
1290 // Load unsigned byte conditionally.
1291 let neverHasSideEffects = 1, isPredicated = 1 in
1292 def LDriub_cPt : LDInst2<(outs IntRegs:$dst),
1293 (ins PredRegs:$src1, MEMri:$addr),
1294 "if ($src1) $dst = memub($addr)",
1297 let neverHasSideEffects = 1, isPredicated = 1 in
1298 def LDriub_cNotPt : LDInst2<(outs IntRegs:$dst),
1299 (ins PredRegs:$src1, MEMri:$addr),
1300 "if (!$src1) $dst = memub($addr)",
1303 let neverHasSideEffects = 1, isPredicated = 1 in
1304 def LDriub_indexed_cPt : LDInst2<(outs IntRegs:$dst),
1305 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1306 "if ($src1) $dst = memub($src2+#$src3)",
1309 let neverHasSideEffects = 1, isPredicated = 1 in
1310 def LDriub_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
1311 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1312 "if (!$src1) $dst = memub($src2+#$src3)",
1315 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1316 def POST_LDriub_cPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1317 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1318 "if ($src1) $dst1 = memub($src2++#$src3)",
1322 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1323 def POST_LDriub_cNotPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1324 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1325 "if (!$src1) $dst1 = memub($src2++#$src3)",
1329 let neverHasSideEffects = 1, isPredicated = 1 in
1330 def LDriub_cdnPt : LDInst2<(outs IntRegs:$dst),
1331 (ins PredRegs:$src1, MEMri:$addr),
1332 "if ($src1.new) $dst = memub($addr)",
1335 let neverHasSideEffects = 1, isPredicated = 1 in
1336 def LDriub_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1337 (ins PredRegs:$src1, MEMri:$addr),
1338 "if (!$src1.new) $dst = memub($addr)",
1341 let neverHasSideEffects = 1, isPredicated = 1 in
1342 def LDriub_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
1343 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1344 "if ($src1.new) $dst = memub($src2+#$src3)",
1347 let neverHasSideEffects = 1, isPredicated = 1 in
1348 def LDriub_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1349 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1350 "if (!$src1.new) $dst = memub($src2+#$src3)",
1353 // Load unsigned halfword.
1354 let isPredicable = 1 in
1355 def LDriuh : LDInst<(outs IntRegs:$dst),
1357 "$dst = memuh($addr)",
1358 [(set (i32 IntRegs:$dst), (i32 (zextloadi16 ADDRriS11_1:$addr)))]>;
1360 // Indexed load unsigned halfword.
1361 let isPredicable = 1, AddedComplexity = 20 in
1362 def LDriuh_indexed : LDInst<(outs IntRegs:$dst),
1363 (ins IntRegs:$src1, s11_1Imm:$offset),
1364 "$dst = memuh($src1+#$offset)",
1365 [(set (i32 IntRegs:$dst),
1366 (i32 (zextloadi16 (add (i32 IntRegs:$src1),
1367 s11_1ImmPred:$offset))))]>;
1369 let neverHasSideEffects = 1 in
1370 def LDriuh_GP : LDInst2<(outs IntRegs:$dst),
1371 (ins globaladdress:$global, u16Imm:$offset),
1372 "$dst = memuh(#$global+$offset)",
1376 let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1377 def POST_LDriuh : LDInst2PI<(outs IntRegs:$dst, IntRegs:$dst2),
1378 (ins IntRegs:$src1, s4Imm:$offset),
1379 "$dst = memuh($src1++#$offset)",
1383 // Load unsigned halfword conditionally.
1384 let neverHasSideEffects = 1, isPredicated = 1 in
1385 def LDriuh_cPt : LDInst2<(outs IntRegs:$dst),
1386 (ins PredRegs:$src1, MEMri:$addr),
1387 "if ($src1) $dst = memuh($addr)",
1390 let neverHasSideEffects = 1, isPredicated = 1 in
1391 def LDriuh_cNotPt : LDInst2<(outs IntRegs:$dst),
1392 (ins PredRegs:$src1, MEMri:$addr),
1393 "if (!$src1) $dst = memuh($addr)",
1396 let neverHasSideEffects = 1, isPredicated = 1 in
1397 def LDriuh_indexed_cPt : LDInst2<(outs IntRegs:$dst),
1398 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1399 "if ($src1) $dst = memuh($src2+#$src3)",
1402 let neverHasSideEffects = 1, isPredicated = 1 in
1403 def LDriuh_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
1404 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1405 "if (!$src1) $dst = memuh($src2+#$src3)",
1408 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1409 def POST_LDriuh_cPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1410 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1411 "if ($src1) $dst1 = memuh($src2++#$src3)",
1415 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1416 def POST_LDriuh_cNotPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1417 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1418 "if (!$src1) $dst1 = memuh($src2++#$src3)",
1422 let neverHasSideEffects = 1, isPredicated = 1 in
1423 def LDriuh_cdnPt : LDInst2<(outs IntRegs:$dst),
1424 (ins PredRegs:$src1, MEMri:$addr),
1425 "if ($src1.new) $dst = memuh($addr)",
1428 let neverHasSideEffects = 1, isPredicated = 1 in
1429 def LDriuh_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1430 (ins PredRegs:$src1, MEMri:$addr),
1431 "if (!$src1.new) $dst = memuh($addr)",
1434 let neverHasSideEffects = 1, isPredicated = 1 in
1435 def LDriuh_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
1436 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1437 "if ($src1.new) $dst = memuh($src2+#$src3)",
1440 let neverHasSideEffects = 1, isPredicated = 1 in
1441 def LDriuh_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1442 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1443 "if (!$src1.new) $dst = memuh($src2+#$src3)",
1448 let isPredicable = 1 in
1449 def LDriw : LDInst<(outs IntRegs:$dst),
1450 (ins MEMri:$addr), "$dst = memw($addr)",
1451 [(set IntRegs:$dst, (i32 (load ADDRriS11_2:$addr)))]>;
1454 let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1455 def LDriw_pred : LDInst<(outs PredRegs:$dst),
1457 "Error; should not emit",
1461 let isPredicable = 1, AddedComplexity = 20 in
1462 def LDriw_indexed : LDInst<(outs IntRegs:$dst),
1463 (ins IntRegs:$src1, s11_2Imm:$offset),
1464 "$dst = memw($src1+#$offset)",
1465 [(set IntRegs:$dst, (i32 (load (add IntRegs:$src1,
1466 s11_2ImmPred:$offset))))]>;
1468 let neverHasSideEffects = 1 in
1469 def LDriw_GP : LDInst2<(outs IntRegs:$dst),
1470 (ins globaladdress:$global, u16Imm:$offset),
1471 "$dst = memw(#$global+$offset)",
1475 let neverHasSideEffects = 1 in
1476 def LDw_GP : LDInst2<(outs IntRegs:$dst),
1477 (ins globaladdress:$global),
1478 "$dst = memw(#$global)",
1482 let isPredicable = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1483 def POST_LDriw : LDInst2PI<(outs IntRegs:$dst, IntRegs:$dst2),
1484 (ins IntRegs:$src1, s4Imm:$offset),
1485 "$dst = memw($src1++#$offset)",
1489 // Load word conditionally.
1491 let neverHasSideEffects = 1, isPredicated = 1 in
1492 def LDriw_cPt : LDInst2<(outs IntRegs:$dst),
1493 (ins PredRegs:$src1, MEMri:$addr),
1494 "if ($src1) $dst = memw($addr)",
1497 let neverHasSideEffects = 1, isPredicated = 1 in
1498 def LDriw_cNotPt : LDInst2<(outs IntRegs:$dst),
1499 (ins PredRegs:$src1, MEMri:$addr),
1500 "if (!$src1) $dst = memw($addr)",
1503 let neverHasSideEffects = 1, isPredicated = 1 in
1504 def LDriw_indexed_cPt : LDInst2<(outs IntRegs:$dst),
1505 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1506 "if ($src1) $dst = memw($src2+#$src3)",
1509 let neverHasSideEffects = 1, isPredicated = 1 in
1510 def LDriw_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
1511 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1512 "if (!$src1) $dst = memw($src2+#$src3)",
1515 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1516 def POST_LDriw_cPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1517 (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3),
1518 "if ($src1) $dst1 = memw($src2++#$src3)",
1522 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
1523 def POST_LDriw_cNotPt : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2),
1524 (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3),
1525 "if (!$src1) $dst1 = memw($src2++#$src3)",
1529 let neverHasSideEffects = 1, isPredicated = 1 in
1530 def LDriw_cdnPt : LDInst2<(outs IntRegs:$dst),
1531 (ins PredRegs:$src1, MEMri:$addr),
1532 "if ($src1.new) $dst = memw($addr)",
1535 let neverHasSideEffects = 1, isPredicated = 1 in
1536 def LDriw_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1537 (ins PredRegs:$src1, MEMri:$addr),
1538 "if (!$src1.new) $dst = memw($addr)",
1541 let neverHasSideEffects = 1, isPredicated = 1 in
1542 def LDriw_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
1543 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1544 "if ($src1.new) $dst = memw($src2+#$src3)",
1547 let neverHasSideEffects = 1, isPredicated = 1 in
1548 def LDriw_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1549 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1550 "if (!$src1.new) $dst = memw($src2+#$src3)",
1553 // Deallocate stack frame.
1554 let Defs = [R29, R30, R31], Uses = [R29], neverHasSideEffects = 1 in {
1555 def DEALLOCFRAME : LDInst2<(outs), (ins i32imm:$amt1),
1560 // Load and unpack bytes to halfwords.
1561 //===----------------------------------------------------------------------===//
1563 //===----------------------------------------------------------------------===//
1565 //===----------------------------------------------------------------------===//
1567 //===----------------------------------------------------------------------===//
1568 //===----------------------------------------------------------------------===//
1570 //===----------------------------------------------------------------------===//
1572 //===----------------------------------------------------------------------===//
1574 //===----------------------------------------------------------------------===//
1575 //===----------------------------------------------------------------------===//
1577 //===----------------------------------------------------------------------===//
1579 //===----------------------------------------------------------------------===//
1581 //===----------------------------------------------------------------------===//
1582 // Multiply and use lower result.
1584 def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1585 "$dst =+ mpyi($src1, #$src2)",
1586 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1587 u8ImmPred:$src2))]>;
1590 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, n8Imm:$src2),
1591 "$dst =- mpyi($src1, #$src2)",
1592 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1593 n8ImmPred:$src2))]>;
1596 // s9 is NOT the same as m9 - but it works.. so far.
1597 // Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
1598 // depending on the value of m9. See Arch Spec.
1599 def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Imm:$src2),
1600 "$dst = mpyi($src1, #$src2)",
1601 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1602 s9ImmPred:$src2))]>;
1605 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1606 "$dst = mpyi($src1, $src2)",
1607 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1608 (i32 IntRegs:$src2)))]>;
1611 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
1612 (ins IntRegs:$src1, IntRegs:$src2, u8Imm:$src3),
1613 "$dst += mpyi($src2, #$src3)",
1614 [(set (i32 IntRegs:$dst),
1615 (add (mul (i32 IntRegs:$src2), u8ImmPred:$src3),
1616 (i32 IntRegs:$src1)))],
1620 def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
1621 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1622 "$dst += mpyi($src2, $src3)",
1623 [(set (i32 IntRegs:$dst),
1624 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1625 (i32 IntRegs:$src1)))],
1629 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
1630 (ins IntRegs:$src1, IntRegs:$src2, u8Imm:$src3),
1631 "$dst -= mpyi($src2, #$src3)",
1632 [(set (i32 IntRegs:$dst),
1633 (sub (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1634 u8ImmPred:$src3)))],
1637 // Multiply and use upper result.
1638 // Rd=mpy(Rs,Rt.H):<<1:rnd:sat
1639 // Rd=mpy(Rs,Rt.L):<<1:rnd:sat
1641 def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1642 "$dst = mpy($src1, $src2)",
1643 [(set (i32 IntRegs:$dst), (mulhs (i32 IntRegs:$src1),
1644 (i32 IntRegs:$src2)))]>;
1646 // Rd=mpy(Rs,Rt):rnd
1648 def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1649 "$dst = mpyu($src1, $src2)",
1650 [(set (i32 IntRegs:$dst), (mulhu (i32 IntRegs:$src1),
1651 (i32 IntRegs:$src2)))]>;
1653 // Multiply and use full result.
1655 def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1656 "$dst = mpyu($src1, $src2)",
1657 [(set (i64 DoubleRegs:$dst),
1658 (mul (i64 (anyext (i32 IntRegs:$src1))),
1659 (i64 (anyext (i32 IntRegs:$src2)))))]>;
1662 def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1663 "$dst = mpy($src1, $src2)",
1664 [(set (i64 DoubleRegs:$dst),
1665 (mul (i64 (sext (i32 IntRegs:$src1))),
1666 (i64 (sext (i32 IntRegs:$src2)))))]>;
1668 // Multiply and accumulate, use full result.
1669 // Rxx[+-]=mpy(Rs,Rt)
1671 def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
1672 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1673 "$dst += mpy($src2, $src3)",
1674 [(set (i64 DoubleRegs:$dst),
1675 (add (mul (i64 (sext (i32 IntRegs:$src2))),
1676 (i64 (sext (i32 IntRegs:$src3)))),
1677 (i64 DoubleRegs:$src1)))],
1681 def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
1682 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1683 "$dst -= mpy($src2, $src3)",
1684 [(set (i64 DoubleRegs:$dst),
1685 (sub (i64 DoubleRegs:$src1),
1686 (mul (i64 (sext (i32 IntRegs:$src2))),
1687 (i64 (sext (i32 IntRegs:$src3))))))],
1690 // Rxx[+-]=mpyu(Rs,Rt)
1692 def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1693 IntRegs:$src2, IntRegs:$src3),
1694 "$dst += mpyu($src2, $src3)",
1695 [(set (i64 DoubleRegs:$dst),
1696 (add (mul (i64 (anyext (i32 IntRegs:$src2))),
1697 (i64 (anyext (i32 IntRegs:$src3)))),
1698 (i64 DoubleRegs:$src1)))], "$src1 = $dst">;
1701 def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
1702 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1703 "$dst += mpyu($src2, $src3)",
1704 [(set (i64 DoubleRegs:$dst),
1705 (sub (i64 DoubleRegs:$src1),
1706 (mul (i64 (anyext (i32 IntRegs:$src2))),
1707 (i64 (anyext (i32 IntRegs:$src3))))))],
1711 def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1712 IntRegs:$src2, IntRegs:$src3),
1713 "$dst += add($src2, $src3)",
1714 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1715 (i32 IntRegs:$src3)),
1716 (i32 IntRegs:$src1)))],
1719 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1720 IntRegs:$src2, s8Imm:$src3),
1721 "$dst += add($src2, #$src3)",
1722 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1724 (i32 IntRegs:$src1)))],
1727 def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1728 IntRegs:$src2, IntRegs:$src3),
1729 "$dst -= add($src2, $src3)",
1730 [(set (i32 IntRegs:$dst),
1731 (sub (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1732 (i32 IntRegs:$src3))))],
1735 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1736 IntRegs:$src2, s8Imm:$src3),
1737 "$dst -= add($src2, #$src3)",
1738 [(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
1739 (add (i32 IntRegs:$src2),
1740 s8ImmPred:$src3)))],
1743 //===----------------------------------------------------------------------===//
1745 //===----------------------------------------------------------------------===//
1747 //===----------------------------------------------------------------------===//
1749 //===----------------------------------------------------------------------===//
1750 //===----------------------------------------------------------------------===//
1752 //===----------------------------------------------------------------------===//
1754 //===----------------------------------------------------------------------===//
1756 //===----------------------------------------------------------------------===//
1757 //===----------------------------------------------------------------------===//
1759 //===----------------------------------------------------------------------===//
1761 //===----------------------------------------------------------------------===//
1763 //===----------------------------------------------------------------------===//
1764 //===----------------------------------------------------------------------===//
1766 //===----------------------------------------------------------------------===//
1768 //===----------------------------------------------------------------------===//
1770 //===----------------------------------------------------------------------===//
1772 /// Assumptions::: ****** DO NOT IGNORE ********
1773 /// 1. Make sure that in post increment store, the zero'th operand is always the
1774 /// post increment operand.
1775 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
1778 // Store doubleword.
1779 let isPredicable = 1 in
1780 def STrid : STInst<(outs),
1781 (ins MEMri:$addr, DoubleRegs:$src1),
1782 "memd($addr) = $src1",
1783 [(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr)]>;
1785 // Indexed store double word.
1786 let AddedComplexity = 10, isPredicable = 1 in
1787 def STrid_indexed : STInst<(outs),
1788 (ins IntRegs:$src1, s11_3Imm:$src2, DoubleRegs:$src3),
1789 "memd($src1+#$src2) = $src3",
1790 [(store (i64 DoubleRegs:$src3),
1791 (add (i32 IntRegs:$src1), s11_3ImmPred:$src2))]>;
1793 let neverHasSideEffects = 1 in
1794 def STrid_GP : STInst2<(outs),
1795 (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),
1796 "memd(#$global+$offset) = $src",
1800 let neverHasSideEffects = 1 in
1801 def STd_GP : STInst2<(outs),
1802 (ins globaladdress:$global, DoubleRegs:$src),
1803 "memd(#$global) = $src",
1807 let hasCtrlDep = 1, isPredicable = 1 in
1808 def POST_STdri : STInstPI<(outs IntRegs:$dst),
1809 (ins DoubleRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1810 "memd($src2++#$offset) = $src1",
1812 (post_store (i64 DoubleRegs:$src1), (i32 IntRegs:$src2),
1813 s4_3ImmPred:$offset))],
1816 // Store doubleword conditionally.
1817 // if ([!]Pv) memd(Rs+#u6:3)=Rtt
1818 // if (Pv) memd(Rs+#u6:3)=Rtt
1819 let AddedComplexity = 10, neverHasSideEffects = 1,
1821 def STrid_cPt : STInst2<(outs),
1822 (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
1823 "if ($src1) memd($addr) = $src2",
1826 // if (!Pv) memd(Rs+#u6:3)=Rtt
1827 let AddedComplexity = 10, neverHasSideEffects = 1,
1829 def STrid_cNotPt : STInst2<(outs),
1830 (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
1831 "if (!$src1) memd($addr) = $src2",
1834 // if (Pv) memd(Rs+#u6:3)=Rtt
1835 let AddedComplexity = 10, neverHasSideEffects = 1,
1837 def STrid_indexed_cPt : STInst2<(outs),
1838 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
1840 "if ($src1) memd($src2+#$src3) = $src4",
1843 // if (!Pv) memd(Rs+#u6:3)=Rtt
1844 let AddedComplexity = 10, neverHasSideEffects = 1,
1846 def STrid_indexed_cNotPt : STInst2<(outs),
1847 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
1849 "if (!$src1) memd($src2+#$src3) = $src4",
1852 // if ([!]Pv) memd(Rx++#s4:3)=Rtt
1853 // if (Pv) memd(Rx++#s4:3)=Rtt
1854 let AddedComplexity = 10, neverHasSideEffects = 1,
1856 def POST_STdri_cPt : STInst2PI<(outs IntRegs:$dst),
1857 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1859 "if ($src1) memd($src3++#$offset) = $src2",
1863 // if (!Pv) memd(Rx++#s4:3)=Rtt
1864 let AddedComplexity = 10, neverHasSideEffects = 1,
1866 def POST_STdri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1867 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1869 "if (!$src1) memd($src3++#$offset) = $src2",
1875 // memb(Rs+#s11:0)=Rt
1876 let isPredicable = 1 in
1877 def STrib : STInst<(outs),
1878 (ins MEMri:$addr, IntRegs:$src1),
1879 "memb($addr) = $src1",
1880 [(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr)]>;
1882 let AddedComplexity = 10, isPredicable = 1 in
1883 def STrib_indexed : STInst<(outs),
1884 (ins IntRegs:$src1, s11_0Imm:$src2, IntRegs:$src3),
1885 "memb($src1+#$src2) = $src3",
1886 [(truncstorei8 (i32 IntRegs:$src3), (add (i32 IntRegs:$src1),
1887 s11_0ImmPred:$src2))]>;
1889 // memb(gp+#u16:0)=Rt
1890 let neverHasSideEffects = 1 in
1891 def STrib_GP : STInst2<(outs),
1892 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1893 "memb(#$global+$offset) = $src",
1898 let neverHasSideEffects = 1 in
1899 def STb_GP : STInst2<(outs),
1900 (ins globaladdress:$global, IntRegs:$src),
1901 "memb(#$global) = $src",
1905 // memb(Rx++#s4:0)=Rt
1906 let hasCtrlDep = 1, isPredicable = 1 in
1907 def POST_STbri : STInstPI<(outs IntRegs:$dst), (ins IntRegs:$src1,
1910 "memb($src2++#$offset) = $src1",
1912 (post_truncsti8 (i32 IntRegs:$src1), (i32 IntRegs:$src2),
1913 s4_0ImmPred:$offset))],
1916 // Store byte conditionally.
1917 // if ([!]Pv) memb(Rs+#u6:0)=Rt
1918 // if (Pv) memb(Rs+#u6:0)=Rt
1919 let neverHasSideEffects = 1, isPredicated = 1 in
1920 def STrib_cPt : STInst2<(outs),
1921 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1922 "if ($src1) memb($addr) = $src2",
1925 // if (!Pv) memb(Rs+#u6:0)=Rt
1926 let neverHasSideEffects = 1, isPredicated = 1 in
1927 def STrib_cNotPt : STInst2<(outs),
1928 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1929 "if (!$src1) memb($addr) = $src2",
1932 // if (Pv) memb(Rs+#u6:0)=Rt
1933 let neverHasSideEffects = 1, isPredicated = 1 in
1934 def STrib_indexed_cPt : STInst2<(outs),
1935 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1936 "if ($src1) memb($src2+#$src3) = $src4",
1939 // if (!Pv) memb(Rs+#u6:0)=Rt
1940 let neverHasSideEffects = 1, isPredicated = 1 in
1941 def STrib_indexed_cNotPt : STInst2<(outs),
1942 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1943 "if (!$src1) memb($src2+#$src3) = $src4",
1946 // if ([!]Pv) memb(Rx++#s4:0)=Rt
1947 // if (Pv) memb(Rx++#s4:0)=Rt
1948 let hasCtrlDep = 1, isPredicated = 1 in
1949 def POST_STbri_cPt : STInst2PI<(outs IntRegs:$dst),
1950 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1951 "if ($src1) memb($src3++#$offset) = $src2",
1954 // if (!Pv) memb(Rx++#s4:0)=Rt
1955 let hasCtrlDep = 1, isPredicated = 1 in
1956 def POST_STbri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1957 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1958 "if (!$src1) memb($src3++#$offset) = $src2",
1963 // memh(Rs+#s11:1)=Rt
1964 let isPredicable = 1 in
1965 def STrih : STInst<(outs),
1966 (ins MEMri:$addr, IntRegs:$src1),
1967 "memh($addr) = $src1",
1968 [(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr)]>;
1971 let AddedComplexity = 10, isPredicable = 1 in
1972 def STrih_indexed : STInst<(outs),
1973 (ins IntRegs:$src1, s11_1Imm:$src2, IntRegs:$src3),
1974 "memh($src1+#$src2) = $src3",
1975 [(truncstorei16 (i32 IntRegs:$src3), (add (i32 IntRegs:$src1),
1976 s11_1ImmPred:$src2))]>;
1978 let neverHasSideEffects = 1 in
1979 def STrih_GP : STInst2<(outs),
1980 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1981 "memh(#$global+$offset) = $src",
1985 let neverHasSideEffects = 1 in
1986 def STh_GP : STInst2<(outs),
1987 (ins globaladdress:$global, IntRegs:$src),
1988 "memh(#$global) = $src",
1992 // memh(Rx++#s4:1)=Rt.H
1993 // memh(Rx++#s4:1)=Rt
1994 let hasCtrlDep = 1, isPredicable = 1 in
1995 def POST_SThri : STInstPI<(outs IntRegs:$dst),
1996 (ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1997 "memh($src2++#$offset) = $src1",
1999 (post_truncsti16 (i32 IntRegs:$src1), (i32 IntRegs:$src2),
2000 s4_1ImmPred:$offset))],
2003 // Store halfword conditionally.
2004 // if ([!]Pv) memh(Rs+#u6:1)=Rt
2005 // if (Pv) memh(Rs+#u6:1)=Rt
2006 let neverHasSideEffects = 1, isPredicated = 1 in
2007 def STrih_cPt : STInst2<(outs),
2008 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2009 "if ($src1) memh($addr) = $src2",
2012 // if (!Pv) memh(Rs+#u6:1)=Rt
2013 let neverHasSideEffects = 1, isPredicated = 1 in
2014 def STrih_cNotPt : STInst2<(outs),
2015 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2016 "if (!$src1) memh($addr) = $src2",
2019 // if (Pv) memh(Rs+#u6:1)=Rt
2020 let neverHasSideEffects = 1, isPredicated = 1 in
2021 def STrih_indexed_cPt : STInst2<(outs),
2022 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
2023 "if ($src1) memh($src2+#$src3) = $src4",
2026 // if (!Pv) memh(Rs+#u6:1)=Rt
2027 let neverHasSideEffects = 1, isPredicated = 1 in
2028 def STrih_indexed_cNotPt : STInst2<(outs),
2029 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
2030 "if (!$src1) memh($src2+#$src3) = $src4",
2033 // if ([!]Pv) memh(Rx++#s4:1)=Rt
2034 // if (Pv) memh(Rx++#s4:1)=Rt
2035 let hasCtrlDep = 1, isPredicated = 1 in
2036 def POST_SThri_cPt : STInst2PI<(outs IntRegs:$dst),
2037 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2038 "if ($src1) memh($src3++#$offset) = $src2",
2041 // if (!Pv) memh(Rx++#s4:1)=Rt
2042 let hasCtrlDep = 1, isPredicated = 1 in
2043 def POST_SThri_cNotPt : STInst2PI<(outs IntRegs:$dst),
2044 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2045 "if (!$src1) memh($src3++#$offset) = $src2",
2051 let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
2052 def STriw_pred : STInst2<(outs),
2053 (ins MEMri:$addr, PredRegs:$src1),
2054 "Error; should not emit",
2057 // memw(Rs+#s11:2)=Rt
2058 let isPredicable = 1 in
2059 def STriw : STInst<(outs),
2060 (ins MEMri:$addr, IntRegs:$src1),
2061 "memw($addr) = $src1",
2062 [(store (i32 IntRegs:$src1), ADDRriS11_2:$addr)]>;
2064 let AddedComplexity = 10, isPredicable = 1 in
2065 def STriw_indexed : STInst<(outs),
2066 (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
2067 "memw($src1+#$src2) = $src3",
2068 [(store (i32 IntRegs:$src3),
2069 (add (i32 IntRegs:$src1), s11_2ImmPred:$src2))]>;
2071 let neverHasSideEffects = 1 in
2072 def STriw_GP : STInst2<(outs),
2073 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2074 "memw(#$global+$offset) = $src",
2078 let neverHasSideEffects = 1 in
2079 def STw_GP : STInst2<(outs),
2080 (ins globaladdress:$global, IntRegs:$src),
2081 "memw(#$global) = $src",
2085 let hasCtrlDep = 1, isPredicable = 1 in
2086 def POST_STwri : STInstPI<(outs IntRegs:$dst),
2087 (ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
2088 "memw($src2++#$offset) = $src1",
2090 (post_store (i32 IntRegs:$src1), (i32 IntRegs:$src2),
2091 s4_2ImmPred:$offset))],
2094 // Store word conditionally.
2095 // if ([!]Pv) memw(Rs+#u6:2)=Rt
2096 // if (Pv) memw(Rs+#u6:2)=Rt
2097 let neverHasSideEffects = 1, isPredicated = 1 in
2098 def STriw_cPt : STInst2<(outs),
2099 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2100 "if ($src1) memw($addr) = $src2",
2103 // if (!Pv) memw(Rs+#u6:2)=Rt
2104 let neverHasSideEffects = 1, isPredicated = 1 in
2105 def STriw_cNotPt : STInst2<(outs),
2106 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2107 "if (!$src1) memw($addr) = $src2",
2110 // if (Pv) memw(Rs+#u6:2)=Rt
2111 let neverHasSideEffects = 1, isPredicated = 1 in
2112 def STriw_indexed_cPt : STInst2<(outs),
2113 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2114 "if ($src1) memw($src2+#$src3) = $src4",
2117 // if (!Pv) memw(Rs+#u6:2)=Rt
2118 let neverHasSideEffects = 1, isPredicated = 1 in
2119 def STriw_indexed_cNotPt : STInst2<(outs),
2120 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2121 "if (!$src1) memw($src2+#$src3) = $src4",
2124 // if ([!]Pv) memw(Rx++#s4:2)=Rt
2125 // if (Pv) memw(Rx++#s4:2)=Rt
2126 let hasCtrlDep = 1, isPredicated = 1 in
2127 def POST_STwri_cPt : STInst2PI<(outs IntRegs:$dst),
2128 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2129 "if ($src1) memw($src3++#$offset) = $src2",
2132 // if (!Pv) memw(Rx++#s4:2)=Rt
2133 let hasCtrlDep = 1, isPredicated = 1 in
2134 def POST_STwri_cNotPt : STInst2PI<(outs IntRegs:$dst),
2135 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2136 "if (!$src1) memw($src3++#$offset) = $src2",
2141 // Allocate stack frame.
2142 let Defs = [R29, R30], Uses = [R31, R30], neverHasSideEffects = 1 in {
2143 def ALLOCFRAME : STInst2<(outs),
2145 "allocframe(#$amt)",
2148 //===----------------------------------------------------------------------===//
2150 //===----------------------------------------------------------------------===//
2152 //===----------------------------------------------------------------------===//
2154 //===----------------------------------------------------------------------===//
2156 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
2157 "$dst = not($src1)",
2158 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
2161 // Sign extend word to doubleword.
2162 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
2163 "$dst = sxtw($src1)",
2164 [(set (i64 DoubleRegs:$dst), (sext (i32 IntRegs:$src1)))]>;
2165 //===----------------------------------------------------------------------===//
2167 //===----------------------------------------------------------------------===//
2169 //===----------------------------------------------------------------------===//
2171 //===----------------------------------------------------------------------===//
2172 //===----------------------------------------------------------------------===//
2174 //===----------------------------------------------------------------------===//
2177 //===----------------------------------------------------------------------===//
2179 //===----------------------------------------------------------------------===//
2180 //===----------------------------------------------------------------------===//
2182 //===----------------------------------------------------------------------===//
2184 //===----------------------------------------------------------------------===//
2186 //===----------------------------------------------------------------------===//
2187 //===----------------------------------------------------------------------===//
2189 //===----------------------------------------------------------------------===//
2191 //===----------------------------------------------------------------------===//
2193 //===----------------------------------------------------------------------===//
2194 // Predicate transfer.
2195 let neverHasSideEffects = 1 in
2196 def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
2197 "$dst = $src1 /* Should almost never emit this. */",
2200 def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1),
2201 "$dst = $src1 /* Should almost never emit this. */",
2202 [(set (i1 PredRegs:$dst), (trunc (i32 IntRegs:$src1)))]>;
2203 //===----------------------------------------------------------------------===//
2205 //===----------------------------------------------------------------------===//
2207 //===----------------------------------------------------------------------===//
2209 //===----------------------------------------------------------------------===//
2210 // Shift by immediate.
2211 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2212 "$dst = asr($src1, #$src2)",
2213 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
2214 u5ImmPred:$src2))]>;
2216 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2217 "$dst = asr($src1, #$src2)",
2218 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
2219 u6ImmPred:$src2))]>;
2221 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2222 "$dst = asl($src1, #$src2)",
2223 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
2224 u5ImmPred:$src2))]>;
2226 def ASLd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2227 "$dst = asl($src1, #$src2)",
2228 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
2229 u6ImmPred:$src2))]>;
2231 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2232 "$dst = lsr($src1, #$src2)",
2233 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
2234 u5ImmPred:$src2))]>;
2236 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2237 "$dst = lsr($src1, #$src2)",
2238 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
2239 u6ImmPred:$src2))]>;
2241 // Shift by immediate and add.
2242 let AddedComplexity = 100 in
2243 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
2245 "$dst = addasl($src1, $src2, #$src3)",
2246 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
2247 (shl (i32 IntRegs:$src2),
2248 u3ImmPred:$src3)))]>;
2250 // Shift by register.
2251 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2252 "$dst = asl($src1, $src2)",
2253 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
2254 (i32 IntRegs:$src2)))]>;
2256 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2257 "$dst = asr($src1, $src2)",
2258 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
2259 (i32 IntRegs:$src2)))]>;
2261 def LSL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2262 "$dst = lsl($src1, $src2)",
2263 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
2264 (i32 IntRegs:$src2)))]>;
2266 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2267 "$dst = lsr($src1, $src2)",
2268 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
2269 (i32 IntRegs:$src2)))]>;
2271 def ASLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2272 "$dst = asl($src1, $src2)",
2273 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
2274 (i32 IntRegs:$src2)))]>;
2276 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2277 "$dst = lsl($src1, $src2)",
2278 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
2279 (i32 IntRegs:$src2)))]>;
2281 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2283 "$dst = asr($src1, $src2)",
2284 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
2285 (i32 IntRegs:$src2)))]>;
2287 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2289 "$dst = lsr($src1, $src2)",
2290 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
2291 (i32 IntRegs:$src2)))]>;
2293 //===----------------------------------------------------------------------===//
2295 //===----------------------------------------------------------------------===//
2297 //===----------------------------------------------------------------------===//
2299 //===----------------------------------------------------------------------===//
2300 //===----------------------------------------------------------------------===//
2302 //===----------------------------------------------------------------------===//
2304 //===----------------------------------------------------------------------===//
2306 //===----------------------------------------------------------------------===//
2307 //===----------------------------------------------------------------------===//
2309 //===----------------------------------------------------------------------===//
2311 //===----------------------------------------------------------------------===//
2313 //===----------------------------------------------------------------------===//
2315 //===----------------------------------------------------------------------===//
2317 //===----------------------------------------------------------------------===//
2318 def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
2319 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
2322 let hasSideEffects = 1, isHexagonSolo = 1 in
2323 def BARRIER : SYSInst<(outs), (ins),
2325 [(HexagonBARRIER)]>;
2327 //===----------------------------------------------------------------------===//
2329 //===----------------------------------------------------------------------===//
2331 // TFRI64 - assembly mapped.
2332 let isReMaterializable = 1 in
2333 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
2335 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
2337 // Pseudo instruction to encode a set of conditional transfers.
2338 // This instruction is used instead of a mux and trades-off codesize
2339 // for performance. We conduct this transformation optimistically in
2340 // the hope that these instructions get promoted to dot-new transfers.
2341 let AddedComplexity = 100, isPredicated = 1 in
2342 def TFR_condset_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
2345 "Error; should not emit",
2346 [(set (i32 IntRegs:$dst),
2347 (i32 (select (i1 PredRegs:$src1),
2348 (i32 IntRegs:$src2),
2349 (i32 IntRegs:$src3))))]>;
2350 let AddedComplexity = 100, isPredicated = 1 in
2351 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
2352 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
2353 "Error; should not emit",
2354 [(set (i32 IntRegs:$dst),
2355 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
2356 s12ImmPred:$src3)))]>;
2358 let AddedComplexity = 100, isPredicated = 1 in
2359 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
2360 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
2361 "Error; should not emit",
2362 [(set (i32 IntRegs:$dst),
2363 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
2364 (i32 IntRegs:$src3))))]>;
2366 let AddedComplexity = 100, isPredicated = 1 in
2367 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
2368 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
2369 "Error; should not emit",
2370 [(set (i32 IntRegs:$dst),
2371 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
2372 s12ImmPred:$src3)))]>;
2374 // Generate frameindex addresses.
2375 let isReMaterializable = 1 in
2376 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
2377 "$dst = add($src1)",
2378 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
2383 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
2384 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
2385 "loop0($offset, #$src2)",
2389 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
2390 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
2391 "loop0($offset, $src2)",
2395 let isBranch = 1, isTerminator = 1, neverHasSideEffects = 1,
2396 Defs = [PC, LC0], Uses = [SA0, LC0] in {
2397 def ENDLOOP0 : Marker<(outs), (ins brtarget:$offset),
2402 // Support for generating global address.
2403 // Taken from X86InstrInfo.td.
2404 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [
2408 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
2409 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
2411 // HI/LO Instructions
2412 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2413 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
2414 "$dst.l = #LO($global)",
2417 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2418 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
2419 "$dst.h = #HI($global)",
2422 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2423 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2424 "$dst.l = #LO($imm_value)",
2428 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2429 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2430 "$dst.h = #HI($imm_value)",
2433 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2434 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2435 "$dst.l = #LO($jt)",
2438 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2439 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2440 "$dst.h = #HI($jt)",
2444 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2445 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2446 "$dst.l = #LO($label)",
2449 let isReMaterializable = 1, isMoveImm = 1 , neverHasSideEffects = 1 in
2450 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2451 "$dst.h = #HI($label)",
2454 // This pattern is incorrect. When we add small data, we should change
2455 // this pattern to use memw(#foo).
2456 // This is for sdata.
2457 let isMoveImm = 1 in
2458 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2459 "$dst = CONST32(#$global)",
2460 [(set (i32 IntRegs:$dst),
2461 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
2463 // This is for non-sdata.
2464 let isReMaterializable = 1, isMoveImm = 1 in
2465 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2466 "$dst = CONST32(#$global)",
2467 [(set (i32 IntRegs:$dst),
2468 (HexagonCONST32 tglobaladdr:$global))]>;
2470 let isReMaterializable = 1, isMoveImm = 1 in
2471 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2472 "$dst = CONST32(#$jt)",
2473 [(set (i32 IntRegs:$dst),
2474 (HexagonCONST32 tjumptable:$jt))]>;
2476 let isReMaterializable = 1, isMoveImm = 1 in
2477 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2478 "$dst = CONST32(#$global)",
2479 [(set (i32 IntRegs:$dst),
2480 (HexagonCONST32_GP tglobaladdr:$global))]>;
2482 let isReMaterializable = 1, isMoveImm = 1 in
2483 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
2484 "$dst = CONST32(#$global)",
2485 [(set (i32 IntRegs:$dst), imm:$global) ]>;
2487 let isReMaterializable = 1, isMoveImm = 1 in
2488 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
2489 "$dst = CONST32($label)",
2490 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
2492 let isReMaterializable = 1, isMoveImm = 1 in
2493 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
2494 "$dst = CONST64(#$global)",
2495 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
2497 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
2498 "$dst = xor($dst, $dst)",
2499 [(set (i1 PredRegs:$dst), 0)]>;
2501 def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2502 "$dst = mpy($src1, $src2)",
2503 [(set (i32 IntRegs:$dst),
2504 (trunc (i64 (srl (i64 (mul (i64 (sext (i32 IntRegs:$src1))),
2505 (i64 (sext (i32 IntRegs:$src2))))),
2508 // Pseudo instructions.
2509 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
2511 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
2512 SDTCisVT<1, i32> ]>;
2514 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
2515 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2517 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
2518 [SDNPHasChain, SDNPOutGlue]>;
2520 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2522 def call : SDNode<"HexagonISD::CALL", SDT_SPCall,
2523 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
2525 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
2526 // Optional Flag and Variable Arguments.
2527 // Its 1 Operand has pointer type.
2528 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
2529 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
2531 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
2532 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
2533 "Should never be emitted",
2534 [(callseq_start timm:$amt)]>;
2537 let Defs = [R29, R30, R31], Uses = [R29] in {
2538 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2539 "Should never be emitted",
2540 [(callseq_end timm:$amt1, timm:$amt2)]>;
2543 let isCall = 1, neverHasSideEffects = 1,
2544 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2545 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2546 def CALL : JInst<(outs), (ins calltarget:$dst, variable_ops),
2550 // Call subroutine from register.
2551 let isCall = 1, neverHasSideEffects = 1,
2552 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2553 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2554 def CALLR : JRInst<(outs), (ins IntRegs:$dst, variable_ops),
2560 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
2561 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2562 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2563 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst, variable_ops),
2564 "jump $dst // TAILCALL", []>;
2566 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
2567 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2568 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2569 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst, variable_ops),
2570 "jump $dst // TAILCALL", []>;
2573 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
2574 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2575 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2576 def TCRETURNR : JInst<(outs), (ins IntRegs:$dst, variable_ops),
2577 "jumpr $dst // TAILCALL", []>;
2579 // Map call instruction.
2580 def : Pat<(call (i32 IntRegs:$dst)),
2581 (CALLR (i32 IntRegs:$dst))>, Requires<[HasV2TOnly]>;
2582 def : Pat<(call tglobaladdr:$dst),
2583 (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
2584 def : Pat<(call texternalsym:$dst),
2585 (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>;
2587 def : Pat<(HexagonTCRet tglobaladdr:$dst),
2588 (TCRETURNtg tglobaladdr:$dst)>;
2589 def : Pat<(HexagonTCRet texternalsym:$dst),
2590 (TCRETURNtext texternalsym:$dst)>;
2591 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
2592 (TCRETURNR (i32 IntRegs:$dst))>;
2594 // Atomic load and store support
2595 // 8 bit atomic load
2596 def : Pat<(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
2597 (i32 (LDub_GP tglobaladdr:$global))>,
2600 def : Pat<(atomic_load_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2601 u16ImmPred:$offset)),
2602 (i32 (LDriub_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2605 def : Pat<(atomic_load_8 ADDRriS11_0:$src1),
2606 (i32 (LDriub ADDRriS11_0:$src1))>;
2608 def : Pat<(atomic_load_8 (add (i32 IntRegs:$src1), s11_0ImmPred:$offset)),
2609 (i32 (LDriub_indexed (i32 IntRegs:$src1), s11_0ImmPred:$offset))>;
2613 // 16 bit atomic load
2614 def : Pat<(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
2615 (i32 (LDuh_GP tglobaladdr:$global))>,
2618 def : Pat<(atomic_load_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2619 u16ImmPred:$offset)),
2620 (i32 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2623 def : Pat<(atomic_load_16 ADDRriS11_1:$src1),
2624 (i32 (LDriuh ADDRriS11_1:$src1))>;
2626 def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)),
2627 (i32 (LDriuh_indexed (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
2631 // 32 bit atomic load
2632 def : Pat<(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
2633 (i32 (LDw_GP tglobaladdr:$global))>,
2636 def : Pat<(atomic_load_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2637 u16ImmPred:$offset)),
2638 (i32 (LDriw_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2641 def : Pat<(atomic_load_32 ADDRriS11_2:$src1),
2642 (i32 (LDriw ADDRriS11_2:$src1))>;
2644 def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),
2645 (i32 (LDriw_indexed (i32 IntRegs:$src1), s11_2ImmPred:$offset))>;
2648 // 64 bit atomic load
2649 def : Pat<(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
2650 (i64 (LDd_GP tglobaladdr:$global))>,
2653 def : Pat<(atomic_load_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2654 u16ImmPred:$offset)),
2655 (i64 (LDrid_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2658 def : Pat<(atomic_load_64 ADDRriS11_3:$src1),
2659 (i64 (LDrid ADDRriS11_3:$src1))>;
2661 def : Pat<(atomic_load_64 (add (i32 IntRegs:$src1), s11_3ImmPred:$offset)),
2662 (i64 (LDrid_indexed (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
2665 // 64 bit atomic store
2666 def : Pat<(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
2667 (i64 DoubleRegs:$src1)),
2668 (STd_GP tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2671 def : Pat<(atomic_store_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2672 u16ImmPred:$offset),
2673 (i64 DoubleRegs:$src1)),
2674 (STrid_GP tglobaladdr:$global, u16ImmPred:$offset,
2675 (i64 DoubleRegs:$src1))>, Requires<[NoV4T]>;
2677 // 8 bit atomic store
2678 def : Pat<(atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
2679 (i32 IntRegs:$src1)),
2680 (STb_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2683 def : Pat<(atomic_store_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2684 u16ImmPred:$offset),
2685 (i32 IntRegs:$src1)),
2686 (STrib_GP tglobaladdr:$global, u16ImmPred:$offset,
2687 (i32 IntRegs:$src1))>, Requires<[NoV4T]>;
2689 def : Pat<(atomic_store_8 ADDRriS11_0:$src2, (i32 IntRegs:$src1)),
2690 (STrib ADDRriS11_0:$src2, (i32 IntRegs:$src1))>;
2692 def : Pat<(atomic_store_8 (add (i32 IntRegs:$src2), s11_0ImmPred:$offset),
2693 (i32 IntRegs:$src1)),
2694 (STrib_indexed (i32 IntRegs:$src2), s11_0ImmPred:$offset,
2695 (i32 IntRegs:$src1))>;
2698 // 16 bit atomic store
2699 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
2700 (i32 IntRegs:$src1)),
2701 (STh_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2704 def : Pat<(atomic_store_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2705 u16ImmPred:$offset),
2706 (i32 IntRegs:$src1)),
2707 (STrih_GP tglobaladdr:$global, u16ImmPred:$offset,
2708 (i32 IntRegs:$src1))>, Requires<[NoV4T]>;
2710 def : Pat<(atomic_store_16 ADDRriS11_1:$src2, (i32 IntRegs:$src1)),
2711 (STrih ADDRriS11_1:$src2, (i32 IntRegs:$src1))>;
2713 def : Pat<(atomic_store_16 (i32 IntRegs:$src1),
2714 (add (i32 IntRegs:$src2), s11_1ImmPred:$offset)),
2715 (STrih_indexed (i32 IntRegs:$src2), s11_1ImmPred:$offset,
2716 (i32 IntRegs:$src1))>;
2719 // 32 bit atomic store
2720 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
2721 (i32 IntRegs:$src1)),
2722 (STw_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2725 def : Pat<(atomic_store_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2726 u16ImmPred:$offset),
2727 (i32 IntRegs:$src1)),
2728 (STriw_GP tglobaladdr:$global, u16ImmPred:$offset,
2729 (i32 IntRegs:$src1))>,
2732 def : Pat<(atomic_store_32 ADDRriS11_2:$src2, (i32 IntRegs:$src1)),
2733 (STriw ADDRriS11_2:$src2, (i32 IntRegs:$src1))>;
2735 def : Pat<(atomic_store_32 (add (i32 IntRegs:$src2), s11_2ImmPred:$offset),
2736 (i32 IntRegs:$src1)),
2737 (STriw_indexed (i32 IntRegs:$src2), s11_2ImmPred:$offset,
2738 (i32 IntRegs:$src1))>;
2743 def : Pat<(atomic_store_64 ADDRriS11_3:$src2, (i64 DoubleRegs:$src1)),
2744 (STrid ADDRriS11_3:$src2, (i64 DoubleRegs:$src1))>;
2746 def : Pat<(atomic_store_64 (add (i32 IntRegs:$src2), s11_3ImmPred:$offset),
2747 (i64 DoubleRegs:$src1)),
2748 (STrid_indexed (i32 IntRegs:$src2), s11_3ImmPred:$offset,
2749 (i64 DoubleRegs:$src1))>;
2751 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
2752 def : Pat <(and (i32 IntRegs:$src1), 65535),
2753 (ZXTH (i32 IntRegs:$src1))>;
2755 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
2756 def : Pat <(and (i32 IntRegs:$src1), 255),
2757 (ZXTB (i32 IntRegs:$src1))>;
2759 // Map Add(p1, true) to p1 = not(p1).
2760 // Add(p1, false) should never be produced,
2761 // if it does, it got to be mapped to NOOP.
2762 def : Pat <(add (i1 PredRegs:$src1), -1),
2763 (NOT_p (i1 PredRegs:$src1))>;
2765 // Map from p0 = setlt(r0, r1) r2 = mux(p0, r3, r4) =>
2766 // p0 = cmp.lt(r0, r1), r0 = mux(p0, r2, r1).
2767 def : Pat <(select (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2768 (i32 IntRegs:$src3),
2769 (i32 IntRegs:$src4)),
2770 (i32 (TFR_condset_rr (CMPLTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2771 (i32 IntRegs:$src4), (i32 IntRegs:$src3)))>,
2772 Requires<[HasV2TOnly]>;
2774 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
2775 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
2776 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
2779 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
2780 // => r0 = TFR_condset_ri(p0, r1, #i)
2781 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
2782 (i32 IntRegs:$src3)),
2783 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
2784 s12ImmPred:$src2))>;
2786 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
2787 // => r0 = TFR_condset_ir(p0, #i, r1)
2788 def : Pat <(select (not PredRegs:$src1), IntRegs:$src2, s12ImmPred:$src3),
2789 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
2790 (i32 IntRegs:$src2)))>;
2792 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
2793 def : Pat <(brcond (not PredRegs:$src1), bb:$offset),
2794 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
2796 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
2797 def : Pat <(and PredRegs:$src1, (not PredRegs:$src2)),
2798 (i1 (AND_pnotp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2800 // Map from store(globaladdress + x) -> memd(#foo + x).
2801 let AddedComplexity = 100 in
2802 def : Pat <(store (i64 DoubleRegs:$src1),
2803 (add (HexagonCONST32_GP tglobaladdr:$global),
2804 u16ImmPred:$offset)),
2805 (STrid_GP tglobaladdr:$global, u16ImmPred:$offset,
2806 (i64 DoubleRegs:$src1))>, Requires<[NoV4T]>;
2808 // Map from store(globaladdress) -> memd(#foo).
2809 let AddedComplexity = 100 in
2810 def : Pat <(store (i64 DoubleRegs:$src1),
2811 (HexagonCONST32_GP tglobaladdr:$global)),
2812 (STd_GP tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2815 // Map from store(globaladdress + x) -> memw(#foo + x).
2816 let AddedComplexity = 100 in
2817 def : Pat <(store (i32 IntRegs:$src1),
2818 (add (HexagonCONST32_GP tglobaladdr:$global),
2819 u16ImmPred:$offset)),
2820 (STriw_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2823 // Map from store(globaladdress) -> memw(#foo + 0).
2824 let AddedComplexity = 100 in
2825 def : Pat <(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2826 (STriw_GP tglobaladdr:$global, 0, (i32 IntRegs:$src1))>;
2828 // Map from store(globaladdress) -> memw(#foo).
2829 let AddedComplexity = 100 in
2830 def : Pat <(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2831 (STriw_GP tglobaladdr:$global, 0, (i32 IntRegs:$src1))>,
2834 // Map from store(globaladdress + x) -> memh(#foo + x).
2835 let AddedComplexity = 100 in
2836 def : Pat <(truncstorei16 (i32 IntRegs:$src1),
2837 (add (HexagonCONST32_GP tglobaladdr:$global),
2838 u16ImmPred:$offset)),
2839 (STrih_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2842 // Map from store(globaladdress) -> memh(#foo).
2843 let AddedComplexity = 100 in
2844 def : Pat <(truncstorei16 (i32 IntRegs:$src1),
2845 (HexagonCONST32_GP tglobaladdr:$global)),
2846 (STh_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2849 // Map from store(globaladdress + x) -> memb(#foo + x).
2850 let AddedComplexity = 100 in
2851 def : Pat <(truncstorei8 (i32 IntRegs:$src1),
2852 (add (HexagonCONST32_GP tglobaladdr:$global),
2853 u16ImmPred:$offset)),
2854 (STrib_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2857 // Map from store(globaladdress) -> memb(#foo).
2858 let AddedComplexity = 100 in
2859 def : Pat <(truncstorei8 (i32 IntRegs:$src1),
2860 (HexagonCONST32_GP tglobaladdr:$global)),
2861 (STb_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2864 // Map from load(globaladdress + x) -> memw(#foo + x).
2865 let AddedComplexity = 100 in
2866 def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global),
2867 u16ImmPred:$offset))),
2868 (i32 (LDriw_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2871 // Map from load(globaladdress) -> memw(#foo).
2872 let AddedComplexity = 100 in
2873 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
2874 (i32 (LDw_GP tglobaladdr:$global))>,
2877 // Map from load(globaladdress + x) -> memd(#foo + x).
2878 let AddedComplexity = 100 in
2879 def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),
2880 u16ImmPred:$offset))),
2881 (i64 (LDrid_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2884 // Map from load(globaladdress) -> memw(#foo + 0).
2885 let AddedComplexity = 100 in
2886 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
2887 (i64 (LDd_GP tglobaladdr:$global))>,
2890 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd.
2891 let AddedComplexity = 100 in
2892 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
2893 (i1 (TFR_PdRs (i32 (LDb_GP tglobaladdr:$global))))>,
2896 // Map from load(globaladdress + x) -> memh(#foo + x).
2897 let AddedComplexity = 100 in
2898 def : Pat <(i32 (extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2899 u16ImmPred:$offset))),
2900 (i32 (LDrih_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2903 // Map from load(globaladdress + x) -> memh(#foo + x).
2904 let AddedComplexity = 100 in
2905 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2906 (i32 (LDrih_GP tglobaladdr:$global, 0))>,
2909 // Map from load(globaladdress + x) -> memuh(#foo + x).
2910 let AddedComplexity = 100 in
2911 def : Pat <(i32 (zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2912 u16ImmPred:$offset))),
2913 (i32 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2916 // Map from load(globaladdress) -> memuh(#foo).
2917 let AddedComplexity = 100 in
2918 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2919 (i32 (LDriuh_GP tglobaladdr:$global, 0))>,
2922 // Map from load(globaladdress) -> memh(#foo).
2923 let AddedComplexity = 100 in
2924 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2925 (i32 (LDh_GP tglobaladdr:$global))>,
2928 // Map from load(globaladdress) -> memuh(#foo).
2929 let AddedComplexity = 100 in
2930 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2931 (i32 (LDuh_GP tglobaladdr:$global))>,
2934 // Map from load(globaladdress + x) -> memb(#foo + x).
2935 let AddedComplexity = 100 in
2936 def : Pat <(i32 (extloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2937 u16ImmPred:$offset))),
2938 (i32 (LDrib_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2941 // Map from load(globaladdress + x) -> memb(#foo + x).
2942 let AddedComplexity = 100 in
2943 def : Pat <(i32 (sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2944 u16ImmPred:$offset))),
2945 (i32 (LDrib_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2948 // Map from load(globaladdress + x) -> memub(#foo + x).
2949 let AddedComplexity = 100 in
2950 def : Pat <(i32 (zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2951 u16ImmPred:$offset))),
2952 (i32 (LDriub_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2955 // Map from load(globaladdress) -> memb(#foo).
2956 let AddedComplexity = 100 in
2957 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2958 (i32 (LDb_GP tglobaladdr:$global))>,
2961 // Map from load(globaladdress) -> memb(#foo).
2962 let AddedComplexity = 100 in
2963 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2964 (i32 (LDb_GP tglobaladdr:$global))>,
2967 // Map from load(globaladdress) -> memub(#foo).
2968 let AddedComplexity = 100 in
2969 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2970 (i32 (LDub_GP tglobaladdr:$global))>,
2973 // When the Interprocedural Global Variable optimizer realizes that a
2974 // certain global variable takes only two constant values, it shrinks the
2975 // global to a boolean. Catch those loads here in the following 3 patterns.
2976 let AddedComplexity = 100 in
2977 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2978 (i32 (LDb_GP tglobaladdr:$global))>,
2981 let AddedComplexity = 100 in
2982 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2983 (i32 (LDb_GP tglobaladdr:$global))>,
2986 let AddedComplexity = 100 in
2987 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2988 (i32 (LDub_GP tglobaladdr:$global))>,
2991 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
2992 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
2993 (i32 (AND_rr (i32 (LDrib ADDRriS11_0:$addr)), (TFRI 0x1)))>;
2995 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
2996 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
2997 (i64 (SXTW (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
2999 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
3000 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
3001 (i64 (SXTW (i32 (SXTH (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
3002 subreg_loreg))))))>;
3004 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
3005 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
3006 (i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
3007 subreg_loreg))))))>;
3009 // We want to prevent emiting pnot's as much as possible.
3010 // Map brcond with an unsupported setcc to a JMP_cNot.
3011 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3013 (JMP_cNot (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
3016 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
3018 (JMP_cNot (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
3020 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
3021 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
3023 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
3024 (JMP_c (i1 PredRegs:$src1), bb:$offset)>;
3026 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
3028 (JMP_cNot (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2), bb:$offset)>;
3030 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3032 (JMP_c (CMPLTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)), bb:$offset)>;
3034 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3036 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
3039 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3041 (JMP_cNot (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
3044 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3046 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
3049 // Map from a 64-bit select to an emulated 64-bit mux.
3050 // Hexagon does not support 64-bit MUXes; so emulate with combines.
3051 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
3052 (i64 DoubleRegs:$src3)),
3053 (i64 (COMBINE_rr (i32 (MUX_rr (i1 PredRegs:$src1),
3054 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
3056 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
3058 (i32 (MUX_rr (i1 PredRegs:$src1),
3059 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
3061 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
3062 subreg_loreg))))))>;
3064 // Map from a 1-bit select to logical ops.
3065 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
3066 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
3067 (i1 PredRegs:$src3)),
3068 (OR_pp (AND_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
3069 (AND_pp (NOT_p (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
3071 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
3072 def : Pat<(i1 (load ADDRriS11_2:$addr)),
3073 (i1 (TFR_PdRs (i32 (LDrib ADDRriS11_2:$addr))))>;
3075 // Map for truncating from 64 immediates to 32 bit immediates.
3076 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
3077 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
3079 // Map for truncating from i64 immediates to i1 bit immediates.
3080 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
3081 (i1 (TFR_PdRs (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
3084 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
3085 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
3086 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
3089 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
3090 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
3091 (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
3093 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
3094 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
3095 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
3098 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
3099 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
3100 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
3103 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
3104 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
3105 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
3107 let AddedComplexity = 100 in
3108 // Map from i1 = constant<-1>; memw(CONST32(#foo)) = i1 -> r0 = 1;
3110 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
3111 (STb_GP tglobaladdr:$global, (TFRI 1))>,
3114 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
3115 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
3116 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
3118 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
3119 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
3120 (STrib ADDRriS11_2:$addr, (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0)) )>;
3122 // Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs).
3123 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
3124 // Better way to do this?
3125 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
3126 (i64 (SXTW (i32 IntRegs:$src1)))>;
3128 // Map cmple -> cmpgt.
3129 // rs <= rt -> !(rs > rt).
3130 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ImmPred:$src2)),
3131 (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), s10ImmPred:$src2)))>;
3133 // rs <= rt -> !(rs > rt).
3134 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3135 (i1 (NOT_p (CMPGTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
3137 // Rss <= Rtt -> !(Rss > Rtt).
3138 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3139 (i1 (NOT_p (CMPGT64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
3141 // Map cmpne -> cmpeq.
3142 // Hexagon_TODO: We should improve on this.
3143 // rs != rt -> !(rs == rt).
3144 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
3145 (i1 (NOT_p(i1 (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2))))>;
3147 // Map cmpne(Rs) -> !cmpeqe(Rs).
3148 // rs != rt -> !(rs == rt).
3149 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3150 (i1 (NOT_p (i1 (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
3152 // Convert setne back to xor for hexagon since we compute w/ pred registers.
3153 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
3154 (i1 (XOR_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
3156 // Map cmpne(Rss) -> !cmpew(Rss).
3157 // rs != rt -> !(rs == rt).
3158 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3159 (i1 (NOT_p (i1 (CMPEHexagon4rr (i64 DoubleRegs:$src1),
3160 (i64 DoubleRegs:$src2)))))>;
3162 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
3163 // rs >= rt -> !(rt > rs).
3164 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3165 (i1 (NOT_p (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
3167 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ImmPred:$src2)),
3168 (i1 (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2))>;
3170 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
3171 // rss >= rtt -> !(rtt > rss).
3172 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3173 (i1 (NOT_p (i1 (CMPGT64rr (i64 DoubleRegs:$src2),
3174 (i64 DoubleRegs:$src1)))))>;
3176 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
3177 // rs < rt -> !(rs >= rt).
3178 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
3179 (i1 (NOT_p (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2)))>;
3181 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
3182 // rs < rt -> rt > rs.
3183 // We can let assembler map it, or we can do in the compiler itself.
3184 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3185 (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
3187 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
3188 // rss < rtt -> (rtt > rss).
3189 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3190 (i1 (CMPGT64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
3192 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
3193 // rs < rt -> rt > rs.
3194 // We can let assembler map it, or we can do in the compiler itself.
3195 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3196 (i1 (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
3198 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
3199 // rs < rt -> rt > rs.
3200 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3201 (i1 (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
3203 // Generate cmpgeu(Rs, #u8)
3204 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ImmPred:$src2)),
3205 (i1 (CMPGEUri (i32 IntRegs:$src1), u8ImmPred:$src2))>;
3207 // Generate cmpgtu(Rs, #u9)
3208 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ImmPred:$src2)),
3209 (i1 (CMPGTUri (i32 IntRegs:$src1), u9ImmPred:$src2))>;
3211 // Map from Rs >= Rt -> !(Rt > Rs).
3212 // rs >= rt -> !(rt > rs).
3213 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3214 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
3216 // Map from Rs >= Rt -> !(Rt > Rs).
3217 // rs >= rt -> !(rt > rs).
3218 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3219 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
3221 // Map from cmpleu(Rs, Rs) -> !cmpgtu(Rs, Rs).
3222 // Map from (Rs <= Rt) -> !(Rs > Rt).
3223 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3224 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
3226 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
3227 // Map from (Rs <= Rt) -> !(Rs > Rt).
3228 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3229 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
3233 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
3234 (i32 (MUX_ii (i1 PredRegs:$src1), -1, 0))>;
3237 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
3238 (i64 (COMBINE_rr (TFRI -1), (MUX_ii (i1 PredRegs:$src1), -1, 0)))>;
3240 // Convert sign-extended load back to load and sign extend.
3242 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
3243 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
3245 // Convert any-extended load back to load and sign extend.
3247 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
3248 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
3250 // Convert sign-extended load back to load and sign extend.
3252 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
3253 (i64 (SXTW (LDrih ADDRriS11_1:$src1)))>;
3255 // Convert sign-extended load back to load and sign extend.
3257 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
3258 (i64 (SXTW (LDriw ADDRriS11_2:$src1)))>;
3263 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
3264 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
3267 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
3268 (i64 (COMBINE_rr (TFRI 0), (MUX_ii (i1 PredRegs:$src1), 1, 0)))>;
3271 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
3272 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>;
3275 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
3276 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>;
3279 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
3280 (i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>;
3283 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
3284 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>;
3286 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
3287 (i32 (LDriw ADDRriS11_0:$src1))>;
3289 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
3290 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
3291 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
3293 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
3294 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
3295 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
3297 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
3298 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
3299 (i64 (SXTW (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))))>;
3302 // Any extended 64-bit load.
3303 // anyext i32 -> i64
3304 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
3305 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>;
3307 // anyext i16 -> i64.
3308 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
3309 (i64 (COMBINE_rr (TFRI 0), (LDrih ADDRriS11_2:$src1)))>;
3311 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
3312 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
3313 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>;
3315 // Multiply 64-bit unsigned and use upper result.
3316 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
3331 (COMBINE_rr (TFRI 0),
3337 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
3339 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
3340 subreg_loreg)))), 32)),
3342 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3343 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
3344 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
3345 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
3346 32)), subreg_loreg)))),
3347 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3348 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
3350 // Multiply 64-bit signed and use upper result.
3351 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
3355 (COMBINE_rr (TFRI 0),
3365 (COMBINE_rr (TFRI 0),
3371 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
3373 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
3374 subreg_loreg)))), 32)),
3376 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3377 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
3378 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
3379 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
3380 32)), subreg_loreg)))),
3381 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3382 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
3384 // Hexagon specific ISD nodes.
3385 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
3386 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
3387 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
3388 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
3389 SDTHexagonADJDYNALLOC>;
3390 // Needed to tag these instructions for stack layout.
3391 let usesCustomInserter = 1 in
3392 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
3394 "$dst = add($src1, #$src2)",
3395 [(set (i32 IntRegs:$dst),
3396 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
3397 s16ImmPred:$src2))]>;
3399 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
3400 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
3401 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
3403 [(set (i32 IntRegs:$dst),
3404 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
3406 let AddedComplexity = 100 in
3407 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
3408 (COPY (i32 IntRegs:$src1))>;
3410 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
3411 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
3413 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
3414 def BR_JT : JRInst<(outs), (ins IntRegs:$src),
3416 [(HexagonBR_JT (i32 IntRegs:$src))]>;
3418 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
3420 def : Pat<(HexagonWrapperJT tjumptable:$dst),
3421 (i32 (CONST32_set_jt tjumptable:$dst))>;
3425 // Multi-class for logical operators :
3426 // Shift by immediate/register and accumulate/logical
3427 multiclass xtype_imm<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
3428 def _ri : SInst_acc<(outs IntRegs:$dst),
3429 (ins IntRegs:$src1, IntRegs:$src2, u5Imm:$src3),
3430 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
3431 [(set (i32 IntRegs:$dst),
3432 (OpNode2 (i32 IntRegs:$src1),
3433 (OpNode1 (i32 IntRegs:$src2),
3434 u5ImmPred:$src3)))],
3437 def d_ri : SInst_acc<(outs DoubleRegs:$dst),
3438 (ins DoubleRegs:$src1, DoubleRegs:$src2, u6Imm:$src3),
3439 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
3440 [(set (i64 DoubleRegs:$dst), (OpNode2 (i64 DoubleRegs:$src1),
3441 (OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
3445 // Multi-class for logical operators :
3446 // Shift by register and accumulate/logical (32/64 bits)
3447 multiclass xtype_reg<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
3448 def _rr : SInst_acc<(outs IntRegs:$dst),
3449 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
3450 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
3451 [(set (i32 IntRegs:$dst),
3452 (OpNode2 (i32 IntRegs:$src1),
3453 (OpNode1 (i32 IntRegs:$src2),
3454 (i32 IntRegs:$src3))))],
3457 def d_rr : SInst_acc<(outs DoubleRegs:$dst),
3458 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3459 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
3460 [(set (i64 DoubleRegs:$dst),
3461 (OpNode2 (i64 DoubleRegs:$src1),
3462 (OpNode1 (i64 DoubleRegs:$src2),
3463 (i32 IntRegs:$src3))))],
3468 multiclass basic_xtype_imm<string OpcStr, SDNode OpNode> {
3469 let AddedComplexity = 100 in
3470 defm _ADD : xtype_imm< !strconcat("+= ", OpcStr), OpNode, add>;
3471 defm _SUB : xtype_imm< !strconcat("-= ", OpcStr), OpNode, sub>;
3472 defm _AND : xtype_imm< !strconcat("&= ", OpcStr), OpNode, and>;
3473 defm _OR : xtype_imm< !strconcat("|= ", OpcStr), OpNode, or>;
3476 multiclass basic_xtype_reg<string OpcStr, SDNode OpNode> {
3477 let AddedComplexity = 100 in
3478 defm _ADD : xtype_reg< !strconcat("+= ", OpcStr), OpNode, add>;
3479 defm _SUB : xtype_reg< !strconcat("-= ", OpcStr), OpNode, sub>;
3480 defm _AND : xtype_reg< !strconcat("&= ", OpcStr), OpNode, and>;
3481 defm _OR : xtype_reg< !strconcat("|= ", OpcStr), OpNode, or>;
3484 multiclass xtype_xor_imm<string OpcStr, SDNode OpNode> {
3485 let AddedComplexity = 100 in
3486 defm _XOR : xtype_imm< !strconcat("^= ", OpcStr), OpNode, xor>;
3489 defm ASL : basic_xtype_imm<"asl", shl>, basic_xtype_reg<"asl", shl>,
3490 xtype_xor_imm<"asl", shl>;
3492 defm LSR : basic_xtype_imm<"lsr", srl>, basic_xtype_reg<"lsr", srl>,
3493 xtype_xor_imm<"lsr", srl>;
3495 defm ASR : basic_xtype_imm<"asr", sra>, basic_xtype_reg<"asr", sra>;
3496 defm LSL : basic_xtype_reg<"lsl", shl>;
3498 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
3499 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
3500 (i32 (MPYI_rin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
3502 //===----------------------------------------------------------------------===//
3503 // V3 Instructions +
3504 //===----------------------------------------------------------------------===//
3506 include "HexagonInstrInfoV3.td"
3508 //===----------------------------------------------------------------------===//
3509 // V3 Instructions -
3510 //===----------------------------------------------------------------------===//
3512 //===----------------------------------------------------------------------===//
3513 // V4 Instructions +
3514 //===----------------------------------------------------------------------===//
3516 include "HexagonInstrInfoV4.td"
3518 //===----------------------------------------------------------------------===//
3519 // V4 Instructions -
3520 //===----------------------------------------------------------------------===//